src/mesa/drivers/dri/i965/gen8_vs_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "program/prog_parameter.h"
  29 #include "program/prog_statevars.h"
  30 #include "intel_batchbuffer.h"
  31
  32 void
  33 gen8_upload_constant_state(struct brw_context *brw,
  34                            const struct brw_stage_state *stage_state,
  35                            bool active, unsigned opcode)
  36 {
  37    /* Disable if the shader stage is inactive or there are no push constants. */
  38    active = active && stage_state->push_const_size != 0;
  39
  40    BEGIN_BATCH(11);
  41    OUT_BATCH(opcode << 16 | (11 - 2));
  42    OUT_BATCH(active ? stage_state->push_const_size : 0);
  43    OUT_BATCH(0);
  44    OUT_BATCH(active ? stage_state->push_const_offset : 0);
  45    OUT_BATCH(0);
  46    OUT_BATCH(0);
  47    OUT_BATCH(0);
  48    OUT_BATCH(0);
  49    OUT_BATCH(0);
  50    OUT_BATCH(0);
  51    OUT_BATCH(0);
  52    ADVANCE_BATCH();
  53 }
  54
  55 static void
  56 upload_vs_state(struct brw_context *brw)
  57 {
  58    struct gl_context *ctx = &brw->ctx;
  59    const struct brw_stage_state *stage_state = &brw->vs.base;
  60    uint32_t floating_point_mode = 0;
  61
  62    /* CACHE_NEW_VS_PROG */
  63    const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base;
  64
  65    /* CACHE_NEW_SAMPLER */
  66    BEGIN_BATCH(2);
  67    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
  68    OUT_BATCH(stage_state->sampler_offset);
  69    ADVANCE_BATCH();
  70
  71    gen8_upload_constant_state(brw, stage_state, true /* active */,
  72                               _3DSTATE_CONSTANT_VS);
  73
  74    /* Use ALT floating point mode for ARB vertex programs, because they
  75     * require 0^0 == 1.
  76     */
  77    if (ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX] == NULL)
  78       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
  79
  80    BEGIN_BATCH(9);
  81    OUT_BATCH(_3DSTATE_VS << 16 | (9 - 2));
  82    OUT_BATCH(stage_state->prog_offset);
  83    OUT_BATCH(0);
  84    OUT_BATCH(floating_point_mode |
  85              ((ALIGN(stage_state->sampler_count, 4) / 4) <<
  86                GEN6_VS_SAMPLER_COUNT_SHIFT) |
  87              ((prog_data->base.binding_table.size_bytes / 4) <<
  88                GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
  89
  90    if (prog_data->total_scratch) {
  91       OUT_RELOC64(stage_state->scratch_bo,
  92                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  93                   ffs(prog_data->total_scratch) - 11);
  94    } else {
  95       OUT_BATCH(0);
  96       OUT_BATCH(0);
  97    }
  98
  99    OUT_BATCH((prog_data->dispatch_grf_start_reg <<
 100               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 101              (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 102              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 103
 104    OUT_BATCH(((brw->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
 105              GEN6_VS_STATISTICS_ENABLE |
 106              GEN6_VS_ENABLE);
 107
 108    /* _NEW_TRANSFORM */
 109    OUT_BATCH((ctx->Transform.ClipPlanesEnabled <<
 110               GEN8_VS_USER_CLIP_DISTANCE_SHIFT));
 111    ADVANCE_BATCH();
 112 }
 113
 114 const struct brw_tracked_state gen8_vs_state = {
 115    .dirty = {
 116       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 117       .brw   = BRW_NEW_CONTEXT |
 118                BRW_NEW_VERTEX_PROGRAM |
 119                BRW_NEW_VS_BINDING_TABLE |
 120                BRW_NEW_BATCH |
 121                BRW_NEW_PUSH_CONSTANT_ALLOCATION,
 122       .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
 123    },
 124    .emit = upload_vs_state,
 125 };