i965/fs: Allocate the param_size array dynamically.
[mesa.git] / src / mesa / drivers / dri / i965 / gen8_wm_depth_stencil.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "intel_batchbuffer.h"
25 #include "intel_fbo.h"
26 #include "brw_context.h"
27 #include "brw_defines.h"
28 #include "brw_state.h"
29
30 static void
31 gen8_upload_wm_depth_stencil(struct brw_context *brw)
32 {
33 struct gl_context *ctx = &brw->ctx;
34 uint32_t dw1 = 0, dw2 = 0;
35
36 /* _NEW_BUFFERS */
37 struct intel_renderbuffer *depth_irb =
38 intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
39
40 struct gl_stencil_attrib *stencil = &ctx->Stencil;
41
42 /* _NEW_STENCIL | _NEW_BUFFERS */
43 if (stencil->_Enabled) {
44 #define FUNC intel_translate_compare_func
45 #define OP intel_translate_stencil_op
46
47 dw1 |=
48 GEN8_WM_DS_STENCIL_TEST_ENABLE |
49 FUNC(stencil->Function[0]) << GEN8_WM_DS_STENCIL_FUNC_SHIFT |
50 OP(stencil->FailFunc[0]) << GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT |
51 OP(stencil->ZFailFunc[0]) << GEN8_WM_DS_Z_FAIL_OP_SHIFT |
52 OP(stencil->ZPassFunc[0]) << GEN8_WM_DS_Z_PASS_OP_SHIFT;
53
54 if (stencil->_WriteEnabled)
55 dw1 |= GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE;
56
57 dw2 |=
58 SET_FIELD(stencil->WriteMask[0] & 0xff, GEN8_WM_DS_STENCIL_WRITE_MASK) |
59 SET_FIELD(stencil->ValueMask[0] & 0xff, GEN8_WM_DS_STENCIL_TEST_MASK);
60
61 if (stencil->_TestTwoSide) {
62 const int b = stencil->_BackFace;
63
64 dw1 |=
65 GEN8_WM_DS_DOUBLE_SIDED_STENCIL_ENABLE |
66 FUNC(stencil->Function[b]) << GEN8_WM_DS_BF_STENCIL_FUNC_SHIFT |
67 OP(stencil->FailFunc[b]) << GEN8_WM_DS_BF_STENCIL_FAIL_OP_SHIFT |
68 OP(stencil->ZFailFunc[b]) << GEN8_WM_DS_BF_Z_FAIL_OP_SHIFT |
69 OP(stencil->ZPassFunc[b]) << GEN8_WM_DS_BF_Z_PASS_OP_SHIFT;
70
71 dw2 |= SET_FIELD(stencil->WriteMask[b] & 0xff,
72 GEN8_WM_DS_BF_STENCIL_WRITE_MASK) |
73 SET_FIELD(stencil->ValueMask[b] & 0xff,
74 GEN8_WM_DS_BF_STENCIL_TEST_MASK);
75 }
76 }
77
78 /* _NEW_DEPTH */
79 if (ctx->Depth.Test && depth_irb) {
80 dw1 |=
81 GEN8_WM_DS_DEPTH_TEST_ENABLE |
82 FUNC(ctx->Depth.Func) << GEN8_WM_DS_DEPTH_FUNC_SHIFT;
83
84 if (ctx->Depth.Mask)
85 dw1 |= GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE;
86 }
87
88 BEGIN_BATCH(3);
89 OUT_BATCH(_3DSTATE_WM_DEPTH_STENCIL << 16 | (3 - 2));
90 OUT_BATCH(dw1);
91 OUT_BATCH(dw2);
92 ADVANCE_BATCH();
93 }
94
95 const struct brw_tracked_state gen8_wm_depth_stencil = {
96 .dirty = {
97 .mesa = _NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL,
98 .brw = BRW_NEW_CONTEXT,
99 .cache = 0,
100 },
101 .emit = gen8_upload_wm_depth_stencil,
102 };