src/mesa/drivers/dri/i965/genX_blorp_exec.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31
  32 #include "blorp/blorp_genX_exec.h"
  33
  34 #include "brw_blorp.h"
  35
  36 static void *
  37 blorp_emit_dwords(struct blorp_batch *batch, unsigned n)
  38 {
  39    assert(batch->blorp->driver_ctx == batch->driver_batch);
  40    struct brw_context *brw = batch->driver_batch;
  41
  42    intel_batchbuffer_begin(brw, n, RENDER_RING);
  43    uint32_t *map = brw->batch.map_next;
  44    brw->batch.map_next += n;
  45    intel_batchbuffer_advance(brw);
  46    return map;
  47 }
  48
  49 static uint64_t
  50 blorp_emit_reloc(struct blorp_batch *batch,
  51                  void *location, struct blorp_address address, uint32_t delta)
  52 {
  53    assert(batch->blorp->driver_ctx == batch->driver_batch);
  54    struct brw_context *brw = batch->driver_batch;
  55
  56    uint32_t offset = (char *)location - (char *)brw->batch.map;
  57    if (brw->gen >= 8) {
  58       return intel_batchbuffer_reloc64(brw, address.buffer, offset,
  59                                        address.read_domains,
  60                                        address.write_domain,
  61                                        address.offset + delta);
  62    } else {
  63       return intel_batchbuffer_reloc(brw, address.buffer, offset,
  64                                      address.read_domains,
  65                                      address.write_domain,
  66                                      address.offset + delta);
  67    }
  68 }
  69
  70 static void
  71 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
  72                     struct blorp_address address, uint32_t delta)
  73 {
  74    assert(batch->blorp->driver_ctx == batch->driver_batch);
  75    struct brw_context *brw = batch->driver_batch;
  76    drm_intel_bo *bo = address.buffer;
  77
  78    drm_intel_bo_emit_reloc(brw->batch.bo, ss_offset,
  79                            bo, address.offset + delta,
  80                            address.read_domains, address.write_domain);
  81
  82    uint64_t reloc_val = bo->offset64 + address.offset + delta;
  83    void *reloc_ptr = (void *)brw->batch.map + ss_offset;
  84 #if GEN_GEN >= 8
  85    *(uint64_t *)reloc_ptr = reloc_val;
  86 #else
  87    *(uint32_t *)reloc_ptr = reloc_val;
  88 #endif
  89 }
  90
  91 static void *
  92 blorp_alloc_dynamic_state(struct blorp_batch *batch,
  93                           enum aub_state_struct_type type,
  94                           uint32_t size,
  95                           uint32_t alignment,
  96                           uint32_t *offset)
  97 {
  98    assert(batch->blorp->driver_ctx == batch->driver_batch);
  99    struct brw_context *brw = batch->driver_batch;
 100
 101    return brw_state_batch(brw, type, size, alignment, offset);
 102 }
 103
 104 static void
 105 blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
 106                           unsigned state_size, unsigned state_alignment,
 107                           uint32_t *bt_offset, uint32_t *surface_offsets,
 108                           void **surface_maps)
 109 {
 110    assert(batch->blorp->driver_ctx == batch->driver_batch);
 111    struct brw_context *brw = batch->driver_batch;
 112
 113    uint32_t *bt_map = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 114                                       num_entries * sizeof(uint32_t), 32,
 115                                       bt_offset);
 116
 117    for (unsigned i = 0; i < num_entries; i++) {
 118       surface_maps[i] = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 119                                         state_size, state_alignment,
 120                                         &(surface_offsets)[i]);
 121       bt_map[i] = surface_offsets[i];
 122    }
 123 }
 124
 125 static void *
 126 blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
 127                           struct blorp_address *addr)
 128 {
 129    assert(batch->blorp->driver_ctx == batch->driver_batch);
 130    struct brw_context *brw = batch->driver_batch;
 131
 132    uint32_t offset;
 133    void *data = brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
 134                                 size, 32, &offset);
 135
 136    *addr = (struct blorp_address) {
 137       .buffer = brw->batch.bo,
 138       .read_domains = I915_GEM_DOMAIN_VERTEX,
 139       .write_domain = 0,
 140       .offset = offset,
 141    };
 142
 143    return data;
 144 }
 145
 146 static void
 147 blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
 148 {
 149    assert(batch->blorp->driver_ctx == batch->driver_batch);
 150    struct brw_context *brw = batch->driver_batch;
 151
 152 #if GEN_GEN >= 7
 153    if (!(brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE)) &&
 154        brw->urb.vsize >= vs_entry_size)
 155       return;
 156
 157    brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 158
 159    gen7_upload_urb(brw, vs_entry_size, false, false);
 160 #else
 161    gen6_upload_urb(brw, vs_entry_size, false, 0);
 162 #endif
 163 }
 164
 165 void
 166 genX(blorp_exec)(struct blorp_batch *batch,
 167                  const struct blorp_params *params)
 168 {
 169    assert(batch->blorp->driver_ctx == batch->driver_batch);
 170    struct brw_context *brw = batch->driver_batch;
 171    struct gl_context *ctx = &brw->ctx;
 172    const uint32_t estimated_max_batch_usage = GEN_GEN >= 8 ? 1800 : 1500;
 173    bool check_aperture_failed_once = false;
 174
 175    /* Flush the sampler and render caches.  We definitely need to flush the
 176     * sampler cache so that we get updated contents from the render cache for
 177     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 178     * docs to flush the cache between reinterpretations of the same surface
 179     * data with different formats, which blorp does for stencil and depth
 180     * data.
 181     */
 182    brw_emit_mi_flush(brw);
 183
 184    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
 185
 186 retry:
 187    intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
 188    intel_batchbuffer_save_state(brw);
 189    drm_intel_bo *saved_bo = brw->batch.bo;
 190    uint32_t saved_used = USED_BATCH(brw->batch);
 191    uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
 192
 193 #if GEN_GEN == 6
 194    /* Emit workaround flushes when we switch from drawing to blorping. */
 195    brw_emit_post_sync_nonzero_flush(brw);
 196 #endif
 197
 198    brw_upload_state_base_address(brw);
 199
 200 #if GEN_GEN >= 8
 201    gen7_l3_state.emit(brw);
 202 #endif
 203
 204    if (brw->use_resource_streamer)
 205       gen7_disable_hw_binding_tables(brw);
 206
 207    brw_emit_depth_stall_flushes(brw);
 208
 209    blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 210       rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
 211       rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
 212    }
 213
 214    blorp_exec(batch, params);
 215
 216    /* Make sure we didn't wrap the batch unintentionally, and make sure we
 217     * reserved enough space that a wrap will never happen.
 218     */
 219    assert(brw->batch.bo == saved_bo);
 220    assert((USED_BATCH(brw->batch) - saved_used) * 4 +
 221           (saved_state_batch_offset - brw->batch.state_batch_offset) <
 222           estimated_max_batch_usage);
 223    /* Shut up compiler warnings on release build */
 224    (void)saved_bo;
 225    (void)saved_used;
 226    (void)saved_state_batch_offset;
 227
 228    /* Check if the blorp op we just did would make our batch likely to fail to
 229     * map all the BOs into the GPU at batch exec time later.  If so, flush the
 230     * batch and try again with nothing else in the batch.
 231     */
 232    if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
 233       if (!check_aperture_failed_once) {
 234          check_aperture_failed_once = true;
 235          intel_batchbuffer_reset_to_saved(brw);
 236          intel_batchbuffer_flush(brw);
 237          goto retry;
 238       } else {
 239          int ret = intel_batchbuffer_flush(brw);
 240          WARN_ONCE(ret == -ENOSPC,
 241                    "i965: blorp emit exceeded available aperture space\n");
 242       }
 243    }
 244
 245    if (unlikely(brw->always_flush_batch))
 246       intel_batchbuffer_flush(brw);
 247
 248    /* We've smashed all state compared to what the normal 3D pipeline
 249     * rendering tracks for GL.
 250     */
 251    brw->ctx.NewDriverState |= BRW_NEW_BLORP;
 252    brw->no_depth_or_stencil = false;
 253    brw->ib.type = -1;
 254
 255    /* Flush the sampler cache so any texturing from the destination is
 256     * coherent.
 257     */
 258    brw_emit_mi_flush(brw);
 259 }