src/mesa/drivers/dri/i965/genX_blorp_exec.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28 #include "intel_fbo.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_state.h"
  32
  33 #include "blorp/blorp_genX_exec.h"
  34
  35 #if GEN_GEN <= 5
  36 #include "gen4_blorp_exec.h"
  37 #endif
  38
  39 #include "brw_blorp.h"
  40
  41 static void *
  42 blorp_emit_dwords(struct blorp_batch *batch, unsigned n)
  43 {
  44    assert(batch->blorp->driver_ctx == batch->driver_batch);
  45    struct brw_context *brw = batch->driver_batch;
  46
  47    intel_batchbuffer_begin(brw, n, RENDER_RING);
  48    uint32_t *map = brw->batch.map_next;
  49    brw->batch.map_next += n;
  50    intel_batchbuffer_advance(brw);
  51    return map;
  52 }
  53
  54 static uint64_t
  55 blorp_emit_reloc(struct blorp_batch *batch,
  56                  void *location, struct blorp_address address, uint32_t delta)
  57 {
  58    assert(batch->blorp->driver_ctx == batch->driver_batch);
  59    struct brw_context *brw = batch->driver_batch;
  60    uint32_t offset;
  61
  62    if (GEN_GEN < 6 && brw_ptr_in_state_buffer(&brw->batch, location)) {
  63       offset = (char *)location - (char *)brw->batch.state_map;
  64       return brw_state_reloc(&brw->batch, offset,
  65                              address.buffer, address.offset + delta,
  66                              address.reloc_flags);
  67    }
  68
  69    assert(!brw_ptr_in_state_buffer(&brw->batch, location));
  70
  71    offset = (char *)location - (char *)brw->batch.map;
  72    return brw_batch_reloc(&brw->batch, offset,
  73                           address.buffer, address.offset + delta,
  74                           address.reloc_flags);
  75 }
  76
  77 static void
  78 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
  79                     struct blorp_address address, uint32_t delta)
  80 {
  81    assert(batch->blorp->driver_ctx == batch->driver_batch);
  82    struct brw_context *brw = batch->driver_batch;
  83    struct brw_bo *bo = address.buffer;
  84
  85    uint64_t reloc_val =
  86       brw_state_reloc(&brw->batch, ss_offset, bo, address.offset + delta,
  87                       address.reloc_flags);
  88
  89    void *reloc_ptr = (void *)brw->batch.state_map + ss_offset;
  90 #if GEN_GEN >= 8
  91    *(uint64_t *)reloc_ptr = reloc_val;
  92 #else
  93    *(uint32_t *)reloc_ptr = reloc_val;
  94 #endif
  95 }
  96
  97 static void *
  98 blorp_alloc_dynamic_state(struct blorp_batch *batch,
  99                           uint32_t size,
 100                           uint32_t alignment,
 101                           uint32_t *offset)
 102 {
 103    assert(batch->blorp->driver_ctx == batch->driver_batch);
 104    struct brw_context *brw = batch->driver_batch;
 105
 106    return brw_state_batch(brw, size, alignment, offset);
 107 }
 108
 109 static void
 110 blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
 111                           unsigned state_size, unsigned state_alignment,
 112                           uint32_t *bt_offset, uint32_t *surface_offsets,
 113                           void **surface_maps)
 114 {
 115    assert(batch->blorp->driver_ctx == batch->driver_batch);
 116    struct brw_context *brw = batch->driver_batch;
 117
 118    uint32_t *bt_map = brw_state_batch(brw,
 119                                       num_entries * sizeof(uint32_t), 32,
 120                                       bt_offset);
 121
 122    for (unsigned i = 0; i < num_entries; i++) {
 123       surface_maps[i] = brw_state_batch(brw,
 124                                         state_size, state_alignment,
 125                                         &(surface_offsets)[i]);
 126       bt_map[i] = surface_offsets[i];
 127    }
 128 }
 129
 130 static void *
 131 blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
 132                           struct blorp_address *addr)
 133 {
 134    assert(batch->blorp->driver_ctx == batch->driver_batch);
 135    struct brw_context *brw = batch->driver_batch;
 136
 137    /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
 138     *
 139     *    "The VF cache needs to be invalidated before binding and then using
 140     *    Vertex Buffers that overlap with any previously bound Vertex Buffer
 141     *    (at a 64B granularity) since the last invalidation.  A VF cache
 142     *    invalidate is performed by setting the "VF Cache Invalidation Enable"
 143     *    bit in PIPE_CONTROL."
 144     *
 145     * This restriction first appears in the Skylake PRM but the internal docs
 146     * also list it as being an issue on Broadwell.  In order to avoid this
 147     * problem, we align all vertex buffer allocations to 64 bytes.
 148     */
 149    uint32_t offset;
 150    void *data = brw_state_batch(brw, size, 64, &offset);
 151
 152    *addr = (struct blorp_address) {
 153       .buffer = brw->batch.state_bo,
 154       .offset = offset,
 155
 156 #if GEN_GEN == 10
 157       .mocs = CNL_MOCS_WB,
 158 #elif GEN_GEN == 9
 159       .mocs = SKL_MOCS_WB,
 160 #elif GEN_GEN == 8
 161       .mocs = BDW_MOCS_WB,
 162 #elif GEN_GEN == 7
 163       .mocs = GEN7_MOCS_L3,
 164 #endif
 165    };
 166
 167    return data;
 168 }
 169
 170 #if GEN_GEN >= 8
 171 static struct blorp_address
 172 blorp_get_workaround_page(struct blorp_batch *batch)
 173 {
 174    assert(batch->blorp->driver_ctx == batch->driver_batch);
 175    struct brw_context *brw = batch->driver_batch;
 176
 177    return (struct blorp_address) {
 178       .buffer = brw->workaround_bo,
 179    };
 180 }
 181 #endif
 182
 183 static void
 184 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
 185 {
 186    /* All allocated states come from the batch which we will flush before we
 187     * submit it.  There's nothing for us to do here.
 188     */
 189 }
 190
 191 static void
 192 blorp_emit_urb_config(struct blorp_batch *batch,
 193                       unsigned vs_entry_size, unsigned sf_entry_size)
 194 {
 195    assert(batch->blorp->driver_ctx == batch->driver_batch);
 196    struct brw_context *brw = batch->driver_batch;
 197
 198 #if GEN_GEN >= 7
 199    if (brw->urb.vsize >= vs_entry_size)
 200       return;
 201
 202    gen7_upload_urb(brw, vs_entry_size, false, false);
 203 #elif GEN_GEN == 6
 204    gen6_upload_urb(brw, vs_entry_size, false, 0);
 205 #else
 206    /* We calculate it now and emit later. */
 207    brw_calculate_urb_fence(brw, 0, vs_entry_size, sf_entry_size);
 208 #endif
 209 }
 210
 211 void
 212 genX(blorp_exec)(struct blorp_batch *batch,
 213                  const struct blorp_params *params)
 214 {
 215    assert(batch->blorp->driver_ctx == batch->driver_batch);
 216    struct brw_context *brw = batch->driver_batch;
 217    struct gl_context *ctx = &brw->ctx;
 218    bool check_aperture_failed_once = false;
 219
 220    /* Flush the sampler and render caches.  We definitely need to flush the
 221     * sampler cache so that we get updated contents from the render cache for
 222     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 223     * docs to flush the cache between reinterpretations of the same surface
 224     * data with different formats, which blorp does for stencil and depth
 225     * data.
 226     */
 227    if (params->src.enabled)
 228       brw_cache_flush_for_read(brw, params->src.addr.buffer);
 229    if (params->dst.enabled)
 230       brw_cache_flush_for_render(brw, params->dst.addr.buffer);
 231    if (params->depth.enabled)
 232       brw_cache_flush_for_depth(brw, params->depth.addr.buffer);
 233    if (params->stencil.enabled)
 234       brw_cache_flush_for_depth(brw, params->stencil.addr.buffer);
 235
 236    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
 237
 238 retry:
 239    intel_batchbuffer_require_space(brw, 1400, RENDER_RING);
 240    brw_require_statebuffer_space(brw, 600);
 241    intel_batchbuffer_save_state(brw);
 242    brw->batch.no_wrap = true;
 243
 244 #if GEN_GEN == 6
 245    /* Emit workaround flushes when we switch from drawing to blorping. */
 246    brw_emit_post_sync_nonzero_flush(brw);
 247 #endif
 248
 249    brw_upload_state_base_address(brw);
 250
 251 #if GEN_GEN >= 8
 252    gen7_l3_state.emit(brw);
 253 #endif
 254
 255 #if GEN_GEN >= 6
 256    brw_emit_depth_stall_flushes(brw);
 257 #endif
 258
 259 #if GEN_GEN == 8
 260    gen8_write_pma_stall_bits(brw, 0);
 261 #endif
 262
 263    blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 264       rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
 265       rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
 266    }
 267
 268    blorp_exec(batch, params);
 269
 270    brw->batch.no_wrap = false;
 271
 272    /* Check if the blorp op we just did would make our batch likely to fail to
 273     * map all the BOs into the GPU at batch exec time later.  If so, flush the
 274     * batch and try again with nothing else in the batch.
 275     */
 276    if (!brw_batch_has_aperture_space(brw, 0)) {
 277       if (!check_aperture_failed_once) {
 278          check_aperture_failed_once = true;
 279          intel_batchbuffer_reset_to_saved(brw);
 280          intel_batchbuffer_flush(brw);
 281          goto retry;
 282       } else {
 283          int ret = intel_batchbuffer_flush(brw);
 284          WARN_ONCE(ret == -ENOSPC,
 285                    "i965: blorp emit exceeded available aperture space\n");
 286       }
 287    }
 288
 289    if (unlikely(brw->always_flush_batch))
 290       intel_batchbuffer_flush(brw);
 291
 292    /* We've smashed all state compared to what the normal 3D pipeline
 293     * rendering tracks for GL.
 294     */
 295    brw->ctx.NewDriverState |= BRW_NEW_BLORP;
 296    brw->no_depth_or_stencil = !params->depth.enabled &&
 297                               !params->stencil.enabled;
 298    brw->ib.index_size = -1;
 299
 300    if (params->dst.enabled)
 301       brw_render_cache_add_bo(brw, params->dst.addr.buffer);
 302    if (params->depth.enabled)
 303       brw_depth_cache_add_bo(brw, params->depth.addr.buffer);
 304    if (params->stencil.enabled)
 305       brw_depth_cache_add_bo(brw, params->stencil.addr.buffer);
 306 }