2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_mipmap_tree.h"
29 #include "brw_context.h"
30 #include "brw_state.h"
32 #include "blorp_priv.h"
34 #include "genxml/gen_macros.h"
37 blorp_emit_dwords(struct brw_context
*brw
, unsigned n
)
39 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
40 uint32_t *map
= brw
->batch
.map_next
;
41 brw
->batch
.map_next
+= n
;
42 intel_batchbuffer_advance(brw
);
46 struct blorp_address
{
48 uint32_t read_domains
;
49 uint32_t write_domain
;
54 blorp_emit_reloc(struct brw_context
*brw
, void *location
,
55 struct blorp_address address
, uint32_t delta
)
57 uint32_t offset
= (char *)location
- (char *)brw
->batch
.map
;
59 return intel_batchbuffer_reloc64(brw
, address
.buffer
, offset
,
62 address
.offset
+ delta
);
64 return intel_batchbuffer_reloc(brw
, address
.buffer
, offset
,
67 address
.offset
+ delta
);
72 blorp_alloc_dynamic_state(struct blorp_context
*blorp
,
73 enum aub_state_struct_type type
,
78 struct brw_context
*brw
= blorp
->driver_ctx
;
79 return brw_state_batch(brw
, type
, size
, alignment
, offset
);
83 blorp_alloc_vertex_buffer(struct blorp_context
*blorp
, uint32_t size
,
84 struct blorp_address
*addr
)
86 struct brw_context
*brw
= blorp
->driver_ctx
;
89 void *data
= brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
92 *addr
= (struct blorp_address
) {
93 .buffer
= brw
->batch
.bo
,
94 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
103 blorp_emit_urb_config(struct brw_context
*brw
, unsigned vs_entry_size
)
106 if (!(brw
->ctx
.NewDriverState
& (BRW_NEW_CONTEXT
| BRW_NEW_URB_SIZE
)) &&
107 brw
->urb
.vsize
>= vs_entry_size
)
110 brw
->ctx
.NewDriverState
|= BRW_NEW_URB_SIZE
;
112 gen7_upload_urb(brw
, vs_entry_size
, false, false);
114 gen6_upload_urb(brw
, vs_entry_size
, false, 0);
119 blorp_emit_3dstate_multisample(struct brw_context
*brw
, unsigned samples
)
122 gen8_emit_3dstate_multisample(brw
, samples
);
124 gen6_emit_3dstate_multisample(brw
, samples
);
128 #define __gen_address_type struct blorp_address
129 #define __gen_user_data struct brw_context
132 __gen_combine_address(struct brw_context
*brw
, void *location
,
133 struct blorp_address address
, uint32_t delta
)
135 if (address
.buffer
== NULL
) {
136 return address
.offset
+ delta
;
138 return blorp_emit_reloc(brw
, location
, address
, delta
);
142 #include "genxml/genX_pack.h"
144 #define _blorp_cmd_length(cmd) cmd ## _length
145 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
146 #define _blorp_cmd_header(cmd) cmd ## _header
147 #define _blorp_cmd_pack(cmd) cmd ## _pack
149 #define blorp_emit(brw, cmd, name) \
150 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
151 *_dst = blorp_emit_dwords(brw, _blorp_cmd_length(cmd)); \
152 __builtin_expect(_dst != NULL, 1); \
153 _blorp_cmd_pack(cmd)(brw, (void *)_dst, &name), \
156 #define blorp_emitn(batch, cmd, n) ({ \
157 uint32_t *_dw = blorp_emit_dwords(batch, n); \
158 struct cmd template = { \
159 _blorp_cmd_header(cmd), \
160 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
162 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
163 _dw + 1; /* Array starts at dw[1] */ \
166 /* Once vertex fetcher has written full VUE entries with complete
167 * header the space requirement is as follows per vertex (in bytes):
169 * Header Position Program constants
170 * +--------+------------+-------------------+
171 * | 16 | 16 | n x 16 |
172 * +--------+------------+-------------------+
174 * where 'n' stands for number of varying inputs expressed as vec4s.
176 * The URB size is in turn expressed in 64 bytes (512 bits).
178 static inline unsigned
179 gen7_blorp_get_vs_entry_size(const struct brw_blorp_params
*params
)
181 const unsigned num_varyings
=
182 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
183 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
185 return DIV_ROUND_UP(total_needed
, 64);
194 * Assign the entire URB to the VS. Even though the VS disabled, URB space
195 * is still needed because the clipper loads the VUE's from the URB. From
196 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
197 * Dword 1.15:0 "VS Number of URB Entries":
198 * This field is always used (even if VS Function Enable is DISABLED).
200 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
201 * safely ignore it because this batch contains only one draw call.
202 * Because of URB corruption caused by allocating a previous GS unit
203 * URB entry to the VS unit, software is required to send a “GS NULL
204 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
205 * plus a dummy DRAW call before any case where VS will be taking over
208 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
209 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
211 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
212 * programmed in order for the programming of this state to be
216 emit_urb_config(struct brw_context
*brw
,
217 const struct brw_blorp_params
*params
)
219 blorp_emit_urb_config(brw
, gen7_blorp_get_vs_entry_size(params
));
223 blorp_emit_vertex_data(struct brw_context
*brw
,
224 const struct brw_blorp_params
*params
,
225 struct blorp_address
*addr
,
228 const float vertices
[] = {
229 /* v0 */ (float)params
->x0
, (float)params
->y1
,
230 /* v1 */ (float)params
->x1
, (float)params
->y1
,
231 /* v2 */ (float)params
->x0
, (float)params
->y0
,
234 void *data
= blorp_alloc_vertex_buffer(&brw
->blorp
, sizeof(vertices
), addr
);
235 memcpy(data
, vertices
, sizeof(vertices
));
236 *size
= sizeof(vertices
);
240 blorp_emit_input_varying_data(struct brw_context
*brw
,
241 const struct brw_blorp_params
*params
,
242 struct blorp_address
*addr
,
245 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
246 const unsigned max_num_varyings
=
247 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
248 const unsigned num_varyings
= params
->wm_prog_data
->num_varying_inputs
;
250 *size
= num_varyings
* vec4_size_in_bytes
;
252 const float *const inputs_src
= (const float *)¶ms
->wm_inputs
;
253 float *inputs
= blorp_alloc_vertex_buffer(&brw
->blorp
, *size
, addr
);
255 /* Walk over the attribute slots, determine if the attribute is used by
256 * the program and when necessary copy the values from the input storage to
257 * the vertex data buffer.
259 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
260 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
262 if (!(params
->wm_prog_data
->inputs_read
& BITFIELD64_BIT(attr
)))
265 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
272 blorp_emit_vertex_buffers(struct brw_context
*brw
,
273 const struct brw_blorp_params
*params
)
275 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
276 memset(vb
, 0, sizeof(vb
));
278 unsigned num_buffers
= 1;
281 blorp_emit_vertex_data(brw
, params
, &vb
[0].BufferStartingAddress
, &size
);
282 vb
[0].VertexBufferIndex
= 0;
283 vb
[0].BufferPitch
= 2 * sizeof(float);
284 vb
[0].VertexBufferMOCS
= brw
->blorp
.mocs
.vb
;
286 vb
[0].AddressModifyEnable
= true;
289 vb
[0].BufferSize
= size
;
291 vb
[0].BufferAccessType
= VERTEXDATA
;
292 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
293 vb
[0].EndAddress
.offset
+= size
- 1;
296 if (params
->wm_prog_data
&& params
->wm_prog_data
->num_varying_inputs
) {
297 blorp_emit_input_varying_data(brw
, params
,
298 &vb
[1].BufferStartingAddress
, &size
);
299 vb
[1].VertexBufferIndex
= 1;
300 vb
[1].BufferPitch
= 0;
301 vb
[1].VertexBufferMOCS
= brw
->blorp
.mocs
.vb
;
303 vb
[1].AddressModifyEnable
= true;
306 vb
[1].BufferSize
= size
;
308 vb
[1].BufferAccessType
= INSTANCEDATA
;
309 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
310 vb
[1].EndAddress
.offset
+= size
- 1;
315 const unsigned num_dwords
=
316 1 + GENX(VERTEX_BUFFER_STATE_length
) * num_buffers
;
317 uint32_t *dw
= blorp_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
319 for (unsigned i
= 0; i
< num_buffers
; i
++) {
320 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &vb
[i
]);
321 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
326 blorp_emit_vertex_elements(struct brw_context
*brw
,
327 const struct brw_blorp_params
*params
)
329 const unsigned num_varyings
=
330 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
331 const unsigned num_elements
= 2 + num_varyings
;
333 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
334 memset(ve
, 0, num_elements
* sizeof(*ve
));
336 /* Setup VBO for the rectangle primitive..
338 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
339 * vertices. The vertices reside in screen space with DirectX
340 * coordinates (that is, (0, 0) is the upper left corner).
347 * Since the VS is disabled, the clipper loads each VUE directly from
348 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
349 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
350 * dw0: Reserved, MBZ.
351 * dw1: Render Target Array Index. The HiZ op does not use indexed
352 * vertices, so set the dword to 0.
353 * dw2: Viewport Index. The HiZ op disables viewport mapping and
354 * scissoring, so set the dword to 0.
355 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
356 * so set the dword to 0.
357 * dw4: Vertex Position X.
358 * dw5: Vertex Position Y.
359 * dw6: Vertex Position Z.
360 * dw7: Vertex Position W.
362 * dw8: Flat vertex input 0
363 * dw9: Flat vertex input 1
365 * dwn: Flat vertex input n - 8
367 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
368 * "Vertex URB Entry (VUE) Formats".
370 * Only vertex position X and Y are going to be variable, Z is fixed to
371 * zero and W to one. Header words dw0-3 are all zero. There is no need to
372 * include the fixed values in the vertex buffer. Vertex fetcher can be
373 * instructed to fill vertex elements with constant values of one and zero
374 * instead of reading them from the buffer.
375 * Flat inputs are program constants that are not interpolated. Moreover
376 * their values will be the same between vertices.
378 * See the vertex element setup below.
380 ve
[0].VertexBufferIndex
= 0;
382 ve
[0].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
383 ve
[0].SourceElementOffset
= 0;
384 ve
[0].Component0Control
= VFCOMP_STORE_0
;
385 ve
[0].Component1Control
= VFCOMP_STORE_0
;
386 ve
[0].Component2Control
= VFCOMP_STORE_0
;
387 ve
[0].Component3Control
= VFCOMP_STORE_0
;
389 ve
[1].VertexBufferIndex
= 0;
391 ve
[1].SourceElementFormat
= ISL_FORMAT_R32G32_FLOAT
;
392 ve
[1].SourceElementOffset
= 0;
393 ve
[1].Component0Control
= VFCOMP_STORE_SRC
;
394 ve
[1].Component1Control
= VFCOMP_STORE_SRC
;
395 ve
[1].Component2Control
= VFCOMP_STORE_0
;
396 ve
[1].Component3Control
= VFCOMP_STORE_1_FP
;
398 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
399 ve
[i
+ 2].VertexBufferIndex
= 1;
400 ve
[i
+ 2].Valid
= true;
401 ve
[i
+ 2].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
402 ve
[i
+ 2].SourceElementOffset
= i
* 4 * sizeof(float);
403 ve
[i
+ 2].Component0Control
= VFCOMP_STORE_SRC
;
404 ve
[i
+ 2].Component1Control
= VFCOMP_STORE_SRC
;
405 ve
[i
+ 2].Component2Control
= VFCOMP_STORE_SRC
;
406 ve
[i
+ 2].Component3Control
= VFCOMP_STORE_SRC
;
409 const unsigned num_dwords
=
410 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
411 uint32_t *dw
= blorp_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
413 for (unsigned i
= 0; i
< num_elements
; i
++) {
414 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &ve
[i
]);
415 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
419 blorp_emit(brw
, GENX(3DSTATE_VF_SGVS
), sgvs
);
421 for (unsigned i
= 0; i
< num_elements
; i
++) {
422 blorp_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
423 vf
.VertexElementIndex
= i
;
424 vf
.InstancingEnable
= false;
428 blorp_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
429 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
435 blorp_emit_sf_config(struct brw_context
*brw
,
436 const struct brw_blorp_params
*params
)
438 const struct brw_blorp_prog_data
*prog_data
= params
->wm_prog_data
;
442 * Disable ViewportTransformEnable (dw2.1)
444 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
445 * Primitives Overview":
446 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
447 * use of screen- space coordinates).
449 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
450 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
452 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
453 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
454 * SOLID: Any triangle or rectangle object found to be front-facing
455 * is rendered as a solid object. This setting is required when
456 * (rendering rectangle (RECTLIST) objects.
461 blorp_emit(brw
, GENX(3DSTATE_SF
), sf
);
463 blorp_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
464 raster
.CullMode
= CULLMODE_NONE
;
467 blorp_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
468 sbe
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
469 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
470 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
471 sbe
.ForceVertexURBEntryReadLength
= true;
472 sbe
.ForceVertexURBEntryReadOffset
= true;
473 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
476 for (unsigned i
= 0; i
< 32; i
++)
477 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
483 blorp_emit(brw
, GENX(3DSTATE_SF
), sf
) {
484 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
485 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
487 sf
.MultisampleRasterizationMode
= params
->dst
.surf
.samples
> 1 ?
488 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
491 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
495 blorp_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
496 sbe
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
498 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
499 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
500 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
502 sbe
.NumberofSFOutputAttributes
= 0;
503 sbe
.VertexURBEntryReadLength
= 1;
507 #else /* GEN_GEN <= 6 */
509 blorp_emit(brw
, GENX(3DSTATE_SF
), sf
) {
510 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
511 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
513 sf
.MultisampleRasterizationMode
= params
->dst
.surf
.samples
> 1 ?
514 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
516 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
518 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
519 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
520 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
522 sf
.NumberofSFOutputAttributes
= 0;
523 sf
.VertexURBEntryReadLength
= 1;
531 blorp_emit_ps_config(struct brw_context
*brw
,
532 const struct brw_blorp_params
*params
)
534 const struct brw_blorp_prog_data
*prog_data
= params
->wm_prog_data
;
536 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
537 * nonzero to prevent the GPU from hanging. While the documentation doesn't
538 * mention this explicitly, it notes that the valid range for the field is
539 * [1,39] = [2,40] threads, which excludes zero.
541 * To be safe (and to minimize extraneous code) we go ahead and fully
542 * configure the WM state whether or not there is a WM program.
547 blorp_emit(brw
, GENX(3DSTATE_WM
), wm
);
549 blorp_emit(brw
, GENX(3DSTATE_PS
), ps
) {
550 if (params
->src
.bo
) {
551 ps
.SamplerCount
= 1; /* Up to 4 samplers */
552 ps
.BindingTableEntryCount
= 2;
554 ps
.BindingTableEntryCount
= 1;
557 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
558 prog_data
->first_curbe_grf_0
;
559 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
560 prog_data
->first_curbe_grf_2
;
562 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
563 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
565 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
566 ps
.KernelStartPointer2
=
567 params
->wm_prog_kernel
+ prog_data
->ksp_offset_2
;
569 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
570 * it implicitly scales for different GT levels (which have some # of
573 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
576 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
578 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
580 switch (params
->fast_clear_op
) {
582 case (1 << 6): /* GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE */
583 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
585 case (3 << 6): /* GEN9_PS_RENDER_TARGET_RESOLVE_FULL */
586 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
589 case (1 << 6): /* GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE */
590 ps
.RenderTargetResolveEnable
= true;
593 case (1 << 8): /* GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE */
594 ps
.RenderTargetFastClearEnable
= true;
599 blorp_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
600 psx
.PixelShaderValid
= true;
603 psx
.PixelShaderKillsPixel
= true;
605 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
607 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
608 psx
.PixelShaderIsPerSample
= true;
613 blorp_emit(brw
, GENX(3DSTATE_WM
), wm
) {
614 switch (params
->hiz_op
) {
615 case GEN6_HIZ_OP_DEPTH_CLEAR
:
616 wm
.DepthBufferClear
= true;
618 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
619 wm
.DepthBufferResolveEnable
= true;
621 case GEN6_HIZ_OP_HIZ_RESOLVE
:
622 wm
.HierarchicalDepthBufferResolveEnable
= true;
624 case GEN6_HIZ_OP_NONE
:
627 unreachable("not reached");
631 wm
.ThreadDispatchEnable
= true;
634 wm
.PixelShaderKillPixel
= true;
636 if (params
->dst
.surf
.samples
> 1) {
637 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
638 wm
.MultisampleDispatchMode
=
639 (prog_data
&& prog_data
->persample_msaa_dispatch
) ?
640 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
642 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
643 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
647 blorp_emit(brw
, GENX(3DSTATE_PS
), ps
) {
648 ps
.MaximumNumberofThreads
= brw
->max_wm_threads
- 1;
655 ps
.DispatchGRFStartRegisterforConstantSetupData0
=
656 prog_data
->first_curbe_grf_0
;
657 ps
.DispatchGRFStartRegisterforConstantSetupData2
=
658 prog_data
->first_curbe_grf_2
;
660 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
661 ps
.KernelStartPointer2
=
662 params
->wm_prog_kernel
+ prog_data
->ksp_offset_2
;
664 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
665 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
667 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
669 /* Gen7 hardware gets angry if we don't enable at least one dispatch
670 * mode, so just enable 16-pixel dispatch if we don't have a program.
672 ps
._16PixelDispatchEnable
= true;
676 ps
.SamplerCount
= 1; /* Up to 4 samplers */
678 switch (params
->fast_clear_op
) {
679 case (1 << 6): /* GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE */
680 ps
.RenderTargetResolveEnable
= true;
682 case (1 << 8): /* GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE */
683 ps
.RenderTargetFastClearEnable
= true;
688 #else /* GEN_GEN <= 6 */
690 blorp_emit(brw
, GENX(3DSTATE_WM
), wm
) {
691 wm
.MaximumNumberofThreads
= brw
->max_wm_threads
- 1;
693 switch (params
->hiz_op
) {
694 case GEN6_HIZ_OP_DEPTH_CLEAR
:
695 wm
.DepthBufferClear
= true;
697 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
698 wm
.DepthBufferResolveEnable
= true;
700 case GEN6_HIZ_OP_HIZ_RESOLVE
:
701 wm
.HierarchicalDepthBufferResolveEnable
= true;
703 case GEN6_HIZ_OP_NONE
:
706 unreachable("not reached");
710 wm
.ThreadDispatchEnable
= true;
712 wm
.DispatchGRFStartRegisterforConstantSetupData0
=
713 prog_data
->first_curbe_grf_0
;
714 wm
.DispatchGRFStartRegisterforConstantSetupData2
=
715 prog_data
->first_curbe_grf_2
;
717 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
718 wm
.KernelStartPointer2
=
719 params
->wm_prog_kernel
+ prog_data
->ksp_offset_2
;
721 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
722 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
724 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
727 if (params
->src
.bo
) {
728 wm
.SamplerCount
= 1; /* Up to 4 samplers */
729 wm
.PixelShaderKillPixel
= true; /* TODO: temporarily smash on */
732 if (params
->dst
.surf
.samples
> 1) {
733 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
734 wm
.MultisampleDispatchMode
=
735 (prog_data
&& prog_data
->persample_msaa_dispatch
) ?
736 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
738 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
739 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
748 blorp_emit_depth_stencil_config(struct brw_context
*brw
,
749 const struct brw_blorp_params
*params
)
751 brw_emit_depth_stall_flushes(brw
);
754 const uint32_t mocs
= 1; /* GEN7_MOCS_L3 */
756 const uint32_t mocs
= 0;
759 blorp_emit(brw
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
760 switch (params
->depth
.surf
.dim
) {
761 case ISL_SURF_DIM_1D
:
762 db
.SurfaceType
= SURFTYPE_1D
;
764 case ISL_SURF_DIM_2D
:
765 db
.SurfaceType
= SURFTYPE_2D
;
767 case ISL_SURF_DIM_3D
:
768 db
.SurfaceType
= SURFTYPE_3D
;
772 db
.SurfaceFormat
= params
->depth_format
;
775 db
.DepthWriteEnable
= true;
779 db
.TiledSurface
= true;
780 db
.TileWalk
= TILEWALK_YMAJOR
;
781 db
.MIPMapLayoutMode
= MIPLAYOUT_BELOW
;
782 db
.SeparateStencilBufferEnable
= true;
785 db
.HierarchicalDepthBufferEnable
= true;
787 db
.Width
= params
->depth
.surf
.logical_level0_px
.width
- 1;
788 db
.Height
= params
->depth
.surf
.logical_level0_px
.height
- 1;
789 db
.RenderTargetViewExtent
= db
.Depth
=
790 MAX2(params
->depth
.surf
.logical_level0_px
.depth
,
791 params
->depth
.surf
.logical_level0_px
.array_len
) - 1;
793 db
.LOD
= params
->depth
.view
.base_level
;
794 db
.MinimumArrayElement
= params
->depth
.view
.base_array_layer
;
796 db
.SurfacePitch
= params
->depth
.surf
.row_pitch
- 1;
797 db
.SurfaceBaseAddress
= (struct blorp_address
) {
798 .buffer
= params
->depth
.bo
,
799 .read_domains
= I915_GEM_DOMAIN_RENDER
,
800 .write_domain
= I915_GEM_DOMAIN_RENDER
,
801 .offset
= params
->depth
.offset
,
803 db
.DepthBufferMOCS
= mocs
;
806 blorp_emit(brw
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hiz
) {
807 hiz
.SurfacePitch
= params
->depth
.aux_surf
.row_pitch
- 1;
808 hiz
.SurfaceBaseAddress
= (struct blorp_address
) {
809 .buffer
= params
->depth
.aux_bo
,
810 .read_domains
= I915_GEM_DOMAIN_RENDER
,
811 .write_domain
= I915_GEM_DOMAIN_RENDER
,
812 .offset
= params
->depth
.aux_offset
,
814 hiz
.HierarchicalDepthBufferMOCS
= mocs
;
817 blorp_emit(brw
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
821 blorp_emit_blend_state(struct brw_context
*brw
,
822 const struct brw_blorp_params
*params
)
824 struct GENX(BLEND_STATE
) blend
;
825 memset(&blend
, 0, sizeof(blend
));
827 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
828 blend
.Entry
[i
].PreBlendColorClampEnable
= true;
829 blend
.Entry
[i
].PostBlendColorClampEnable
= true;
830 blend
.Entry
[i
].ColorClampRange
= COLORCLAMP_RTFORMAT
;
832 blend
.Entry
[i
].WriteDisableRed
= params
->color_write_disable
[0];
833 blend
.Entry
[i
].WriteDisableGreen
= params
->color_write_disable
[1];
834 blend
.Entry
[i
].WriteDisableBlue
= params
->color_write_disable
[2];
835 blend
.Entry
[i
].WriteDisableAlpha
= params
->color_write_disable
[3];
839 void *state
= blorp_alloc_dynamic_state(&brw
->blorp
,
840 AUB_TRACE_BLEND_STATE
,
841 GENX(BLEND_STATE_length
) * 4,
843 GENX(BLEND_STATE_pack
)(NULL
, state
, &blend
);
846 blorp_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
847 sp
.BlendStatePointer
= offset
;
849 sp
.BlendStatePointerValid
= true;
855 blorp_emit(brw
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
856 ps_blend
.HasWriteableRT
= true;
864 blorp_emit_color_calc_state(struct brw_context
*brw
,
865 const struct brw_blorp_params
*params
)
868 void *state
= blorp_alloc_dynamic_state(&brw
->blorp
,
870 GENX(COLOR_CALC_STATE_length
) * 4,
872 memset(state
, 0, GENX(COLOR_CALC_STATE_length
) * 4);
875 blorp_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
876 sp
.ColorCalcStatePointer
= offset
;
878 sp
.ColorCalcStatePointerValid
= true;
887 blorp_emit_depth_stencil_state(struct brw_context
*brw
,
888 const struct brw_blorp_params
*params
)
892 /* On gen8+, DEPTH_STENCIL state is simply an instruction */
893 blorp_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), ds
);
896 #else /* GEN_GEN <= 7 */
898 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
899 * - 7.5.3.1 Depth Buffer Clear
900 * - 7.5.3.2 Depth Buffer Resolve
901 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
903 struct GENX(DEPTH_STENCIL_STATE
) ds
= {
904 .DepthBufferWriteEnable
= true,
907 if (params
->hiz_op
== GEN6_HIZ_OP_DEPTH_RESOLVE
) {
908 ds
.DepthTestEnable
= true;
909 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
913 void *state
= blorp_alloc_dynamic_state(&brw
->blorp
,
914 AUB_TRACE_DEPTH_STENCIL_STATE
,
915 GENX(DEPTH_STENCIL_STATE_length
) * 4,
917 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
920 blorp_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
921 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
931 blorp_emit_surface_states(struct brw_context
*brw
,
932 const struct brw_blorp_params
*params
)
934 uint32_t bind_offset
;
936 brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
937 sizeof(uint32_t) * BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
,
938 32, /* alignment */ &bind_offset
);
940 bind
[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
] =
941 brw_blorp_emit_surface_state(brw
, ¶ms
->dst
,
942 I915_GEM_DOMAIN_RENDER
,
943 I915_GEM_DOMAIN_RENDER
, true);
944 if (params
->src
.bo
) {
945 bind
[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
] =
946 brw_blorp_emit_surface_state(brw
, ¶ms
->src
,
947 I915_GEM_DOMAIN_SAMPLER
, 0, false);
951 blorp_emit(brw
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
952 bt
.PointertoPSBindingTable
= bind_offset
;
955 blorp_emit(brw
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
956 bt
.PSBindingTableChange
= true;
957 bt
.PointertoPSBindingTable
= bind_offset
;
963 blorp_emit_sampler_state(struct brw_context
*brw
,
964 const struct brw_blorp_params
*params
)
966 struct GENX(SAMPLER_STATE
) sampler
= {
967 .MipModeFilter
= MIPFILTER_NONE
,
968 .MagModeFilter
= MAPFILTER_LINEAR
,
969 .MinModeFilter
= MAPFILTER_LINEAR
,
972 .TCXAddressControlMode
= TCM_CLAMP
,
973 .TCYAddressControlMode
= TCM_CLAMP
,
974 .TCZAddressControlMode
= TCM_CLAMP
,
975 .MaximumAnisotropy
= RATIO21
,
976 .RAddressMinFilterRoundingEnable
= true,
977 .RAddressMagFilterRoundingEnable
= true,
978 .VAddressMinFilterRoundingEnable
= true,
979 .VAddressMagFilterRoundingEnable
= true,
980 .UAddressMinFilterRoundingEnable
= true,
981 .UAddressMagFilterRoundingEnable
= true,
982 .NonnormalizedCoordinateEnable
= true,
986 void *state
= blorp_alloc_dynamic_state(&brw
->blorp
,
987 AUB_TRACE_SAMPLER_STATE
,
988 GENX(SAMPLER_STATE_length
) * 4,
990 GENX(SAMPLER_STATE_pack
)(NULL
, state
, &sampler
);
993 blorp_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
994 ssp
.PointertoPSSamplerState
= offset
;
997 blorp_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
998 ssp
.VSSamplerStateChange
= true;
999 ssp
.GSSamplerStateChange
= true;
1000 ssp
.PSSamplerStateChange
= true;
1001 ssp
.PointertoPSSamplerState
= offset
;
1006 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
1008 blorp_emit_viewport_state(struct brw_context
*brw
,
1009 const struct brw_blorp_params
*params
)
1011 uint32_t cc_vp_offset
;
1013 void *state
= blorp_alloc_dynamic_state(&brw
->blorp
,
1014 AUB_TRACE_CC_VP_STATE
,
1015 GENX(CC_VIEWPORT_length
) * 4, 32,
1018 GENX(CC_VIEWPORT_pack
)(brw
, state
,
1019 &(struct GENX(CC_VIEWPORT
)) {
1020 .MinimumDepth
= 0.0,
1021 .MaximumDepth
= 1.0,
1025 blorp_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
1026 vsp
.CCViewportPointer
= cc_vp_offset
;
1029 blorp_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
1030 vsp
.CCViewportStateChange
= true;
1031 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1038 * \brief Execute a blit or render pass operation.
1040 * To execute the operation, this function manually constructs and emits a
1041 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1042 * constructing and after emitting the batch.
1044 * This function alters no GL state.
1047 genX(blorp_exec
)(struct brw_context
*brw
,
1048 const struct brw_blorp_params
*params
)
1050 uint32_t blend_state_offset
= 0;
1051 uint32_t color_calc_state_offset
= 0;
1052 uint32_t depth_stencil_state_offset
;
1055 /* Emit workaround flushes when we switch from drawing to blorping. */
1056 brw_emit_post_sync_nonzero_flush(brw
);
1059 brw_upload_state_base_address(brw
);
1062 gen7_l3_state
.emit(brw
);
1065 blorp_emit_vertex_buffers(brw
, params
);
1066 blorp_emit_vertex_elements(brw
, params
);
1068 emit_urb_config(brw
, params
);
1070 if (params
->wm_prog_data
) {
1071 blend_state_offset
= blorp_emit_blend_state(brw
, params
);
1072 color_calc_state_offset
= blorp_emit_color_calc_state(brw
, params
);
1074 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(brw
, params
);
1077 /* 3DSTATE_CC_STATE_POINTERS
1079 * The pointer offsets are relative to
1080 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1082 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1084 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1085 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1086 * one CC_STATE_POINTERS packet so we have to emit that here.
1088 blorp_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1089 cc
.BLEND_STATEChange
= true;
1090 cc
.COLOR_CALC_STATEChange
= true;
1091 cc
.DEPTH_STENCIL_STATEChange
= true;
1092 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1093 cc
.PointertoCOLOR_CALC_STATE
= color_calc_state_offset
;
1094 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1097 (void)blend_state_offset
;
1098 (void)color_calc_state_offset
;
1099 (void)depth_stencil_state_offset
;
1102 blorp_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1104 blorp_emit(brw
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1105 blorp_emit(brw
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1107 blorp_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1108 blorp_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1110 if (brw
->use_resource_streamer
)
1111 gen7_disable_hw_binding_tables(brw
);
1113 if (params
->wm_prog_data
)
1114 blorp_emit_surface_states(brw
, params
);
1117 blorp_emit_sampler_state(brw
, params
);
1119 blorp_emit_3dstate_multisample(brw
, params
->dst
.surf
.samples
);
1121 blorp_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1122 mask
.SampleMask
= (1 << params
->dst
.surf
.samples
) - 1;
1125 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1126 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1128 * [DevSNB] A pipeline flush must be programmed prior to a
1129 * 3DSTATE_VS command that causes the VS Function Enable to
1130 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1131 * command with CS stall bit set and a post sync operation.
1133 * We've already done one at the start of the BLORP operation.
1135 blorp_emit(brw
, GENX(3DSTATE_VS
), vs
);
1137 blorp_emit(brw
, GENX(3DSTATE_HS
), hs
);
1138 blorp_emit(brw
, GENX(3DSTATE_TE
), te
);
1139 blorp_emit(brw
, GENX(3DSTATE_DS
), DS
);
1140 blorp_emit(brw
, GENX(3DSTATE_STREAMOUT
), so
);
1142 blorp_emit(brw
, GENX(3DSTATE_GS
), gs
);
1144 blorp_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1145 clip
.PerspectiveDivideDisable
= true;
1148 blorp_emit_sf_config(brw
, params
);
1149 blorp_emit_ps_config(brw
, params
);
1151 blorp_emit_viewport_state(brw
, params
);
1153 if (params
->depth
.bo
) {
1154 blorp_emit_depth_stencil_config(brw
, params
);
1156 brw_emit_depth_stall_flushes(brw
);
1158 blorp_emit(brw
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1159 db
.SurfaceType
= SURFTYPE_NULL
;
1160 db
.SurfaceFormat
= D32_FLOAT
;
1162 blorp_emit(brw
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hiz
);
1163 blorp_emit(brw
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
1166 /* 3DSTATE_CLEAR_PARAMS
1168 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
1169 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
1170 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
1172 blorp_emit(brw
, GENX(3DSTATE_CLEAR_PARAMS
), clear
) {
1173 clear
.DepthClearValueValid
= true;
1174 clear
.DepthClearValue
= params
->depth
.clear_color
.u32
[0];
1177 blorp_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
1178 rect
.ClippedDrawingRectangleXMax
= MAX2(params
->x1
, params
->x0
) - 1;
1179 rect
.ClippedDrawingRectangleYMax
= MAX2(params
->y1
, params
->y0
) - 1;
1182 blorp_emit(brw
, GENX(3DPRIMITIVE
), prim
) {
1183 prim
.VertexAccessType
= SEQUENTIAL
;
1184 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1185 prim
.VertexCountPerInstance
= 3;
1186 prim
.InstanceCount
= params
->num_layers
;