src/mesa/drivers/dri/i965/genX_blorp_exec.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31
  32 #include "genX_blorp_exec.h"
  33
  34 #include "brw_blorp.h"
  35
  36 static void *
  37 blorp_emit_dwords(struct blorp_batch *batch, unsigned n)
  38 {
  39    assert(batch->blorp->driver_ctx == batch->driver_batch);
  40    struct brw_context *brw = batch->driver_batch;
  41
  42    intel_batchbuffer_begin(brw, n, RENDER_RING);
  43    uint32_t *map = brw->batch.map_next;
  44    brw->batch.map_next += n;
  45    intel_batchbuffer_advance(brw);
  46    return map;
  47 }
  48
  49 static uint64_t
  50 blorp_emit_reloc(struct blorp_batch *batch,
  51                  void *location, struct blorp_address address, uint32_t delta)
  52 {
  53    assert(batch->blorp->driver_ctx == batch->driver_batch);
  54    struct brw_context *brw = batch->driver_batch;
  55
  56    uint32_t offset = (char *)location - (char *)brw->batch.map;
  57    if (brw->gen >= 8) {
  58       return intel_batchbuffer_reloc64(brw, address.buffer, offset,
  59                                        address.read_domains,
  60                                        address.write_domain,
  61                                        address.offset + delta);
  62    } else {
  63       return intel_batchbuffer_reloc(brw, address.buffer, offset,
  64                                      address.read_domains,
  65                                      address.write_domain,
  66                                      address.offset + delta);
  67    }
  68 }
  69
  70 static void
  71 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
  72                     struct blorp_address address, uint32_t delta)
  73 {
  74    assert(batch->blorp->driver_ctx == batch->driver_batch);
  75    struct brw_context *brw = batch->driver_batch;
  76
  77    drm_intel_bo_emit_reloc(brw->batch.bo, ss_offset,
  78                            address.buffer, address.offset + delta,
  79                            address.read_domains, address.write_domain);
  80
  81    uint64_t reloc_val = address.buffer->offset64 + address.offset + delta;
  82    void *reloc_ptr = (void *)brw->batch.map + ss_offset;
  83 #if GEN_GEN >= 8
  84    *(uint64_t *)reloc_ptr = reloc_val;
  85 #else
  86    *(uint32_t *)reloc_ptr = reloc_val;
  87 #endif
  88 }
  89
  90 static void *
  91 blorp_alloc_dynamic_state(struct blorp_batch *batch,
  92                           enum aub_state_struct_type type,
  93                           uint32_t size,
  94                           uint32_t alignment,
  95                           uint32_t *offset)
  96 {
  97    assert(batch->blorp->driver_ctx == batch->driver_batch);
  98    struct brw_context *brw = batch->driver_batch;
  99
 100    return brw_state_batch(brw, type, size, alignment, offset);
 101 }
 102
 103 static void
 104 blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
 105                           unsigned state_size, unsigned state_alignment,
 106                           uint32_t *bt_offset, uint32_t **bt_map,
 107                           void **surface_maps)
 108 {
 109    assert(batch->blorp->driver_ctx == batch->driver_batch);
 110    struct brw_context *brw = batch->driver_batch;
 111
 112    *bt_map = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 113                              num_entries * sizeof(uint32_t), 32,
 114                              bt_offset);
 115
 116    for (unsigned i = 0; i < num_entries; i++) {
 117       surface_maps[i] = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 118                                         state_size, state_alignment,
 119                                         &(*bt_map)[i]);
 120    }
 121 }
 122
 123 static void *
 124 blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
 125                           struct blorp_address *addr)
 126 {
 127    assert(batch->blorp->driver_ctx == batch->driver_batch);
 128    struct brw_context *brw = batch->driver_batch;
 129
 130    uint32_t offset;
 131    void *data = brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
 132                                 size, 32, &offset);
 133
 134    *addr = (struct blorp_address) {
 135       .buffer = brw->batch.bo,
 136       .read_domains = I915_GEM_DOMAIN_VERTEX,
 137       .write_domain = 0,
 138       .offset = offset,
 139    };
 140
 141    return data;
 142 }
 143
 144 static void
 145 blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
 146 {
 147    assert(batch->blorp->driver_ctx == batch->driver_batch);
 148    struct brw_context *brw = batch->driver_batch;
 149
 150 #if GEN_GEN >= 7
 151    if (!(brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE)) &&
 152        brw->urb.vsize >= vs_entry_size)
 153       return;
 154
 155    brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 156
 157    gen7_upload_urb(brw, vs_entry_size, false, false);
 158 #else
 159    gen6_upload_urb(brw, vs_entry_size, false, 0);
 160 #endif
 161 }
 162
 163 static void
 164 blorp_emit_3dstate_multisample(struct blorp_batch *batch, unsigned samples)
 165 {
 166    assert(batch->blorp->driver_ctx == batch->driver_batch);
 167    struct brw_context *brw = batch->driver_batch;
 168
 169 #if GEN_GEN >= 8
 170    gen8_emit_3dstate_multisample(brw, samples);
 171 #else
 172    gen6_emit_3dstate_multisample(brw, samples);
 173 #endif
 174 }
 175
 176 void
 177 genX(blorp_exec)(struct blorp_batch *batch,
 178                  const struct brw_blorp_params *params)
 179 {
 180    assert(batch->blorp->driver_ctx == batch->driver_batch);
 181    struct brw_context *brw = batch->driver_batch;
 182    struct gl_context *ctx = &brw->ctx;
 183    const uint32_t estimated_max_batch_usage = GEN_GEN >= 8 ? 1800 : 1500;
 184    bool check_aperture_failed_once = false;
 185
 186    /* Flush the sampler and render caches.  We definitely need to flush the
 187     * sampler cache so that we get updated contents from the render cache for
 188     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 189     * docs to flush the cache between reinterpretations of the same surface
 190     * data with different formats, which blorp does for stencil and depth
 191     * data.
 192     */
 193    brw_emit_mi_flush(brw);
 194
 195    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
 196
 197 retry:
 198    intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
 199    intel_batchbuffer_save_state(brw);
 200    drm_intel_bo *saved_bo = brw->batch.bo;
 201    uint32_t saved_used = USED_BATCH(brw->batch);
 202    uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
 203
 204 #if GEN_GEN == 6
 205    /* Emit workaround flushes when we switch from drawing to blorping. */
 206    brw_emit_post_sync_nonzero_flush(brw);
 207 #endif
 208
 209    brw_upload_state_base_address(brw);
 210
 211 #if GEN_GEN >= 8
 212    gen7_l3_state.emit(brw);
 213 #endif
 214
 215    if (brw->use_resource_streamer)
 216       gen7_disable_hw_binding_tables(brw);
 217
 218    brw_emit_depth_stall_flushes(brw);
 219
 220    blorp_exec(batch, params);
 221
 222    /* Make sure we didn't wrap the batch unintentionally, and make sure we
 223     * reserved enough space that a wrap will never happen.
 224     */
 225    assert(brw->batch.bo == saved_bo);
 226    assert((USED_BATCH(brw->batch) - saved_used) * 4 +
 227           (saved_state_batch_offset - brw->batch.state_batch_offset) <
 228           estimated_max_batch_usage);
 229    /* Shut up compiler warnings on release build */
 230    (void)saved_bo;
 231    (void)saved_used;
 232    (void)saved_state_batch_offset;
 233
 234    /* Check if the blorp op we just did would make our batch likely to fail to
 235     * map all the BOs into the GPU at batch exec time later.  If so, flush the
 236     * batch and try again with nothing else in the batch.
 237     */
 238    if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
 239       if (!check_aperture_failed_once) {
 240          check_aperture_failed_once = true;
 241          intel_batchbuffer_reset_to_saved(brw);
 242          intel_batchbuffer_flush(brw);
 243          goto retry;
 244       } else {
 245          int ret = intel_batchbuffer_flush(brw);
 246          WARN_ONCE(ret == -ENOSPC,
 247                    "i965: blorp emit exceeded available aperture space\n");
 248       }
 249    }
 250
 251    if (unlikely(brw->always_flush_batch))
 252       intel_batchbuffer_flush(brw);
 253
 254    /* We've smashed all state compared to what the normal 3D pipeline
 255     * rendering tracks for GL.
 256     */
 257    brw->ctx.NewDriverState |= BRW_NEW_BLORP;
 258    brw->no_depth_or_stencil = false;
 259    brw->ib.type = -1;
 260
 261    /* Flush the sampler cache so any texturing from the destination is
 262     * coherent.
 263     */
 264    brw_emit_mi_flush(brw);
 265 }