2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_mipmap_tree.h"
29 #include "brw_context.h"
30 #include "brw_state.h"
32 #include "blorp/blorp_genX_exec.h"
34 #include "brw_blorp.h"
37 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
)
39 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
40 struct brw_context
*brw
= batch
->driver_batch
;
42 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
43 uint32_t *map
= brw
->batch
.map_next
;
44 brw
->batch
.map_next
+= n
;
45 intel_batchbuffer_advance(brw
);
50 blorp_emit_reloc(struct blorp_batch
*batch
,
51 void *location
, struct blorp_address address
, uint32_t delta
)
53 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
54 struct brw_context
*brw
= batch
->driver_batch
;
56 uint32_t offset
= (char *)location
- (char *)brw
->batch
.map
;
58 return intel_batchbuffer_reloc64(brw
, address
.buffer
, offset
,
61 address
.offset
+ delta
);
63 return intel_batchbuffer_reloc(brw
, address
.buffer
, offset
,
66 address
.offset
+ delta
);
71 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
72 struct blorp_address address
, uint32_t delta
)
74 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
75 struct brw_context
*brw
= batch
->driver_batch
;
76 drm_intel_bo
*bo
= address
.buffer
;
78 drm_intel_bo_emit_reloc(brw
->batch
.bo
, ss_offset
,
79 bo
, address
.offset
+ delta
,
80 address
.read_domains
, address
.write_domain
);
82 uint64_t reloc_val
= bo
->offset64
+ address
.offset
+ delta
;
83 void *reloc_ptr
= (void *)brw
->batch
.map
+ ss_offset
;
85 *(uint64_t *)reloc_ptr
= reloc_val
;
87 *(uint32_t *)reloc_ptr
= reloc_val
;
92 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
93 enum aub_state_struct_type type
,
98 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
99 struct brw_context
*brw
= batch
->driver_batch
;
101 return brw_state_batch(brw
, type
, size
, alignment
, offset
);
105 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
106 unsigned state_size
, unsigned state_alignment
,
107 uint32_t *bt_offset
, uint32_t *surface_offsets
,
110 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
111 struct brw_context
*brw
= batch
->driver_batch
;
113 uint32_t *bt_map
= brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
114 num_entries
* sizeof(uint32_t), 32,
117 for (unsigned i
= 0; i
< num_entries
; i
++) {
118 surface_maps
[i
] = brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
119 state_size
, state_alignment
,
120 &(surface_offsets
)[i
]);
121 bt_map
[i
] = surface_offsets
[i
];
126 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
127 struct blorp_address
*addr
)
129 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
130 struct brw_context
*brw
= batch
->driver_batch
;
133 void *data
= brw_state_batch(brw
, AUB_TRACE_VERTEX_BUFFER
,
136 *addr
= (struct blorp_address
) {
137 .buffer
= brw
->batch
.bo
,
138 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
147 blorp_emit_urb_config(struct blorp_batch
*batch
, unsigned vs_entry_size
)
149 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
150 struct brw_context
*brw
= batch
->driver_batch
;
153 if (!(brw
->ctx
.NewDriverState
& (BRW_NEW_CONTEXT
| BRW_NEW_URB_SIZE
)) &&
154 brw
->urb
.vsize
>= vs_entry_size
)
157 brw
->ctx
.NewDriverState
|= BRW_NEW_URB_SIZE
;
159 gen7_upload_urb(brw
, vs_entry_size
, false, false);
161 gen6_upload_urb(brw
, vs_entry_size
, false, 0);
166 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
, unsigned samples
)
168 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
169 struct brw_context
*brw
= batch
->driver_batch
;
172 gen8_emit_3dstate_multisample(brw
, samples
);
174 gen6_emit_3dstate_multisample(brw
, samples
);
179 genX(blorp_exec
)(struct blorp_batch
*batch
,
180 const struct blorp_params
*params
)
182 assert(batch
->blorp
->driver_ctx
== batch
->driver_batch
);
183 struct brw_context
*brw
= batch
->driver_batch
;
184 struct gl_context
*ctx
= &brw
->ctx
;
185 const uint32_t estimated_max_batch_usage
= GEN_GEN
>= 8 ? 1800 : 1500;
186 bool check_aperture_failed_once
= false;
188 /* Flush the sampler and render caches. We definitely need to flush the
189 * sampler cache so that we get updated contents from the render cache for
190 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
191 * docs to flush the cache between reinterpretations of the same surface
192 * data with different formats, which blorp does for stencil and depth
195 brw_emit_mi_flush(brw
);
197 brw_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
200 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, RENDER_RING
);
201 intel_batchbuffer_save_state(brw
);
202 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
203 uint32_t saved_used
= USED_BATCH(brw
->batch
);
204 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
207 /* Emit workaround flushes when we switch from drawing to blorping. */
208 brw_emit_post_sync_nonzero_flush(brw
);
211 brw_upload_state_base_address(brw
);
214 gen7_l3_state
.emit(brw
);
217 if (brw
->use_resource_streamer
)
218 gen7_disable_hw_binding_tables(brw
);
220 brw_emit_depth_stall_flushes(brw
);
222 blorp_exec(batch
, params
);
224 /* Make sure we didn't wrap the batch unintentionally, and make sure we
225 * reserved enough space that a wrap will never happen.
227 assert(brw
->batch
.bo
== saved_bo
);
228 assert((USED_BATCH(brw
->batch
) - saved_used
) * 4 +
229 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
230 estimated_max_batch_usage
);
231 /* Shut up compiler warnings on release build */
234 (void)saved_state_batch_offset
;
236 /* Check if the blorp op we just did would make our batch likely to fail to
237 * map all the BOs into the GPU at batch exec time later. If so, flush the
238 * batch and try again with nothing else in the batch.
240 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
241 if (!check_aperture_failed_once
) {
242 check_aperture_failed_once
= true;
243 intel_batchbuffer_reset_to_saved(brw
);
244 intel_batchbuffer_flush(brw
);
247 int ret
= intel_batchbuffer_flush(brw
);
248 WARN_ONCE(ret
== -ENOSPC
,
249 "i965: blorp emit exceeded available aperture space\n");
253 if (unlikely(brw
->always_flush_batch
))
254 intel_batchbuffer_flush(brw
);
256 /* We've smashed all state compared to what the normal 3D pipeline
257 * rendering tracks for GL.
259 brw
->ctx
.NewDriverState
|= BRW_NEW_BLORP
;
260 brw
->no_depth_or_stencil
= false;
263 /* Flush the sampler cache so any texturing from the destination is
266 brw_emit_mi_flush(brw
);