src/mesa/drivers/dri/i965/genX_blorp_exec.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28 #include "intel_fbo.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_state.h"
  32
  33 #include "blorp/blorp_genX_exec.h"
  34
  35 #include "brw_blorp.h"
  36
  37 static void *
  38 blorp_emit_dwords(struct blorp_batch *batch, unsigned n)
  39 {
  40    assert(batch->blorp->driver_ctx == batch->driver_batch);
  41    struct brw_context *brw = batch->driver_batch;
  42
  43    intel_batchbuffer_begin(brw, n, RENDER_RING);
  44    uint32_t *map = brw->batch.map_next;
  45    brw->batch.map_next += n;
  46    intel_batchbuffer_advance(brw);
  47    return map;
  48 }
  49
  50 static uint64_t
  51 blorp_emit_reloc(struct blorp_batch *batch,
  52                  void *location, struct blorp_address address, uint32_t delta)
  53 {
  54    assert(batch->blorp->driver_ctx == batch->driver_batch);
  55    struct brw_context *brw = batch->driver_batch;
  56
  57    uint32_t offset = (char *)location - (char *)brw->batch.map;
  58    return intel_batchbuffer_reloc(&brw->batch, address.buffer, offset,
  59                                   address.read_domains,
  60                                   address.write_domain,
  61                                   address.offset + delta);
  62 }
  63
  64 static void
  65 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
  66                     struct blorp_address address, uint32_t delta)
  67 {
  68    assert(batch->blorp->driver_ctx == batch->driver_batch);
  69    struct brw_context *brw = batch->driver_batch;
  70    drm_intel_bo *bo = address.buffer;
  71
  72    drm_intel_bo_emit_reloc(brw->batch.bo, ss_offset,
  73                            bo, address.offset + delta,
  74                            address.read_domains, address.write_domain);
  75
  76    uint64_t reloc_val = bo->offset64 + address.offset + delta;
  77    void *reloc_ptr = (void *)brw->batch.map + ss_offset;
  78 #if GEN_GEN >= 8
  79    *(uint64_t *)reloc_ptr = reloc_val;
  80 #else
  81    *(uint32_t *)reloc_ptr = reloc_val;
  82 #endif
  83 }
  84
  85 static void *
  86 blorp_alloc_dynamic_state(struct blorp_batch *batch,
  87                           uint32_t size,
  88                           uint32_t alignment,
  89                           uint32_t *offset)
  90 {
  91    assert(batch->blorp->driver_ctx == batch->driver_batch);
  92    struct brw_context *brw = batch->driver_batch;
  93
  94    return brw_state_batch(brw, size, alignment, offset);
  95 }
  96
  97 static void
  98 blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
  99                           unsigned state_size, unsigned state_alignment,
 100                           uint32_t *bt_offset, uint32_t *surface_offsets,
 101                           void **surface_maps)
 102 {
 103    assert(batch->blorp->driver_ctx == batch->driver_batch);
 104    struct brw_context *brw = batch->driver_batch;
 105
 106    uint32_t *bt_map = brw_state_batch(brw,
 107                                       num_entries * sizeof(uint32_t), 32,
 108                                       bt_offset);
 109
 110    for (unsigned i = 0; i < num_entries; i++) {
 111       surface_maps[i] = brw_state_batch(brw,
 112                                         state_size, state_alignment,
 113                                         &(surface_offsets)[i]);
 114       bt_map[i] = surface_offsets[i];
 115    }
 116 }
 117
 118 static void *
 119 blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
 120                           struct blorp_address *addr)
 121 {
 122    assert(batch->blorp->driver_ctx == batch->driver_batch);
 123    struct brw_context *brw = batch->driver_batch;
 124
 125    uint32_t offset;
 126    void *data = brw_state_batch(brw, size, 32, &offset);
 127
 128    *addr = (struct blorp_address) {
 129       .buffer = brw->batch.bo,
 130       .read_domains = I915_GEM_DOMAIN_VERTEX,
 131       .write_domain = 0,
 132       .offset = offset,
 133    };
 134
 135    return data;
 136 }
 137
 138 static void
 139 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
 140 {
 141    /* All allocated states come from the batch which we will flush before we
 142     * submit it.  There's nothing for us to do here.
 143     */
 144 }
 145
 146 static void
 147 blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
 148 {
 149    assert(batch->blorp->driver_ctx == batch->driver_batch);
 150    struct brw_context *brw = batch->driver_batch;
 151
 152 #if GEN_GEN >= 7
 153    if (!(brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE)) &&
 154        brw->urb.vsize >= vs_entry_size)
 155       return;
 156
 157    brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 158
 159    gen7_upload_urb(brw, vs_entry_size, false, false);
 160 #else
 161    gen6_upload_urb(brw, vs_entry_size, false, 0);
 162 #endif
 163 }
 164
 165 void
 166 genX(blorp_exec)(struct blorp_batch *batch,
 167                  const struct blorp_params *params)
 168 {
 169    assert(batch->blorp->driver_ctx == batch->driver_batch);
 170    struct brw_context *brw = batch->driver_batch;
 171    struct gl_context *ctx = &brw->ctx;
 172    const uint32_t estimated_max_batch_usage = GEN_GEN >= 8 ? 1800 : 1500;
 173    bool check_aperture_failed_once = false;
 174
 175    /* Flush the sampler and render caches.  We definitely need to flush the
 176     * sampler cache so that we get updated contents from the render cache for
 177     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 178     * docs to flush the cache between reinterpretations of the same surface
 179     * data with different formats, which blorp does for stencil and depth
 180     * data.
 181     */
 182    if (params->src.enabled)
 183       brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
 184    brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
 185
 186    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
 187
 188 retry:
 189    intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
 190    intel_batchbuffer_save_state(brw);
 191    drm_intel_bo *saved_bo = brw->batch.bo;
 192    uint32_t saved_used = USED_BATCH(brw->batch);
 193    uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
 194
 195 #if GEN_GEN == 6
 196    /* Emit workaround flushes when we switch from drawing to blorping. */
 197    brw_emit_post_sync_nonzero_flush(brw);
 198 #endif
 199
 200    brw_upload_state_base_address(brw);
 201
 202 #if GEN_GEN >= 8
 203    gen7_l3_state.emit(brw);
 204 #endif
 205
 206    brw_emit_depth_stall_flushes(brw);
 207
 208 #if GEN_GEN == 8
 209    gen8_write_pma_stall_bits(brw, 0);
 210 #endif
 211
 212    blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 213       rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
 214       rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
 215    }
 216
 217    blorp_exec(batch, params);
 218
 219    /* Make sure we didn't wrap the batch unintentionally, and make sure we
 220     * reserved enough space that a wrap will never happen.
 221     */
 222    assert(brw->batch.bo == saved_bo);
 223    assert((USED_BATCH(brw->batch) - saved_used) * 4 +
 224           (saved_state_batch_offset - brw->batch.state_batch_offset) <
 225           estimated_max_batch_usage);
 226    /* Shut up compiler warnings on release build */
 227    (void)saved_bo;
 228    (void)saved_used;
 229    (void)saved_state_batch_offset;
 230
 231    /* Check if the blorp op we just did would make our batch likely to fail to
 232     * map all the BOs into the GPU at batch exec time later.  If so, flush the
 233     * batch and try again with nothing else in the batch.
 234     */
 235    if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
 236       if (!check_aperture_failed_once) {
 237          check_aperture_failed_once = true;
 238          intel_batchbuffer_reset_to_saved(brw);
 239          intel_batchbuffer_flush(brw);
 240          goto retry;
 241       } else {
 242          int ret = intel_batchbuffer_flush(brw);
 243          WARN_ONCE(ret == -ENOSPC,
 244                    "i965: blorp emit exceeded available aperture space\n");
 245       }
 246    }
 247
 248    if (unlikely(brw->always_flush_batch))
 249       intel_batchbuffer_flush(brw);
 250
 251    /* We've smashed all state compared to what the normal 3D pipeline
 252     * rendering tracks for GL.
 253     */
 254    brw->ctx.NewDriverState |= BRW_NEW_BLORP;
 255    brw->no_depth_or_stencil = false;
 256    brw->ib.type = -1;
 257
 258    if (params->dst.enabled)
 259       brw_render_cache_set_add_bo(brw, params->dst.addr.buffer);
 260    if (params->depth.enabled)
 261       brw_render_cache_set_add_bo(brw, params->depth.addr.buffer);
 262    if (params->stencil.enabled)
 263       brw_render_cache_set_add_bo(brw, params->stencil.addr.buffer);
 264 }