2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_defines.h"
41 #include "brw_multisample_state.h"
42 #include "brw_state.h"
46 #include "intel_batchbuffer.h"
47 #include "intel_buffer_objects.h"
48 #include "intel_fbo.h"
50 #include "main/enums.h"
51 #include "main/fbobject.h"
52 #include "main/framebuffer.h"
53 #include "main/glformats.h"
54 #include "main/samplerobj.h"
55 #include "main/shaderapi.h"
56 #include "main/stencil.h"
57 #include "main/transformfeedback.h"
58 #include "main/varray.h"
59 #include "main/viewport.h"
60 #include "util/half_float.h"
63 emit_dwords(struct brw_context
*brw
, unsigned n
)
65 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
66 uint32_t *map
= brw
->batch
.map_next
;
67 brw
->batch
.map_next
+= n
;
68 intel_batchbuffer_advance(brw
);
74 uint32_t read_domains
;
75 uint32_t write_domain
;
80 emit_reloc(struct brw_context
*brw
,
81 void *location
, struct brw_address address
, uint32_t delta
)
83 uint32_t offset
= (char *) location
- (char *) brw
->batch
.map
;
85 return brw_emit_reloc(&brw
->batch
, offset
, address
.bo
,
86 address
.offset
+ delta
,
88 address
.write_domain
);
91 #define __gen_address_type struct brw_address
92 #define __gen_user_data struct brw_context
95 __gen_combine_address(struct brw_context
*brw
, void *location
,
96 struct brw_address address
, uint32_t delta
)
98 if (address
.bo
== NULL
) {
99 return address
.offset
+ delta
;
101 return emit_reloc(brw
, location
, address
, delta
);
105 static inline struct brw_address
106 render_bo(struct brw_bo
*bo
, uint32_t offset
)
108 return (struct brw_address
) {
111 .read_domains
= I915_GEM_DOMAIN_RENDER
,
112 .write_domain
= I915_GEM_DOMAIN_RENDER
,
116 static inline struct brw_address
117 render_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
119 return (struct brw_address
) {
122 .read_domains
= I915_GEM_DOMAIN_RENDER
,
127 static inline struct brw_address
128 instruction_bo(struct brw_bo
*bo
, uint32_t offset
)
130 return (struct brw_address
) {
133 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
134 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
138 static inline struct brw_address
139 instruction_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
141 return (struct brw_address
) {
144 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
149 static inline struct brw_address
150 vertex_bo(struct brw_bo
*bo
, uint32_t offset
)
152 return (struct brw_address
) {
155 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
161 static inline struct brw_address
162 KSP(struct brw_context
*brw
, uint32_t offset
)
164 return instruction_bo(brw
->cache
.bo
, offset
);
167 static inline struct brw_address
168 KSP_ro(struct brw_context
*brw
, uint32_t offset
)
170 return instruction_ro_bo(brw
->cache
.bo
, offset
);
173 static inline uint32_t
174 KSP(struct brw_context
*brw
, uint32_t offset
)
183 #include "genxml/genX_pack.h"
185 #define _brw_cmd_length(cmd) cmd ## _length
186 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
187 #define _brw_cmd_header(cmd) cmd ## _header
188 #define _brw_cmd_pack(cmd) cmd ## _pack
190 #define brw_batch_emit(brw, cmd, name) \
191 for (struct cmd name = { _brw_cmd_header(cmd) }, \
192 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
193 __builtin_expect(_dst != NULL, 1); \
194 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
197 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
198 uint32_t *_dw = emit_dwords(brw, n); \
199 struct cmd template = { \
200 _brw_cmd_header(cmd), \
201 .DWordLength = n - _brw_cmd_length_bias(cmd), \
204 _brw_cmd_pack(cmd)(brw, _dw, &template); \
205 _dw + 1; /* Array starts at dw[1] */ \
208 #define brw_state_emit(brw, cmd, align, offset, name) \
209 for (struct cmd name = { 0, }, \
210 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
212 __builtin_expect(_dst != NULL, 1); \
213 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
217 * Polygon stipple packet
220 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
222 struct gl_context
*ctx
= &brw
->ctx
;
225 if (!ctx
->Polygon
.StippleFlag
)
228 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
229 /* Polygon stipple is provided in OpenGL order, i.e. bottom
230 * row first. If we're rendering to a window (i.e. the
231 * default frame buffer object, 0), then we need to invert
232 * it to match our pixel layout. But if we're rendering
233 * to a FBO (i.e. any named frame buffer object), we *don't*
234 * need to invert - we already match the layout.
236 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
237 for (unsigned i
= 0; i
< 32; i
++)
238 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
240 for (unsigned i
= 0; i
< 32; i
++)
241 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
246 static const struct brw_tracked_state
genX(polygon_stipple
) = {
248 .mesa
= _NEW_POLYGON
|
250 .brw
= BRW_NEW_CONTEXT
,
252 .emit
= genX(upload_polygon_stipple
),
256 * Polygon stipple offset packet
259 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
261 struct gl_context
*ctx
= &brw
->ctx
;
264 if (!ctx
->Polygon
.StippleFlag
)
267 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
270 * If we're drawing to a system window we have to invert the Y axis
271 * in order to match the OpenGL pixel coordinate system, and our
272 * offset must be matched to the window position. If we're drawing
273 * to a user-created FBO then our native pixel coordinate system
274 * works just fine, and there's no window system to worry about.
276 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
277 poly
.PolygonStippleYOffset
=
278 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
283 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
285 .mesa
= _NEW_BUFFERS
|
287 .brw
= BRW_NEW_CONTEXT
,
289 .emit
= genX(upload_polygon_stipple_offset
),
293 * Line stipple packet
296 genX(upload_line_stipple
)(struct brw_context
*brw
)
298 struct gl_context
*ctx
= &brw
->ctx
;
300 if (!ctx
->Line
.StippleFlag
)
303 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
304 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
306 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
307 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
311 static const struct brw_tracked_state
genX(line_stipple
) = {
314 .brw
= BRW_NEW_CONTEXT
,
316 .emit
= genX(upload_line_stipple
),
319 /* Constant single cliprect for framebuffer object or DRI2 drawing */
321 genX(upload_drawing_rect
)(struct brw_context
*brw
)
323 struct gl_context
*ctx
= &brw
->ctx
;
324 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
325 const unsigned int fb_width
= _mesa_geometric_width(fb
);
326 const unsigned int fb_height
= _mesa_geometric_height(fb
);
328 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
329 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
330 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
334 static const struct brw_tracked_state
genX(drawing_rect
) = {
336 .mesa
= _NEW_BUFFERS
,
337 .brw
= BRW_NEW_BLORP
|
340 .emit
= genX(upload_drawing_rect
),
344 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
348 unsigned start_offset
,
353 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
354 .VertexBufferIndex
= buffer_nr
,
355 .BufferPitch
= stride
,
356 .BufferStartingAddress
= vertex_bo(bo
, start_offset
),
358 .BufferSize
= end_offset
- start_offset
,
362 .AddressModifyEnable
= true,
366 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
367 .InstanceDataStepRate
= step_rate
,
369 .EndAddress
= vertex_bo(bo
, end_offset
- 1),
374 .VertexBufferMOCS
= CNL_MOCS_WB
,
376 .VertexBufferMOCS
= SKL_MOCS_WB
,
378 .VertexBufferMOCS
= BDW_MOCS_WB
,
380 .VertexBufferMOCS
= GEN7_MOCS_L3
,
384 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
385 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
389 is_passthru_format(uint32_t format
)
392 case ISL_FORMAT_R64_PASSTHRU
:
393 case ISL_FORMAT_R64G64_PASSTHRU
:
394 case ISL_FORMAT_R64G64B64_PASSTHRU
:
395 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
403 uploads_needed(uint32_t format
)
405 if (!is_passthru_format(format
))
409 case ISL_FORMAT_R64_PASSTHRU
:
410 case ISL_FORMAT_R64G64_PASSTHRU
:
412 case ISL_FORMAT_R64G64B64_PASSTHRU
:
413 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
416 unreachable("not reached");
421 * Returns the format that we are finally going to use when upload a vertex
422 * element. It will only change if we are using *64*PASSTHRU formats, as for
423 * gen < 8 they need to be splitted on two *32*FLOAT formats.
425 * @upload points in which upload we are. Valid values are [0,1]
428 downsize_format_if_needed(uint32_t format
,
431 assert(upload
== 0 || upload
== 1);
433 if (!is_passthru_format(format
))
437 case ISL_FORMAT_R64_PASSTHRU
:
438 return ISL_FORMAT_R32G32_FLOAT
;
439 case ISL_FORMAT_R64G64_PASSTHRU
:
440 return ISL_FORMAT_R32G32B32A32_FLOAT
;
441 case ISL_FORMAT_R64G64B64_PASSTHRU
:
442 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
443 : ISL_FORMAT_R32G32_FLOAT
;
444 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
445 return ISL_FORMAT_R32G32B32A32_FLOAT
;
447 unreachable("not reached");
452 * Returns the number of componentes associated with a format that is used on
453 * a 64 to 32 format split. See downsize_format()
456 upload_format_size(uint32_t upload_format
)
458 switch (upload_format
) {
459 case ISL_FORMAT_R32G32_FLOAT
:
461 case ISL_FORMAT_R32G32B32A32_FLOAT
:
464 unreachable("not reached");
469 genX(emit_vertices
)(struct brw_context
*brw
)
473 brw_prepare_vertices(brw
);
474 brw_prepare_shader_draw_parameters(brw
);
477 brw_emit_query_begin(brw
);
480 const struct brw_vs_prog_data
*vs_prog_data
=
481 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
484 struct gl_context
*ctx
= &brw
->ctx
;
485 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
486 ctx
->Polygon
.BackMode
!= GL_FILL
);
488 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
489 unsigned vue
= brw
->vb
.nr_enabled
;
491 /* The element for the edge flags must always be last, so we have to
492 * insert the SGVS before it in that case.
494 if (uses_edge_flag
) {
500 "Trying to insert VID/IID past 33rd vertex element, "
501 "need to reorder the vertex attrbutes.");
503 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
504 if (vs_prog_data
->uses_vertexid
) {
505 vfs
.VertexIDEnable
= true;
506 vfs
.VertexIDComponentNumber
= 2;
507 vfs
.VertexIDElementOffset
= vue
;
510 if (vs_prog_data
->uses_instanceid
) {
511 vfs
.InstanceIDEnable
= true;
512 vfs
.InstanceIDComponentNumber
= 3;
513 vfs
.InstanceIDElementOffset
= vue
;
517 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
518 vfi
.InstancingEnable
= true;
519 vfi
.VertexElementIndex
= vue
;
522 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
525 /* Normally we don't need an element for the SGVS attribute because the
526 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
527 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
528 * we're using draw parameters then we need an element for the those
529 * values. Additionally if there is an edge flag element then the SGVS
530 * can't be inserted past that so we need a dummy element to ensure that
531 * the edge flag is the last one.
533 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
534 vs_prog_data
->uses_baseinstance
||
535 ((vs_prog_data
->uses_instanceid
||
536 vs_prog_data
->uses_vertexid
)
539 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
540 vs_prog_data
->uses_baseinstance
||
541 vs_prog_data
->uses_instanceid
||
542 vs_prog_data
->uses_vertexid
);
544 unsigned nr_elements
=
545 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
548 /* If any of the formats of vb.enabled needs more that one upload, we need
549 * to add it to nr_elements
551 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
552 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
553 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
555 if (uploads_needed(format
) > 1)
560 /* If the VS doesn't read any inputs (calculating vertex position from
561 * a state variable for some reason, for example), emit a single pad
562 * VERTEX_ELEMENT struct and bail.
564 * The stale VB state stays in place, but they don't do anything unless
565 * a VE loads from them.
567 if (nr_elements
== 0) {
568 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
569 1 + GENX(VERTEX_ELEMENT_STATE_length
));
570 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
572 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
573 .Component0Control
= VFCOMP_STORE_0
,
574 .Component1Control
= VFCOMP_STORE_0
,
575 .Component2Control
= VFCOMP_STORE_0
,
576 .Component3Control
= VFCOMP_STORE_1_FP
,
578 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
582 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
583 const bool uses_draw_params
=
584 vs_prog_data
->uses_basevertex
||
585 vs_prog_data
->uses_baseinstance
;
586 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
587 uses_draw_params
+ vs_prog_data
->uses_drawid
;
590 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
592 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
593 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
595 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
596 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
597 /* Prior to Haswell and Bay Trail we have to use 4-component formats
598 * to fake 3-component ones. In particular, we do this for
599 * half-float and 8 and 16-bit integer formats. This means that the
600 * vertex element may poke over the end of the buffer by 2 bytes.
602 const unsigned padding
=
603 (GEN_GEN
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
604 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
605 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
612 if (uses_draw_params
) {
613 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
614 brw
->draw
.draw_params_bo
,
615 brw
->draw
.draw_params_offset
,
616 brw
->draw
.draw_params_bo
->size
,
621 if (vs_prog_data
->uses_drawid
) {
622 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
623 brw
->draw
.draw_id_bo
,
624 brw
->draw
.draw_id_offset
,
625 brw
->draw
.draw_id_bo
->size
,
631 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
632 * presumably for VertexID/InstanceID.
635 assert(nr_elements
<= 34);
636 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
638 assert(nr_elements
<= 18);
641 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
642 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
644 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
645 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
646 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
647 uint32_t comp0
= VFCOMP_STORE_SRC
;
648 uint32_t comp1
= VFCOMP_STORE_SRC
;
649 uint32_t comp2
= VFCOMP_STORE_SRC
;
650 uint32_t comp3
= VFCOMP_STORE_SRC
;
651 const unsigned num_uploads
= GEN_GEN
< 8 ? uploads_needed(format
) : 1;
654 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
655 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
656 * element which has edge flag enabled."
658 assert(!(is_passthru_format(format
) && uses_edge_flag
));
661 /* The gen4 driver expects edgeflag to come in as a float, and passes
662 * that float on to the tests in the clipper. Mesa's current vertex
663 * attribute value for EdgeFlag is stored as a float, which works out.
664 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
665 * integer ubyte. Just rewrite that to convert to a float.
667 * Gen6+ passes edgeflag as sideband along with the vertex, instead
668 * of in the VUE. We have to upload it sideband as the last vertex
669 * element according to the B-Spec.
672 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
673 gen6_edgeflag_input
= input
;
678 for (unsigned c
= 0; c
< num_uploads
; c
++) {
679 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
680 downsize_format_if_needed(format
, c
);
681 /* If we need more that one upload, the offset stride would be 128
682 * bits (16 bytes), as for previous uploads we are using the full
684 const unsigned offset
= input
->offset
+ c
* 16;
686 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
687 upload_format_size(upload_format
) : input
->glarray
->Size
;
690 case 0: comp0
= VFCOMP_STORE_0
;
691 case 1: comp1
= VFCOMP_STORE_0
;
692 case 2: comp2
= VFCOMP_STORE_0
;
694 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
695 comp3
= VFCOMP_STORE_0
;
696 } else if (input
->glarray
->Integer
) {
697 comp3
= VFCOMP_STORE_1_INT
;
699 comp3
= VFCOMP_STORE_1_FP
;
706 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
708 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
709 * formats, 64-bit components are stored in the URB without any
710 * conversion. In this case, vertex elements must be written as 128
711 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
712 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
713 * component into the URB, Component 1 must be specified as
714 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
715 * order to output a 128-bit vertex element, or Components 1-3 must
716 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
717 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
718 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
721 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
722 /* Store vertex elements which correspond to double and dvec2 vertex
723 * shader inputs as 128-bit vertex elements, instead of 256-bits.
725 comp2
= VFCOMP_NOSTORE
;
726 comp3
= VFCOMP_NOSTORE
;
730 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
731 .VertexBufferIndex
= input
->buffer
,
733 .SourceElementFormat
= upload_format
,
734 .SourceElementOffset
= offset
,
735 .Component0Control
= comp0
,
736 .Component1Control
= comp1
,
737 .Component2Control
= comp2
,
738 .Component3Control
= comp3
,
740 .DestinationElementOffset
= i
* 4,
744 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
745 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
749 if (needs_sgvs_element
) {
750 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
752 .Component0Control
= VFCOMP_STORE_0
,
753 .Component1Control
= VFCOMP_STORE_0
,
754 .Component2Control
= VFCOMP_STORE_0
,
755 .Component3Control
= VFCOMP_STORE_0
,
757 .DestinationElementOffset
= i
* 4,
762 if (vs_prog_data
->uses_basevertex
||
763 vs_prog_data
->uses_baseinstance
) {
764 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
765 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
766 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
767 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
770 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
771 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
772 if (vs_prog_data
->uses_basevertex
)
773 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
775 if (vs_prog_data
->uses_baseinstance
)
776 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
778 if (vs_prog_data
->uses_vertexid
)
779 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
781 if (vs_prog_data
->uses_instanceid
)
782 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
785 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
786 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
789 if (vs_prog_data
->uses_drawid
) {
790 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
792 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
793 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
794 .Component0Control
= VFCOMP_STORE_SRC
,
795 .Component1Control
= VFCOMP_STORE_0
,
796 .Component2Control
= VFCOMP_STORE_0
,
797 .Component3Control
= VFCOMP_STORE_0
,
799 .DestinationElementOffset
= i
* 4,
803 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
804 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
808 if (gen6_edgeflag_input
) {
809 const uint32_t format
=
810 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
812 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
814 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
815 .EdgeFlagEnable
= true,
816 .SourceElementFormat
= format
,
817 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
818 .Component0Control
= VFCOMP_STORE_SRC
,
819 .Component1Control
= VFCOMP_STORE_0
,
820 .Component2Control
= VFCOMP_STORE_0
,
821 .Component3Control
= VFCOMP_STORE_0
,
824 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
825 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
830 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
831 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
832 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
833 unsigned element_index
;
835 /* The edge flag element is reordered to be the last one in the code
836 * above so we need to compensate for that in the element indices used
839 if (input
== gen6_edgeflag_input
)
840 element_index
= nr_elements
- 1;
844 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
845 vfi
.VertexElementIndex
= element_index
;
846 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
847 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
851 if (vs_prog_data
->uses_drawid
) {
852 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
854 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
855 vfi
.VertexElementIndex
= element
;
861 static const struct brw_tracked_state
genX(vertices
) = {
863 .mesa
= _NEW_POLYGON
,
864 .brw
= BRW_NEW_BATCH
|
867 BRW_NEW_VS_PROG_DATA
,
869 .emit
= genX(emit_vertices
),
873 genX(emit_index_buffer
)(struct brw_context
*brw
)
875 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
877 if (index_buffer
== NULL
)
880 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
881 #if GEN_GEN < 8 && !GEN_IS_HASWELL
882 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
884 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
885 ib
.BufferStartingAddress
= vertex_bo(brw
->ib
.bo
, 0);
887 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
888 ib
.BufferSize
= brw
->ib
.size
;
890 ib
.BufferEndingAddress
= vertex_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
895 static const struct brw_tracked_state
genX(index_buffer
) = {
898 .brw
= BRW_NEW_BATCH
|
900 BRW_NEW_INDEX_BUFFER
,
902 .emit
= genX(emit_index_buffer
),
905 #if GEN_IS_HASWELL || GEN_GEN >= 8
907 genX(upload_cut_index
)(struct brw_context
*brw
)
909 const struct gl_context
*ctx
= &brw
->ctx
;
911 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
912 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
913 vf
.IndexedDrawCutIndexEnable
= true;
914 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
919 const struct brw_tracked_state
genX(cut_index
) = {
921 .mesa
= _NEW_TRANSFORM
,
922 .brw
= BRW_NEW_INDEX_BUFFER
,
924 .emit
= genX(upload_cut_index
),
930 * Determine the appropriate attribute override value to store into the
931 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
932 * override value contains two pieces of information: the location of the
933 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
934 * flag indicating whether to "swizzle" the attribute based on the direction
935 * the triangle is facing.
937 * If an attribute is "swizzled", then the given VUE location is used for
938 * front-facing triangles, and the VUE location that immediately follows is
939 * used for back-facing triangles. We use this to implement the mapping from
940 * gl_FrontColor/gl_BackColor to gl_Color.
942 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
943 * being instructed to begin reading attribute data. It can be set to a
944 * nonzero value to prevent the SF unit from wasting time reading elements of
945 * the VUE that are not needed by the fragment shader. It is measured in
946 * 256-bit increments.
949 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
950 const struct brw_vue_map
*vue_map
,
951 int urb_entry_read_offset
, int fs_attr
,
952 bool two_side_color
, uint32_t *max_source_attr
)
954 /* Find the VUE slot for this attribute. */
955 int slot
= vue_map
->varying_to_slot
[fs_attr
];
957 /* Viewport and Layer are stored in the VUE header. We need to override
958 * them to zero if earlier stages didn't write them, as GL requires that
959 * they read back as zero when not explicitly set.
961 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
962 attr
->ComponentOverrideX
= true;
963 attr
->ComponentOverrideW
= true;
964 attr
->ConstantSource
= CONST_0000
;
966 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
967 attr
->ComponentOverrideY
= true;
968 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
969 attr
->ComponentOverrideZ
= true;
974 /* If there was only a back color written but not front, use back
975 * as the color instead of undefined
977 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
978 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
979 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
980 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
983 /* This attribute does not exist in the VUE--that means that the vertex
984 * shader did not write to it. This means that either:
986 * (a) This attribute is a texture coordinate, and it is going to be
987 * replaced with point coordinates (as a consequence of a call to
988 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
989 * hardware will ignore whatever attribute override we supply.
991 * (b) This attribute is read by the fragment shader but not written by
992 * the vertex shader, so its value is undefined. Therefore the
993 * attribute override we supply doesn't matter.
995 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
996 * previous shader stage.
998 * Note that we don't have to worry about the cases where the attribute
999 * is gl_PointCoord or is undergoing point sprite coordinate
1000 * replacement, because in those cases, this function isn't called.
1002 * In case (c), we need to program the attribute overrides so that the
1003 * primitive ID will be stored in this slot. In every other case, the
1004 * attribute override we supply doesn't matter. So just go ahead and
1005 * program primitive ID in every case.
1007 attr
->ComponentOverrideW
= true;
1008 attr
->ComponentOverrideX
= true;
1009 attr
->ComponentOverrideY
= true;
1010 attr
->ComponentOverrideZ
= true;
1011 attr
->ConstantSource
= PRIM_ID
;
1015 /* Compute the location of the attribute relative to urb_entry_read_offset.
1016 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1017 * it counts for two 128-bit VUE slots.
1019 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1020 assert(source_attr
>= 0 && source_attr
< 32);
1022 /* If we are doing two-sided color, and the VUE slot following this one
1023 * represents a back-facing color, then we need to instruct the SF unit to
1024 * do back-facing swizzling.
1026 bool swizzling
= two_side_color
&&
1027 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1028 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1029 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1030 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1032 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1033 if (*max_source_attr
< source_attr
+ swizzling
)
1034 *max_source_attr
= source_attr
+ swizzling
;
1036 attr
->SourceAttribute
= source_attr
;
1038 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1043 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1044 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1045 uint32_t *point_sprite_enables
,
1046 uint32_t *urb_entry_read_length
,
1047 uint32_t *urb_entry_read_offset
)
1049 const struct gl_context
*ctx
= &brw
->ctx
;
1052 const struct gl_point_attrib
*point
= &ctx
->Point
;
1054 /* BRW_NEW_FS_PROG_DATA */
1055 const struct brw_wm_prog_data
*wm_prog_data
=
1056 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1057 uint32_t max_source_attr
= 0;
1059 *point_sprite_enables
= 0;
1061 /* BRW_NEW_FRAGMENT_PROGRAM
1063 * If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
1064 * the full vertex header. Otherwise, we can program the SF to start
1065 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
1066 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1067 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
1070 bool fs_needs_vue_header
= brw
->fragment_program
->info
.inputs_read
&
1071 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1073 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
1075 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1076 * description of dw10 Point Sprite Texture Coordinate Enable:
1078 * "This field must be programmed to zero when non-point primitives
1081 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1082 * must be programmed to zero when rendering non-point primitives, but
1083 * the IvyBridge PRM does, and if we don't, we get garbage.
1085 * This is not required on Haswell, as the hardware ignores this state
1086 * when drawing non-points -- although we do still need to be careful to
1087 * correctly set the attr overrides.
1090 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1092 bool drawing_points
= brw_is_drawing_points(brw
);
1094 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1095 int input_index
= wm_prog_data
->urb_setup
[attr
];
1097 if (input_index
< 0)
1101 bool point_sprite
= false;
1102 if (drawing_points
) {
1103 if (point
->PointSprite
&&
1104 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1105 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1106 point_sprite
= true;
1109 if (attr
== VARYING_SLOT_PNTC
)
1110 point_sprite
= true;
1113 *point_sprite_enables
|= (1 << input_index
);
1116 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1117 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1119 if (!point_sprite
) {
1120 genX(get_attr_override
)(&attribute
,
1121 &brw
->vue_map_geom_out
,
1122 *urb_entry_read_offset
, attr
,
1123 _mesa_vertex_program_two_side_enabled(ctx
),
1127 /* The hardware can only do the overrides on 16 overrides at a
1128 * time, and the other up to 16 have to be lined up so that the
1129 * input index = the output index. We'll need to do some
1130 * tweaking to make sure that's the case.
1132 if (input_index
< 16)
1133 attr_overrides
[input_index
] = attribute
;
1135 assert(attribute
.SourceAttribute
== input_index
);
1138 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1139 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1141 * "This field should be set to the minimum length required to read the
1142 * maximum source attribute. The maximum source attribute is indicated
1143 * by the maximum value of the enabled Attribute # Source Attribute if
1144 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1145 * enable is not set.
1146 * read_length = ceiling((max_source_attr + 1) / 2)
1148 * [errata] Corruption/Hang possible if length programmed larger than
1151 * Similar text exists for Ivy Bridge.
1153 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1157 /* ---------------------------------------------------------------------- */
1160 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1162 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1164 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1168 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1170 struct gl_context
*ctx
= &brw
->ctx
;
1173 struct intel_renderbuffer
*depth_irb
=
1174 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1177 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1180 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1181 const int b
= stencil
->_BackFace
;
1183 if (depth
->Test
&& depth_irb
) {
1184 ds
->DepthTestEnable
= true;
1185 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1186 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1189 if (brw
->stencil_enabled
) {
1190 ds
->StencilTestEnable
= true;
1191 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1192 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1194 ds
->StencilTestFunction
=
1195 intel_translate_compare_func(stencil
->Function
[0]);
1197 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1198 ds
->StencilPassDepthPassOp
=
1199 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1200 ds
->StencilPassDepthFailOp
=
1201 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1203 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1205 if (brw
->stencil_two_sided
) {
1206 ds
->DoubleSidedStencilEnable
= true;
1207 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1208 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1210 ds
->BackfaceStencilTestFunction
=
1211 intel_translate_compare_func(stencil
->Function
[b
]);
1212 ds
->BackfaceStencilFailOp
=
1213 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1214 ds
->BackfaceStencilPassDepthPassOp
=
1215 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1216 ds
->BackfaceStencilPassDepthFailOp
=
1217 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1221 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1222 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1229 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1232 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1233 set_depth_stencil_bits(brw
, &wmds
);
1237 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1238 set_depth_stencil_bits(brw
, &ds
);
1241 /* Now upload a pointer to the indirect state */
1243 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1244 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1245 ptr
.DEPTH_STENCIL_STATEChange
= true;
1248 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1249 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1255 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1257 .mesa
= _NEW_BUFFERS
|
1260 .brw
= BRW_NEW_BLORP
|
1261 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1263 BRW_NEW_STATE_BASE_ADDRESS
),
1265 .emit
= genX(upload_depth_stencil_state
),
1269 /* ---------------------------------------------------------------------- */
1273 genX(upload_clip_state
)(struct brw_context
*brw
)
1275 struct gl_context
*ctx
= &brw
->ctx
;
1278 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1280 /* BRW_NEW_FS_PROG_DATA */
1281 struct brw_wm_prog_data
*wm_prog_data
=
1282 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1284 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1285 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1287 if (wm_prog_data
->barycentric_interp_modes
&
1288 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1289 clip
.NonPerspectiveBarycentricEnable
= true;
1292 clip
.EarlyCullEnable
= true;
1296 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1298 if (ctx
->Polygon
.CullFlag
) {
1299 switch (ctx
->Polygon
.CullFaceMode
) {
1301 clip
.CullMode
= CULLMODE_FRONT
;
1304 clip
.CullMode
= CULLMODE_BACK
;
1306 case GL_FRONT_AND_BACK
:
1307 clip
.CullMode
= CULLMODE_BOTH
;
1310 unreachable("Should not get here: invalid CullFlag");
1313 clip
.CullMode
= CULLMODE_NONE
;
1318 clip
.UserClipDistanceCullTestEnableBitmask
=
1319 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1321 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1325 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1326 clip
.TriangleStripListProvokingVertexSelect
= 0;
1327 clip
.TriangleFanProvokingVertexSelect
= 1;
1328 clip
.LineStripListProvokingVertexSelect
= 0;
1330 clip
.TriangleStripListProvokingVertexSelect
= 2;
1331 clip
.TriangleFanProvokingVertexSelect
= 2;
1332 clip
.LineStripListProvokingVertexSelect
= 1;
1335 /* _NEW_TRANSFORM */
1336 clip
.UserClipDistanceClipTestEnableBitmask
=
1337 ctx
->Transform
.ClipPlanesEnabled
;
1340 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1343 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1344 clip
.APIMode
= APIMODE_D3D
;
1346 clip
.APIMode
= APIMODE_OGL
;
1348 clip
.GuardbandClipTestEnable
= true;
1350 /* BRW_NEW_VIEWPORT_COUNT */
1351 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1353 if (ctx
->RasterDiscard
) {
1354 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1356 perf_debug("Rasterizer discard is currently implemented via the "
1357 "clipper; having the GS not write primitives would "
1358 "likely be faster.\n");
1361 clip
.ClipMode
= CLIPMODE_NORMAL
;
1364 clip
.ClipEnable
= true;
1367 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1369 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1370 clip
.ViewportXYClipTestEnable
= true;
1372 clip
.MinimumPointWidth
= 0.125;
1373 clip
.MaximumPointWidth
= 255.875;
1374 clip
.MaximumVPIndex
= viewport_count
- 1;
1375 if (_mesa_geometric_layers(fb
) == 0)
1376 clip
.ForceZeroRTAIndexEnable
= true;
1380 static const struct brw_tracked_state
genX(clip_state
) = {
1382 .mesa
= _NEW_BUFFERS
|
1386 .brw
= BRW_NEW_BLORP
|
1388 BRW_NEW_FS_PROG_DATA
|
1389 BRW_NEW_GS_PROG_DATA
|
1390 BRW_NEW_VS_PROG_DATA
|
1391 BRW_NEW_META_IN_PROGRESS
|
1393 BRW_NEW_RASTERIZER_DISCARD
|
1394 BRW_NEW_TES_PROG_DATA
|
1395 BRW_NEW_VIEWPORT_COUNT
,
1397 .emit
= genX(upload_clip_state
),
1401 /* ---------------------------------------------------------------------- */
1404 genX(upload_sf
)(struct brw_context
*brw
)
1406 struct gl_context
*ctx
= &brw
->ctx
;
1411 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1412 UNUSED
const bool multisampled_fbo
=
1413 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1417 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1419 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1421 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1422 sf
.KernelStartPointer
= KSP_ro(brw
, brw
->sf
.prog_offset
);
1423 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1424 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1425 sf
.DispatchGRFStartRegisterForURBData
= 3;
1426 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1427 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1428 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1429 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1431 /* STATE_PREFETCH command description describes this state as being
1432 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1435 sf
.SetupViewportStateOffset
=
1436 instruction_ro_bo(brw
->batch
.bo
, brw
->sf
.vp_offset
);
1438 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1440 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1441 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1443 sf
.MaximumNumberofThreads
=
1444 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1446 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1448 sf
.DestinationOriginHorizontalBias
= 0.5;
1449 sf
.DestinationOriginVerticalBias
= 0.5;
1451 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1452 sf
.StatisticsEnable
= true;
1454 sf
.ViewportTransformEnable
= true;
1458 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1463 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1465 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1466 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1467 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1469 switch (ctx
->Polygon
.FrontMode
) {
1471 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1474 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1477 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1480 unreachable("not reached");
1483 switch (ctx
->Polygon
.BackMode
) {
1485 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1488 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1491 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1494 unreachable("not reached");
1497 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1498 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1500 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1501 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1502 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1505 sf
.ScissorRectangleEnable
= true;
1507 if (ctx
->Polygon
.CullFlag
) {
1508 switch (ctx
->Polygon
.CullFaceMode
) {
1510 sf
.CullMode
= CULLMODE_FRONT
;
1513 sf
.CullMode
= CULLMODE_BACK
;
1515 case GL_FRONT_AND_BACK
:
1516 sf
.CullMode
= CULLMODE_BOTH
;
1519 unreachable("not reached");
1522 sf
.CullMode
= CULLMODE_NONE
;
1526 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1533 if (brw
->is_cherryview
)
1534 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1536 sf
.LineWidth
= brw_get_line_width(brw
);
1538 sf
.LineWidth
= brw_get_line_width(brw
);
1541 if (ctx
->Line
.SmoothFlag
) {
1542 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1544 sf
.AntiAliasingEnable
= true;
1548 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1549 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1550 /* Clamp to the hardware limits */
1551 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1553 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1554 if (use_state_point_size(brw
))
1555 sf
.PointWidthSource
= State
;
1558 /* _NEW_POINT | _NEW_MULTISAMPLE */
1559 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1560 !ctx
->Point
.PointSprite
)
1561 sf
.SmoothPointEnable
= true;
1564 #if GEN_IS_G4X || GEN_GEN >= 5
1565 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1569 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1570 sf
.TriangleStripListProvokingVertexSelect
= 2;
1571 sf
.TriangleFanProvokingVertexSelect
= 2;
1572 sf
.LineStripListProvokingVertexSelect
= 1;
1574 sf
.TriangleFanProvokingVertexSelect
= 1;
1578 /* BRW_NEW_FS_PROG_DATA */
1579 const struct brw_wm_prog_data
*wm_prog_data
=
1580 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1582 sf
.AttributeSwizzleEnable
= true;
1583 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1586 * Window coordinates in an FBO are inverted, which means point
1587 * sprite origin must be inverted, too.
1589 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1590 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1592 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1595 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1596 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1598 uint32_t urb_entry_read_length
;
1599 uint32_t urb_entry_read_offset
;
1600 uint32_t point_sprite_enables
;
1601 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1602 &urb_entry_read_length
,
1603 &urb_entry_read_offset
);
1604 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1605 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1606 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1607 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1612 static const struct brw_tracked_state
genX(sf_state
) = {
1614 .mesa
= _NEW_LIGHT
|
1618 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1619 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1620 .brw
= BRW_NEW_BLORP
|
1621 BRW_NEW_VUE_MAP_GEOM_OUT
|
1622 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1623 BRW_NEW_PROGRAM_CACHE
|
1624 BRW_NEW_SF_PROG_DATA
|
1628 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1629 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1630 BRW_NEW_GS_PROG_DATA
|
1632 BRW_NEW_TES_PROG_DATA
1634 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1635 BRW_NEW_FRAGMENT_PROGRAM
1638 .emit
= genX(upload_sf
),
1641 /* ---------------------------------------------------------------------- */
1645 genX(upload_wm
)(struct brw_context
*brw
)
1647 struct gl_context
*ctx
= &brw
->ctx
;
1649 /* BRW_NEW_FS_PROG_DATA */
1650 const struct brw_wm_prog_data
*wm_prog_data
=
1651 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1653 UNUSED
bool writes_depth
=
1654 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1657 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1658 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1660 /* We can't fold this into gen6_upload_wm_push_constants(), because
1661 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1662 * (3DSTATE_CONSTANT_PS [DevSNB]):
1664 * "[DevSNB]: This packet must be followed by WM_STATE."
1666 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1667 if (wm_prog_data
->base
.nr_params
!= 0) {
1668 wmcp
.Buffer0Valid
= true;
1669 /* Pointer to the WM constant buffer. Covered by the set of
1670 * state flags from gen6_upload_wm_push_constants.
1672 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1673 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1678 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1679 wm
.StatisticsEnable
= true;
1680 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1681 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1684 if (wm_prog_data
->base
.use_alt_mode
)
1685 wm
.FloatingPointMode
= Alternate
;
1687 wm
.SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1688 wm
.BindingTableEntryCount
= wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1689 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1690 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1691 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1692 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1693 wm_prog_data
->base
.dispatch_grf_start_reg
;
1694 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1695 wm_prog_data
->dispatch_grf_start_reg_2
;
1696 wm
.KernelStartPointer0
= stage_state
->prog_offset
;
1697 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1698 wm_prog_data
->prog_offset_2
;
1699 wm
.DualSourceBlendEnable
=
1700 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1701 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1702 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1703 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1705 /* From the SNB PRM, volume 2 part 1, page 281:
1706 * "If the PS kernel does not need the Position XY Offsets
1707 * to compute a Position XY value, then this field should be
1708 * programmed to POSOFFSET_NONE."
1710 * "SW Recommendation: If the PS kernel needs the Position Offsets
1711 * to compute a Position XY value, this field should match Position
1712 * ZW Interpolation Mode to ensure a consistent position.xyzw
1714 * We only require XY sample offsets. So, this recommendation doesn't
1715 * look useful at the moment. We might need this in future.
1717 if (wm_prog_data
->uses_pos_offset
)
1718 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1720 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1722 if (wm_prog_data
->base
.total_scratch
) {
1723 wm
.ScratchSpaceBasePointer
=
1724 render_bo(stage_state
->scratch_bo
,
1725 ffs(stage_state
->per_thread_scratch
) - 11);
1728 wm
.PixelShaderComputedDepth
= writes_depth
;
1731 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1734 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1737 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1738 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1742 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1744 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1745 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1746 if (wm_prog_data
->uses_kill
||
1747 _mesa_is_alpha_test_enabled(ctx
) ||
1748 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1749 wm_prog_data
->uses_omask
) {
1750 wm
.PixelShaderKillsPixel
= true;
1753 /* _NEW_BUFFERS | _NEW_COLOR */
1754 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1755 wm_prog_data
->has_side_effects
|| wm
.PixelShaderKillsPixel
) {
1756 wm
.ThreadDispatchEnable
= true;
1758 if (multisampled_fbo
) {
1759 /* _NEW_MULTISAMPLE */
1760 if (ctx
->Multisample
.Enabled
)
1761 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1763 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1765 if (wm_prog_data
->persample_dispatch
)
1766 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1768 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1770 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1771 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1775 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1776 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1779 /* The "UAV access enable" bits are unnecessary on HSW because they only
1780 * seem to have an effect on the HW-assisted coherency mechanism which we
1781 * don't need, and the rasterization-related UAV_ONLY flag and the
1782 * DISPATCH_ENABLE bit can be set independently from it.
1783 * C.f. gen8_upload_ps_extra().
1785 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1789 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1790 wm_prog_data
->has_side_effects
)
1796 /* BRW_NEW_FS_PROG_DATA */
1797 if (wm_prog_data
->early_fragment_tests
)
1798 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1799 else if (wm_prog_data
->has_side_effects
)
1800 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1805 static const struct brw_tracked_state
genX(wm_state
) = {
1809 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1813 (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
1814 .brw
= BRW_NEW_BLORP
|
1815 BRW_NEW_FS_PROG_DATA
|
1816 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
1818 .emit
= genX(upload_wm
),
1822 /* ---------------------------------------------------------------------- */
1824 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1825 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
1826 pkt.SamplerCount = \
1827 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1828 pkt.BindingTableEntryCount = \
1829 stage_prog_data->binding_table.size_bytes / 4; \
1830 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
1832 if (stage_prog_data->total_scratch) { \
1833 pkt.ScratchSpaceBasePointer = \
1834 render_bo(stage_state->scratch_bo, 0); \
1835 pkt.PerThreadScratchSpace = \
1836 ffs(stage_state->per_thread_scratch) - 11; \
1839 pkt.DispatchGRFStartRegisterForURBData = \
1840 stage_prog_data->dispatch_grf_start_reg; \
1841 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1842 pkt.prefix##URBEntryReadOffset = 0; \
1844 pkt.StatisticsEnable = true; \
1848 genX(upload_vs_state
)(struct brw_context
*brw
)
1850 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
1851 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1852 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
1854 /* BRW_NEW_VS_PROG_DATA */
1855 const struct brw_vue_prog_data
*vue_prog_data
=
1856 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
1857 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
1859 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
1860 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
1863 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1864 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1866 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
1867 * command that causes the VS Function Enable to toggle. Pipeline
1868 * flush can be executed by sending a PIPE_CONTROL command with CS
1869 * stall bit set and a post sync operation.
1871 * We've already done such a flush at the start of state upload, so we
1872 * don't need to do another one here.
1874 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
1875 if (stage_state
->push_const_size
!= 0) {
1876 cvs
.Buffer0Valid
= true;
1877 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
1878 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1883 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
1884 gen7_emit_vs_workaround_flush(brw
);
1887 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
1889 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1890 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
1892 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1894 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1897 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
1898 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
1899 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
1901 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
1902 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1904 vs
.MaximumNumberofThreads
=
1905 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
1907 vs
.StatisticsEnable
= false;
1908 vs
.SamplerStatePointer
=
1909 instruction_ro_bo(brw
->batch
.bo
, stage_state
->sampler_offset
);
1913 /* Force single program flow on Ironlake. We cannot reliably get
1914 * all applications working without it. See:
1915 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
1917 * The most notable and reliably failing application is the Humus
1920 vs
.SingleProgramFlow
= true;
1921 vs
.SamplerCount
= 0; /* hardware requirement */
1925 vs
.SIMD8DispatchEnable
=
1926 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
1928 vs
.UserClipDistanceCullTestEnableBitmask
=
1929 vue_prog_data
->cull_distance_mask
;
1934 /* Based on my reading of the simulator, the VS constants don't get
1935 * pulled into the VS FF unit until an appropriate pipeline flush
1936 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
1937 * references to them into a little FIFO. The flushes are common,
1938 * but don't reliably happen between this and a 3DPRIMITIVE, causing
1939 * the primitive to use the wrong constants. Then the FIFO
1940 * containing the constant setup gets added to again on the next
1941 * constants change, and eventually when a flush does happen the
1942 * unit is overwhelmed by constant changes and dies.
1944 * To avoid this, send a PIPE_CONTROL down the line that will
1945 * update the unit immediately loading the constants. The flush
1946 * type bits here were those set by the STATE_BASE_ADDRESS whose
1947 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
1948 * bug reports that led to this workaround, and may be more than
1949 * what is strictly required to avoid the issue.
1951 brw_emit_pipe_control_flush(brw
,
1952 PIPE_CONTROL_DEPTH_STALL
|
1953 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1954 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
1958 static const struct brw_tracked_state
genX(vs_state
) = {
1960 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
1961 .brw
= BRW_NEW_BATCH
|
1964 BRW_NEW_VS_PROG_DATA
|
1965 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
1966 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1967 BRW_NEW_PROGRAM_CACHE
|
1968 BRW_NEW_SAMPLER_STATE_TABLE
|
1972 .emit
= genX(upload_vs_state
),
1975 /* ---------------------------------------------------------------------- */
1978 genX(upload_cc_viewport
)(struct brw_context
*brw
)
1980 struct gl_context
*ctx
= &brw
->ctx
;
1982 /* BRW_NEW_VIEWPORT_COUNT */
1983 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1985 struct GENX(CC_VIEWPORT
) ccv
;
1986 uint32_t cc_vp_offset
;
1988 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
1991 for (unsigned i
= 0; i
< viewport_count
; i
++) {
1992 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
1993 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
1994 if (ctx
->Transform
.DepthClamp
) {
1995 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
1996 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
1998 ccv
.MinimumDepth
= 0.0;
1999 ccv
.MaximumDepth
= 1.0;
2001 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2002 cc_map
+= GENX(CC_VIEWPORT_length
);
2006 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2007 ptr
.CCViewportPointer
= cc_vp_offset
;
2010 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2011 vp
.CCViewportStateChange
= 1;
2012 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2015 brw
->cc
.vp_offset
= cc_vp_offset
;
2016 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2020 const struct brw_tracked_state
genX(cc_vp
) = {
2022 .mesa
= _NEW_TRANSFORM
|
2024 .brw
= BRW_NEW_BATCH
|
2026 BRW_NEW_VIEWPORT_COUNT
,
2028 .emit
= genX(upload_cc_viewport
)
2031 /* ---------------------------------------------------------------------- */
2034 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2035 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2036 struct GENX(SCISSOR_RECT
) *sc
)
2040 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2041 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2042 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2043 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2044 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2046 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2047 /* If the scissor was out of bounds and got clamped to 0 width/height
2048 * at the bounds, the subtraction of 1 from maximums could produce a
2049 * negative number and thus not clip anything. Instead, just provide
2050 * a min > max scissor inside the bounds, which produces the expected
2053 sc
->ScissorRectangleXMin
= 1;
2054 sc
->ScissorRectangleXMax
= 0;
2055 sc
->ScissorRectangleYMin
= 1;
2056 sc
->ScissorRectangleYMax
= 0;
2057 } else if (render_to_fbo
) {
2058 /* texmemory: Y=0=bottom */
2059 sc
->ScissorRectangleXMin
= bbox
[0];
2060 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2061 sc
->ScissorRectangleYMin
= bbox
[2];
2062 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2064 /* memory: Y=0=top */
2065 sc
->ScissorRectangleXMin
= bbox
[0];
2066 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2067 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2068 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2074 genX(upload_scissor_state
)(struct brw_context
*brw
)
2076 struct gl_context
*ctx
= &brw
->ctx
;
2077 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2078 struct GENX(SCISSOR_RECT
) scissor
;
2079 uint32_t scissor_state_offset
;
2080 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2081 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2082 uint32_t *scissor_map
;
2084 /* BRW_NEW_VIEWPORT_COUNT */
2085 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2087 scissor_map
= brw_state_batch(
2088 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2089 32, &scissor_state_offset
);
2091 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2093 /* The scissor only needs to handle the intersection of drawable and
2094 * scissor rect. Clipping to the boundaries of static shared buffers
2095 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2097 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2098 * inclusive but max is exclusive.
2100 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2101 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2102 GENX(SCISSOR_RECT_pack
)(
2103 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2106 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2107 ptr
.ScissorRectPointer
= scissor_state_offset
;
2111 static const struct brw_tracked_state
genX(scissor_state
) = {
2113 .mesa
= _NEW_BUFFERS
|
2116 .brw
= BRW_NEW_BATCH
|
2118 BRW_NEW_VIEWPORT_COUNT
,
2120 .emit
= genX(upload_scissor_state
),
2124 /* ---------------------------------------------------------------------- */
2127 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2128 float m00
, float m11
, float m30
, float m31
,
2129 float *xmin
, float *xmax
,
2130 float *ymin
, float *ymax
)
2132 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2133 * Strips and Fans documentation:
2135 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2136 * fixed-point "guardband" range supported by the rasterization hardware"
2140 * "In almost all circumstances, if an object’s vertices are actually
2141 * modified by this clamping (i.e., had X or Y coordinates outside of
2142 * the guardband extent the rendered object will not match the intended
2143 * result. Therefore software should take steps to ensure that this does
2144 * not happen - e.g., by clipping objects such that they do not exceed
2145 * these limits after the Drawing Rectangle is applied."
2147 * I believe the fundamental restriction is that the rasterizer (in
2148 * the SF/WM stages) have a limit on the number of pixels that can be
2149 * rasterized. We need to ensure any coordinates beyond the rasterizer
2150 * limit are handled by the clipper. So effectively that limit becomes
2151 * the clipper's guardband size.
2153 * It goes on to say:
2155 * "In addition, in order to be correctly rendered, objects must have a
2156 * screenspace bounding box not exceeding 8K in the X or Y direction.
2157 * This additional restriction must also be comprehended by software,
2158 * i.e., enforced by use of clipping."
2160 * This makes no sense. Gen7+ hardware supports 16K render targets,
2161 * and you definitely need to be able to draw polygons that fill the
2162 * surface. Our assumption is that the rasterizer was limited to 8K
2163 * on Sandybridge, which only supports 8K surfaces, and it was actually
2164 * increased to 16K on Ivybridge and later.
2166 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2168 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2170 if (m00
!= 0 && m11
!= 0) {
2171 /* First, we compute the screen-space render area */
2172 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2173 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2174 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2175 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2177 /* We want the guardband to be centered on that */
2178 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2179 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2180 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2181 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2183 /* Now we need it in native device coordinates */
2184 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2185 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2186 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2187 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2189 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2190 * flipped upside-down. X should be fine though.
2192 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2193 *xmin
= ndc_gb_xmin
;
2194 *xmax
= ndc_gb_xmax
;
2195 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2196 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2198 /* The viewport scales to 0, so nothing will be rendered. */
2207 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2209 struct gl_context
*ctx
= &brw
->ctx
;
2210 float y_scale
, y_bias
;
2212 /* BRW_NEW_VIEWPORT_COUNT */
2213 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2216 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2217 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2218 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2222 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2223 uint32_t sf_clip_vp_offset
;
2224 uint32_t *sf_clip_map
=
2225 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2226 64, &sf_clip_vp_offset
);
2228 struct GENX(SF_VIEWPORT
) sfv
;
2229 struct GENX(CLIP_VIEWPORT
) clv
;
2230 uint32_t sf_vp_offset
, clip_vp_offset
;
2232 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2234 uint32_t *clip_map
=
2235 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2236 32, &clip_vp_offset
);
2240 if (render_to_fbo
) {
2245 y_bias
= (float)fb_height
;
2248 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2249 /* _NEW_VIEWPORT: Guardband Clipping */
2250 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2251 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2253 sfv
.ViewportMatrixElementm00
= scale
[0];
2254 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2255 sfv
.ViewportMatrixElementm22
= scale
[2],
2256 sfv
.ViewportMatrixElementm30
= translate
[0],
2257 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2258 sfv
.ViewportMatrixElementm32
= translate
[2],
2259 brw_calculate_guardband_size(fb_width
, fb_height
,
2260 sfv
.ViewportMatrixElementm00
,
2261 sfv
.ViewportMatrixElementm11
,
2262 sfv
.ViewportMatrixElementm30
,
2263 sfv
.ViewportMatrixElementm31
,
2264 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2267 clv
.XMinClipGuardband
= gb_xmin
;
2268 clv
.XMaxClipGuardband
= gb_xmax
;
2269 clv
.YMinClipGuardband
= gb_ymin
;
2270 clv
.YMaxClipGuardband
= gb_ymax
;
2273 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2274 &sfv
.ScissorRectangle
);
2276 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2277 * The hardware will take the intersection of the drawing rectangle,
2278 * scissor rectangle, and the viewport extents. We don't need to be
2279 * smart, and can therefore just program the viewport extents.
2281 const float viewport_Xmax
=
2282 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2283 const float viewport_Ymax
=
2284 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2286 if (render_to_fbo
) {
2287 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2288 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2289 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2290 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2292 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2293 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2294 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2295 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2300 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2301 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2303 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2304 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2305 sf_map
+= GENX(SF_VIEWPORT_length
);
2306 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2311 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2312 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2315 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2316 vp
.SFViewportStateChange
= 1;
2317 vp
.CLIPViewportStateChange
= 1;
2318 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2319 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2322 brw
->sf
.vp_offset
= sf_vp_offset
;
2323 brw
->clip
.vp_offset
= clip_vp_offset
;
2324 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2328 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2330 .mesa
= _NEW_BUFFERS
|
2332 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2333 .brw
= BRW_NEW_BATCH
|
2335 BRW_NEW_VIEWPORT_COUNT
,
2337 .emit
= genX(upload_sf_clip_viewport
),
2340 /* ---------------------------------------------------------------------- */
2344 genX(upload_gs_state
)(struct brw_context
*brw
)
2346 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2347 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2348 /* BRW_NEW_GEOMETRY_PROGRAM */
2349 bool active
= brw
->geometry_program
;
2351 /* BRW_NEW_GS_PROG_DATA */
2352 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2353 const struct brw_vue_prog_data
*vue_prog_data
=
2354 brw_vue_prog_data(stage_prog_data
);
2356 const struct brw_gs_prog_data
*gs_prog_data
=
2357 brw_gs_prog_data(stage_prog_data
);
2361 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2362 if (active
&& stage_state
->push_const_size
!= 0) {
2363 cgs
.Buffer0Valid
= true;
2364 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2365 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2370 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2372 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2373 * Geometry > Geometry Shader > State:
2375 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2376 * whole fixed function pipeline when the GS enable changes value in
2379 * The hardware architects have clarified that in this context "flush the
2380 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2383 if (brw
->gt
== 2 && brw
->gs
.enabled
!= active
)
2384 gen7_emit_cs_stall_flush(brw
);
2388 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2389 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2392 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2393 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2394 gs
.ControlDataHeaderSize
=
2395 gs_prog_data
->control_data_header_size_hwords
;
2397 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2398 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2400 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2402 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2405 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2406 * Ivy Bridge and Haswell.
2408 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2409 * strip to be delivered to the geometry shader in an order that does
2410 * not strictly follow the OpenGL spec, but preserves triangle
2411 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2412 * the geometry shader sees triangles:
2414 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2416 * (Clearing the bit is even worse, because it fails to preserve
2419 * Triangle strips with adjacency always ordered in a way that preserves
2420 * triangle orientation but does not strictly follow the OpenGL spec,
2421 * regardless of the setting of this bit.
2423 * On Haswell, both triangle strips and triangle strips with adjacency
2424 * are always ordered in a way that preserves triangle orientation.
2425 * Setting this bit causes the ordering to strictly follow the OpenGL
2428 * So in either case we want to set the bit. Unfortunately on Ivy
2429 * Bridge this will get the order close to correct but not perfect.
2431 gs
.ReorderMode
= TRAILING
;
2432 gs
.MaximumNumberofThreads
=
2433 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2434 : (devinfo
->max_gs_threads
- 1);
2437 gs
.SOStatisticsEnable
= true;
2438 gs
.RenderingEnabled
= 1;
2439 if (brw
->geometry_program
->info
.has_transform_feedback_varyings
)
2440 gs
.SVBIPayloadEnable
= true;
2442 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2443 * was previously done for gen6.
2445 * TODO: test with both disabled to see if the HW is behaving
2446 * as expected, like in gen7.
2448 gs
.SingleProgramFlow
= true;
2449 gs
.VectorMaskEnable
= true;
2453 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2455 if (gs_prog_data
->static_vertex_count
!= -1) {
2456 gs
.StaticOutput
= true;
2457 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2459 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2461 gs
.UserClipDistanceCullTestEnableBitmask
=
2462 vue_prog_data
->cull_distance_mask
;
2464 const int urb_entry_write_offset
= 1;
2465 const uint32_t urb_entry_output_length
=
2466 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2467 urb_entry_write_offset
;
2469 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2470 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2474 } else if (brw
->ff_gs
.prog_active
) {
2475 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
2476 * program. This function provides the needed 3DSTATE_GS for this.
2478 upload_gs_state_for_tf(brw
);
2481 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2482 gs
.StatisticsEnable
= true;
2484 gs
.RenderingEnabled
= true;
2488 gs
.DispatchGRFStartRegisterForURBData
= 1;
2490 gs
.IncludeVertexHandles
= true;
2496 brw
->gs
.enabled
= active
;
2500 static const struct brw_tracked_state
genX(gs_state
) = {
2502 .mesa
= (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
2503 .brw
= BRW_NEW_BATCH
|
2506 BRW_NEW_GEOMETRY_PROGRAM
|
2507 BRW_NEW_GS_PROG_DATA
|
2508 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2510 .emit
= genX(upload_gs_state
),
2514 /* ---------------------------------------------------------------------- */
2516 UNUSED
static GLenum
2517 fix_dual_blend_alpha_to_one(GLenum function
)
2523 case GL_ONE_MINUS_SRC1_ALPHA
:
2530 #define blend_factor(x) brw_translate_blend_factor(x)
2531 #define blend_eqn(x) brw_translate_blend_equation(x)
2535 genX(upload_blend_state
)(struct brw_context
*brw
)
2537 struct gl_context
*ctx
= &brw
->ctx
;
2540 /* We need at least one BLEND_STATE written, because we might do
2541 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2542 * for computed depth or alpha test), which will do an FB write
2543 * with render target 0, which will reference BLEND_STATE[0] for
2544 * alpha test enable.
2546 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2547 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2548 nr_draw_buffers
= 1;
2550 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2552 size
+= GENX(BLEND_STATE_length
) * 4;
2555 uint32_t *blend_map
;
2556 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2559 struct GENX(BLEND_STATE
) blend
= { 0 };
2562 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2563 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2566 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2567 * "If drawbuffer zero is not NONE and the buffer it references has an
2568 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2569 * operations are skipped."
2571 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2572 /* _NEW_MULTISAMPLE */
2573 if (_mesa_is_multisample_enabled(ctx
)) {
2574 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2575 blend
.AlphaToCoverageEnable
= true;
2576 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2578 if (ctx
->Multisample
.SampleAlphaToOne
)
2579 blend
.AlphaToOneEnable
= true;
2583 if (ctx
->Color
.AlphaEnabled
) {
2584 blend
.AlphaTestEnable
= true;
2585 blend
.AlphaTestFunction
=
2586 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2589 if (ctx
->Color
.DitherFlag
) {
2590 blend
.ColorDitherEnable
= true;
2595 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2596 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2602 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2604 /* Used for implementing the following bit of GL_EXT_texture_integer:
2605 * "Per-fragment operations that require floating-point color
2606 * components, including multisample alpha operations, alpha test,
2607 * blending, and dithering, have no effect when the corresponding
2608 * colors are written to an integer color buffer."
2610 bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2613 if (ctx
->Color
.ColorLogicOpEnabled
) {
2614 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2615 : GL_UNSIGNED_NORMALIZED
;
2616 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2617 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2618 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2620 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2621 _mesa_enum_to_string(rb_type
));
2622 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2623 entry
.LogicOpEnable
= true;
2624 entry
.LogicOpFunction
=
2625 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2627 } else if (ctx
->Color
.BlendEnabled
& (1 << i
) && !integer
&&
2628 !ctx
->Color
._AdvancedBlendMode
) {
2629 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2630 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2631 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2632 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2633 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2634 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2636 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2637 srcRGB
= dstRGB
= GL_ONE
;
2639 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2640 srcA
= dstA
= GL_ONE
;
2642 /* Due to hardware limitations, the destination may have information
2643 * in an alpha channel even when the format specifies no alpha
2644 * channel. In order to avoid getting any incorrect blending due to
2645 * that alpha channel, coerce the blend factors to values that will
2646 * not read the alpha channel, but will instead use the correct
2647 * implicit value for alpha.
2649 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2650 GL_TEXTURE_ALPHA_TYPE
)) {
2651 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2652 srcA
= brw_fix_xRGB_alpha(srcA
);
2653 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2654 dstA
= brw_fix_xRGB_alpha(dstA
);
2657 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2658 * "If Dual Source Blending is enabled, this bit must be disabled."
2660 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2661 * and leave it enabled anyway.
2663 if (ctx
->Color
.Blend
[i
]._UsesDualSrc
&& blend
.AlphaToOneEnable
) {
2664 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2665 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2666 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2667 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2670 entry
.ColorBufferBlendEnable
= true;
2671 entry
.DestinationBlendFactor
= blend_factor(dstRGB
);
2672 entry
.SourceBlendFactor
= blend_factor(srcRGB
);
2673 entry
.DestinationAlphaBlendFactor
= blend_factor(dstA
);
2674 entry
.SourceAlphaBlendFactor
= blend_factor(srcA
);
2675 entry
.ColorBlendFunction
= blend_eqn(eqRGB
);
2676 entry
.AlphaBlendFunction
= blend_eqn(eqA
);
2678 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2679 blend
.IndependentAlphaBlendEnable
= true;
2682 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2683 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2685 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2686 * clamping in the fragment shader. For its clamping of
2687 * blending, the spec says:
2689 * "RESOLVED: For fixed-point color buffers, the inputs and
2690 * the result of the blending equation are clamped. For
2691 * floating-point color buffers, no clamping occurs."
2693 * So, generally, we want clamping to the render target's range.
2694 * And, good news, the hardware tables for both pre- and
2695 * post-blend color clamping are either ignored, or any are
2696 * allowed, or clamping is required but RT range clamping is a
2699 entry
.PreBlendColorClampEnable
= true;
2700 entry
.PostBlendColorClampEnable
= true;
2701 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2703 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2704 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2705 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2706 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2709 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2711 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2717 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2721 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2722 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2723 ptr
.BLEND_STATEChange
= true;
2726 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2727 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2729 ptr
.BlendStatePointerValid
= true;
2735 static const struct brw_tracked_state
genX(blend_state
) = {
2737 .mesa
= _NEW_BUFFERS
|
2740 .brw
= BRW_NEW_BATCH
|
2742 BRW_NEW_STATE_BASE_ADDRESS
,
2744 .emit
= genX(upload_blend_state
),
2748 /* ---------------------------------------------------------------------- */
2751 UNUSED
static const uint32_t push_constant_opcodes
[] = {
2752 [MESA_SHADER_VERTEX
] = 21,
2753 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2754 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2755 [MESA_SHADER_GEOMETRY
] = 22,
2756 [MESA_SHADER_FRAGMENT
] = 23,
2757 [MESA_SHADER_COMPUTE
] = 0,
2761 upload_constant_state(struct brw_context
*brw
,
2762 struct brw_stage_state
*stage_state
,
2763 bool active
, uint32_t stage
)
2765 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
2766 active
= active
&& stage_state
->push_const_size
!= 0;
2768 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2769 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2771 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2772 pkt
.ConstantBody
.ReadLength
[2] = stage_state
->push_const_size
;
2773 pkt
.ConstantBody
.Buffer
[2] =
2774 render_ro_bo(brw
->curbe
.curbe_bo
, stage_state
->push_const_offset
);
2776 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
2777 pkt
.ConstantBody
.Buffer
[0].offset
=
2778 stage_state
->push_const_offset
| mocs
;
2783 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
2789 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
2791 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2793 /* _BRW_NEW_VERTEX_PROGRAM */
2794 const struct brw_program
*vp
= brw_program_const(brw
->vertex_program
);
2795 /* BRW_NEW_VS_PROG_DATA */
2796 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
2798 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
2799 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
2802 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !brw
->is_baytrail
)
2803 gen7_emit_vs_workaround_flush(brw
);
2805 upload_constant_state(brw
, stage_state
, true /* active */,
2806 MESA_SHADER_VERTEX
);
2810 static const struct brw_tracked_state
genX(vs_push_constants
) = {
2812 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2814 .brw
= BRW_NEW_BATCH
|
2816 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2817 BRW_NEW_VERTEX_PROGRAM
|
2818 BRW_NEW_VS_PROG_DATA
,
2820 .emit
= genX(upload_vs_push_constants
),
2824 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
2826 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2828 /* BRW_NEW_GEOMETRY_PROGRAM */
2829 const struct brw_program
*gp
= brw_program_const(brw
->geometry_program
);
2832 /* BRW_NEW_GS_PROG_DATA */
2833 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
2835 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
2836 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
2840 upload_constant_state(brw
, stage_state
, gp
, MESA_SHADER_GEOMETRY
);
2844 static const struct brw_tracked_state
genX(gs_push_constants
) = {
2846 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2848 .brw
= BRW_NEW_BATCH
|
2850 BRW_NEW_GEOMETRY_PROGRAM
|
2851 BRW_NEW_GS_PROG_DATA
|
2852 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2854 .emit
= genX(upload_gs_push_constants
),
2858 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
2860 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
2861 /* BRW_NEW_FRAGMENT_PROGRAM */
2862 const struct brw_program
*fp
= brw_program_const(brw
->fragment_program
);
2863 /* BRW_NEW_FS_PROG_DATA */
2864 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
2866 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
2868 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
2871 upload_constant_state(brw
, stage_state
, true, MESA_SHADER_FRAGMENT
);
2875 static const struct brw_tracked_state
genX(wm_push_constants
) = {
2877 .mesa
= _NEW_PROGRAM_CONSTANTS
,
2878 .brw
= BRW_NEW_BATCH
|
2880 BRW_NEW_FRAGMENT_PROGRAM
|
2881 BRW_NEW_FS_PROG_DATA
|
2882 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2884 .emit
= genX(upload_wm_push_constants
),
2888 /* ---------------------------------------------------------------------- */
2892 genX(determine_sample_mask
)(struct brw_context
*brw
)
2894 struct gl_context
*ctx
= &brw
->ctx
;
2895 float coverage
= 1.0f
;
2896 float coverage_invert
= false;
2897 unsigned sample_mask
= ~0u;
2899 /* BRW_NEW_NUM_SAMPLES */
2900 unsigned num_samples
= brw
->num_samples
;
2902 if (_mesa_is_multisample_enabled(ctx
)) {
2903 if (ctx
->Multisample
.SampleCoverage
) {
2904 coverage
= ctx
->Multisample
.SampleCoverageValue
;
2905 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
2907 if (ctx
->Multisample
.SampleMask
) {
2908 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
2912 if (num_samples
> 1) {
2913 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
2914 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
2915 if (coverage_invert
)
2916 coverage_bits
^= (1 << num_samples
) - 1;
2917 return coverage_bits
& sample_mask
;
2924 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
2925 unsigned num_samples
)
2927 assert(brw
->num_samples
<= 16);
2929 unsigned log2_samples
= ffs(MAX2(num_samples
, 1)) - 1;
2931 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
2932 multi
.PixelLocation
= CENTER
;
2933 multi
.NumberofMultisamples
= log2_samples
;
2935 GEN_SAMPLE_POS_4X(multi
.Sample
);
2937 switch (num_samples
) {
2939 GEN_SAMPLE_POS_1X(multi
.Sample
);
2942 GEN_SAMPLE_POS_2X(multi
.Sample
);
2945 GEN_SAMPLE_POS_4X(multi
.Sample
);
2948 GEN_SAMPLE_POS_8X(multi
.Sample
);
2958 genX(upload_multisample_state
)(struct brw_context
*brw
)
2960 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
2962 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
2963 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
2967 static const struct brw_tracked_state
genX(multisample_state
) = {
2969 .mesa
= _NEW_MULTISAMPLE
,
2970 .brw
= BRW_NEW_BLORP
|
2972 BRW_NEW_NUM_SAMPLES
,
2974 .emit
= genX(upload_multisample_state
)
2978 /* ---------------------------------------------------------------------- */
2982 genX(upload_color_calc_state
)(struct brw_context
*brw
)
2984 struct gl_context
*ctx
= &brw
->ctx
;
2986 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
2988 cc
.AlphaTestFormat
= ALPHATEST_UNORM8
;
2989 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
2990 ctx
->Color
.AlphaRef
);
2994 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
2995 cc
.BackfaceStencilReferenceValue
=
2996 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3000 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3001 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3002 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3003 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3006 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3007 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3009 ptr
.ColorCalcStatePointerValid
= true;
3014 static const struct brw_tracked_state
genX(color_calc_state
) = {
3016 .mesa
= _NEW_COLOR
|
3018 .brw
= BRW_NEW_BATCH
|
3021 BRW_NEW_STATE_BASE_ADDRESS
,
3023 .emit
= genX(upload_color_calc_state
),
3028 /* ---------------------------------------------------------------------- */
3032 genX(upload_sbe
)(struct brw_context
*brw
)
3034 struct gl_context
*ctx
= &brw
->ctx
;
3035 /* BRW_NEW_FS_PROG_DATA */
3036 const struct brw_wm_prog_data
*wm_prog_data
=
3037 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3039 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3041 #define attr_overrides sbe.Attribute
3043 uint32_t urb_entry_read_length
;
3044 uint32_t urb_entry_read_offset
;
3045 uint32_t point_sprite_enables
;
3047 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3048 sbe
.AttributeSwizzleEnable
= true;
3049 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3052 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3056 * Window coordinates in an FBO are inverted, which means point
3057 * sprite origin must be inverted.
3059 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3060 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3062 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3064 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3065 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3066 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3067 * BRW_NEW_VUE_MAP_GEOM_OUT
3069 genX(calculate_attr_overrides
)(brw
,
3071 &point_sprite_enables
,
3072 &urb_entry_read_length
,
3073 &urb_entry_read_offset
);
3075 /* Typically, the URB entry read length and offset should be programmed
3076 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3077 * stage which produces geometry. However, we don't know the proper
3078 * value until we call calculate_attr_overrides().
3080 * To fit with our existing code, we override the inherited values and
3081 * specify it here directly, as we did on previous generations.
3083 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3084 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3085 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3086 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3089 sbe
.ForceVertexURBEntryReadLength
= true;
3090 sbe
.ForceVertexURBEntryReadOffset
= true;
3094 /* prepare the active component dwords */
3095 int input_index
= 0;
3096 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
3097 if (!(brw
->fragment_program
->info
.inputs_read
&
3098 BITFIELD64_BIT(attr
))) {
3102 assert(input_index
< 32);
3104 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3111 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3112 for (int i
= 0; i
< 16; i
++)
3113 sbes
.Attribute
[i
] = attr_overrides
[i
];
3117 #undef attr_overrides
3120 static const struct brw_tracked_state
genX(sbe_state
) = {
3122 .mesa
= _NEW_BUFFERS
|
3127 .brw
= BRW_NEW_BLORP
|
3129 BRW_NEW_FRAGMENT_PROGRAM
|
3130 BRW_NEW_FS_PROG_DATA
|
3131 BRW_NEW_GS_PROG_DATA
|
3132 BRW_NEW_TES_PROG_DATA
|
3133 BRW_NEW_VUE_MAP_GEOM_OUT
|
3134 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3137 .emit
= genX(upload_sbe
),
3141 /* ---------------------------------------------------------------------- */
3145 * Outputs the 3DSTATE_SO_DECL_LIST command.
3147 * The data output is a series of 64-bit entries containing a SO_DECL per
3148 * stream. We only have one stream of rendering coming out of the GS unit, so
3149 * we only emit stream 0 (low 16 bits) SO_DECLs.
3152 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3153 const struct brw_vue_map
*vue_map
)
3155 struct gl_context
*ctx
= &brw
->ctx
;
3156 /* BRW_NEW_TRANSFORM_FEEDBACK */
3157 struct gl_transform_feedback_object
*xfb_obj
=
3158 ctx
->TransformFeedback
.CurrentObject
;
3159 const struct gl_transform_feedback_info
*linked_xfb_info
=
3160 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3161 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3162 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3163 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3164 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3166 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3168 memset(so_decl
, 0, sizeof(so_decl
));
3170 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3171 * command feels strange -- each dword pair contains a SO_DECL per stream.
3173 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3174 const struct gl_transform_feedback_output
*output
=
3175 &linked_xfb_info
->Outputs
[i
];
3176 const int buffer
= output
->OutputBuffer
;
3177 const int varying
= output
->OutputRegister
;
3178 const unsigned stream_id
= output
->StreamId
;
3179 assert(stream_id
< MAX_VERTEX_STREAMS
);
3181 buffer_mask
[stream_id
] |= 1 << buffer
;
3183 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3185 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3186 * array. Instead, it simply increments DstOffset for the following
3187 * input by the number of components that should be skipped.
3189 * Our hardware is unusual in that it requires us to program SO_DECLs
3190 * for fake "hole" components, rather than simply taking the offset
3191 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3192 * program as many size = 4 holes as we can, then a final hole to
3193 * accommodate the final 1, 2, or 3 remaining.
3195 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3197 while (skip_components
> 0) {
3198 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3200 .OutputBufferSlot
= output
->OutputBuffer
,
3201 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3203 skip_components
-= 4;
3206 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3208 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3209 .OutputBufferSlot
= output
->OutputBuffer
,
3210 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3212 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3215 if (decls
[stream_id
] > max_decls
)
3216 max_decls
= decls
[stream_id
];
3220 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3221 .StreamtoBufferSelects0
= buffer_mask
[0],
3222 .StreamtoBufferSelects1
= buffer_mask
[1],
3223 .StreamtoBufferSelects2
= buffer_mask
[2],
3224 .StreamtoBufferSelects3
= buffer_mask
[3],
3225 .NumEntries0
= decls
[0],
3226 .NumEntries1
= decls
[1],
3227 .NumEntries2
= decls
[2],
3228 .NumEntries3
= decls
[3]);
3230 for (int i
= 0; i
< max_decls
; i
++) {
3231 GENX(SO_DECL_ENTRY_pack
)(
3232 brw
, dw
+ 2 + i
* 2,
3233 &(struct GENX(SO_DECL_ENTRY
)) {
3234 .Stream0Decl
= so_decl
[0][i
],
3235 .Stream1Decl
= so_decl
[1][i
],
3236 .Stream2Decl
= so_decl
[2][i
],
3237 .Stream3Decl
= so_decl
[3][i
],
3243 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3245 struct gl_context
*ctx
= &brw
->ctx
;
3246 /* BRW_NEW_TRANSFORM_FEEDBACK */
3247 struct gl_transform_feedback_object
*xfb_obj
=
3248 ctx
->TransformFeedback
.CurrentObject
;
3250 const struct gl_transform_feedback_info
*linked_xfb_info
=
3251 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3253 struct brw_transform_feedback_object
*brw_obj
=
3254 (struct brw_transform_feedback_object
*) xfb_obj
;
3255 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3258 /* Set up the up to 4 output buffers. These are the ranges defined in the
3259 * gl_transform_feedback_object.
3261 for (int i
= 0; i
< 4; i
++) {
3262 struct intel_buffer_object
*bufferobj
=
3263 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3266 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3267 sob
.SOBufferIndex
= i
;
3272 uint32_t start
= xfb_obj
->Offset
[i
];
3273 assert(start
% 4 == 0);
3274 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3276 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
);
3277 assert(end
<= bo
->size
);
3279 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3280 sob
.SOBufferIndex
= i
;
3282 sob
.SurfaceBaseAddress
= render_bo(bo
, start
);
3284 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3285 sob
.SurfaceEndAddress
= render_bo(bo
, end
);
3287 sob
.SOBufferEnable
= true;
3288 sob
.StreamOffsetWriteEnable
= true;
3289 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3290 sob
.SOBufferMOCS
= mocs_wb
;
3292 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3293 sob
.StreamOutputBufferOffsetAddress
=
3294 instruction_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3296 if (brw_obj
->zero_offsets
) {
3297 /* Zero out the offset and write that to offset_bo */
3298 sob
.StreamOffset
= 0;
3300 /* Use offset_bo as the "Stream Offset." */
3301 sob
.StreamOffset
= 0xFFFFFFFF;
3308 brw_obj
->zero_offsets
= false;
3313 query_active(struct gl_query_object
*q
)
3315 return q
&& q
->Active
;
3319 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3320 const struct brw_vue_map
*vue_map
)
3322 struct gl_context
*ctx
= &brw
->ctx
;
3323 /* BRW_NEW_TRANSFORM_FEEDBACK */
3324 struct gl_transform_feedback_object
*xfb_obj
=
3325 ctx
->TransformFeedback
.CurrentObject
;
3327 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3329 int urb_entry_read_offset
= 0;
3330 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3331 urb_entry_read_offset
;
3333 sos
.SOFunctionEnable
= true;
3334 sos
.SOStatisticsEnable
= true;
3336 /* BRW_NEW_RASTERIZER_DISCARD */
3337 if (ctx
->RasterDiscard
) {
3338 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3339 sos
.RenderingDisable
= true;
3341 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3342 "query active relies on the clipper.");
3347 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3348 sos
.ReorderMode
= TRAILING
;
3351 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3352 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3353 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3354 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3356 const struct gl_transform_feedback_info
*linked_xfb_info
=
3357 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3358 /* Set buffer pitches; 0 means unbound. */
3359 if (xfb_obj
->Buffers
[0])
3360 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3361 if (xfb_obj
->Buffers
[1])
3362 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3363 if (xfb_obj
->Buffers
[2])
3364 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3365 if (xfb_obj
->Buffers
[3])
3366 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3369 /* We always read the whole vertex. This could be reduced at some
3370 * point by reading less and offsetting the register index in the
3373 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3374 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3375 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3376 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3377 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3378 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3379 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3380 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3386 genX(upload_sol
)(struct brw_context
*brw
)
3388 struct gl_context
*ctx
= &brw
->ctx
;
3389 /* BRW_NEW_TRANSFORM_FEEDBACK */
3390 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3393 genX(upload_3dstate_so_buffers
)(brw
);
3395 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3396 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3399 /* Finally, set up the SOL stage. This command must always follow updates to
3400 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3401 * MMIO register updates (current performed by the kernel at each batch
3404 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3407 static const struct brw_tracked_state
genX(sol_state
) = {
3410 .brw
= BRW_NEW_BATCH
|
3412 BRW_NEW_RASTERIZER_DISCARD
|
3413 BRW_NEW_VUE_MAP_GEOM_OUT
|
3414 BRW_NEW_TRANSFORM_FEEDBACK
,
3416 .emit
= genX(upload_sol
),
3420 /* ---------------------------------------------------------------------- */
3424 genX(upload_ps
)(struct brw_context
*brw
)
3426 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3427 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3429 /* BRW_NEW_FS_PROG_DATA */
3430 const struct brw_wm_prog_data
*prog_data
=
3431 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3432 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3437 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3438 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3439 * incorrect for subspans where some of the pixels are unlit. We believe
3440 * the bit just didn't take effect in previous generations.
3442 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3445 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3447 /* BRW_NEW_FS_PROG_DATA */
3448 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3450 if (prog_data
->base
.use_alt_mode
)
3451 ps
.FloatingPointMode
= Alternate
;
3453 /* Haswell requires the sample mask to be set in this packet as well as
3454 * in 3DSTATE_SAMPLE_MASK; the values should match.
3457 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3459 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3462 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3463 * it implicitly scales for different GT levels (which have some # of
3466 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3469 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3471 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3473 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3476 if (prog_data
->base
.nr_params
> 0)
3477 ps
.PushConstantEnable
= true;
3480 /* From the IVB PRM, volume 2 part 1, page 287:
3481 * "This bit is inserted in the PS payload header and made available to
3482 * the DataPort (either via the message header or via header bypass) to
3483 * indicate that oMask data (one or two phases) is included in Render
3484 * Target Write messages. If present, the oMask data is used to mask off
3487 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3489 /* The hardware wedges if you have this bit set but don't turn on any
3490 * dual source blend factors.
3492 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3494 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3495 (ctx
->Color
.BlendEnabled
& 1) &&
3496 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3498 /* BRW_NEW_FS_PROG_DATA */
3499 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3502 /* From the documentation for this packet:
3503 * "If the PS kernel does not need the Position XY Offsets to
3504 * compute a Position Value, then this field should be programmed
3505 * to POSOFFSET_NONE."
3507 * "SW Recommendation: If the PS kernel needs the Position Offsets
3508 * to compute a Position XY value, this field should match Position
3509 * ZW Interpolation Mode to ensure a consistent position.xyzw
3512 * We only require XY sample offsets. So, this recommendation doesn't
3513 * look useful at the moment. We might need this in future.
3515 if (prog_data
->uses_pos_offset
)
3516 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3518 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3520 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3521 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3522 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3523 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3524 prog_data
->base
.dispatch_grf_start_reg
;
3525 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3526 prog_data
->dispatch_grf_start_reg_2
;
3528 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3529 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3530 prog_data
->prog_offset_2
;
3532 if (prog_data
->base
.total_scratch
) {
3533 ps
.ScratchSpaceBasePointer
=
3534 render_bo(stage_state
->scratch_bo
,
3535 ffs(stage_state
->per_thread_scratch
) - 11);
3540 static const struct brw_tracked_state
genX(ps_state
) = {
3542 .mesa
= _NEW_MULTISAMPLE
|
3543 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3546 .brw
= BRW_NEW_BATCH
|
3548 BRW_NEW_FS_PROG_DATA
,
3550 .emit
= genX(upload_ps
),
3554 /* ---------------------------------------------------------------------- */
3558 genX(upload_hs_state
)(struct brw_context
*brw
)
3560 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3561 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3562 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3563 const struct brw_vue_prog_data
*vue_prog_data
=
3564 brw_vue_prog_data(stage_prog_data
);
3566 /* BRW_NEW_TES_PROG_DATA */
3567 struct brw_tcs_prog_data
*tcs_prog_data
=
3568 brw_tcs_prog_data(stage_prog_data
);
3570 if (!tcs_prog_data
) {
3571 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3573 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3574 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3576 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3577 hs
.IncludeVertexHandles
= true;
3579 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3584 static const struct brw_tracked_state
genX(hs_state
) = {
3587 .brw
= BRW_NEW_BATCH
|
3589 BRW_NEW_TCS_PROG_DATA
|
3590 BRW_NEW_TESS_PROGRAMS
,
3592 .emit
= genX(upload_hs_state
),
3596 genX(upload_ds_state
)(struct brw_context
*brw
)
3598 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3599 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3600 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3602 /* BRW_NEW_TES_PROG_DATA */
3603 const struct brw_tes_prog_data
*tes_prog_data
=
3604 brw_tes_prog_data(stage_prog_data
);
3605 const struct brw_vue_prog_data
*vue_prog_data
=
3606 brw_vue_prog_data(stage_prog_data
);
3608 if (!tes_prog_data
) {
3609 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3611 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3612 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3614 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3615 ds
.ComputeWCoordinateEnable
=
3616 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3619 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3620 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3621 ds
.UserClipDistanceCullTestEnableBitmask
=
3622 vue_prog_data
->cull_distance_mask
;
3628 static const struct brw_tracked_state
genX(ds_state
) = {
3631 .brw
= BRW_NEW_BATCH
|
3633 BRW_NEW_TESS_PROGRAMS
|
3634 BRW_NEW_TES_PROG_DATA
,
3636 .emit
= genX(upload_ds_state
),
3639 /* ---------------------------------------------------------------------- */
3642 upload_te_state(struct brw_context
*brw
)
3644 /* BRW_NEW_TESS_PROGRAMS */
3645 bool active
= brw
->tess_eval_program
;
3647 /* BRW_NEW_TES_PROG_DATA */
3648 const struct brw_tes_prog_data
*tes_prog_data
=
3649 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
3652 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
3653 te
.Partitioning
= tes_prog_data
->partitioning
;
3654 te
.OutputTopology
= tes_prog_data
->output_topology
;
3655 te
.TEDomain
= tes_prog_data
->domain
;
3657 te
.MaximumTessellationFactorOdd
= 63.0;
3658 te
.MaximumTessellationFactorNotOdd
= 64.0;
3661 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
3665 static const struct brw_tracked_state
genX(te_state
) = {
3668 .brw
= BRW_NEW_BLORP
|
3670 BRW_NEW_TES_PROG_DATA
|
3671 BRW_NEW_TESS_PROGRAMS
,
3673 .emit
= upload_te_state
,
3676 /* ---------------------------------------------------------------------- */
3679 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
3681 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3682 /* BRW_NEW_TESS_PROGRAMS */
3683 const struct brw_program
*tep
= brw_program_const(brw
->tess_eval_program
);
3686 /* BRW_NEW_TES_PROG_DATA */
3687 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
3688 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
3689 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
3692 upload_constant_state(brw
, stage_state
, tep
, MESA_SHADER_TESS_EVAL
);
3695 static const struct brw_tracked_state
genX(tes_push_constants
) = {
3697 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3698 .brw
= BRW_NEW_BATCH
|
3700 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3701 BRW_NEW_TESS_PROGRAMS
|
3702 BRW_NEW_TES_PROG_DATA
,
3704 .emit
= genX(upload_tes_push_constants
),
3708 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
3710 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3711 /* BRW_NEW_TESS_PROGRAMS */
3712 const struct brw_program
*tcp
= brw_program_const(brw
->tess_ctrl_program
);
3713 bool active
= brw
->tess_eval_program
;
3716 /* BRW_NEW_TCS_PROG_DATA */
3717 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
3719 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
3720 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
3723 upload_constant_state(brw
, stage_state
, active
, MESA_SHADER_TESS_CTRL
);
3726 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
3728 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3729 .brw
= BRW_NEW_BATCH
|
3731 BRW_NEW_DEFAULT_TESS_LEVELS
|
3732 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3733 BRW_NEW_TESS_PROGRAMS
|
3734 BRW_NEW_TCS_PROG_DATA
,
3736 .emit
= genX(upload_tcs_push_constants
),
3741 /* ---------------------------------------------------------------------- */
3745 genX(upload_cs_state
)(struct brw_context
*brw
)
3747 if (!brw
->cs
.base
.prog_data
)
3751 uint32_t *desc
= (uint32_t*) brw_state_batch(
3752 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
3755 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
3756 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
3757 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3758 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3760 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
3761 brw_emit_buffer_surface_state(
3762 brw
, &stage_state
->surf_offset
[
3763 prog_data
->binding_table
.shader_time_start
],
3764 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
3765 brw
->shader_time
.bo
->size
, 1, true);
3768 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
3769 32, &stage_state
->bind_bo_offset
);
3771 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
3772 if (prog_data
->total_scratch
) {
3776 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
3777 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
3779 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 11;
3780 } else if (GEN_IS_HASWELL
) {
3781 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
3782 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
3784 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 12;
3786 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
3787 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
3789 bo_offset
= stage_state
->per_thread_scratch
/ 1024 - 1;
3791 vfe
.ScratchSpaceBasePointer
=
3792 render_bo(stage_state
->scratch_bo
, bo_offset
);
3795 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
3796 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
3797 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
3798 vfe
.ResetGatewayTimer
=
3799 Resettingrelativetimerandlatchingtheglobaltimestamp
;
3801 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
3807 /* We are uploading duplicated copies of push constant uniforms for each
3808 * thread. Although the local id data needs to vary per thread, it won't
3809 * change for other uniform data. Unfortunately this duplication is
3810 * required for gen7. As of Haswell, this duplication can be avoided,
3811 * but this older mechanism with duplicated data continues to work.
3813 * FINISHME: As of Haswell, we could make use of the
3814 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
3815 * field to only store one copy of uniform data.
3817 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
3818 * which is described in the GPGPU_WALKER command and in the Broadwell
3819 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
3820 * Operations => GPGPU Mode => Indirect Payload Storage.
3822 * Note: The constant data is built in brw_upload_cs_push_constants
3825 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
3827 const uint32_t vfe_curbe_allocation
=
3828 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
3829 cs_prog_data
->push
.cross_thread
.regs
, 2);
3830 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
3833 if (cs_prog_data
->push
.total
.size
> 0) {
3834 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3835 curbe
.CURBETotalDataLength
=
3836 ALIGN(cs_prog_data
->push
.total
.size
, 64);
3837 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
3841 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
3842 memcpy(bind
, stage_state
->surf_offset
,
3843 prog_data
->binding_table
.size_bytes
);
3844 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
3845 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
3846 .SamplerStatePointer
= stage_state
->sampler_offset
,
3847 .SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4) >> 2,
3848 .BindingTablePointer
= stage_state
->bind_bo_offset
,
3849 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
3850 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
3851 .SharedLocalMemorySize
= encode_slm_size(devinfo
->gen
,
3852 prog_data
->total_shared
),
3853 .BarrierEnable
= cs_prog_data
->uses_barrier
,
3854 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3855 .CrossThreadConstantDataReadLength
=
3856 cs_prog_data
->push
.cross_thread
.regs
,
3860 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
3862 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
3863 load
.InterfaceDescriptorTotalLength
=
3864 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3865 load
.InterfaceDescriptorDataStartAddress
= offset
;
3869 static const struct brw_tracked_state
genX(cs_state
) = {
3871 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3872 .brw
= BRW_NEW_BATCH
|
3874 BRW_NEW_CS_PROG_DATA
|
3875 BRW_NEW_SAMPLER_STATE_TABLE
|
3878 .emit
= genX(upload_cs_state
)
3883 /* ---------------------------------------------------------------------- */
3887 genX(upload_raster
)(struct brw_context
*brw
)
3889 struct gl_context
*ctx
= &brw
->ctx
;
3892 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3895 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
3898 struct gl_point_attrib
*point
= &ctx
->Point
;
3900 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
3901 if (brw
->polygon_front_bit
== render_to_fbo
)
3902 raster
.FrontWinding
= CounterClockwise
;
3904 if (polygon
->CullFlag
) {
3905 switch (polygon
->CullFaceMode
) {
3907 raster
.CullMode
= CULLMODE_FRONT
;
3910 raster
.CullMode
= CULLMODE_BACK
;
3912 case GL_FRONT_AND_BACK
:
3913 raster
.CullMode
= CULLMODE_BOTH
;
3916 unreachable("not reached");
3919 raster
.CullMode
= CULLMODE_NONE
;
3922 point
->SmoothFlag
= raster
.SmoothPointEnable
;
3924 raster
.DXMultisampleRasterizationEnable
=
3925 _mesa_is_multisample_enabled(ctx
);
3927 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
3928 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
3929 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
3931 switch (polygon
->FrontMode
) {
3933 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
3936 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
3939 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
3942 unreachable("not reached");
3945 switch (polygon
->BackMode
) {
3947 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
3950 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
3953 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
3956 unreachable("not reached");
3960 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
3963 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
3965 /* _NEW_TRANSFORM */
3966 if (!ctx
->Transform
.DepthClamp
) {
3968 raster
.ViewportZFarClipTestEnable
= true;
3969 raster
.ViewportZNearClipTestEnable
= true;
3971 raster
.ViewportZClipTestEnable
= true;
3975 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
3977 raster
.ConservativeRasterizationEnable
=
3978 ctx
->IntelConservativeRasterization
;
3981 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
3982 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
3984 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
3988 static const struct brw_tracked_state
genX(raster_state
) = {
3990 .mesa
= _NEW_BUFFERS
|
3997 .brw
= BRW_NEW_BLORP
|
3999 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4001 .emit
= genX(upload_raster
),
4005 /* ---------------------------------------------------------------------- */
4009 genX(upload_ps_extra
)(struct brw_context
*brw
)
4011 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4013 const struct brw_wm_prog_data
*prog_data
=
4014 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4016 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4017 psx
.PixelShaderValid
= true;
4018 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4019 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4020 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4021 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4022 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4023 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4025 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4026 if (prog_data
->uses_sample_mask
) {
4028 if (prog_data
->post_depth_coverage
)
4029 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4030 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4031 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4033 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4035 psx
.PixelShaderUsesInputCoverageMask
= true;
4039 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4041 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4042 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4045 /* The stricter cross-primitive coherency guarantees that the hardware
4046 * gives us with the "Accesses UAV" bit set for at least one shader stage
4047 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4048 * are redundant within the current image, atomic counter and SSBO GL
4049 * APIs, which all have very loose ordering and coherency requirements
4050 * and generally rely on the application to insert explicit barriers when
4051 * a shader invocation is expected to see the memory writes performed by
4052 * the invocations of some previous primitive. Regardless of the value
4053 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4054 * cause an in most cases useless DC flush when the lowermost stage with
4055 * the bit set finishes execution.
4057 * It would be nice to disable it, but in some cases we can't because on
4058 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4059 * signal (which could be set independently from the coherency mechanism
4060 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4061 * determine whether the hardware skips execution of the fragment shader
4062 * or not via the ThreadDispatchEnable signal. However if we know that
4063 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4064 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4065 * difference so we may just disable it here.
4067 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4068 * take into account KillPixels when no depth or stencil writes are
4069 * enabled. In order for occlusion queries to work correctly with no
4070 * attachments, we need to force-enable here.
4072 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4075 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4076 !brw_color_buffer_write_enabled(brw
))
4077 psx
.PixelShaderHasUAV
= true;
4081 const struct brw_tracked_state
genX(ps_extra
) = {
4083 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4084 .brw
= BRW_NEW_BLORP
|
4086 BRW_NEW_FRAGMENT_PROGRAM
|
4087 BRW_NEW_FS_PROG_DATA
|
4088 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4090 .emit
= genX(upload_ps_extra
),
4094 /* ---------------------------------------------------------------------- */
4098 genX(upload_ps_blend
)(struct brw_context
*brw
)
4100 struct gl_context
*ctx
= &brw
->ctx
;
4103 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4104 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4107 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4109 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4110 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4111 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4113 bool alpha_to_one
= false;
4115 if (!buffer0_is_integer
) {
4116 /* _NEW_MULTISAMPLE */
4118 if (_mesa_is_multisample_enabled(ctx
)) {
4119 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4120 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4123 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4126 /* Used for implementing the following bit of GL_EXT_texture_integer:
4127 * "Per-fragment operations that require floating-point color
4128 * components, including multisample alpha operations, alpha test,
4129 * blending, and dithering, have no effect when the corresponding
4130 * colors are written to an integer color buffer."
4132 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4133 * "If drawbuffer zero is not NONE and the buffer it references has an
4134 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4135 * operations are skipped."
4137 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4138 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4139 GLenum eqA
= color
->Blend
[0].EquationA
;
4140 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4141 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4142 GLenum srcA
= color
->Blend
[0].SrcA
;
4143 GLenum dstA
= color
->Blend
[0].DstA
;
4145 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4146 srcRGB
= dstRGB
= GL_ONE
;
4148 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4149 srcA
= dstA
= GL_ONE
;
4151 /* Due to hardware limitations, the destination may have information
4152 * in an alpha channel even when the format specifies no alpha
4153 * channel. In order to avoid getting any incorrect blending due to
4154 * that alpha channel, coerce the blend factors to values that will
4155 * not read the alpha channel, but will instead use the correct
4156 * implicit value for alpha.
4158 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4159 GL_TEXTURE_ALPHA_TYPE
)) {
4160 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4161 srcA
= brw_fix_xRGB_alpha(srcA
);
4162 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4163 dstA
= brw_fix_xRGB_alpha(dstA
);
4166 /* Alpha to One doesn't work with Dual Color Blending. Override
4167 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4169 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4170 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4171 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4172 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4173 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4176 pb
.ColorBufferBlendEnable
= true;
4177 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4178 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4179 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4180 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4182 pb
.IndependentAlphaBlendEnable
=
4183 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4188 static const struct brw_tracked_state
genX(ps_blend
) = {
4190 .mesa
= _NEW_BUFFERS
|
4193 .brw
= BRW_NEW_BLORP
|
4195 BRW_NEW_FRAGMENT_PROGRAM
,
4197 .emit
= genX(upload_ps_blend
)
4201 /* ---------------------------------------------------------------------- */
4205 genX(emit_vf_topology
)(struct brw_context
*brw
)
4207 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4208 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4212 static const struct brw_tracked_state
genX(vf_topology
) = {
4215 .brw
= BRW_NEW_BLORP
|
4218 .emit
= genX(emit_vf_topology
),
4222 /* ---------------------------------------------------------------------- */
4226 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4228 uint32_t offset_in_bytes
,
4231 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4232 mi_rpc
.MemoryAddress
= instruction_bo(bo
, offset_in_bytes
);
4233 mi_rpc
.ReportID
= report_id
;
4238 /* ---------------------------------------------------------------------- */
4241 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4244 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4245 struct brw_stage_state
*stage_state
)
4248 static const uint16_t packet_headers
[] = {
4249 [MESA_SHADER_VERTEX
] = 43,
4250 [MESA_SHADER_TESS_CTRL
] = 44,
4251 [MESA_SHADER_TESS_EVAL
] = 45,
4252 [MESA_SHADER_GEOMETRY
] = 46,
4253 [MESA_SHADER_FRAGMENT
] = 47,
4256 /* Ivybridge requires a workaround flush before VS packets. */
4257 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4258 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4259 gen7_emit_vs_workaround_flush(brw
);
4262 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4263 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4264 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4270 has_component(mesa_format format
, int i
)
4272 if (_mesa_is_format_color_format(format
))
4273 return _mesa_format_has_color_component(format
, i
);
4275 /* depth and stencil have only one component */
4280 * Upload SAMPLER_BORDER_COLOR_STATE.
4283 genX(upload_default_color
)(struct brw_context
*brw
,
4284 const struct gl_sampler_object
*sampler
,
4285 mesa_format format
, GLenum base_format
,
4286 bool is_integer_format
, bool is_stencil_sampling
,
4287 uint32_t *sdc_offset
)
4289 union gl_color_union color
;
4291 switch (base_format
) {
4292 case GL_DEPTH_COMPONENT
:
4293 /* GL specs that border color for depth textures is taken from the
4294 * R channel, while the hardware uses A. Spam R into all the
4295 * channels for safety.
4297 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4298 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4299 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4300 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4306 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4309 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4310 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4311 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4312 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4315 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4316 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4317 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4318 color
.ui
[3] = float_as_int(1.0);
4320 case GL_LUMINANCE_ALPHA
:
4321 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4322 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4323 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4324 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4327 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4328 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4329 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4330 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4334 /* In some cases we use an RGBA surface format for GL RGB textures,
4335 * where we've initialized the A channel to 1.0. We also have to set
4336 * the border color alpha to 1.0 in that case.
4338 if (base_format
== GL_RGB
)
4339 color
.ui
[3] = float_as_int(1.0);
4342 if (brw
->gen
>= 8) {
4344 } else if (brw
->is_haswell
&& (is_integer_format
|| is_stencil_sampling
)) {
4348 uint32_t *sdc
= brw_state_batch(
4349 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4350 alignment
, sdc_offset
);
4352 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4354 #define ASSIGN(dst, src) \
4359 #define ASSIGNu16(dst, src) \
4361 dst = (uint16_t)src; \
4364 #define ASSIGNu8(dst, src) \
4366 dst = (uint8_t)src; \
4369 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4370 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4371 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4372 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4373 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4376 /* On Broadwell, the border color is represented as four 32-bit floats,
4377 * integers, or unsigned values, interpreted according to the surface
4378 * format. This matches the sampler->BorderColor union exactly; just
4379 * memcpy the values.
4381 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4382 #elif GEN_IS_HASWELL
4383 if (is_integer_format
|| is_stencil_sampling
) {
4384 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4385 const int bits_per_channel
=
4386 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4388 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4389 * "If any color channel is missing from the surface format,
4390 * corresponding border color should be programmed as zero and if
4391 * alpha channel is missing, corresponding Alpha border color should
4392 * be programmed as 1."
4394 unsigned c
[4] = { 0, 0, 0, 1 };
4395 for (int i
= 0; i
< 4; i
++) {
4396 if (has_component(format
, i
))
4400 switch (bits_per_channel
) {
4402 /* Copy RGBA in order. */
4403 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4406 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4408 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4411 if (base_format
== GL_RG
) {
4412 /* Careful inspection of the tables reveals that for RG32 formats,
4413 * the green channel needs to go where blue normally belongs.
4415 state
.BorderColor32bitRed
= c
[0];
4416 state
.BorderColor32bitBlue
= c
[1];
4417 state
.BorderColor32bitAlpha
= 1;
4419 /* Copy RGBA in order. */
4420 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4424 assert(!"Invalid number of bits per channel in integer format.");
4428 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4430 #elif GEN_GEN == 5 || GEN_GEN == 6
4431 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4432 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4433 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4435 #define MESA_FLOAT_TO_HALF(dst, src) \
4436 dst = _mesa_float_to_half(src);
4438 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4440 #undef MESA_FLOAT_TO_HALF
4442 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4443 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4444 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4445 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4447 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4449 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4451 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4455 #undef BORDER_COLOR_ATTR
4457 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4461 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4468 /* GL_CLAMP is the weird mode where coordinates are clamped to
4469 * [0.0, 1.0], so linear filtering of coordinates outside of
4470 * [0.0, 1.0] give you half edge texel value and half border
4473 * Gen8+ supports this natively.
4475 return TCM_HALF_BORDER
;
4477 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4478 * and set clamp_border here, which gets the result desired.
4479 * We just use clamp(_to_edge) for nearest, because for nearest
4480 * clamping to 1.0 gives border color instead of the desired
4486 return TCM_CLAMP_BORDER
;
4488 case GL_CLAMP_TO_EDGE
:
4490 case GL_CLAMP_TO_BORDER
:
4491 return TCM_CLAMP_BORDER
;
4492 case GL_MIRRORED_REPEAT
:
4494 case GL_MIRROR_CLAMP_TO_EDGE
:
4495 return TCM_MIRROR_ONCE
;
4502 * Return true if the given wrap mode requires the border color to exist.
4505 wrap_mode_needs_border_color(unsigned wrap_mode
)
4508 return wrap_mode
== TCM_CLAMP_BORDER
||
4509 wrap_mode
== TCM_HALF_BORDER
;
4511 return wrap_mode
== TCM_CLAMP_BORDER
;
4516 * Sets the sampler state for a single unit based off of the sampler key
4520 genX(update_sampler_state
)(struct brw_context
*brw
,
4521 GLenum target
, bool tex_cube_map_seamless
,
4522 GLfloat tex_unit_lod_bias
,
4523 mesa_format format
, GLenum base_format
,
4524 const struct gl_texture_object
*texObj
,
4525 const struct gl_sampler_object
*sampler
,
4526 uint32_t *sampler_state
,
4527 uint32_t batch_offset_for_sampler_state
)
4529 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
4531 /* Select min and mip filters. */
4532 switch (sampler
->MinFilter
) {
4534 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4535 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4538 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4539 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4541 case GL_NEAREST_MIPMAP_NEAREST
:
4542 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4543 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4545 case GL_LINEAR_MIPMAP_NEAREST
:
4546 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4547 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4549 case GL_NEAREST_MIPMAP_LINEAR
:
4550 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4551 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4553 case GL_LINEAR_MIPMAP_LINEAR
:
4554 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4555 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4558 unreachable("not reached");
4561 /* Select mag filter. */
4562 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
4563 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
4565 /* Enable anisotropic filtering if desired. */
4566 samp_st
.MaximumAnisotropy
= RATIO21
;
4568 if (sampler
->MaxAnisotropy
> 1.0f
) {
4569 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
4570 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
4571 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
4572 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
4574 if (sampler
->MaxAnisotropy
> 2.0f
) {
4575 samp_st
.MaximumAnisotropy
=
4576 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
4580 /* Set address rounding bits if not using nearest filtering. */
4581 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
4582 samp_st
.UAddressMinFilterRoundingEnable
= true;
4583 samp_st
.VAddressMinFilterRoundingEnable
= true;
4584 samp_st
.RAddressMinFilterRoundingEnable
= true;
4587 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
4588 samp_st
.UAddressMagFilterRoundingEnable
= true;
4589 samp_st
.VAddressMagFilterRoundingEnable
= true;
4590 samp_st
.RAddressMagFilterRoundingEnable
= true;
4593 bool either_nearest
=
4594 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
4595 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
4596 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
4597 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
4599 if (target
== GL_TEXTURE_CUBE_MAP
||
4600 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
4601 /* Cube maps must use the same wrap mode for all three coordinate
4602 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
4604 * Ivybridge and Baytrail seem to have problems with CUBE mode and
4605 * integer formats. Fall back to CLAMP for now.
4607 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
4608 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
4617 } else if (target
== GL_TEXTURE_1D
) {
4618 /* There's a bug in 1D texture sampling - it actually pays
4619 * attention to the wrap_t value, though it should not.
4620 * Override the wrap_t value here to GL_REPEAT to keep
4621 * any nonexistent border pixels from floating in.
4626 samp_st
.TCXAddressControlMode
= wrap_s
;
4627 samp_st
.TCYAddressControlMode
= wrap_t
;
4628 samp_st
.TCZAddressControlMode
= wrap_r
;
4630 samp_st
.ShadowFunction
=
4631 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
4632 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
4635 /* Set shadow function. */
4636 samp_st
.AnisotropicAlgorithm
=
4637 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
4638 EWAApproximation
: LEGACY
;
4642 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
4645 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
4646 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
4647 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
4648 samp_st
.TextureLODBias
=
4649 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
4652 samp_st
.BaseMipLevel
=
4653 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
4654 samp_st
.MinandMagStateNotEqual
=
4655 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
4658 /* Upload the border color if necessary. If not, just point it at
4659 * offset 0 (the start of the batch) - the color should be ignored,
4660 * but that address won't fault in case something reads it anyway.
4662 uint32_t border_color_offset
= 0;
4663 if (wrap_mode_needs_border_color(wrap_s
) ||
4664 wrap_mode_needs_border_color(wrap_t
) ||
4665 wrap_mode_needs_border_color(wrap_r
)) {
4666 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
4667 texObj
->_IsIntegerFormat
,
4668 texObj
->StencilSampling
,
4669 &border_color_offset
);
4672 samp_st
.BorderColorPointer
= border_color_offset
;
4675 samp_st
.BorderColorPointer
+= brw
->batch
.bo
->offset64
; /* reloc */
4676 brw_emit_reloc(&brw
->batch
, batch_offset_for_sampler_state
+ 8,
4677 brw
->batch
.bo
, border_color_offset
,
4678 I915_GEM_DOMAIN_SAMPLER
, 0);
4682 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
4684 samp_st
.LODPreClampEnable
= true;
4687 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
4691 update_sampler_state(struct brw_context
*brw
,
4693 uint32_t *sampler_state
,
4694 uint32_t batch_offset_for_sampler_state
)
4696 struct gl_context
*ctx
= &brw
->ctx
;
4697 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
4698 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
4699 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
4701 /* These don't use samplers at all. */
4702 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
4705 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
4706 genX(update_sampler_state
)(brw
, texObj
->Target
,
4707 ctx
->Texture
.CubeMapSeamless
,
4709 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
4711 sampler_state
, batch_offset_for_sampler_state
);
4715 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
4716 struct gl_program
*prog
,
4717 struct brw_stage_state
*stage_state
)
4719 struct gl_context
*ctx
= &brw
->ctx
;
4720 uint32_t sampler_count
= stage_state
->sampler_count
;
4722 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
4724 if (sampler_count
== 0)
4727 /* SAMPLER_STATE is 4 DWords on all platforms. */
4728 const int dwords
= GENX(SAMPLER_STATE_length
);
4729 const int size_in_bytes
= dwords
* sizeof(uint32_t);
4731 uint32_t *sampler_state
= brw_state_batch(brw
,
4732 sampler_count
* size_in_bytes
,
4733 32, &stage_state
->sampler_offset
);
4734 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
4736 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
4738 for (unsigned s
= 0; s
< sampler_count
; s
++) {
4739 if (SamplersUsed
& (1 << s
)) {
4740 const unsigned unit
= prog
->SamplerUnits
[s
];
4741 if (ctx
->Texture
.Unit
[unit
]._Current
) {
4742 update_sampler_state(brw
, unit
, sampler_state
,
4743 batch_offset_for_sampler_state
);
4747 sampler_state
+= dwords
;
4748 batch_offset_for_sampler_state
+= size_in_bytes
;
4751 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
4752 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
4753 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
4755 /* Flag that the sampler state table pointer has changed; later atoms
4758 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
4763 genX(upload_fs_samplers
)(struct brw_context
*brw
)
4765 /* BRW_NEW_FRAGMENT_PROGRAM */
4766 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
4767 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
4770 static const struct brw_tracked_state
genX(fs_samplers
) = {
4772 .mesa
= _NEW_TEXTURE
,
4773 .brw
= BRW_NEW_BATCH
|
4775 BRW_NEW_FRAGMENT_PROGRAM
,
4777 .emit
= genX(upload_fs_samplers
),
4781 genX(upload_vs_samplers
)(struct brw_context
*brw
)
4783 /* BRW_NEW_VERTEX_PROGRAM */
4784 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
4785 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
4788 static const struct brw_tracked_state
genX(vs_samplers
) = {
4790 .mesa
= _NEW_TEXTURE
,
4791 .brw
= BRW_NEW_BATCH
|
4793 BRW_NEW_VERTEX_PROGRAM
,
4795 .emit
= genX(upload_vs_samplers
),
4800 genX(upload_gs_samplers
)(struct brw_context
*brw
)
4802 /* BRW_NEW_GEOMETRY_PROGRAM */
4803 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
4807 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
4811 static const struct brw_tracked_state
genX(gs_samplers
) = {
4813 .mesa
= _NEW_TEXTURE
,
4814 .brw
= BRW_NEW_BATCH
|
4816 BRW_NEW_GEOMETRY_PROGRAM
,
4818 .emit
= genX(upload_gs_samplers
),
4824 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
4826 /* BRW_NEW_TESS_PROGRAMS */
4827 struct gl_program
*tcs
= (struct gl_program
*) brw
->tess_ctrl_program
;
4831 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
4834 static const struct brw_tracked_state
genX(tcs_samplers
) = {
4836 .mesa
= _NEW_TEXTURE
,
4837 .brw
= BRW_NEW_BATCH
|
4839 BRW_NEW_TESS_PROGRAMS
,
4841 .emit
= genX(upload_tcs_samplers
),
4847 genX(upload_tes_samplers
)(struct brw_context
*brw
)
4849 /* BRW_NEW_TESS_PROGRAMS */
4850 struct gl_program
*tes
= (struct gl_program
*) brw
->tess_eval_program
;
4854 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
4857 static const struct brw_tracked_state
genX(tes_samplers
) = {
4859 .mesa
= _NEW_TEXTURE
,
4860 .brw
= BRW_NEW_BATCH
|
4862 BRW_NEW_TESS_PROGRAMS
,
4864 .emit
= genX(upload_tes_samplers
),
4870 genX(upload_cs_samplers
)(struct brw_context
*brw
)
4872 /* BRW_NEW_COMPUTE_PROGRAM */
4873 struct gl_program
*cs
= (struct gl_program
*) brw
->compute_program
;
4877 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
4880 const struct brw_tracked_state
genX(cs_samplers
) = {
4882 .mesa
= _NEW_TEXTURE
,
4883 .brw
= BRW_NEW_BATCH
|
4885 BRW_NEW_COMPUTE_PROGRAM
,
4887 .emit
= genX(upload_cs_samplers
),
4891 /* ---------------------------------------------------------------------- */
4894 genX(init_atoms
)(struct brw_context
*brw
)
4897 static const struct brw_tracked_state
*render_atoms
[] =
4899 /* Once all the programs are done, we know how large urb entry
4900 * sizes need to be and can decide if we need to change the urb
4904 &brw_recalculate_urb_fence
,
4909 /* Surface state setup. Must come before the VS/WM unit. The binding
4910 * table upload must be last.
4912 &brw_vs_pull_constants
,
4913 &brw_wm_pull_constants
,
4914 &brw_renderbuffer_surfaces
,
4915 &brw_renderbuffer_read_surfaces
,
4916 &brw_texture_surfaces
,
4917 &brw_vs_binding_table
,
4918 &brw_wm_binding_table
,
4923 /* These set up state for brw_psp_urb_cbs */
4925 &genX(sf_clip_viewport
),
4927 &genX(vs_state
), /* always required, enabled or not */
4933 &brw_invariant_state
,
4935 &brw_binding_table_pointers
,
4936 &brw_blend_constant_color
,
4940 &genX(polygon_stipple
),
4941 &genX(polygon_stipple_offset
),
4943 &genX(line_stipple
),
4947 &genX(drawing_rect
),
4948 &brw_indices
, /* must come before brw_vertices */
4949 &genX(index_buffer
),
4952 &brw_constant_buffer
4955 static const struct brw_tracked_state
*render_atoms
[] =
4957 &genX(sf_clip_viewport
),
4959 /* Command packets: */
4964 &genX(blend_state
), /* must do before cc unit */
4965 &genX(color_calc_state
), /* must do before cc unit */
4966 &genX(depth_stencil_state
), /* must do before cc unit */
4968 &genX(vs_push_constants
), /* Before vs_state */
4969 &genX(gs_push_constants
), /* Before gs_state */
4970 &genX(wm_push_constants
), /* Before wm_state */
4972 /* Surface state setup. Must come before the VS/WM unit. The binding
4973 * table upload must be last.
4975 &brw_vs_pull_constants
,
4976 &brw_vs_ubo_surfaces
,
4977 &brw_gs_pull_constants
,
4978 &brw_gs_ubo_surfaces
,
4979 &brw_wm_pull_constants
,
4980 &brw_wm_ubo_surfaces
,
4981 &gen6_renderbuffer_surfaces
,
4982 &brw_renderbuffer_read_surfaces
,
4983 &brw_texture_surfaces
,
4985 &brw_vs_binding_table
,
4986 &gen6_gs_binding_table
,
4987 &brw_wm_binding_table
,
4992 &gen6_sampler_state
,
4993 &genX(multisample_state
),
5001 &genX(scissor_state
),
5003 &gen6_binding_table_pointers
,
5007 &genX(polygon_stipple
),
5008 &genX(polygon_stipple_offset
),
5010 &genX(line_stipple
),
5012 &genX(drawing_rect
),
5014 &brw_indices
, /* must come before brw_vertices */
5015 &genX(index_buffer
),
5019 static const struct brw_tracked_state
*render_atoms
[] =
5021 /* Command packets: */
5024 &genX(sf_clip_viewport
),
5027 &gen7_push_constant_space
,
5029 &genX(blend_state
), /* must do before cc unit */
5030 &genX(color_calc_state
), /* must do before cc unit */
5031 &genX(depth_stencil_state
), /* must do before cc unit */
5033 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5034 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5035 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5036 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5037 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5039 &genX(vs_push_constants
), /* Before vs_state */
5040 &genX(tcs_push_constants
),
5041 &genX(tes_push_constants
),
5042 &genX(gs_push_constants
), /* Before gs_state */
5043 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5045 /* Surface state setup. Must come before the VS/WM unit. The binding
5046 * table upload must be last.
5048 &brw_vs_pull_constants
,
5049 &brw_vs_ubo_surfaces
,
5050 &brw_vs_abo_surfaces
,
5051 &brw_tcs_pull_constants
,
5052 &brw_tcs_ubo_surfaces
,
5053 &brw_tcs_abo_surfaces
,
5054 &brw_tes_pull_constants
,
5055 &brw_tes_ubo_surfaces
,
5056 &brw_tes_abo_surfaces
,
5057 &brw_gs_pull_constants
,
5058 &brw_gs_ubo_surfaces
,
5059 &brw_gs_abo_surfaces
,
5060 &brw_wm_pull_constants
,
5061 &brw_wm_ubo_surfaces
,
5062 &brw_wm_abo_surfaces
,
5063 &gen6_renderbuffer_surfaces
,
5064 &brw_renderbuffer_read_surfaces
,
5065 &brw_texture_surfaces
,
5066 &brw_vs_binding_table
,
5067 &brw_tcs_binding_table
,
5068 &brw_tes_binding_table
,
5069 &brw_gs_binding_table
,
5070 &brw_wm_binding_table
,
5074 &genX(tcs_samplers
),
5075 &genX(tes_samplers
),
5077 &genX(multisample_state
),
5091 &genX(scissor_state
),
5095 &genX(polygon_stipple
),
5096 &genX(polygon_stipple_offset
),
5098 &genX(line_stipple
),
5100 &genX(drawing_rect
),
5102 &brw_indices
, /* must come before brw_vertices */
5103 &genX(index_buffer
),
5111 static const struct brw_tracked_state
*render_atoms
[] =
5114 &genX(sf_clip_viewport
),
5117 &gen7_push_constant_space
,
5120 &genX(color_calc_state
),
5122 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5123 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5124 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5125 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5126 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5128 &genX(vs_push_constants
), /* Before vs_state */
5129 &genX(tcs_push_constants
),
5130 &genX(tes_push_constants
),
5131 &genX(gs_push_constants
), /* Before gs_state */
5132 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5134 /* Surface state setup. Must come before the VS/WM unit. The binding
5135 * table upload must be last.
5137 &brw_vs_pull_constants
,
5138 &brw_vs_ubo_surfaces
,
5139 &brw_vs_abo_surfaces
,
5140 &brw_tcs_pull_constants
,
5141 &brw_tcs_ubo_surfaces
,
5142 &brw_tcs_abo_surfaces
,
5143 &brw_tes_pull_constants
,
5144 &brw_tes_ubo_surfaces
,
5145 &brw_tes_abo_surfaces
,
5146 &brw_gs_pull_constants
,
5147 &brw_gs_ubo_surfaces
,
5148 &brw_gs_abo_surfaces
,
5149 &brw_wm_pull_constants
,
5150 &brw_wm_ubo_surfaces
,
5151 &brw_wm_abo_surfaces
,
5152 &gen6_renderbuffer_surfaces
,
5153 &brw_renderbuffer_read_surfaces
,
5154 &brw_texture_surfaces
,
5155 &brw_vs_binding_table
,
5156 &brw_tcs_binding_table
,
5157 &brw_tes_binding_table
,
5158 &brw_gs_binding_table
,
5159 &brw_wm_binding_table
,
5163 &genX(tcs_samplers
),
5164 &genX(tes_samplers
),
5166 &genX(multisample_state
),
5175 &genX(raster_state
),
5181 &genX(depth_stencil_state
),
5184 &genX(scissor_state
),
5188 &genX(polygon_stipple
),
5189 &genX(polygon_stipple_offset
),
5191 &genX(line_stipple
),
5193 &genX(drawing_rect
),
5198 &genX(index_buffer
),
5206 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5207 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5208 render_atoms
, ARRAY_SIZE(render_atoms
));
5211 static const struct brw_tracked_state
*compute_atoms
[] =
5214 &brw_cs_image_surfaces
,
5215 &gen7_cs_push_constants
,
5216 &brw_cs_pull_constants
,
5217 &brw_cs_ubo_surfaces
,
5218 &brw_cs_abo_surfaces
,
5219 &brw_cs_texture_surfaces
,
5220 &brw_cs_work_groups_surface
,
5225 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5226 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5227 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5229 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);