2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_defines.h"
41 #include "brw_multisample_state.h"
42 #include "brw_state.h"
46 #include "intel_batchbuffer.h"
47 #include "intel_buffer_objects.h"
48 #include "intel_fbo.h"
50 #include "main/enums.h"
51 #include "main/fbobject.h"
52 #include "main/framebuffer.h"
53 #include "main/glformats.h"
54 #include "main/samplerobj.h"
55 #include "main/shaderapi.h"
56 #include "main/stencil.h"
57 #include "main/transformfeedback.h"
58 #include "main/varray.h"
59 #include "main/viewport.h"
60 #include "util/half_float.h"
63 emit_dwords(struct brw_context
*brw
, unsigned n
)
65 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
66 uint32_t *map
= brw
->batch
.map_next
;
67 brw
->batch
.map_next
+= n
;
68 intel_batchbuffer_advance(brw
);
78 #define __gen_address_type struct brw_address
79 #define __gen_user_data struct brw_context
82 __gen_combine_address(struct brw_context
*brw
, void *location
,
83 struct brw_address address
, uint32_t delta
)
85 struct intel_batchbuffer
*batch
= &brw
->batch
;
88 if (address
.bo
== NULL
) {
89 return address
.offset
+ delta
;
91 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
92 offset
= (char *) location
- (char *) brw
->batch
.state_map
;
93 return brw_state_reloc(batch
, offset
, address
.bo
,
94 address
.offset
+ delta
,
98 assert(!brw_ptr_in_state_buffer(batch
, location
));
100 offset
= (char *) location
- (char *) brw
->batch
.map
;
101 return brw_batch_reloc(batch
, offset
, address
.bo
,
102 address
.offset
+ delta
,
103 address
.reloc_flags
);
107 static struct brw_address
108 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
110 return (struct brw_address
) {
113 .reloc_flags
= RELOC_WRITE
,
117 static struct brw_address
118 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
120 return (struct brw_address
) {
126 UNUSED
static struct brw_address
127 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
129 return (struct brw_address
) {
132 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
137 static struct brw_address
138 KSP(struct brw_context
*brw
, uint32_t offset
)
140 return ro_bo(brw
->cache
.bo
, offset
);
144 KSP(struct brw_context
*brw
, uint32_t offset
)
150 #include "genxml/genX_pack.h"
152 #define _brw_cmd_length(cmd) cmd ## _length
153 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
154 #define _brw_cmd_header(cmd) cmd ## _header
155 #define _brw_cmd_pack(cmd) cmd ## _pack
157 #define brw_batch_emit(brw, cmd, name) \
158 for (struct cmd name = { _brw_cmd_header(cmd) }, \
159 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
160 __builtin_expect(_dst != NULL, 1); \
161 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
164 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
165 uint32_t *_dw = emit_dwords(brw, n); \
166 struct cmd template = { \
167 _brw_cmd_header(cmd), \
168 .DWordLength = n - _brw_cmd_length_bias(cmd), \
171 _brw_cmd_pack(cmd)(brw, _dw, &template); \
172 _dw + 1; /* Array starts at dw[1] */ \
175 #define brw_state_emit(brw, cmd, align, offset, name) \
176 for (struct cmd name = {}, \
177 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
179 __builtin_expect(_dst != NULL, 1); \
180 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
184 * Polygon stipple packet
187 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
189 struct gl_context
*ctx
= &brw
->ctx
;
192 if (!ctx
->Polygon
.StippleFlag
)
195 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
196 /* Polygon stipple is provided in OpenGL order, i.e. bottom
197 * row first. If we're rendering to a window (i.e. the
198 * default frame buffer object, 0), then we need to invert
199 * it to match our pixel layout. But if we're rendering
200 * to a FBO (i.e. any named frame buffer object), we *don't*
201 * need to invert - we already match the layout.
203 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
204 for (unsigned i
= 0; i
< 32; i
++)
205 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
207 for (unsigned i
= 0; i
< 32; i
++)
208 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
213 static const struct brw_tracked_state
genX(polygon_stipple
) = {
215 .mesa
= _NEW_POLYGON
|
217 .brw
= BRW_NEW_CONTEXT
,
219 .emit
= genX(upload_polygon_stipple
),
223 * Polygon stipple offset packet
226 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
228 struct gl_context
*ctx
= &brw
->ctx
;
231 if (!ctx
->Polygon
.StippleFlag
)
234 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
237 * If we're drawing to a system window we have to invert the Y axis
238 * in order to match the OpenGL pixel coordinate system, and our
239 * offset must be matched to the window position. If we're drawing
240 * to a user-created FBO then our native pixel coordinate system
241 * works just fine, and there's no window system to worry about.
243 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
244 poly
.PolygonStippleYOffset
=
245 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
250 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
252 .mesa
= _NEW_BUFFERS
|
254 .brw
= BRW_NEW_CONTEXT
,
256 .emit
= genX(upload_polygon_stipple_offset
),
260 * Line stipple packet
263 genX(upload_line_stipple
)(struct brw_context
*brw
)
265 struct gl_context
*ctx
= &brw
->ctx
;
267 if (!ctx
->Line
.StippleFlag
)
270 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
271 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
273 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
274 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
278 static const struct brw_tracked_state
genX(line_stipple
) = {
281 .brw
= BRW_NEW_CONTEXT
,
283 .emit
= genX(upload_line_stipple
),
286 /* Constant single cliprect for framebuffer object or DRI2 drawing */
288 genX(upload_drawing_rect
)(struct brw_context
*brw
)
290 struct gl_context
*ctx
= &brw
->ctx
;
291 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
292 const unsigned int fb_width
= _mesa_geometric_width(fb
);
293 const unsigned int fb_height
= _mesa_geometric_height(fb
);
295 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
296 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
297 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
301 static const struct brw_tracked_state
genX(drawing_rect
) = {
303 .mesa
= _NEW_BUFFERS
,
304 .brw
= BRW_NEW_BLORP
|
307 .emit
= genX(upload_drawing_rect
),
311 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
315 unsigned start_offset
,
320 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
321 .VertexBufferIndex
= buffer_nr
,
322 .BufferPitch
= stride
,
323 .BufferStartingAddress
= ro_bo(bo
, start_offset
),
325 .BufferSize
= end_offset
- start_offset
,
329 .AddressModifyEnable
= true,
333 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
334 .InstanceDataStepRate
= step_rate
,
336 .EndAddress
= ro_bo(bo
, end_offset
- 1),
341 .VertexBufferMOCS
= CNL_MOCS_WB
,
343 .VertexBufferMOCS
= SKL_MOCS_WB
,
345 .VertexBufferMOCS
= BDW_MOCS_WB
,
347 .VertexBufferMOCS
= GEN7_MOCS_L3
,
351 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
352 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
356 is_passthru_format(uint32_t format
)
359 case ISL_FORMAT_R64_PASSTHRU
:
360 case ISL_FORMAT_R64G64_PASSTHRU
:
361 case ISL_FORMAT_R64G64B64_PASSTHRU
:
362 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
370 uploads_needed(uint32_t format
)
372 if (!is_passthru_format(format
))
376 case ISL_FORMAT_R64_PASSTHRU
:
377 case ISL_FORMAT_R64G64_PASSTHRU
:
379 case ISL_FORMAT_R64G64B64_PASSTHRU
:
380 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
383 unreachable("not reached");
388 * Returns the format that we are finally going to use when upload a vertex
389 * element. It will only change if we are using *64*PASSTHRU formats, as for
390 * gen < 8 they need to be splitted on two *32*FLOAT formats.
392 * @upload points in which upload we are. Valid values are [0,1]
395 downsize_format_if_needed(uint32_t format
,
398 assert(upload
== 0 || upload
== 1);
400 if (!is_passthru_format(format
))
404 case ISL_FORMAT_R64_PASSTHRU
:
405 return ISL_FORMAT_R32G32_FLOAT
;
406 case ISL_FORMAT_R64G64_PASSTHRU
:
407 return ISL_FORMAT_R32G32B32A32_FLOAT
;
408 case ISL_FORMAT_R64G64B64_PASSTHRU
:
409 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
410 : ISL_FORMAT_R32G32_FLOAT
;
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
412 return ISL_FORMAT_R32G32B32A32_FLOAT
;
414 unreachable("not reached");
419 * Returns the number of componentes associated with a format that is used on
420 * a 64 to 32 format split. See downsize_format()
423 upload_format_size(uint32_t upload_format
)
425 switch (upload_format
) {
426 case ISL_FORMAT_R32G32_FLOAT
:
428 case ISL_FORMAT_R32G32B32A32_FLOAT
:
431 unreachable("not reached");
436 genX(emit_vertices
)(struct brw_context
*brw
)
438 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
441 brw_prepare_vertices(brw
);
442 brw_prepare_shader_draw_parameters(brw
);
445 brw_emit_query_begin(brw
);
448 const struct brw_vs_prog_data
*vs_prog_data
=
449 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
452 struct gl_context
*ctx
= &brw
->ctx
;
453 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
454 ctx
->Polygon
.BackMode
!= GL_FILL
);
456 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
457 unsigned vue
= brw
->vb
.nr_enabled
;
459 /* The element for the edge flags must always be last, so we have to
460 * insert the SGVS before it in that case.
462 if (uses_edge_flag
) {
468 "Trying to insert VID/IID past 33rd vertex element, "
469 "need to reorder the vertex attrbutes.");
471 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
472 if (vs_prog_data
->uses_vertexid
) {
473 vfs
.VertexIDEnable
= true;
474 vfs
.VertexIDComponentNumber
= 2;
475 vfs
.VertexIDElementOffset
= vue
;
478 if (vs_prog_data
->uses_instanceid
) {
479 vfs
.InstanceIDEnable
= true;
480 vfs
.InstanceIDComponentNumber
= 3;
481 vfs
.InstanceIDElementOffset
= vue
;
485 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
486 vfi
.InstancingEnable
= true;
487 vfi
.VertexElementIndex
= vue
;
490 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
493 /* Normally we don't need an element for the SGVS attribute because the
494 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
495 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
496 * we're using draw parameters then we need an element for the those
497 * values. Additionally if there is an edge flag element then the SGVS
498 * can't be inserted past that so we need a dummy element to ensure that
499 * the edge flag is the last one.
501 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
502 vs_prog_data
->uses_baseinstance
||
503 ((vs_prog_data
->uses_instanceid
||
504 vs_prog_data
->uses_vertexid
)
507 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
508 vs_prog_data
->uses_baseinstance
||
509 vs_prog_data
->uses_instanceid
||
510 vs_prog_data
->uses_vertexid
);
512 unsigned nr_elements
=
513 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
516 /* If any of the formats of vb.enabled needs more that one upload, we need
517 * to add it to nr_elements
519 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
520 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
521 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
523 if (uploads_needed(format
) > 1)
528 /* If the VS doesn't read any inputs (calculating vertex position from
529 * a state variable for some reason, for example), emit a single pad
530 * VERTEX_ELEMENT struct and bail.
532 * The stale VB state stays in place, but they don't do anything unless
533 * a VE loads from them.
535 if (nr_elements
== 0) {
536 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
537 1 + GENX(VERTEX_ELEMENT_STATE_length
));
538 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
540 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
541 .Component0Control
= VFCOMP_STORE_0
,
542 .Component1Control
= VFCOMP_STORE_0
,
543 .Component2Control
= VFCOMP_STORE_0
,
544 .Component3Control
= VFCOMP_STORE_1_FP
,
546 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
550 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
551 const bool uses_draw_params
=
552 vs_prog_data
->uses_basevertex
||
553 vs_prog_data
->uses_baseinstance
;
554 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
555 uses_draw_params
+ vs_prog_data
->uses_drawid
;
558 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
560 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
561 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
563 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
564 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
565 /* Prior to Haswell and Bay Trail we have to use 4-component formats
566 * to fake 3-component ones. In particular, we do this for
567 * half-float and 8 and 16-bit integer formats. This means that the
568 * vertex element may poke over the end of the buffer by 2 bytes.
570 const unsigned padding
=
571 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
572 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
573 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
580 if (uses_draw_params
) {
581 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
582 brw
->draw
.draw_params_bo
,
583 brw
->draw
.draw_params_offset
,
584 brw
->draw
.draw_params_bo
->size
,
589 if (vs_prog_data
->uses_drawid
) {
590 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
591 brw
->draw
.draw_id_bo
,
592 brw
->draw
.draw_id_offset
,
593 brw
->draw
.draw_id_bo
->size
,
599 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
600 * presumably for VertexID/InstanceID.
603 assert(nr_elements
<= 34);
604 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
606 assert(nr_elements
<= 18);
609 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
610 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
612 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
613 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
614 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
615 uint32_t comp0
= VFCOMP_STORE_SRC
;
616 uint32_t comp1
= VFCOMP_STORE_SRC
;
617 uint32_t comp2
= VFCOMP_STORE_SRC
;
618 uint32_t comp3
= VFCOMP_STORE_SRC
;
619 const unsigned num_uploads
= GEN_GEN
< 8 ? uploads_needed(format
) : 1;
622 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
623 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
624 * element which has edge flag enabled."
626 assert(!(is_passthru_format(format
) && uses_edge_flag
));
629 /* The gen4 driver expects edgeflag to come in as a float, and passes
630 * that float on to the tests in the clipper. Mesa's current vertex
631 * attribute value for EdgeFlag is stored as a float, which works out.
632 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
633 * integer ubyte. Just rewrite that to convert to a float.
635 * Gen6+ passes edgeflag as sideband along with the vertex, instead
636 * of in the VUE. We have to upload it sideband as the last vertex
637 * element according to the B-Spec.
640 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
641 gen6_edgeflag_input
= input
;
646 for (unsigned c
= 0; c
< num_uploads
; c
++) {
647 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
648 downsize_format_if_needed(format
, c
);
649 /* If we need more that one upload, the offset stride would be 128
650 * bits (16 bytes), as for previous uploads we are using the full
652 const unsigned offset
= input
->offset
+ c
* 16;
654 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
655 upload_format_size(upload_format
) : input
->glarray
->Size
;
658 case 0: comp0
= VFCOMP_STORE_0
;
659 case 1: comp1
= VFCOMP_STORE_0
;
660 case 2: comp2
= VFCOMP_STORE_0
;
662 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
663 comp3
= VFCOMP_STORE_0
;
664 } else if (input
->glarray
->Integer
) {
665 comp3
= VFCOMP_STORE_1_INT
;
667 comp3
= VFCOMP_STORE_1_FP
;
674 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
676 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
677 * formats, 64-bit components are stored in the URB without any
678 * conversion. In this case, vertex elements must be written as 128
679 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
680 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
681 * component into the URB, Component 1 must be specified as
682 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
683 * order to output a 128-bit vertex element, or Components 1-3 must
684 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
685 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
686 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
689 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
690 /* Store vertex elements which correspond to double and dvec2 vertex
691 * shader inputs as 128-bit vertex elements, instead of 256-bits.
693 comp2
= VFCOMP_NOSTORE
;
694 comp3
= VFCOMP_NOSTORE
;
698 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
699 .VertexBufferIndex
= input
->buffer
,
701 .SourceElementFormat
= upload_format
,
702 .SourceElementOffset
= offset
,
703 .Component0Control
= comp0
,
704 .Component1Control
= comp1
,
705 .Component2Control
= comp2
,
706 .Component3Control
= comp3
,
708 .DestinationElementOffset
= i
* 4,
712 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
713 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
717 if (needs_sgvs_element
) {
718 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
720 .Component0Control
= VFCOMP_STORE_0
,
721 .Component1Control
= VFCOMP_STORE_0
,
722 .Component2Control
= VFCOMP_STORE_0
,
723 .Component3Control
= VFCOMP_STORE_0
,
725 .DestinationElementOffset
= i
* 4,
730 if (vs_prog_data
->uses_basevertex
||
731 vs_prog_data
->uses_baseinstance
) {
732 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
733 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
734 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
735 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
738 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
739 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
740 if (vs_prog_data
->uses_basevertex
)
741 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
743 if (vs_prog_data
->uses_baseinstance
)
744 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
746 if (vs_prog_data
->uses_vertexid
)
747 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
749 if (vs_prog_data
->uses_instanceid
)
750 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
753 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
754 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
757 if (vs_prog_data
->uses_drawid
) {
758 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
760 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
761 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32_UINT
,
762 .Component0Control
= VFCOMP_STORE_SRC
,
763 .Component1Control
= VFCOMP_STORE_0
,
764 .Component2Control
= VFCOMP_STORE_0
,
765 .Component3Control
= VFCOMP_STORE_0
,
767 .DestinationElementOffset
= i
* 4,
771 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
772 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
776 if (gen6_edgeflag_input
) {
777 const uint32_t format
=
778 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
780 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
782 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
783 .EdgeFlagEnable
= true,
784 .SourceElementFormat
= format
,
785 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
786 .Component0Control
= VFCOMP_STORE_SRC
,
787 .Component1Control
= VFCOMP_STORE_0
,
788 .Component2Control
= VFCOMP_STORE_0
,
789 .Component3Control
= VFCOMP_STORE_0
,
792 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
793 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
798 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
799 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
800 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
801 unsigned element_index
;
803 /* The edge flag element is reordered to be the last one in the code
804 * above so we need to compensate for that in the element indices used
807 if (input
== gen6_edgeflag_input
)
808 element_index
= nr_elements
- 1;
812 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
813 vfi
.VertexElementIndex
= element_index
;
814 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
815 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
819 if (vs_prog_data
->uses_drawid
) {
820 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
822 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
823 vfi
.VertexElementIndex
= element
;
829 static const struct brw_tracked_state
genX(vertices
) = {
831 .mesa
= _NEW_POLYGON
,
832 .brw
= BRW_NEW_BATCH
|
835 BRW_NEW_VS_PROG_DATA
,
837 .emit
= genX(emit_vertices
),
841 genX(emit_index_buffer
)(struct brw_context
*brw
)
843 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
845 if (index_buffer
== NULL
)
848 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
849 #if GEN_GEN < 8 && !GEN_IS_HASWELL
850 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
852 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
853 ib
.BufferStartingAddress
= ro_bo(brw
->ib
.bo
, 0);
855 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
856 ib
.BufferSize
= brw
->ib
.size
;
858 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
863 static const struct brw_tracked_state
genX(index_buffer
) = {
866 .brw
= BRW_NEW_BATCH
|
868 BRW_NEW_INDEX_BUFFER
,
870 .emit
= genX(emit_index_buffer
),
873 #if GEN_IS_HASWELL || GEN_GEN >= 8
875 genX(upload_cut_index
)(struct brw_context
*brw
)
877 const struct gl_context
*ctx
= &brw
->ctx
;
879 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
880 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
881 vf
.IndexedDrawCutIndexEnable
= true;
882 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
887 const struct brw_tracked_state
genX(cut_index
) = {
889 .mesa
= _NEW_TRANSFORM
,
890 .brw
= BRW_NEW_INDEX_BUFFER
,
892 .emit
= genX(upload_cut_index
),
898 * Determine the appropriate attribute override value to store into the
899 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
900 * override value contains two pieces of information: the location of the
901 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
902 * flag indicating whether to "swizzle" the attribute based on the direction
903 * the triangle is facing.
905 * If an attribute is "swizzled", then the given VUE location is used for
906 * front-facing triangles, and the VUE location that immediately follows is
907 * used for back-facing triangles. We use this to implement the mapping from
908 * gl_FrontColor/gl_BackColor to gl_Color.
910 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
911 * being instructed to begin reading attribute data. It can be set to a
912 * nonzero value to prevent the SF unit from wasting time reading elements of
913 * the VUE that are not needed by the fragment shader. It is measured in
914 * 256-bit increments.
917 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
918 const struct brw_vue_map
*vue_map
,
919 int urb_entry_read_offset
, int fs_attr
,
920 bool two_side_color
, uint32_t *max_source_attr
)
922 /* Find the VUE slot for this attribute. */
923 int slot
= vue_map
->varying_to_slot
[fs_attr
];
925 /* Viewport and Layer are stored in the VUE header. We need to override
926 * them to zero if earlier stages didn't write them, as GL requires that
927 * they read back as zero when not explicitly set.
929 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
930 attr
->ComponentOverrideX
= true;
931 attr
->ComponentOverrideW
= true;
932 attr
->ConstantSource
= CONST_0000
;
934 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
935 attr
->ComponentOverrideY
= true;
936 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
937 attr
->ComponentOverrideZ
= true;
942 /* If there was only a back color written but not front, use back
943 * as the color instead of undefined
945 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
946 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
947 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
948 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
951 /* This attribute does not exist in the VUE--that means that the vertex
952 * shader did not write to it. This means that either:
954 * (a) This attribute is a texture coordinate, and it is going to be
955 * replaced with point coordinates (as a consequence of a call to
956 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
957 * hardware will ignore whatever attribute override we supply.
959 * (b) This attribute is read by the fragment shader but not written by
960 * the vertex shader, so its value is undefined. Therefore the
961 * attribute override we supply doesn't matter.
963 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
964 * previous shader stage.
966 * Note that we don't have to worry about the cases where the attribute
967 * is gl_PointCoord or is undergoing point sprite coordinate
968 * replacement, because in those cases, this function isn't called.
970 * In case (c), we need to program the attribute overrides so that the
971 * primitive ID will be stored in this slot. In every other case, the
972 * attribute override we supply doesn't matter. So just go ahead and
973 * program primitive ID in every case.
975 attr
->ComponentOverrideW
= true;
976 attr
->ComponentOverrideX
= true;
977 attr
->ComponentOverrideY
= true;
978 attr
->ComponentOverrideZ
= true;
979 attr
->ConstantSource
= PRIM_ID
;
983 /* Compute the location of the attribute relative to urb_entry_read_offset.
984 * Each increment of urb_entry_read_offset represents a 256-bit value, so
985 * it counts for two 128-bit VUE slots.
987 int source_attr
= slot
- 2 * urb_entry_read_offset
;
988 assert(source_attr
>= 0 && source_attr
< 32);
990 /* If we are doing two-sided color, and the VUE slot following this one
991 * represents a back-facing color, then we need to instruct the SF unit to
992 * do back-facing swizzling.
994 bool swizzling
= two_side_color
&&
995 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
996 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
997 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
998 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1000 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1001 if (*max_source_attr
< source_attr
+ swizzling
)
1002 *max_source_attr
= source_attr
+ swizzling
;
1004 attr
->SourceAttribute
= source_attr
;
1006 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1011 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1012 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1013 uint32_t *point_sprite_enables
,
1014 uint32_t *urb_entry_read_length
,
1015 uint32_t *urb_entry_read_offset
)
1017 const struct gl_context
*ctx
= &brw
->ctx
;
1020 const struct gl_point_attrib
*point
= &ctx
->Point
;
1022 /* BRW_NEW_FRAGMENT_PROGRAM */
1023 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1025 /* BRW_NEW_FS_PROG_DATA */
1026 const struct brw_wm_prog_data
*wm_prog_data
=
1027 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1028 uint32_t max_source_attr
= 0;
1030 *point_sprite_enables
= 0;
1032 /* If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
1033 * the full vertex header. Otherwise, we can program the SF to start
1034 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
1035 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1036 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
1039 bool fs_needs_vue_header
= fp
->info
.inputs_read
&
1040 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1042 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
1044 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1045 * description of dw10 Point Sprite Texture Coordinate Enable:
1047 * "This field must be programmed to zero when non-point primitives
1050 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1051 * must be programmed to zero when rendering non-point primitives, but
1052 * the IvyBridge PRM does, and if we don't, we get garbage.
1054 * This is not required on Haswell, as the hardware ignores this state
1055 * when drawing non-points -- although we do still need to be careful to
1056 * correctly set the attr overrides.
1059 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1061 bool drawing_points
= brw_is_drawing_points(brw
);
1063 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1064 int input_index
= wm_prog_data
->urb_setup
[attr
];
1066 if (input_index
< 0)
1070 bool point_sprite
= false;
1071 if (drawing_points
) {
1072 if (point
->PointSprite
&&
1073 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1074 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1075 point_sprite
= true;
1078 if (attr
== VARYING_SLOT_PNTC
)
1079 point_sprite
= true;
1082 *point_sprite_enables
|= (1 << input_index
);
1085 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1086 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1088 if (!point_sprite
) {
1089 genX(get_attr_override
)(&attribute
,
1090 &brw
->vue_map_geom_out
,
1091 *urb_entry_read_offset
, attr
,
1092 _mesa_vertex_program_two_side_enabled(ctx
),
1096 /* The hardware can only do the overrides on 16 overrides at a
1097 * time, and the other up to 16 have to be lined up so that the
1098 * input index = the output index. We'll need to do some
1099 * tweaking to make sure that's the case.
1101 if (input_index
< 16)
1102 attr_overrides
[input_index
] = attribute
;
1104 assert(attribute
.SourceAttribute
== input_index
);
1107 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1108 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1110 * "This field should be set to the minimum length required to read the
1111 * maximum source attribute. The maximum source attribute is indicated
1112 * by the maximum value of the enabled Attribute # Source Attribute if
1113 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1114 * enable is not set.
1115 * read_length = ceiling((max_source_attr + 1) / 2)
1117 * [errata] Corruption/Hang possible if length programmed larger than
1120 * Similar text exists for Ivy Bridge.
1122 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1126 /* ---------------------------------------------------------------------- */
1129 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1131 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1133 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1137 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1139 struct gl_context
*ctx
= &brw
->ctx
;
1142 struct intel_renderbuffer
*depth_irb
=
1143 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1146 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1149 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1150 const int b
= stencil
->_BackFace
;
1152 if (depth
->Test
&& depth_irb
) {
1153 ds
->DepthTestEnable
= true;
1154 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1155 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1158 if (brw
->stencil_enabled
) {
1159 ds
->StencilTestEnable
= true;
1160 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1161 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1163 ds
->StencilTestFunction
=
1164 intel_translate_compare_func(stencil
->Function
[0]);
1166 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1167 ds
->StencilPassDepthPassOp
=
1168 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1169 ds
->StencilPassDepthFailOp
=
1170 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1172 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1174 if (brw
->stencil_two_sided
) {
1175 ds
->DoubleSidedStencilEnable
= true;
1176 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1177 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1179 ds
->BackfaceStencilTestFunction
=
1180 intel_translate_compare_func(stencil
->Function
[b
]);
1181 ds
->BackfaceStencilFailOp
=
1182 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1183 ds
->BackfaceStencilPassDepthPassOp
=
1184 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1185 ds
->BackfaceStencilPassDepthFailOp
=
1186 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1189 #if GEN_GEN <= 5 || GEN_GEN >= 9
1190 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1191 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1198 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1201 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1202 set_depth_stencil_bits(brw
, &wmds
);
1206 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1207 set_depth_stencil_bits(brw
, &ds
);
1210 /* Now upload a pointer to the indirect state */
1212 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1213 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1214 ptr
.DEPTH_STENCIL_STATEChange
= true;
1217 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1218 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1224 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1226 .mesa
= _NEW_BUFFERS
|
1229 .brw
= BRW_NEW_BLORP
|
1230 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1232 BRW_NEW_STATE_BASE_ADDRESS
),
1234 .emit
= genX(upload_depth_stencil_state
),
1238 /* ---------------------------------------------------------------------- */
1243 genX(upload_clip_state
)(struct brw_context
*brw
)
1245 struct gl_context
*ctx
= &brw
->ctx
;
1247 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1248 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1249 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1250 clip
.GRFRegisterCount
=
1251 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1252 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1253 clip
.SingleProgramFlow
= true;
1254 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1255 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1257 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1258 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1259 clip
.DispatchGRFStartRegisterForURBData
= 1;
1260 clip
.VertexURBEntryReadOffset
= 0;
1262 /* BRW_NEW_URB_FENCE */
1263 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1264 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1266 if (brw
->urb
.nr_clip_entries
>= 10) {
1267 /* Half of the URB entries go to each thread, and it has to be an
1270 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1272 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1273 * only 2 threads can output VUEs at a time.
1275 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1277 assert(brw
->urb
.nr_clip_entries
>= 5);
1278 clip
.MaximumNumberofThreads
= 1 - 1;
1281 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1282 clip
.UserClipFlagsMustClipEnable
= true;
1283 clip
.GuardbandClipTestEnable
= true;
1285 clip
.ClipperViewportStatePointer
=
1286 ro_bo(brw
->batch
.state_bo
, brw
->clip
.vp_offset
);
1288 clip
.ScreenSpaceViewportXMin
= -1;
1289 clip
.ScreenSpaceViewportXMax
= 1;
1290 clip
.ScreenSpaceViewportYMin
= -1;
1291 clip
.ScreenSpaceViewportYMax
= 1;
1293 clip
.ViewportXYClipTestEnable
= true;
1294 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1296 /* _NEW_TRANSFORM */
1297 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1298 clip
.UserClipDistanceClipTestEnableBitmask
=
1299 ctx
->Transform
.ClipPlanesEnabled
;
1301 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1304 clip
.UserClipDistanceClipTestEnableBitmask
=
1305 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1308 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1309 clip
.APIMode
= APIMODE_D3D
;
1311 clip
.APIMode
= APIMODE_OGL
;
1313 clip
.GuardbandClipTestEnable
= true;
1315 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1318 clip
.NegativeWClipTestEnable
= true;
1323 const struct brw_tracked_state
genX(clip_state
) = {
1325 .mesa
= _NEW_TRANSFORM
|
1327 .brw
= BRW_NEW_BATCH
|
1329 BRW_NEW_CLIP_PROG_DATA
|
1330 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1331 BRW_NEW_PROGRAM_CACHE
|
1334 .emit
= genX(upload_clip_state
),
1340 genX(upload_clip_state
)(struct brw_context
*brw
)
1342 struct gl_context
*ctx
= &brw
->ctx
;
1345 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1347 /* BRW_NEW_FS_PROG_DATA */
1348 struct brw_wm_prog_data
*wm_prog_data
=
1349 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1351 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1352 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1354 if (wm_prog_data
->barycentric_interp_modes
&
1355 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1356 clip
.NonPerspectiveBarycentricEnable
= true;
1359 clip
.EarlyCullEnable
= true;
1363 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1365 if (ctx
->Polygon
.CullFlag
) {
1366 switch (ctx
->Polygon
.CullFaceMode
) {
1368 clip
.CullMode
= CULLMODE_FRONT
;
1371 clip
.CullMode
= CULLMODE_BACK
;
1373 case GL_FRONT_AND_BACK
:
1374 clip
.CullMode
= CULLMODE_BOTH
;
1377 unreachable("Should not get here: invalid CullFlag");
1380 clip
.CullMode
= CULLMODE_NONE
;
1385 clip
.UserClipDistanceCullTestEnableBitmask
=
1386 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1388 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1392 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1393 clip
.TriangleStripListProvokingVertexSelect
= 0;
1394 clip
.TriangleFanProvokingVertexSelect
= 1;
1395 clip
.LineStripListProvokingVertexSelect
= 0;
1397 clip
.TriangleStripListProvokingVertexSelect
= 2;
1398 clip
.TriangleFanProvokingVertexSelect
= 2;
1399 clip
.LineStripListProvokingVertexSelect
= 1;
1402 /* _NEW_TRANSFORM */
1403 clip
.UserClipDistanceClipTestEnableBitmask
=
1404 ctx
->Transform
.ClipPlanesEnabled
;
1407 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1410 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1411 clip
.APIMode
= APIMODE_D3D
;
1413 clip
.APIMode
= APIMODE_OGL
;
1415 clip
.GuardbandClipTestEnable
= true;
1417 /* BRW_NEW_VIEWPORT_COUNT */
1418 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1420 if (ctx
->RasterDiscard
) {
1421 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1423 perf_debug("Rasterizer discard is currently implemented via the "
1424 "clipper; having the GS not write primitives would "
1425 "likely be faster.\n");
1428 clip
.ClipMode
= CLIPMODE_NORMAL
;
1431 clip
.ClipEnable
= true;
1434 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1436 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1437 clip
.ViewportXYClipTestEnable
= true;
1439 clip
.MinimumPointWidth
= 0.125;
1440 clip
.MaximumPointWidth
= 255.875;
1441 clip
.MaximumVPIndex
= viewport_count
- 1;
1442 if (_mesa_geometric_layers(fb
) == 0)
1443 clip
.ForceZeroRTAIndexEnable
= true;
1447 static const struct brw_tracked_state
genX(clip_state
) = {
1449 .mesa
= _NEW_BUFFERS
|
1453 .brw
= BRW_NEW_BLORP
|
1455 BRW_NEW_FS_PROG_DATA
|
1456 BRW_NEW_GS_PROG_DATA
|
1457 BRW_NEW_VS_PROG_DATA
|
1458 BRW_NEW_META_IN_PROGRESS
|
1460 BRW_NEW_RASTERIZER_DISCARD
|
1461 BRW_NEW_TES_PROG_DATA
|
1462 BRW_NEW_VIEWPORT_COUNT
,
1464 .emit
= genX(upload_clip_state
),
1468 /* ---------------------------------------------------------------------- */
1471 genX(upload_sf
)(struct brw_context
*brw
)
1473 struct gl_context
*ctx
= &brw
->ctx
;
1478 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1479 UNUSED
const bool multisampled_fbo
=
1480 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1484 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1486 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1488 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1489 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1490 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1491 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1492 sf
.DispatchGRFStartRegisterForURBData
= 3;
1493 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1494 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1495 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1496 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1498 /* STATE_PREFETCH command description describes this state as being
1499 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1502 sf
.SetupViewportStateOffset
=
1503 ro_bo(brw
->batch
.state_bo
, brw
->sf
.vp_offset
);
1505 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1507 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1508 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1510 sf
.MaximumNumberofThreads
=
1511 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1513 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1515 sf
.DestinationOriginHorizontalBias
= 0.5;
1516 sf
.DestinationOriginVerticalBias
= 0.5;
1518 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1519 sf
.StatisticsEnable
= true;
1521 sf
.ViewportTransformEnable
= true;
1525 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1530 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1532 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1533 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1534 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1536 switch (ctx
->Polygon
.FrontMode
) {
1538 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1541 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1544 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1547 unreachable("not reached");
1550 switch (ctx
->Polygon
.BackMode
) {
1552 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1555 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1558 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1561 unreachable("not reached");
1564 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1565 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1567 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1568 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1569 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1572 sf
.ScissorRectangleEnable
= true;
1574 if (ctx
->Polygon
.CullFlag
) {
1575 switch (ctx
->Polygon
.CullFaceMode
) {
1577 sf
.CullMode
= CULLMODE_FRONT
;
1580 sf
.CullMode
= CULLMODE_BACK
;
1582 case GL_FRONT_AND_BACK
:
1583 sf
.CullMode
= CULLMODE_BOTH
;
1586 unreachable("not reached");
1589 sf
.CullMode
= CULLMODE_NONE
;
1593 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1600 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1602 if (devinfo
->is_cherryview
)
1603 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1605 sf
.LineWidth
= brw_get_line_width(brw
);
1607 sf
.LineWidth
= brw_get_line_width(brw
);
1610 if (ctx
->Line
.SmoothFlag
) {
1611 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1613 sf
.AntiAliasingEnable
= true;
1617 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1618 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1619 /* Clamp to the hardware limits */
1620 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1622 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1623 if (use_state_point_size(brw
))
1624 sf
.PointWidthSource
= State
;
1627 /* _NEW_POINT | _NEW_MULTISAMPLE */
1628 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1629 !ctx
->Point
.PointSprite
)
1630 sf
.SmoothPointEnable
= true;
1633 #if GEN_IS_G4X || GEN_GEN >= 5
1634 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1638 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1639 sf
.TriangleStripListProvokingVertexSelect
= 2;
1640 sf
.TriangleFanProvokingVertexSelect
= 2;
1641 sf
.LineStripListProvokingVertexSelect
= 1;
1643 sf
.TriangleFanProvokingVertexSelect
= 1;
1647 /* BRW_NEW_FS_PROG_DATA */
1648 const struct brw_wm_prog_data
*wm_prog_data
=
1649 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1651 sf
.AttributeSwizzleEnable
= true;
1652 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1655 * Window coordinates in an FBO are inverted, which means point
1656 * sprite origin must be inverted, too.
1658 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1659 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1661 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1664 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1665 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1667 uint32_t urb_entry_read_length
;
1668 uint32_t urb_entry_read_offset
;
1669 uint32_t point_sprite_enables
;
1670 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1671 &urb_entry_read_length
,
1672 &urb_entry_read_offset
);
1673 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1674 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1675 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1676 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1681 static const struct brw_tracked_state
genX(sf_state
) = {
1683 .mesa
= _NEW_LIGHT
|
1687 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1688 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1689 .brw
= BRW_NEW_BLORP
|
1690 BRW_NEW_VUE_MAP_GEOM_OUT
|
1691 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1692 BRW_NEW_PROGRAM_CACHE
|
1693 BRW_NEW_SF_PROG_DATA
|
1697 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1698 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1699 BRW_NEW_GS_PROG_DATA
|
1701 BRW_NEW_TES_PROG_DATA
1703 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1704 BRW_NEW_FRAGMENT_PROGRAM
1707 .emit
= genX(upload_sf
),
1710 /* ---------------------------------------------------------------------- */
1713 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1715 struct gl_context
*ctx
= &brw
->ctx
;
1716 /* BRW_NEW_FRAGMENT_PROGRAM */
1717 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1721 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1722 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1723 uint64_t outputs_written
= fp
->info
.outputs_written
;
1726 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1727 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1728 (ctx
->Color
.ColorMask
[i
][0] ||
1729 ctx
->Color
.ColorMask
[i
][1] ||
1730 ctx
->Color
.ColorMask
[i
][2] ||
1731 ctx
->Color
.ColorMask
[i
][3])) {
1740 genX(upload_wm
)(struct brw_context
*brw
)
1742 struct gl_context
*ctx
= &brw
->ctx
;
1744 /* BRW_NEW_FS_PROG_DATA */
1745 const struct brw_wm_prog_data
*wm_prog_data
=
1746 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1748 UNUSED
bool writes_depth
=
1749 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1750 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1751 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1754 /* We can't fold this into gen6_upload_wm_push_constants(), because
1755 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1756 * (3DSTATE_CONSTANT_PS [DevSNB]):
1758 * "[DevSNB]: This packet must be followed by WM_STATE."
1760 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1761 if (wm_prog_data
->base
.nr_params
!= 0) {
1762 wmcp
.Buffer0Valid
= true;
1763 /* Pointer to the WM constant buffer. Covered by the set of
1764 * state flags from gen6_upload_wm_push_constants.
1766 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1767 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1773 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1774 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1775 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1777 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1778 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1780 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1781 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1782 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1783 /* These two fields should be the same pre-gen6, which is why we
1784 * only have one hardware field to program for both dispatch
1787 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1788 wm_prog_data
->dispatch_grf_start_reg_2
);
1791 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1792 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1794 if (stage_state
->sampler_count
)
1795 wm
.SamplerStatePointer
=
1796 ro_bo(brw
->batch
.state_bo
, stage_state
->sampler_offset
);
1798 if (wm_prog_data
->prog_offset_2
)
1799 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1802 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1803 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1804 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1805 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1806 wm
.EarlyDepthTestEnable
= true;
1807 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1808 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1811 if (ctx
->Polygon
.OffsetFill
) {
1812 wm
.GlobalDepthOffsetEnable
= true;
1813 /* Something weird going on with legacy_global_depth_bias,
1814 * offset_constant, scaling and MRD. This value passes glean
1815 * but gives some odd results elsewere (eg. the
1816 * quad-offset-units test).
1818 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1820 /* This is the only value that passes glean:
1822 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1825 wm
.DepthCoefficientURBReadOffset
= 1;
1828 /* BRW_NEW_STATS_WM */
1829 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1832 if (wm_prog_data
->base
.use_alt_mode
)
1833 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1835 wm
.SamplerCount
= GEN_GEN
== 5 ?
1836 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1838 wm
.BindingTableEntryCount
=
1839 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1840 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1841 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1842 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1843 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1844 wm_prog_data
->base
.dispatch_grf_start_reg
;
1846 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1847 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1851 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1852 wm
.KernelStartPointer2
=
1853 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1858 wm
.DualSourceBlendEnable
=
1859 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1860 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1861 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1862 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1864 /* From the SNB PRM, volume 2 part 1, page 281:
1865 * "If the PS kernel does not need the Position XY Offsets
1866 * to compute a Position XY value, then this field should be
1867 * programmed to POSOFFSET_NONE."
1869 * "SW Recommendation: If the PS kernel needs the Position Offsets
1870 * to compute a Position XY value, this field should match Position
1871 * ZW Interpolation Mode to ensure a consistent position.xyzw
1873 * We only require XY sample offsets. So, this recommendation doesn't
1874 * look useful at the moment. We might need this in future.
1876 if (wm_prog_data
->uses_pos_offset
)
1877 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1879 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1881 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1882 wm_prog_data
->dispatch_grf_start_reg_2
;
1885 if (wm_prog_data
->base
.total_scratch
) {
1886 wm
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
1887 wm
.PerThreadScratchSpace
=
1888 ffs(stage_state
->per_thread_scratch
) - 11;
1891 wm
.PixelShaderComputedDepth
= writes_depth
;
1895 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1898 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1903 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1906 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1908 if (multisampled_fbo
) {
1909 /* _NEW_MULTISAMPLE */
1910 if (ctx
->Multisample
.Enabled
)
1911 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1913 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1915 if (wm_prog_data
->persample_dispatch
)
1916 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1918 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1920 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1921 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1924 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1925 if (wm_prog_data
->uses_kill
||
1926 _mesa_is_alpha_test_enabled(ctx
) ||
1927 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1928 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1929 wm
.PixelShaderKillsPixel
= true;
1932 /* _NEW_BUFFERS | _NEW_COLOR */
1933 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1934 wm
.PixelShaderKillsPixel
||
1935 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1936 wm
.ThreadDispatchEnable
= true;
1940 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1941 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1944 /* The "UAV access enable" bits are unnecessary on HSW because they only
1945 * seem to have an effect on the HW-assisted coherency mechanism which we
1946 * don't need, and the rasterization-related UAV_ONLY flag and the
1947 * DISPATCH_ENABLE bit can be set independently from it.
1948 * C.f. gen8_upload_ps_extra().
1950 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1954 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1955 wm_prog_data
->has_side_effects
)
1961 /* BRW_NEW_FS_PROG_DATA */
1962 if (wm_prog_data
->early_fragment_tests
)
1963 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1964 else if (wm_prog_data
->has_side_effects
)
1965 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1970 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
1971 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
1972 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1975 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
1980 static const struct brw_tracked_state
genX(wm_state
) = {
1984 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1987 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
1988 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
1989 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
1990 .brw
= BRW_NEW_BLORP
|
1991 BRW_NEW_FS_PROG_DATA
|
1992 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1993 BRW_NEW_FRAGMENT_PROGRAM
|
1994 BRW_NEW_PROGRAM_CACHE
|
1995 BRW_NEW_SAMPLER_STATE_TABLE
|
1998 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2000 .emit
= genX(upload_wm
),
2003 /* ---------------------------------------------------------------------- */
2005 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2006 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2007 pkt.SamplerCount = \
2008 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2009 pkt.BindingTableEntryCount = \
2010 stage_prog_data->binding_table.size_bytes / 4; \
2011 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2013 if (stage_prog_data->total_scratch) { \
2014 pkt.ScratchSpaceBasePointer = rw_bo(stage_state->scratch_bo, 0); \
2015 pkt.PerThreadScratchSpace = \
2016 ffs(stage_state->per_thread_scratch) - 11; \
2019 pkt.DispatchGRFStartRegisterForURBData = \
2020 stage_prog_data->dispatch_grf_start_reg; \
2021 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2022 pkt.prefix##URBEntryReadOffset = 0; \
2024 pkt.StatisticsEnable = true; \
2028 genX(upload_vs_state
)(struct brw_context
*brw
)
2030 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2031 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2032 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2034 /* BRW_NEW_VS_PROG_DATA */
2035 const struct brw_vue_prog_data
*vue_prog_data
=
2036 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2037 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2039 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2040 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2043 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2044 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2046 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2047 * command that causes the VS Function Enable to toggle. Pipeline
2048 * flush can be executed by sending a PIPE_CONTROL command with CS
2049 * stall bit set and a post sync operation.
2051 * We've already done such a flush at the start of state upload, so we
2052 * don't need to do another one here.
2054 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2055 if (stage_state
->push_const_size
!= 0) {
2056 cvs
.Buffer0Valid
= true;
2057 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2058 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2063 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2064 gen7_emit_vs_workaround_flush(brw
);
2067 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2069 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2070 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2072 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2074 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2077 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2078 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2079 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2081 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2082 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2084 vs
.MaximumNumberofThreads
=
2085 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2087 vs
.StatisticsEnable
= false;
2088 vs
.SamplerStatePointer
=
2089 ro_bo(brw
->batch
.state_bo
, stage_state
->sampler_offset
);
2093 /* Force single program flow on Ironlake. We cannot reliably get
2094 * all applications working without it. See:
2095 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2097 * The most notable and reliably failing application is the Humus
2100 vs
.SingleProgramFlow
= true;
2101 vs
.SamplerCount
= 0; /* hardware requirement */
2105 vs
.SIMD8DispatchEnable
=
2106 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2108 vs
.UserClipDistanceCullTestEnableBitmask
=
2109 vue_prog_data
->cull_distance_mask
;
2114 /* Based on my reading of the simulator, the VS constants don't get
2115 * pulled into the VS FF unit until an appropriate pipeline flush
2116 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2117 * references to them into a little FIFO. The flushes are common,
2118 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2119 * the primitive to use the wrong constants. Then the FIFO
2120 * containing the constant setup gets added to again on the next
2121 * constants change, and eventually when a flush does happen the
2122 * unit is overwhelmed by constant changes and dies.
2124 * To avoid this, send a PIPE_CONTROL down the line that will
2125 * update the unit immediately loading the constants. The flush
2126 * type bits here were those set by the STATE_BASE_ADDRESS whose
2127 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2128 * bug reports that led to this workaround, and may be more than
2129 * what is strictly required to avoid the issue.
2131 brw_emit_pipe_control_flush(brw
,
2132 PIPE_CONTROL_DEPTH_STALL
|
2133 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2134 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2138 static const struct brw_tracked_state
genX(vs_state
) = {
2140 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2141 .brw
= BRW_NEW_BATCH
|
2144 BRW_NEW_VS_PROG_DATA
|
2145 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2146 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2147 BRW_NEW_PROGRAM_CACHE
|
2148 BRW_NEW_SAMPLER_STATE_TABLE
|
2152 .emit
= genX(upload_vs_state
),
2155 /* ---------------------------------------------------------------------- */
2158 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2160 struct gl_context
*ctx
= &brw
->ctx
;
2162 /* BRW_NEW_VIEWPORT_COUNT */
2163 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2165 struct GENX(CC_VIEWPORT
) ccv
;
2166 uint32_t cc_vp_offset
;
2168 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2171 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2172 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2173 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2174 if (ctx
->Transform
.DepthClamp
) {
2175 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2176 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2178 ccv
.MinimumDepth
= 0.0;
2179 ccv
.MaximumDepth
= 1.0;
2181 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2182 cc_map
+= GENX(CC_VIEWPORT_length
);
2186 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2187 ptr
.CCViewportPointer
= cc_vp_offset
;
2190 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2191 vp
.CCViewportStateChange
= 1;
2192 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2195 brw
->cc
.vp_offset
= cc_vp_offset
;
2196 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2200 const struct brw_tracked_state
genX(cc_vp
) = {
2202 .mesa
= _NEW_TRANSFORM
|
2204 .brw
= BRW_NEW_BATCH
|
2206 BRW_NEW_VIEWPORT_COUNT
,
2208 .emit
= genX(upload_cc_viewport
)
2211 /* ---------------------------------------------------------------------- */
2214 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2215 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2216 struct GENX(SCISSOR_RECT
) *sc
)
2220 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2221 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2222 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2223 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2224 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2226 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2227 /* If the scissor was out of bounds and got clamped to 0 width/height
2228 * at the bounds, the subtraction of 1 from maximums could produce a
2229 * negative number and thus not clip anything. Instead, just provide
2230 * a min > max scissor inside the bounds, which produces the expected
2233 sc
->ScissorRectangleXMin
= 1;
2234 sc
->ScissorRectangleXMax
= 0;
2235 sc
->ScissorRectangleYMin
= 1;
2236 sc
->ScissorRectangleYMax
= 0;
2237 } else if (render_to_fbo
) {
2238 /* texmemory: Y=0=bottom */
2239 sc
->ScissorRectangleXMin
= bbox
[0];
2240 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2241 sc
->ScissorRectangleYMin
= bbox
[2];
2242 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2244 /* memory: Y=0=top */
2245 sc
->ScissorRectangleXMin
= bbox
[0];
2246 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2247 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2248 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2254 genX(upload_scissor_state
)(struct brw_context
*brw
)
2256 struct gl_context
*ctx
= &brw
->ctx
;
2257 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2258 struct GENX(SCISSOR_RECT
) scissor
;
2259 uint32_t scissor_state_offset
;
2260 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2261 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2262 uint32_t *scissor_map
;
2264 /* BRW_NEW_VIEWPORT_COUNT */
2265 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2267 scissor_map
= brw_state_batch(
2268 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2269 32, &scissor_state_offset
);
2271 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2273 /* The scissor only needs to handle the intersection of drawable and
2274 * scissor rect. Clipping to the boundaries of static shared buffers
2275 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2277 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2278 * inclusive but max is exclusive.
2280 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2281 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2282 GENX(SCISSOR_RECT_pack
)(
2283 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2286 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2287 ptr
.ScissorRectPointer
= scissor_state_offset
;
2291 static const struct brw_tracked_state
genX(scissor_state
) = {
2293 .mesa
= _NEW_BUFFERS
|
2296 .brw
= BRW_NEW_BATCH
|
2298 BRW_NEW_VIEWPORT_COUNT
,
2300 .emit
= genX(upload_scissor_state
),
2304 /* ---------------------------------------------------------------------- */
2307 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2308 float m00
, float m11
, float m30
, float m31
,
2309 float *xmin
, float *xmax
,
2310 float *ymin
, float *ymax
)
2312 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2313 * Strips and Fans documentation:
2315 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2316 * fixed-point "guardband" range supported by the rasterization hardware"
2320 * "In almost all circumstances, if an object’s vertices are actually
2321 * modified by this clamping (i.e., had X or Y coordinates outside of
2322 * the guardband extent the rendered object will not match the intended
2323 * result. Therefore software should take steps to ensure that this does
2324 * not happen - e.g., by clipping objects such that they do not exceed
2325 * these limits after the Drawing Rectangle is applied."
2327 * I believe the fundamental restriction is that the rasterizer (in
2328 * the SF/WM stages) have a limit on the number of pixels that can be
2329 * rasterized. We need to ensure any coordinates beyond the rasterizer
2330 * limit are handled by the clipper. So effectively that limit becomes
2331 * the clipper's guardband size.
2333 * It goes on to say:
2335 * "In addition, in order to be correctly rendered, objects must have a
2336 * screenspace bounding box not exceeding 8K in the X or Y direction.
2337 * This additional restriction must also be comprehended by software,
2338 * i.e., enforced by use of clipping."
2340 * This makes no sense. Gen7+ hardware supports 16K render targets,
2341 * and you definitely need to be able to draw polygons that fill the
2342 * surface. Our assumption is that the rasterizer was limited to 8K
2343 * on Sandybridge, which only supports 8K surfaces, and it was actually
2344 * increased to 16K on Ivybridge and later.
2346 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2348 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2350 if (m00
!= 0 && m11
!= 0) {
2351 /* First, we compute the screen-space render area */
2352 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2353 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2354 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2355 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2357 /* We want the guardband to be centered on that */
2358 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2359 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2360 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2361 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2363 /* Now we need it in native device coordinates */
2364 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2365 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2366 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2367 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2369 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2370 * flipped upside-down. X should be fine though.
2372 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2373 *xmin
= ndc_gb_xmin
;
2374 *xmax
= ndc_gb_xmax
;
2375 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2376 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2378 /* The viewport scales to 0, so nothing will be rendered. */
2387 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2389 struct gl_context
*ctx
= &brw
->ctx
;
2390 float y_scale
, y_bias
;
2392 /* BRW_NEW_VIEWPORT_COUNT */
2393 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2396 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2397 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2398 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2402 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2403 uint32_t sf_clip_vp_offset
;
2404 uint32_t *sf_clip_map
=
2405 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2406 64, &sf_clip_vp_offset
);
2408 struct GENX(SF_VIEWPORT
) sfv
;
2409 struct GENX(CLIP_VIEWPORT
) clv
;
2410 uint32_t sf_vp_offset
, clip_vp_offset
;
2412 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2414 uint32_t *clip_map
=
2415 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2416 32, &clip_vp_offset
);
2420 if (render_to_fbo
) {
2425 y_bias
= (float)fb_height
;
2428 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2429 /* _NEW_VIEWPORT: Guardband Clipping */
2430 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2431 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2433 sfv
.ViewportMatrixElementm00
= scale
[0];
2434 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2435 sfv
.ViewportMatrixElementm22
= scale
[2],
2436 sfv
.ViewportMatrixElementm30
= translate
[0],
2437 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2438 sfv
.ViewportMatrixElementm32
= translate
[2],
2439 brw_calculate_guardband_size(fb_width
, fb_height
,
2440 sfv
.ViewportMatrixElementm00
,
2441 sfv
.ViewportMatrixElementm11
,
2442 sfv
.ViewportMatrixElementm30
,
2443 sfv
.ViewportMatrixElementm31
,
2444 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2447 clv
.XMinClipGuardband
= gb_xmin
;
2448 clv
.XMaxClipGuardband
= gb_xmax
;
2449 clv
.YMinClipGuardband
= gb_ymin
;
2450 clv
.YMaxClipGuardband
= gb_ymax
;
2453 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2454 &sfv
.ScissorRectangle
);
2456 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2457 * The hardware will take the intersection of the drawing rectangle,
2458 * scissor rectangle, and the viewport extents. We don't need to be
2459 * smart, and can therefore just program the viewport extents.
2461 const float viewport_Xmax
=
2462 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2463 const float viewport_Ymax
=
2464 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2466 if (render_to_fbo
) {
2467 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2468 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2469 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2470 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2472 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2473 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2474 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2475 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2480 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2481 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2483 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2484 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2485 sf_map
+= GENX(SF_VIEWPORT_length
);
2486 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2491 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2492 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2495 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2496 vp
.SFViewportStateChange
= 1;
2497 vp
.CLIPViewportStateChange
= 1;
2498 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2499 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2502 brw
->sf
.vp_offset
= sf_vp_offset
;
2503 brw
->clip
.vp_offset
= clip_vp_offset
;
2504 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2508 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2510 .mesa
= _NEW_BUFFERS
|
2512 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2513 .brw
= BRW_NEW_BATCH
|
2515 BRW_NEW_VIEWPORT_COUNT
,
2517 .emit
= genX(upload_sf_clip_viewport
),
2520 /* ---------------------------------------------------------------------- */
2523 genX(upload_gs_state
)(struct brw_context
*brw
)
2525 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2526 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2527 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2528 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2529 /* BRW_NEW_GEOMETRY_PROGRAM */
2530 bool active
= GEN_GEN
>= 6 && gs_prog
;
2532 /* BRW_NEW_GS_PROG_DATA */
2533 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2534 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2535 brw_vue_prog_data(stage_prog_data
);
2537 const struct brw_gs_prog_data
*gs_prog_data
=
2538 brw_gs_prog_data(stage_prog_data
);
2542 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2543 if (active
&& stage_state
->push_const_size
!= 0) {
2544 cgs
.Buffer0Valid
= true;
2545 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2546 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2551 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2553 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2554 * Geometry > Geometry Shader > State:
2556 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2557 * whole fixed function pipeline when the GS enable changes value in
2560 * The hardware architects have clarified that in this context "flush the
2561 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2564 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2565 gen7_emit_cs_stall_flush(brw
);
2569 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2571 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2572 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2577 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2580 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2581 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2582 gs
.ControlDataHeaderSize
=
2583 gs_prog_data
->control_data_header_size_hwords
;
2585 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2586 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2588 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2590 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2593 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2594 * Ivy Bridge and Haswell.
2596 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2597 * strip to be delivered to the geometry shader in an order that does
2598 * not strictly follow the OpenGL spec, but preserves triangle
2599 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2600 * the geometry shader sees triangles:
2602 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2604 * (Clearing the bit is even worse, because it fails to preserve
2607 * Triangle strips with adjacency always ordered in a way that preserves
2608 * triangle orientation but does not strictly follow the OpenGL spec,
2609 * regardless of the setting of this bit.
2611 * On Haswell, both triangle strips and triangle strips with adjacency
2612 * are always ordered in a way that preserves triangle orientation.
2613 * Setting this bit causes the ordering to strictly follow the OpenGL
2616 * So in either case we want to set the bit. Unfortunately on Ivy
2617 * Bridge this will get the order close to correct but not perfect.
2619 gs
.ReorderMode
= TRAILING
;
2620 gs
.MaximumNumberofThreads
=
2621 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2622 : (devinfo
->max_gs_threads
- 1);
2625 gs
.SOStatisticsEnable
= true;
2626 if (gs_prog
->info
.has_transform_feedback_varyings
)
2627 gs
.SVBIPayloadEnable
= true;
2629 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2630 * was previously done for gen6.
2632 * TODO: test with both disabled to see if the HW is behaving
2633 * as expected, like in gen7.
2635 gs
.SingleProgramFlow
= true;
2636 gs
.VectorMaskEnable
= true;
2640 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2642 if (gs_prog_data
->static_vertex_count
!= -1) {
2643 gs
.StaticOutput
= true;
2644 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2646 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2648 gs
.UserClipDistanceCullTestEnableBitmask
=
2649 vue_prog_data
->cull_distance_mask
;
2651 const int urb_entry_write_offset
= 1;
2652 const uint32_t urb_entry_output_length
=
2653 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2654 urb_entry_write_offset
;
2656 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2657 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2663 if (!active
&& brw
->ff_gs
.prog_active
) {
2664 /* In gen6, transform feedback for the VS stage is done with an
2665 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2668 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2669 gs
.SingleProgramFlow
= true;
2670 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2671 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2674 gs
.GRFRegisterCount
=
2675 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2676 /* BRW_NEW_URB_FENCE */
2677 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2678 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2679 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2680 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2683 gs
.VectorMaskEnable
= true;
2684 gs
.SVBIPayloadEnable
= true;
2685 gs
.SVBIPostIncrementEnable
= true;
2686 gs
.SVBIPostIncrementValue
=
2687 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2688 gs
.SOStatisticsEnable
= true;
2689 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2693 if (!active
&& !brw
->ff_gs
.prog_active
) {
2695 gs
.DispatchGRFStartRegisterForURBData
= 1;
2697 gs
.IncludeVertexHandles
= true;
2703 gs
.StatisticsEnable
= true;
2705 #if GEN_GEN == 5 || GEN_GEN == 6
2706 gs
.RenderingEnabled
= true;
2709 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2714 brw
->gs
.enabled
= active
;
2718 static const struct brw_tracked_state
genX(gs_state
) = {
2720 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2721 .brw
= BRW_NEW_BATCH
|
2723 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2724 BRW_NEW_PROGRAM_CACHE
|
2726 BRW_NEW_VIEWPORT_COUNT
2728 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2729 BRW_NEW_GEOMETRY_PROGRAM
|
2730 BRW_NEW_GS_PROG_DATA
2732 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2734 .emit
= genX(upload_gs_state
),
2737 /* ---------------------------------------------------------------------- */
2739 UNUSED
static GLenum
2740 fix_dual_blend_alpha_to_one(GLenum function
)
2746 case GL_ONE_MINUS_SRC1_ALPHA
:
2753 #define blend_factor(x) brw_translate_blend_factor(x)
2754 #define blend_eqn(x) brw_translate_blend_equation(x)
2757 * Modify blend function to force destination alpha to 1.0
2759 * If \c function specifies a blend function that uses destination alpha,
2760 * replace it with a function that hard-wires destination alpha to 1.0. This
2761 * is used when rendering to xRGB targets.
2764 brw_fix_xRGB_alpha(GLenum function
)
2770 case GL_ONE_MINUS_DST_ALPHA
:
2771 case GL_SRC_ALPHA_SATURATE
:
2779 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2781 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2785 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2788 struct gl_context
*ctx
= &brw
->ctx
;
2791 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2793 bool independent_alpha_blend
= false;
2795 /* Used for implementing the following bit of GL_EXT_texture_integer:
2796 * "Per-fragment operations that require floating-point color
2797 * components, including multisample alpha operations, alpha test,
2798 * blending, and dithering, have no effect when the corresponding
2799 * colors are written to an integer color buffer."
2801 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2803 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2804 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2807 if (ctx
->Color
.ColorLogicOpEnabled
) {
2808 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2809 : GL_UNSIGNED_NORMALIZED
;
2810 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2811 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2812 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2814 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2815 _mesa_enum_to_string(rb_type
));
2816 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2817 entry
->LogicOpEnable
= true;
2818 entry
->LogicOpFunction
=
2819 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2821 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2822 && (GEN_GEN
<= 5 || !integer
)) {
2823 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2824 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2825 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2826 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2827 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2828 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2830 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2831 srcRGB
= dstRGB
= GL_ONE
;
2833 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2834 srcA
= dstA
= GL_ONE
;
2836 /* Due to hardware limitations, the destination may have information
2837 * in an alpha channel even when the format specifies no alpha
2838 * channel. In order to avoid getting any incorrect blending due to
2839 * that alpha channel, coerce the blend factors to values that will
2840 * not read the alpha channel, but will instead use the correct
2841 * implicit value for alpha.
2843 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2844 GL_TEXTURE_ALPHA_TYPE
)) {
2845 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2846 srcA
= brw_fix_xRGB_alpha(srcA
);
2847 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2848 dstA
= brw_fix_xRGB_alpha(dstA
);
2851 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2852 * "If Dual Source Blending is enabled, this bit must be disabled."
2854 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2855 * and leave it enabled anyway.
2857 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2858 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2859 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2860 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2861 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2864 entry
->ColorBufferBlendEnable
= true;
2865 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2866 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2867 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2868 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2869 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2870 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2872 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2873 independent_alpha_blend
= true;
2876 return independent_alpha_blend
;
2881 genX(upload_blend_state
)(struct brw_context
*brw
)
2883 struct gl_context
*ctx
= &brw
->ctx
;
2886 /* We need at least one BLEND_STATE written, because we might do
2887 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2888 * for computed depth or alpha test), which will do an FB write
2889 * with render target 0, which will reference BLEND_STATE[0] for
2890 * alpha test enable.
2892 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2893 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2894 nr_draw_buffers
= 1;
2896 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2898 size
+= GENX(BLEND_STATE_length
) * 4;
2901 uint32_t *blend_map
;
2902 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2905 struct GENX(BLEND_STATE
) blend
= { 0 };
2908 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2909 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2912 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2913 * "If drawbuffer zero is not NONE and the buffer it references has an
2914 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2915 * operations are skipped."
2917 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2918 /* _NEW_MULTISAMPLE */
2919 if (_mesa_is_multisample_enabled(ctx
)) {
2920 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2921 blend
.AlphaToCoverageEnable
= true;
2922 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2924 if (ctx
->Multisample
.SampleAlphaToOne
)
2925 blend
.AlphaToOneEnable
= true;
2929 if (ctx
->Color
.AlphaEnabled
) {
2930 blend
.AlphaTestEnable
= true;
2931 blend
.AlphaTestFunction
=
2932 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2935 if (ctx
->Color
.DitherFlag
) {
2936 blend
.ColorDitherEnable
= true;
2941 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2942 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2946 blend
.IndependentAlphaBlendEnable
=
2947 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
2948 blend
.IndependentAlphaBlendEnable
;
2950 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2951 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2953 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2954 * clamping in the fragment shader. For its clamping of
2955 * blending, the spec says:
2957 * "RESOLVED: For fixed-point color buffers, the inputs and
2958 * the result of the blending equation are clamped. For
2959 * floating-point color buffers, no clamping occurs."
2961 * So, generally, we want clamping to the render target's range.
2962 * And, good news, the hardware tables for both pre- and
2963 * post-blend color clamping are either ignored, or any are
2964 * allowed, or clamping is required but RT range clamping is a
2967 entry
.PreBlendColorClampEnable
= true;
2968 entry
.PostBlendColorClampEnable
= true;
2969 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2971 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2972 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2973 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2974 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2977 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2979 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2985 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2989 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2990 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2991 ptr
.BLEND_STATEChange
= true;
2994 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2995 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2997 ptr
.BlendStatePointerValid
= true;
3003 static const struct brw_tracked_state
genX(blend_state
) = {
3005 .mesa
= _NEW_BUFFERS
|
3008 .brw
= BRW_NEW_BATCH
|
3010 BRW_NEW_STATE_BASE_ADDRESS
,
3012 .emit
= genX(upload_blend_state
),
3016 /* ---------------------------------------------------------------------- */
3019 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3020 [MESA_SHADER_VERTEX
] = 21,
3021 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3022 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3023 [MESA_SHADER_GEOMETRY
] = 22,
3024 [MESA_SHADER_FRAGMENT
] = 23,
3025 [MESA_SHADER_COMPUTE
] = 0,
3029 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3031 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3032 struct gl_context
*ctx
= &brw
->ctx
;
3034 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3036 struct brw_stage_state
*stage_states
[] = {
3044 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3045 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3046 gen7_emit_vs_workaround_flush(brw
);
3048 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3049 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3050 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3052 if (!stage_state
->push_constants_dirty
)
3055 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3056 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3057 if (stage_state
->prog_data
) {
3058 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3059 /* The Skylake PRM contains the following restriction:
3061 * "The driver must ensure The following case does not occur
3062 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3063 * buffer 3 read length equal to zero committed followed by a
3064 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3067 * To avoid this, we program the buffers in the highest slots.
3068 * This way, slot 0 is only used if slot 3 is also used.
3072 for (int i
= 3; i
>= 0; i
--) {
3073 const struct brw_ubo_range
*range
=
3074 &stage_state
->prog_data
->ubo_ranges
[i
];
3076 if (range
->length
== 0)
3079 const struct gl_uniform_block
*block
=
3080 prog
->sh
.UniformBlocks
[range
->block
];
3081 const struct gl_uniform_buffer_binding
*binding
=
3082 &ctx
->UniformBufferBindings
[block
->Binding
];
3084 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3085 static unsigned msg_id
= 0;
3086 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3087 MESA_DEBUG_TYPE_UNDEFINED
,
3088 MESA_DEBUG_SEVERITY_HIGH
,
3089 "UBO %d unbound, %s shader uniform data "
3090 "will be undefined.",
3092 _mesa_shader_stage_to_string(stage
));
3096 assert(binding
->Offset
% 32 == 0);
3098 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3099 intel_buffer_object(binding
->BufferObject
),
3100 binding
->Offset
, range
->length
* 32, false);
3102 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3103 pkt
.ConstantBody
.Buffer
[n
] =
3104 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3108 if (stage_state
->push_const_size
> 0) {
3110 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3111 pkt
.ConstantBody
.Buffer
[n
] =
3112 ro_bo(stage_state
->push_const_bo
,
3113 stage_state
->push_const_offset
);
3116 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3117 pkt
.ConstantBody
.Buffer
[0].offset
=
3118 stage_state
->push_const_offset
| mocs
;
3123 stage_state
->push_constants_dirty
= false;
3126 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3129 const struct brw_tracked_state
genX(push_constant_packets
) = {
3132 .brw
= BRW_NEW_DRAW_CALL
,
3134 .emit
= genX(upload_push_constant_packets
),
3140 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3142 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3144 /* BRW_NEW_VERTEX_PROGRAM */
3145 const struct brw_program
*vp
=
3146 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
3147 /* BRW_NEW_VS_PROG_DATA */
3148 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3150 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
3151 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
3154 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3156 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3158 .brw
= BRW_NEW_BATCH
|
3160 BRW_NEW_VERTEX_PROGRAM
|
3161 BRW_NEW_VS_PROG_DATA
,
3163 .emit
= genX(upload_vs_push_constants
),
3167 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3169 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3171 /* BRW_NEW_GEOMETRY_PROGRAM */
3172 const struct brw_program
*gp
=
3173 brw_program_const(brw
->programs
[MESA_SHADER_GEOMETRY
]);
3176 /* BRW_NEW_GS_PROG_DATA */
3177 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3179 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
3180 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
3184 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3186 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3188 .brw
= BRW_NEW_BATCH
|
3190 BRW_NEW_GEOMETRY_PROGRAM
|
3191 BRW_NEW_GS_PROG_DATA
,
3193 .emit
= genX(upload_gs_push_constants
),
3197 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3199 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3200 /* BRW_NEW_FRAGMENT_PROGRAM */
3201 const struct brw_program
*fp
=
3202 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
3203 /* BRW_NEW_FS_PROG_DATA */
3204 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3206 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
3208 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
3211 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3213 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3214 .brw
= BRW_NEW_BATCH
|
3216 BRW_NEW_FRAGMENT_PROGRAM
|
3217 BRW_NEW_FS_PROG_DATA
,
3219 .emit
= genX(upload_wm_push_constants
),
3223 /* ---------------------------------------------------------------------- */
3227 genX(determine_sample_mask
)(struct brw_context
*brw
)
3229 struct gl_context
*ctx
= &brw
->ctx
;
3230 float coverage
= 1.0f
;
3231 float coverage_invert
= false;
3232 unsigned sample_mask
= ~0u;
3234 /* BRW_NEW_NUM_SAMPLES */
3235 unsigned num_samples
= brw
->num_samples
;
3237 if (_mesa_is_multisample_enabled(ctx
)) {
3238 if (ctx
->Multisample
.SampleCoverage
) {
3239 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3240 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3242 if (ctx
->Multisample
.SampleMask
) {
3243 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3247 if (num_samples
> 1) {
3248 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3249 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3250 if (coverage_invert
)
3251 coverage_bits
^= (1 << num_samples
) - 1;
3252 return coverage_bits
& sample_mask
;
3259 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3260 unsigned num_samples
)
3262 unsigned log2_samples
= ffs(num_samples
) - 1;
3264 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3265 multi
.PixelLocation
= CENTER
;
3266 multi
.NumberofMultisamples
= log2_samples
;
3268 GEN_SAMPLE_POS_4X(multi
.Sample
);
3270 switch (num_samples
) {
3272 GEN_SAMPLE_POS_1X(multi
.Sample
);
3275 GEN_SAMPLE_POS_2X(multi
.Sample
);
3278 GEN_SAMPLE_POS_4X(multi
.Sample
);
3281 GEN_SAMPLE_POS_8X(multi
.Sample
);
3291 genX(upload_multisample_state
)(struct brw_context
*brw
)
3293 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3295 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3297 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3298 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3302 static const struct brw_tracked_state
genX(multisample_state
) = {
3304 .mesa
= _NEW_MULTISAMPLE
,
3305 .brw
= BRW_NEW_BLORP
|
3307 BRW_NEW_NUM_SAMPLES
,
3309 .emit
= genX(upload_multisample_state
)
3313 /* ---------------------------------------------------------------------- */
3316 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3318 struct gl_context
*ctx
= &brw
->ctx
;
3320 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3322 cc
.IndependentAlphaBlendEnable
=
3323 set_blend_entry_bits(brw
, &cc
, 0, false);
3324 set_depth_stencil_bits(brw
, &cc
);
3326 if (ctx
->Color
.AlphaEnabled
&&
3327 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3328 cc
.AlphaTestEnable
= true;
3329 cc
.AlphaTestFunction
=
3330 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3333 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3335 cc
.StatisticsEnable
= brw
->stats_wm
;
3337 cc
.CCViewportStatePointer
=
3338 ro_bo(brw
->batch
.state_bo
, brw
->cc
.vp_offset
);
3341 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3342 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3343 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3344 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3348 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3349 cc
.BackfaceStencilReferenceValue
=
3350 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3356 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3357 ctx
->Color
.AlphaRef
);
3361 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3362 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3364 ptr
.ColorCalcStatePointerValid
= true;
3368 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3372 static const struct brw_tracked_state
genX(color_calc_state
) = {
3374 .mesa
= _NEW_COLOR
|
3376 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3379 .brw
= BRW_NEW_BATCH
|
3381 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3383 : BRW_NEW_CC_STATE
|
3384 BRW_NEW_STATE_BASE_ADDRESS
),
3386 .emit
= genX(upload_color_calc_state
),
3390 /* ---------------------------------------------------------------------- */
3394 genX(upload_sbe
)(struct brw_context
*brw
)
3396 struct gl_context
*ctx
= &brw
->ctx
;
3397 /* BRW_NEW_FRAGMENT_PROGRAM */
3398 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3399 /* BRW_NEW_FS_PROG_DATA */
3400 const struct brw_wm_prog_data
*wm_prog_data
=
3401 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3403 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3405 #define attr_overrides sbe.Attribute
3407 uint32_t urb_entry_read_length
;
3408 uint32_t urb_entry_read_offset
;
3409 uint32_t point_sprite_enables
;
3411 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3412 sbe
.AttributeSwizzleEnable
= true;
3413 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3416 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3420 * Window coordinates in an FBO are inverted, which means point
3421 * sprite origin must be inverted.
3423 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3424 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3426 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3428 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3429 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3430 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3431 * BRW_NEW_VUE_MAP_GEOM_OUT
3433 genX(calculate_attr_overrides
)(brw
,
3435 &point_sprite_enables
,
3436 &urb_entry_read_length
,
3437 &urb_entry_read_offset
);
3439 /* Typically, the URB entry read length and offset should be programmed
3440 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3441 * stage which produces geometry. However, we don't know the proper
3442 * value until we call calculate_attr_overrides().
3444 * To fit with our existing code, we override the inherited values and
3445 * specify it here directly, as we did on previous generations.
3447 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3448 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3449 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3450 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3453 sbe
.ForceVertexURBEntryReadLength
= true;
3454 sbe
.ForceVertexURBEntryReadOffset
= true;
3458 /* prepare the active component dwords */
3459 int input_index
= 0;
3460 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
3461 if (!(fp
->info
.inputs_read
& BITFIELD64_BIT(attr
)))
3464 assert(input_index
< 32);
3466 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3473 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3474 for (int i
= 0; i
< 16; i
++)
3475 sbes
.Attribute
[i
] = attr_overrides
[i
];
3479 #undef attr_overrides
3482 static const struct brw_tracked_state
genX(sbe_state
) = {
3484 .mesa
= _NEW_BUFFERS
|
3489 .brw
= BRW_NEW_BLORP
|
3491 BRW_NEW_FRAGMENT_PROGRAM
|
3492 BRW_NEW_FS_PROG_DATA
|
3493 BRW_NEW_GS_PROG_DATA
|
3494 BRW_NEW_TES_PROG_DATA
|
3495 BRW_NEW_VUE_MAP_GEOM_OUT
|
3496 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3499 .emit
= genX(upload_sbe
),
3503 /* ---------------------------------------------------------------------- */
3507 * Outputs the 3DSTATE_SO_DECL_LIST command.
3509 * The data output is a series of 64-bit entries containing a SO_DECL per
3510 * stream. We only have one stream of rendering coming out of the GS unit, so
3511 * we only emit stream 0 (low 16 bits) SO_DECLs.
3514 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3515 const struct brw_vue_map
*vue_map
)
3517 struct gl_context
*ctx
= &brw
->ctx
;
3518 /* BRW_NEW_TRANSFORM_FEEDBACK */
3519 struct gl_transform_feedback_object
*xfb_obj
=
3520 ctx
->TransformFeedback
.CurrentObject
;
3521 const struct gl_transform_feedback_info
*linked_xfb_info
=
3522 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3523 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3524 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3525 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3526 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3528 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3530 memset(so_decl
, 0, sizeof(so_decl
));
3532 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3533 * command feels strange -- each dword pair contains a SO_DECL per stream.
3535 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3536 const struct gl_transform_feedback_output
*output
=
3537 &linked_xfb_info
->Outputs
[i
];
3538 const int buffer
= output
->OutputBuffer
;
3539 const int varying
= output
->OutputRegister
;
3540 const unsigned stream_id
= output
->StreamId
;
3541 assert(stream_id
< MAX_VERTEX_STREAMS
);
3543 buffer_mask
[stream_id
] |= 1 << buffer
;
3545 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3547 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3548 * array. Instead, it simply increments DstOffset for the following
3549 * input by the number of components that should be skipped.
3551 * Our hardware is unusual in that it requires us to program SO_DECLs
3552 * for fake "hole" components, rather than simply taking the offset
3553 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3554 * program as many size = 4 holes as we can, then a final hole to
3555 * accommodate the final 1, 2, or 3 remaining.
3557 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3559 while (skip_components
> 0) {
3560 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3562 .OutputBufferSlot
= output
->OutputBuffer
,
3563 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3565 skip_components
-= 4;
3568 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3570 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3571 .OutputBufferSlot
= output
->OutputBuffer
,
3572 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3574 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3577 if (decls
[stream_id
] > max_decls
)
3578 max_decls
= decls
[stream_id
];
3582 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3583 .StreamtoBufferSelects0
= buffer_mask
[0],
3584 .StreamtoBufferSelects1
= buffer_mask
[1],
3585 .StreamtoBufferSelects2
= buffer_mask
[2],
3586 .StreamtoBufferSelects3
= buffer_mask
[3],
3587 .NumEntries0
= decls
[0],
3588 .NumEntries1
= decls
[1],
3589 .NumEntries2
= decls
[2],
3590 .NumEntries3
= decls
[3]);
3592 for (int i
= 0; i
< max_decls
; i
++) {
3593 GENX(SO_DECL_ENTRY_pack
)(
3594 brw
, dw
+ 2 + i
* 2,
3595 &(struct GENX(SO_DECL_ENTRY
)) {
3596 .Stream0Decl
= so_decl
[0][i
],
3597 .Stream1Decl
= so_decl
[1][i
],
3598 .Stream2Decl
= so_decl
[2][i
],
3599 .Stream3Decl
= so_decl
[3][i
],
3605 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3607 struct gl_context
*ctx
= &brw
->ctx
;
3608 /* BRW_NEW_TRANSFORM_FEEDBACK */
3609 struct gl_transform_feedback_object
*xfb_obj
=
3610 ctx
->TransformFeedback
.CurrentObject
;
3612 const struct gl_transform_feedback_info
*linked_xfb_info
=
3613 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3615 struct brw_transform_feedback_object
*brw_obj
=
3616 (struct brw_transform_feedback_object
*) xfb_obj
;
3617 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3620 /* Set up the up to 4 output buffers. These are the ranges defined in the
3621 * gl_transform_feedback_object.
3623 for (int i
= 0; i
< 4; i
++) {
3624 struct intel_buffer_object
*bufferobj
=
3625 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3628 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3629 sob
.SOBufferIndex
= i
;
3634 uint32_t start
= xfb_obj
->Offset
[i
];
3635 assert(start
% 4 == 0);
3636 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3638 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3639 assert(end
<= bo
->size
);
3641 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3642 sob
.SOBufferIndex
= i
;
3644 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3646 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3647 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3649 sob
.SOBufferEnable
= true;
3650 sob
.StreamOffsetWriteEnable
= true;
3651 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3652 sob
.SOBufferMOCS
= mocs_wb
;
3654 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3655 sob
.StreamOutputBufferOffsetAddress
=
3656 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3658 if (brw_obj
->zero_offsets
) {
3659 /* Zero out the offset and write that to offset_bo */
3660 sob
.StreamOffset
= 0;
3662 /* Use offset_bo as the "Stream Offset." */
3663 sob
.StreamOffset
= 0xFFFFFFFF;
3670 brw_obj
->zero_offsets
= false;
3675 query_active(struct gl_query_object
*q
)
3677 return q
&& q
->Active
;
3681 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3682 const struct brw_vue_map
*vue_map
)
3684 struct gl_context
*ctx
= &brw
->ctx
;
3685 /* BRW_NEW_TRANSFORM_FEEDBACK */
3686 struct gl_transform_feedback_object
*xfb_obj
=
3687 ctx
->TransformFeedback
.CurrentObject
;
3689 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3691 int urb_entry_read_offset
= 0;
3692 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3693 urb_entry_read_offset
;
3695 sos
.SOFunctionEnable
= true;
3696 sos
.SOStatisticsEnable
= true;
3698 /* BRW_NEW_RASTERIZER_DISCARD */
3699 if (ctx
->RasterDiscard
) {
3700 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3701 sos
.RenderingDisable
= true;
3703 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3704 "query active relies on the clipper.\n");
3709 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3710 sos
.ReorderMode
= TRAILING
;
3713 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3714 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3715 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3716 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3718 const struct gl_transform_feedback_info
*linked_xfb_info
=
3719 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3720 /* Set buffer pitches; 0 means unbound. */
3721 if (xfb_obj
->Buffers
[0])
3722 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3723 if (xfb_obj
->Buffers
[1])
3724 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3725 if (xfb_obj
->Buffers
[2])
3726 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3727 if (xfb_obj
->Buffers
[3])
3728 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3731 /* We always read the whole vertex. This could be reduced at some
3732 * point by reading less and offsetting the register index in the
3735 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3736 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3737 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3738 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3739 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3740 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3741 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3742 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3748 genX(upload_sol
)(struct brw_context
*brw
)
3750 struct gl_context
*ctx
= &brw
->ctx
;
3751 /* BRW_NEW_TRANSFORM_FEEDBACK */
3752 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3755 genX(upload_3dstate_so_buffers
)(brw
);
3757 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3758 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3761 /* Finally, set up the SOL stage. This command must always follow updates to
3762 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3763 * MMIO register updates (current performed by the kernel at each batch
3766 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3769 static const struct brw_tracked_state
genX(sol_state
) = {
3772 .brw
= BRW_NEW_BATCH
|
3774 BRW_NEW_RASTERIZER_DISCARD
|
3775 BRW_NEW_VUE_MAP_GEOM_OUT
|
3776 BRW_NEW_TRANSFORM_FEEDBACK
,
3778 .emit
= genX(upload_sol
),
3782 /* ---------------------------------------------------------------------- */
3786 genX(upload_ps
)(struct brw_context
*brw
)
3788 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3789 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3791 /* BRW_NEW_FS_PROG_DATA */
3792 const struct brw_wm_prog_data
*prog_data
=
3793 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3794 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3799 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3800 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3801 * incorrect for subspans where some of the pixels are unlit. We believe
3802 * the bit just didn't take effect in previous generations.
3804 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3807 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3809 /* BRW_NEW_FS_PROG_DATA */
3810 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3812 if (prog_data
->base
.use_alt_mode
)
3813 ps
.FloatingPointMode
= Alternate
;
3815 /* Haswell requires the sample mask to be set in this packet as well as
3816 * in 3DSTATE_SAMPLE_MASK; the values should match.
3819 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3821 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3824 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3825 * it implicitly scales for different GT levels (which have some # of
3828 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3831 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3833 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3835 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3838 if (prog_data
->base
.nr_params
> 0 ||
3839 prog_data
->base
.ubo_ranges
[0].length
> 0)
3840 ps
.PushConstantEnable
= true;
3843 /* From the IVB PRM, volume 2 part 1, page 287:
3844 * "This bit is inserted in the PS payload header and made available to
3845 * the DataPort (either via the message header or via header bypass) to
3846 * indicate that oMask data (one or two phases) is included in Render
3847 * Target Write messages. If present, the oMask data is used to mask off
3850 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3852 /* The hardware wedges if you have this bit set but don't turn on any
3853 * dual source blend factors.
3855 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3857 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3858 (ctx
->Color
.BlendEnabled
& 1) &&
3859 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3861 /* BRW_NEW_FS_PROG_DATA */
3862 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3865 /* From the documentation for this packet:
3866 * "If the PS kernel does not need the Position XY Offsets to
3867 * compute a Position Value, then this field should be programmed
3868 * to POSOFFSET_NONE."
3870 * "SW Recommendation: If the PS kernel needs the Position Offsets
3871 * to compute a Position XY value, this field should match Position
3872 * ZW Interpolation Mode to ensure a consistent position.xyzw
3875 * We only require XY sample offsets. So, this recommendation doesn't
3876 * look useful at the moment. We might need this in future.
3878 if (prog_data
->uses_pos_offset
)
3879 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3881 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3883 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3884 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3885 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3886 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3887 prog_data
->base
.dispatch_grf_start_reg
;
3888 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3889 prog_data
->dispatch_grf_start_reg_2
;
3891 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3892 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3893 prog_data
->prog_offset_2
;
3895 if (prog_data
->base
.total_scratch
) {
3896 ps
.ScratchSpaceBasePointer
=
3897 rw_bo(stage_state
->scratch_bo
,
3898 ffs(stage_state
->per_thread_scratch
) - 11);
3903 static const struct brw_tracked_state
genX(ps_state
) = {
3905 .mesa
= _NEW_MULTISAMPLE
|
3906 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3909 .brw
= BRW_NEW_BATCH
|
3911 BRW_NEW_FS_PROG_DATA
,
3913 .emit
= genX(upload_ps
),
3917 /* ---------------------------------------------------------------------- */
3921 genX(upload_hs_state
)(struct brw_context
*brw
)
3923 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3924 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3925 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3926 const struct brw_vue_prog_data
*vue_prog_data
=
3927 brw_vue_prog_data(stage_prog_data
);
3929 /* BRW_NEW_TES_PROG_DATA */
3930 struct brw_tcs_prog_data
*tcs_prog_data
=
3931 brw_tcs_prog_data(stage_prog_data
);
3933 if (!tcs_prog_data
) {
3934 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3936 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3937 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3939 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3940 hs
.IncludeVertexHandles
= true;
3942 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3947 static const struct brw_tracked_state
genX(hs_state
) = {
3950 .brw
= BRW_NEW_BATCH
|
3952 BRW_NEW_TCS_PROG_DATA
|
3953 BRW_NEW_TESS_PROGRAMS
,
3955 .emit
= genX(upload_hs_state
),
3959 genX(upload_ds_state
)(struct brw_context
*brw
)
3961 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3962 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3963 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3965 /* BRW_NEW_TES_PROG_DATA */
3966 const struct brw_tes_prog_data
*tes_prog_data
=
3967 brw_tes_prog_data(stage_prog_data
);
3968 const struct brw_vue_prog_data
*vue_prog_data
=
3969 brw_vue_prog_data(stage_prog_data
);
3971 if (!tes_prog_data
) {
3972 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3974 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3975 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3977 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3978 ds
.ComputeWCoordinateEnable
=
3979 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3982 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3983 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3984 ds
.UserClipDistanceCullTestEnableBitmask
=
3985 vue_prog_data
->cull_distance_mask
;
3991 static const struct brw_tracked_state
genX(ds_state
) = {
3994 .brw
= BRW_NEW_BATCH
|
3996 BRW_NEW_TESS_PROGRAMS
|
3997 BRW_NEW_TES_PROG_DATA
,
3999 .emit
= genX(upload_ds_state
),
4002 /* ---------------------------------------------------------------------- */
4005 upload_te_state(struct brw_context
*brw
)
4007 /* BRW_NEW_TESS_PROGRAMS */
4008 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4010 /* BRW_NEW_TES_PROG_DATA */
4011 const struct brw_tes_prog_data
*tes_prog_data
=
4012 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4015 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4016 te
.Partitioning
= tes_prog_data
->partitioning
;
4017 te
.OutputTopology
= tes_prog_data
->output_topology
;
4018 te
.TEDomain
= tes_prog_data
->domain
;
4020 te
.MaximumTessellationFactorOdd
= 63.0;
4021 te
.MaximumTessellationFactorNotOdd
= 64.0;
4024 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4028 static const struct brw_tracked_state
genX(te_state
) = {
4031 .brw
= BRW_NEW_BLORP
|
4033 BRW_NEW_TES_PROG_DATA
|
4034 BRW_NEW_TESS_PROGRAMS
,
4036 .emit
= upload_te_state
,
4039 /* ---------------------------------------------------------------------- */
4042 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4044 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4045 /* BRW_NEW_TESS_PROGRAMS */
4046 const struct brw_program
*tep
=
4047 brw_program_const(brw
->programs
[MESA_SHADER_TESS_EVAL
]);
4050 /* BRW_NEW_TES_PROG_DATA */
4051 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4052 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
4053 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
4057 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4059 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4060 .brw
= BRW_NEW_BATCH
|
4062 BRW_NEW_TESS_PROGRAMS
|
4063 BRW_NEW_TES_PROG_DATA
,
4065 .emit
= genX(upload_tes_push_constants
),
4069 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4071 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4072 /* BRW_NEW_TESS_PROGRAMS */
4073 const struct brw_program
*tcp
=
4074 brw_program_const(brw
->programs
[MESA_SHADER_TESS_CTRL
]);
4075 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4078 /* BRW_NEW_TCS_PROG_DATA */
4079 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4081 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
4082 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
4086 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4088 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4089 .brw
= BRW_NEW_BATCH
|
4091 BRW_NEW_DEFAULT_TESS_LEVELS
|
4092 BRW_NEW_TESS_PROGRAMS
|
4093 BRW_NEW_TCS_PROG_DATA
,
4095 .emit
= genX(upload_tcs_push_constants
),
4100 /* ---------------------------------------------------------------------- */
4104 genX(upload_cs_state
)(struct brw_context
*brw
)
4106 if (!brw
->cs
.base
.prog_data
)
4110 uint32_t *desc
= (uint32_t*) brw_state_batch(
4111 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4114 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4115 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4116 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4117 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4119 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4120 brw_emit_buffer_surface_state(
4121 brw
, &stage_state
->surf_offset
[
4122 prog_data
->binding_table
.shader_time_start
],
4123 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4124 brw
->shader_time
.bo
->size
, 1,
4128 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4129 32, &stage_state
->bind_bo_offset
);
4131 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4132 if (prog_data
->total_scratch
) {
4136 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4137 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4139 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 11;
4140 } else if (GEN_IS_HASWELL
) {
4141 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4142 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4144 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 12;
4146 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4147 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4149 bo_offset
= stage_state
->per_thread_scratch
/ 1024 - 1;
4151 vfe
.ScratchSpaceBasePointer
=
4152 rw_bo(stage_state
->scratch_bo
, bo_offset
);
4155 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4156 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4157 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4158 vfe
.ResetGatewayTimer
=
4159 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4161 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4167 /* We are uploading duplicated copies of push constant uniforms for each
4168 * thread. Although the local id data needs to vary per thread, it won't
4169 * change for other uniform data. Unfortunately this duplication is
4170 * required for gen7. As of Haswell, this duplication can be avoided,
4171 * but this older mechanism with duplicated data continues to work.
4173 * FINISHME: As of Haswell, we could make use of the
4174 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4175 * field to only store one copy of uniform data.
4177 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4178 * which is described in the GPGPU_WALKER command and in the Broadwell
4179 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4180 * Operations => GPGPU Mode => Indirect Payload Storage.
4182 * Note: The constant data is built in brw_upload_cs_push_constants
4185 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4187 const uint32_t vfe_curbe_allocation
=
4188 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4189 cs_prog_data
->push
.cross_thread
.regs
, 2);
4190 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4193 if (cs_prog_data
->push
.total
.size
> 0) {
4194 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4195 curbe
.CURBETotalDataLength
=
4196 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4197 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4201 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4202 memcpy(bind
, stage_state
->surf_offset
,
4203 prog_data
->binding_table
.size_bytes
);
4204 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4205 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4206 .SamplerStatePointer
= stage_state
->sampler_offset
,
4207 .SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4) >> 2,
4208 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4209 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4210 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4211 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4212 prog_data
->total_shared
),
4213 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4214 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4215 .CrossThreadConstantDataReadLength
=
4216 cs_prog_data
->push
.cross_thread
.regs
,
4220 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4222 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4223 load
.InterfaceDescriptorTotalLength
=
4224 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4225 load
.InterfaceDescriptorDataStartAddress
= offset
;
4229 static const struct brw_tracked_state
genX(cs_state
) = {
4231 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4232 .brw
= BRW_NEW_BATCH
|
4234 BRW_NEW_CS_PROG_DATA
|
4235 BRW_NEW_SAMPLER_STATE_TABLE
|
4238 .emit
= genX(upload_cs_state
)
4243 /* ---------------------------------------------------------------------- */
4247 genX(upload_raster
)(struct brw_context
*brw
)
4249 struct gl_context
*ctx
= &brw
->ctx
;
4252 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4255 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4258 struct gl_point_attrib
*point
= &ctx
->Point
;
4260 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4261 if (brw
->polygon_front_bit
== render_to_fbo
)
4262 raster
.FrontWinding
= CounterClockwise
;
4264 if (polygon
->CullFlag
) {
4265 switch (polygon
->CullFaceMode
) {
4267 raster
.CullMode
= CULLMODE_FRONT
;
4270 raster
.CullMode
= CULLMODE_BACK
;
4272 case GL_FRONT_AND_BACK
:
4273 raster
.CullMode
= CULLMODE_BOTH
;
4276 unreachable("not reached");
4279 raster
.CullMode
= CULLMODE_NONE
;
4282 point
->SmoothFlag
= raster
.SmoothPointEnable
;
4284 raster
.DXMultisampleRasterizationEnable
=
4285 _mesa_is_multisample_enabled(ctx
);
4287 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4288 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4289 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4291 switch (polygon
->FrontMode
) {
4293 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4296 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4299 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4302 unreachable("not reached");
4305 switch (polygon
->BackMode
) {
4307 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4310 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4313 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4316 unreachable("not reached");
4320 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4323 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4325 /* _NEW_TRANSFORM */
4326 if (!ctx
->Transform
.DepthClamp
) {
4328 raster
.ViewportZFarClipTestEnable
= true;
4329 raster
.ViewportZNearClipTestEnable
= true;
4331 raster
.ViewportZClipTestEnable
= true;
4335 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4337 raster
.ConservativeRasterizationEnable
=
4338 ctx
->IntelConservativeRasterization
;
4341 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4342 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4344 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4348 static const struct brw_tracked_state
genX(raster_state
) = {
4350 .mesa
= _NEW_BUFFERS
|
4357 .brw
= BRW_NEW_BLORP
|
4359 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4361 .emit
= genX(upload_raster
),
4365 /* ---------------------------------------------------------------------- */
4369 genX(upload_ps_extra
)(struct brw_context
*brw
)
4371 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4373 const struct brw_wm_prog_data
*prog_data
=
4374 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4376 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4377 psx
.PixelShaderValid
= true;
4378 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4379 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4380 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4381 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4382 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4383 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4385 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4386 if (prog_data
->uses_sample_mask
) {
4388 if (prog_data
->post_depth_coverage
)
4389 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4390 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4391 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4393 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4395 psx
.PixelShaderUsesInputCoverageMask
= true;
4399 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4401 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4402 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4405 /* The stricter cross-primitive coherency guarantees that the hardware
4406 * gives us with the "Accesses UAV" bit set for at least one shader stage
4407 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4408 * are redundant within the current image, atomic counter and SSBO GL
4409 * APIs, which all have very loose ordering and coherency requirements
4410 * and generally rely on the application to insert explicit barriers when
4411 * a shader invocation is expected to see the memory writes performed by
4412 * the invocations of some previous primitive. Regardless of the value
4413 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4414 * cause an in most cases useless DC flush when the lowermost stage with
4415 * the bit set finishes execution.
4417 * It would be nice to disable it, but in some cases we can't because on
4418 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4419 * signal (which could be set independently from the coherency mechanism
4420 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4421 * determine whether the hardware skips execution of the fragment shader
4422 * or not via the ThreadDispatchEnable signal. However if we know that
4423 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4424 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4425 * difference so we may just disable it here.
4427 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4428 * take into account KillPixels when no depth or stencil writes are
4429 * enabled. In order for occlusion queries to work correctly with no
4430 * attachments, we need to force-enable here.
4432 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4435 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4436 !brw_color_buffer_write_enabled(brw
))
4437 psx
.PixelShaderHasUAV
= true;
4441 const struct brw_tracked_state
genX(ps_extra
) = {
4443 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4444 .brw
= BRW_NEW_BLORP
|
4446 BRW_NEW_FRAGMENT_PROGRAM
|
4447 BRW_NEW_FS_PROG_DATA
|
4448 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4450 .emit
= genX(upload_ps_extra
),
4454 /* ---------------------------------------------------------------------- */
4458 genX(upload_ps_blend
)(struct brw_context
*brw
)
4460 struct gl_context
*ctx
= &brw
->ctx
;
4463 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4464 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4467 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4469 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4470 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4471 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4473 bool alpha_to_one
= false;
4475 if (!buffer0_is_integer
) {
4476 /* _NEW_MULTISAMPLE */
4478 if (_mesa_is_multisample_enabled(ctx
)) {
4479 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4480 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4483 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4486 /* Used for implementing the following bit of GL_EXT_texture_integer:
4487 * "Per-fragment operations that require floating-point color
4488 * components, including multisample alpha operations, alpha test,
4489 * blending, and dithering, have no effect when the corresponding
4490 * colors are written to an integer color buffer."
4492 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4493 * "If drawbuffer zero is not NONE and the buffer it references has an
4494 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4495 * operations are skipped."
4497 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4498 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4499 GLenum eqA
= color
->Blend
[0].EquationA
;
4500 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4501 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4502 GLenum srcA
= color
->Blend
[0].SrcA
;
4503 GLenum dstA
= color
->Blend
[0].DstA
;
4505 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4506 srcRGB
= dstRGB
= GL_ONE
;
4508 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4509 srcA
= dstA
= GL_ONE
;
4511 /* Due to hardware limitations, the destination may have information
4512 * in an alpha channel even when the format specifies no alpha
4513 * channel. In order to avoid getting any incorrect blending due to
4514 * that alpha channel, coerce the blend factors to values that will
4515 * not read the alpha channel, but will instead use the correct
4516 * implicit value for alpha.
4518 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4519 GL_TEXTURE_ALPHA_TYPE
)) {
4520 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4521 srcA
= brw_fix_xRGB_alpha(srcA
);
4522 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4523 dstA
= brw_fix_xRGB_alpha(dstA
);
4526 /* Alpha to One doesn't work with Dual Color Blending. Override
4527 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4529 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4530 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4531 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4532 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4533 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4536 pb
.ColorBufferBlendEnable
= true;
4537 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4538 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4539 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4540 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4542 pb
.IndependentAlphaBlendEnable
=
4543 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4548 static const struct brw_tracked_state
genX(ps_blend
) = {
4550 .mesa
= _NEW_BUFFERS
|
4553 .brw
= BRW_NEW_BLORP
|
4555 BRW_NEW_FRAGMENT_PROGRAM
,
4557 .emit
= genX(upload_ps_blend
)
4561 /* ---------------------------------------------------------------------- */
4565 genX(emit_vf_topology
)(struct brw_context
*brw
)
4567 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4568 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4572 static const struct brw_tracked_state
genX(vf_topology
) = {
4575 .brw
= BRW_NEW_BLORP
|
4578 .emit
= genX(emit_vf_topology
),
4582 /* ---------------------------------------------------------------------- */
4586 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4588 uint32_t offset_in_bytes
,
4591 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4592 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4593 mi_rpc
.ReportID
= report_id
;
4598 /* ---------------------------------------------------------------------- */
4601 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4604 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4605 struct brw_stage_state
*stage_state
)
4608 static const uint16_t packet_headers
[] = {
4609 [MESA_SHADER_VERTEX
] = 43,
4610 [MESA_SHADER_TESS_CTRL
] = 44,
4611 [MESA_SHADER_TESS_EVAL
] = 45,
4612 [MESA_SHADER_GEOMETRY
] = 46,
4613 [MESA_SHADER_FRAGMENT
] = 47,
4616 /* Ivybridge requires a workaround flush before VS packets. */
4617 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4618 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4619 gen7_emit_vs_workaround_flush(brw
);
4622 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4623 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4624 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4630 has_component(mesa_format format
, int i
)
4632 if (_mesa_is_format_color_format(format
))
4633 return _mesa_format_has_color_component(format
, i
);
4635 /* depth and stencil have only one component */
4640 * Upload SAMPLER_BORDER_COLOR_STATE.
4643 genX(upload_default_color
)(struct brw_context
*brw
,
4644 const struct gl_sampler_object
*sampler
,
4645 mesa_format format
, GLenum base_format
,
4646 bool is_integer_format
, bool is_stencil_sampling
,
4647 uint32_t *sdc_offset
)
4649 union gl_color_union color
;
4651 switch (base_format
) {
4652 case GL_DEPTH_COMPONENT
:
4653 /* GL specs that border color for depth textures is taken from the
4654 * R channel, while the hardware uses A. Spam R into all the
4655 * channels for safety.
4657 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4658 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4659 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4660 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4666 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4669 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4670 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4671 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4672 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4675 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4676 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4677 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4678 color
.ui
[3] = float_as_int(1.0);
4680 case GL_LUMINANCE_ALPHA
:
4681 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4682 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4683 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4684 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4687 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4688 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4689 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4690 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4694 /* In some cases we use an RGBA surface format for GL RGB textures,
4695 * where we've initialized the A channel to 1.0. We also have to set
4696 * the border color alpha to 1.0 in that case.
4698 if (base_format
== GL_RGB
)
4699 color
.ui
[3] = float_as_int(1.0);
4704 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4708 uint32_t *sdc
= brw_state_batch(
4709 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4710 alignment
, sdc_offset
);
4712 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4714 #define ASSIGN(dst, src) \
4719 #define ASSIGNu16(dst, src) \
4721 dst = (uint16_t)src; \
4724 #define ASSIGNu8(dst, src) \
4726 dst = (uint8_t)src; \
4729 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4730 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4731 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4732 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4733 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4736 /* On Broadwell, the border color is represented as four 32-bit floats,
4737 * integers, or unsigned values, interpreted according to the surface
4738 * format. This matches the sampler->BorderColor union exactly; just
4739 * memcpy the values.
4741 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4742 #elif GEN_IS_HASWELL
4743 if (is_integer_format
|| is_stencil_sampling
) {
4744 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4745 const int bits_per_channel
=
4746 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4748 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4749 * "If any color channel is missing from the surface format,
4750 * corresponding border color should be programmed as zero and if
4751 * alpha channel is missing, corresponding Alpha border color should
4752 * be programmed as 1."
4754 unsigned c
[4] = { 0, 0, 0, 1 };
4755 for (int i
= 0; i
< 4; i
++) {
4756 if (has_component(format
, i
))
4760 switch (bits_per_channel
) {
4762 /* Copy RGBA in order. */
4763 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4766 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4768 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4771 if (base_format
== GL_RG
) {
4772 /* Careful inspection of the tables reveals that for RG32 formats,
4773 * the green channel needs to go where blue normally belongs.
4775 state
.BorderColor32bitRed
= c
[0];
4776 state
.BorderColor32bitBlue
= c
[1];
4777 state
.BorderColor32bitAlpha
= 1;
4779 /* Copy RGBA in order. */
4780 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4784 assert(!"Invalid number of bits per channel in integer format.");
4788 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4790 #elif GEN_GEN == 5 || GEN_GEN == 6
4791 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4792 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4793 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4795 #define MESA_FLOAT_TO_HALF(dst, src) \
4796 dst = _mesa_float_to_half(src);
4798 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4800 #undef MESA_FLOAT_TO_HALF
4802 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4803 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4804 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4805 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4807 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4809 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4811 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4815 #undef BORDER_COLOR_ATTR
4817 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4821 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4828 /* GL_CLAMP is the weird mode where coordinates are clamped to
4829 * [0.0, 1.0], so linear filtering of coordinates outside of
4830 * [0.0, 1.0] give you half edge texel value and half border
4833 * Gen8+ supports this natively.
4835 return TCM_HALF_BORDER
;
4837 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4838 * and set clamp_border here, which gets the result desired.
4839 * We just use clamp(_to_edge) for nearest, because for nearest
4840 * clamping to 1.0 gives border color instead of the desired
4846 return TCM_CLAMP_BORDER
;
4848 case GL_CLAMP_TO_EDGE
:
4850 case GL_CLAMP_TO_BORDER
:
4851 return TCM_CLAMP_BORDER
;
4852 case GL_MIRRORED_REPEAT
:
4854 case GL_MIRROR_CLAMP_TO_EDGE
:
4855 return TCM_MIRROR_ONCE
;
4862 * Return true if the given wrap mode requires the border color to exist.
4865 wrap_mode_needs_border_color(unsigned wrap_mode
)
4868 return wrap_mode
== TCM_CLAMP_BORDER
||
4869 wrap_mode
== TCM_HALF_BORDER
;
4871 return wrap_mode
== TCM_CLAMP_BORDER
;
4876 * Sets the sampler state for a single unit based off of the sampler key
4880 genX(update_sampler_state
)(struct brw_context
*brw
,
4881 GLenum target
, bool tex_cube_map_seamless
,
4882 GLfloat tex_unit_lod_bias
,
4883 mesa_format format
, GLenum base_format
,
4884 const struct gl_texture_object
*texObj
,
4885 const struct gl_sampler_object
*sampler
,
4886 uint32_t *sampler_state
,
4887 uint32_t batch_offset_for_sampler_state
)
4889 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
4891 /* Select min and mip filters. */
4892 switch (sampler
->MinFilter
) {
4894 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4895 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4898 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4899 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4901 case GL_NEAREST_MIPMAP_NEAREST
:
4902 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4903 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4905 case GL_LINEAR_MIPMAP_NEAREST
:
4906 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4907 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4909 case GL_NEAREST_MIPMAP_LINEAR
:
4910 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4911 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4913 case GL_LINEAR_MIPMAP_LINEAR
:
4914 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4915 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4918 unreachable("not reached");
4921 /* Select mag filter. */
4922 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
4923 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
4925 /* Enable anisotropic filtering if desired. */
4926 samp_st
.MaximumAnisotropy
= RATIO21
;
4928 if (sampler
->MaxAnisotropy
> 1.0f
) {
4929 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
4930 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
4931 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
4932 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
4934 if (sampler
->MaxAnisotropy
> 2.0f
) {
4935 samp_st
.MaximumAnisotropy
=
4936 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
4940 /* Set address rounding bits if not using nearest filtering. */
4941 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
4942 samp_st
.UAddressMinFilterRoundingEnable
= true;
4943 samp_st
.VAddressMinFilterRoundingEnable
= true;
4944 samp_st
.RAddressMinFilterRoundingEnable
= true;
4947 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
4948 samp_st
.UAddressMagFilterRoundingEnable
= true;
4949 samp_st
.VAddressMagFilterRoundingEnable
= true;
4950 samp_st
.RAddressMagFilterRoundingEnable
= true;
4953 bool either_nearest
=
4954 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
4955 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
4956 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
4957 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
4959 if (target
== GL_TEXTURE_CUBE_MAP
||
4960 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
4961 /* Cube maps must use the same wrap mode for all three coordinate
4962 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
4964 * Ivybridge and Baytrail seem to have problems with CUBE mode and
4965 * integer formats. Fall back to CLAMP for now.
4967 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
4968 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
4977 } else if (target
== GL_TEXTURE_1D
) {
4978 /* There's a bug in 1D texture sampling - it actually pays
4979 * attention to the wrap_t value, though it should not.
4980 * Override the wrap_t value here to GL_REPEAT to keep
4981 * any nonexistent border pixels from floating in.
4986 samp_st
.TCXAddressControlMode
= wrap_s
;
4987 samp_st
.TCYAddressControlMode
= wrap_t
;
4988 samp_st
.TCZAddressControlMode
= wrap_r
;
4990 samp_st
.ShadowFunction
=
4991 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
4992 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
4995 /* Set shadow function. */
4996 samp_st
.AnisotropicAlgorithm
=
4997 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
4998 EWAApproximation
: LEGACY
;
5002 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5005 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5006 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5007 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5008 samp_st
.TextureLODBias
=
5009 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5012 samp_st
.BaseMipLevel
=
5013 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5014 samp_st
.MinandMagStateNotEqual
=
5015 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5018 /* Upload the border color if necessary. If not, just point it at
5019 * offset 0 (the start of the batch) - the color should be ignored,
5020 * but that address won't fault in case something reads it anyway.
5022 uint32_t border_color_offset
= 0;
5023 if (wrap_mode_needs_border_color(wrap_s
) ||
5024 wrap_mode_needs_border_color(wrap_t
) ||
5025 wrap_mode_needs_border_color(wrap_r
)) {
5026 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5027 texObj
->_IsIntegerFormat
,
5028 texObj
->StencilSampling
,
5029 &border_color_offset
);
5032 samp_st
.BorderColorPointer
=
5033 ro_bo(brw
->batch
.state_bo
, border_color_offset
);
5035 samp_st
.BorderColorPointer
= border_color_offset
;
5039 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5041 samp_st
.LODPreClampEnable
= true;
5044 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5048 update_sampler_state(struct brw_context
*brw
,
5050 uint32_t *sampler_state
,
5051 uint32_t batch_offset_for_sampler_state
)
5053 struct gl_context
*ctx
= &brw
->ctx
;
5054 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5055 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5056 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5058 /* These don't use samplers at all. */
5059 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5062 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5063 genX(update_sampler_state
)(brw
, texObj
->Target
,
5064 ctx
->Texture
.CubeMapSeamless
,
5066 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5068 sampler_state
, batch_offset_for_sampler_state
);
5072 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5073 struct gl_program
*prog
,
5074 struct brw_stage_state
*stage_state
)
5076 struct gl_context
*ctx
= &brw
->ctx
;
5077 uint32_t sampler_count
= stage_state
->sampler_count
;
5079 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5081 if (sampler_count
== 0)
5084 /* SAMPLER_STATE is 4 DWords on all platforms. */
5085 const int dwords
= GENX(SAMPLER_STATE_length
);
5086 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5088 uint32_t *sampler_state
= brw_state_batch(brw
,
5089 sampler_count
* size_in_bytes
,
5090 32, &stage_state
->sampler_offset
);
5091 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5093 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
5095 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5096 if (SamplersUsed
& (1 << s
)) {
5097 const unsigned unit
= prog
->SamplerUnits
[s
];
5098 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5099 update_sampler_state(brw
, unit
, sampler_state
,
5100 batch_offset_for_sampler_state
);
5104 sampler_state
+= dwords
;
5105 batch_offset_for_sampler_state
+= size_in_bytes
;
5108 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5109 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5110 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5112 /* Flag that the sampler state table pointer has changed; later atoms
5115 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5120 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5122 /* BRW_NEW_FRAGMENT_PROGRAM */
5123 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5124 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5127 static const struct brw_tracked_state
genX(fs_samplers
) = {
5129 .mesa
= _NEW_TEXTURE
,
5130 .brw
= BRW_NEW_BATCH
|
5132 BRW_NEW_FRAGMENT_PROGRAM
,
5134 .emit
= genX(upload_fs_samplers
),
5138 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5140 /* BRW_NEW_VERTEX_PROGRAM */
5141 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5142 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5145 static const struct brw_tracked_state
genX(vs_samplers
) = {
5147 .mesa
= _NEW_TEXTURE
,
5148 .brw
= BRW_NEW_BATCH
|
5150 BRW_NEW_VERTEX_PROGRAM
,
5152 .emit
= genX(upload_vs_samplers
),
5157 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5159 /* BRW_NEW_GEOMETRY_PROGRAM */
5160 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5164 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5168 static const struct brw_tracked_state
genX(gs_samplers
) = {
5170 .mesa
= _NEW_TEXTURE
,
5171 .brw
= BRW_NEW_BATCH
|
5173 BRW_NEW_GEOMETRY_PROGRAM
,
5175 .emit
= genX(upload_gs_samplers
),
5181 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5183 /* BRW_NEW_TESS_PROGRAMS */
5184 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5188 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5191 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5193 .mesa
= _NEW_TEXTURE
,
5194 .brw
= BRW_NEW_BATCH
|
5196 BRW_NEW_TESS_PROGRAMS
,
5198 .emit
= genX(upload_tcs_samplers
),
5204 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5206 /* BRW_NEW_TESS_PROGRAMS */
5207 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5211 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5214 static const struct brw_tracked_state
genX(tes_samplers
) = {
5216 .mesa
= _NEW_TEXTURE
,
5217 .brw
= BRW_NEW_BATCH
|
5219 BRW_NEW_TESS_PROGRAMS
,
5221 .emit
= genX(upload_tes_samplers
),
5227 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5229 /* BRW_NEW_COMPUTE_PROGRAM */
5230 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5234 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5237 const struct brw_tracked_state
genX(cs_samplers
) = {
5239 .mesa
= _NEW_TEXTURE
,
5240 .brw
= BRW_NEW_BATCH
|
5242 BRW_NEW_COMPUTE_PROGRAM
,
5244 .emit
= genX(upload_cs_samplers
),
5248 /* ---------------------------------------------------------------------- */
5252 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5254 struct gl_context
*ctx
= &brw
->ctx
;
5256 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5257 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5258 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5259 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5260 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5264 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5267 .brw
= BRW_NEW_CONTEXT
|
5270 .emit
= genX(upload_blend_constant_color
)
5274 /* ---------------------------------------------------------------------- */
5277 genX(init_atoms
)(struct brw_context
*brw
)
5280 static const struct brw_tracked_state
*render_atoms
[] =
5282 /* Once all the programs are done, we know how large urb entry
5283 * sizes need to be and can decide if we need to change the urb
5287 &brw_recalculate_urb_fence
,
5290 &genX(color_calc_state
),
5292 /* Surface state setup. Must come before the VS/WM unit. The binding
5293 * table upload must be last.
5295 &brw_vs_pull_constants
,
5296 &brw_wm_pull_constants
,
5297 &brw_renderbuffer_surfaces
,
5298 &brw_renderbuffer_read_surfaces
,
5299 &brw_texture_surfaces
,
5300 &brw_vs_binding_table
,
5301 &brw_wm_binding_table
,
5306 /* These set up state for brw_psp_urb_cbs */
5308 &genX(sf_clip_viewport
),
5310 &genX(vs_state
), /* always required, enabled or not */
5316 &brw_invariant_state
,
5318 &brw_binding_table_pointers
,
5319 &genX(blend_constant_color
),
5323 &genX(polygon_stipple
),
5324 &genX(polygon_stipple_offset
),
5326 &genX(line_stipple
),
5330 &genX(drawing_rect
),
5331 &brw_indices
, /* must come before brw_vertices */
5332 &genX(index_buffer
),
5335 &brw_constant_buffer
5338 static const struct brw_tracked_state
*render_atoms
[] =
5340 &genX(sf_clip_viewport
),
5342 /* Command packets: */
5347 &genX(blend_state
), /* must do before cc unit */
5348 &genX(color_calc_state
), /* must do before cc unit */
5349 &genX(depth_stencil_state
), /* must do before cc unit */
5351 &genX(vs_push_constants
), /* Before vs_state */
5352 &genX(gs_push_constants
), /* Before gs_state */
5353 &genX(wm_push_constants
), /* Before wm_state */
5355 /* Surface state setup. Must come before the VS/WM unit. The binding
5356 * table upload must be last.
5358 &brw_vs_pull_constants
,
5359 &brw_vs_ubo_surfaces
,
5360 &brw_gs_pull_constants
,
5361 &brw_gs_ubo_surfaces
,
5362 &brw_wm_pull_constants
,
5363 &brw_wm_ubo_surfaces
,
5364 &gen6_renderbuffer_surfaces
,
5365 &brw_renderbuffer_read_surfaces
,
5366 &brw_texture_surfaces
,
5368 &brw_vs_binding_table
,
5369 &gen6_gs_binding_table
,
5370 &brw_wm_binding_table
,
5375 &gen6_sampler_state
,
5376 &genX(multisample_state
),
5384 &genX(scissor_state
),
5386 &gen6_binding_table_pointers
,
5390 &genX(polygon_stipple
),
5391 &genX(polygon_stipple_offset
),
5393 &genX(line_stipple
),
5395 &genX(drawing_rect
),
5397 &brw_indices
, /* must come before brw_vertices */
5398 &genX(index_buffer
),
5402 static const struct brw_tracked_state
*render_atoms
[] =
5404 /* Command packets: */
5407 &genX(sf_clip_viewport
),
5410 &gen7_push_constant_space
,
5412 &genX(blend_state
), /* must do before cc unit */
5413 &genX(color_calc_state
), /* must do before cc unit */
5414 &genX(depth_stencil_state
), /* must do before cc unit */
5416 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5417 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5418 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5419 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5420 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5422 &genX(vs_push_constants
), /* Before vs_state */
5423 &genX(tcs_push_constants
),
5424 &genX(tes_push_constants
),
5425 &genX(gs_push_constants
), /* Before gs_state */
5426 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5428 /* Surface state setup. Must come before the VS/WM unit. The binding
5429 * table upload must be last.
5431 &brw_vs_pull_constants
,
5432 &brw_vs_ubo_surfaces
,
5433 &brw_vs_abo_surfaces
,
5434 &brw_tcs_pull_constants
,
5435 &brw_tcs_ubo_surfaces
,
5436 &brw_tcs_abo_surfaces
,
5437 &brw_tes_pull_constants
,
5438 &brw_tes_ubo_surfaces
,
5439 &brw_tes_abo_surfaces
,
5440 &brw_gs_pull_constants
,
5441 &brw_gs_ubo_surfaces
,
5442 &brw_gs_abo_surfaces
,
5443 &brw_wm_pull_constants
,
5444 &brw_wm_ubo_surfaces
,
5445 &brw_wm_abo_surfaces
,
5446 &gen6_renderbuffer_surfaces
,
5447 &brw_renderbuffer_read_surfaces
,
5448 &brw_texture_surfaces
,
5450 &genX(push_constant_packets
),
5452 &brw_vs_binding_table
,
5453 &brw_tcs_binding_table
,
5454 &brw_tes_binding_table
,
5455 &brw_gs_binding_table
,
5456 &brw_wm_binding_table
,
5460 &genX(tcs_samplers
),
5461 &genX(tes_samplers
),
5463 &genX(multisample_state
),
5477 &genX(scissor_state
),
5481 &genX(polygon_stipple
),
5482 &genX(polygon_stipple_offset
),
5484 &genX(line_stipple
),
5486 &genX(drawing_rect
),
5488 &brw_indices
, /* must come before brw_vertices */
5489 &genX(index_buffer
),
5497 static const struct brw_tracked_state
*render_atoms
[] =
5500 &genX(sf_clip_viewport
),
5503 &gen7_push_constant_space
,
5506 &genX(color_calc_state
),
5508 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5509 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5510 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5511 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5512 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5514 &genX(vs_push_constants
), /* Before vs_state */
5515 &genX(tcs_push_constants
),
5516 &genX(tes_push_constants
),
5517 &genX(gs_push_constants
), /* Before gs_state */
5518 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5520 /* Surface state setup. Must come before the VS/WM unit. The binding
5521 * table upload must be last.
5523 &brw_vs_pull_constants
,
5524 &brw_vs_ubo_surfaces
,
5525 &brw_vs_abo_surfaces
,
5526 &brw_tcs_pull_constants
,
5527 &brw_tcs_ubo_surfaces
,
5528 &brw_tcs_abo_surfaces
,
5529 &brw_tes_pull_constants
,
5530 &brw_tes_ubo_surfaces
,
5531 &brw_tes_abo_surfaces
,
5532 &brw_gs_pull_constants
,
5533 &brw_gs_ubo_surfaces
,
5534 &brw_gs_abo_surfaces
,
5535 &brw_wm_pull_constants
,
5536 &brw_wm_ubo_surfaces
,
5537 &brw_wm_abo_surfaces
,
5538 &gen6_renderbuffer_surfaces
,
5539 &brw_renderbuffer_read_surfaces
,
5540 &brw_texture_surfaces
,
5542 &genX(push_constant_packets
),
5544 &brw_vs_binding_table
,
5545 &brw_tcs_binding_table
,
5546 &brw_tes_binding_table
,
5547 &brw_gs_binding_table
,
5548 &brw_wm_binding_table
,
5552 &genX(tcs_samplers
),
5553 &genX(tes_samplers
),
5555 &genX(multisample_state
),
5564 &genX(raster_state
),
5570 &genX(depth_stencil_state
),
5573 &genX(scissor_state
),
5577 &genX(polygon_stipple
),
5578 &genX(polygon_stipple_offset
),
5580 &genX(line_stipple
),
5582 &genX(drawing_rect
),
5587 &genX(index_buffer
),
5595 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5596 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5597 render_atoms
, ARRAY_SIZE(render_atoms
));
5600 static const struct brw_tracked_state
*compute_atoms
[] =
5603 &brw_cs_image_surfaces
,
5604 &gen7_cs_push_constants
,
5605 &brw_cs_pull_constants
,
5606 &brw_cs_ubo_surfaces
,
5607 &brw_cs_abo_surfaces
,
5608 &brw_cs_texture_surfaces
,
5609 &brw_cs_work_groups_surface
,
5614 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5615 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5616 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5618 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);