2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "dev/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 UNUSED
static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 static struct brw_address
124 rw_32_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_32BIT
,
133 static struct brw_address
134 ro_32_bo(struct brw_bo
*bo
, uint32_t offset
)
136 return (struct brw_address
) {
139 .reloc_flags
= RELOC_32BIT
,
143 UNUSED
static struct brw_address
144 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
146 return (struct brw_address
) {
149 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
154 static struct brw_address
155 KSP(struct brw_context
*brw
, uint32_t offset
)
157 return ro_bo(brw
->cache
.bo
, offset
);
161 KSP(UNUSED
struct brw_context
*brw
, uint32_t offset
)
167 #include "genxml/genX_pack.h"
169 #define _brw_cmd_length(cmd) cmd ## _length
170 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
171 #define _brw_cmd_header(cmd) cmd ## _header
172 #define _brw_cmd_pack(cmd) cmd ## _pack
174 #define brw_batch_emit(brw, cmd, name) \
175 for (struct cmd name = { _brw_cmd_header(cmd) }, \
176 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
177 __builtin_expect(_dst != NULL, 1); \
178 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
182 uint32_t *_dw = emit_dwords(brw, n); \
183 struct cmd template = { \
184 _brw_cmd_header(cmd), \
185 .DWordLength = n - _brw_cmd_length_bias(cmd), \
188 _brw_cmd_pack(cmd)(brw, _dw, &template); \
189 _dw + 1; /* Array starts at dw[1] */ \
192 #define brw_state_emit(brw, cmd, align, offset, name) \
193 for (struct cmd name = {}, \
194 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
196 __builtin_expect(_dst != NULL, 1); \
197 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
201 * Polygon stipple packet
204 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
206 struct gl_context
*ctx
= &brw
->ctx
;
209 if (!ctx
->Polygon
.StippleFlag
)
212 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
213 /* Polygon stipple is provided in OpenGL order, i.e. bottom
214 * row first. If we're rendering to a window (i.e. the
215 * default frame buffer object, 0), then we need to invert
216 * it to match our pixel layout. But if we're rendering
217 * to a FBO (i.e. any named frame buffer object), we *don't*
218 * need to invert - we already match the layout.
220 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
221 for (unsigned i
= 0; i
< 32; i
++)
222 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
224 for (unsigned i
= 0; i
< 32; i
++)
225 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
230 static const struct brw_tracked_state
genX(polygon_stipple
) = {
232 .mesa
= _NEW_POLYGON
|
234 .brw
= BRW_NEW_CONTEXT
,
236 .emit
= genX(upload_polygon_stipple
),
240 * Polygon stipple offset packet
243 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
245 struct gl_context
*ctx
= &brw
->ctx
;
248 if (!ctx
->Polygon
.StippleFlag
)
251 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
254 * If we're drawing to a system window we have to invert the Y axis
255 * in order to match the OpenGL pixel coordinate system, and our
256 * offset must be matched to the window position. If we're drawing
257 * to a user-created FBO then our native pixel coordinate system
258 * works just fine, and there's no window system to worry about.
260 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
261 poly
.PolygonStippleYOffset
=
262 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
267 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
269 .mesa
= _NEW_BUFFERS
|
271 .brw
= BRW_NEW_CONTEXT
,
273 .emit
= genX(upload_polygon_stipple_offset
),
277 * Line stipple packet
280 genX(upload_line_stipple
)(struct brw_context
*brw
)
282 struct gl_context
*ctx
= &brw
->ctx
;
284 if (!ctx
->Line
.StippleFlag
)
287 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
288 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
290 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
291 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
295 static const struct brw_tracked_state
genX(line_stipple
) = {
298 .brw
= BRW_NEW_CONTEXT
,
300 .emit
= genX(upload_line_stipple
),
303 /* Constant single cliprect for framebuffer object or DRI2 drawing */
305 genX(upload_drawing_rect
)(struct brw_context
*brw
)
307 struct gl_context
*ctx
= &brw
->ctx
;
308 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
309 const unsigned int fb_width
= _mesa_geometric_width(fb
);
310 const unsigned int fb_height
= _mesa_geometric_height(fb
);
312 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
313 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
314 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
318 static const struct brw_tracked_state
genX(drawing_rect
) = {
320 .mesa
= _NEW_BUFFERS
,
321 .brw
= BRW_NEW_BLORP
|
324 .emit
= genX(upload_drawing_rect
),
328 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
332 unsigned start_offset
,
333 MAYBE_UNUSED
unsigned end_offset
,
335 MAYBE_UNUSED
unsigned step_rate
)
337 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
338 .VertexBufferIndex
= buffer_nr
,
339 .BufferPitch
= stride
,
341 /* The VF cache designers apparently cut corners, and made the cache
342 * only consider the bottom 32 bits of memory addresses. If you happen
343 * to have two vertex buffers which get placed exactly 4 GiB apart and
344 * use them in back-to-back draw calls, you can get collisions. To work
345 * around this problem, we restrict vertex buffers to the low 32 bits of
348 .BufferStartingAddress
= ro_32_bo(bo
, start_offset
),
350 .BufferSize
= end_offset
- start_offset
,
354 .AddressModifyEnable
= true,
358 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
359 .InstanceDataStepRate
= step_rate
,
361 .EndAddress
= ro_bo(bo
, end_offset
- 1),
366 .VertexBufferMOCS
= ICL_MOCS_WB
,
368 .VertexBufferMOCS
= CNL_MOCS_WB
,
370 .VertexBufferMOCS
= SKL_MOCS_WB
,
372 .VertexBufferMOCS
= BDW_MOCS_WB
,
374 .VertexBufferMOCS
= GEN7_MOCS_L3
,
378 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
379 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
383 is_passthru_format(uint32_t format
)
386 case ISL_FORMAT_R64_PASSTHRU
:
387 case ISL_FORMAT_R64G64_PASSTHRU
:
388 case ISL_FORMAT_R64G64B64_PASSTHRU
:
389 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
397 uploads_needed(uint32_t format
,
400 if (!is_passthru_format(format
))
407 case ISL_FORMAT_R64_PASSTHRU
:
408 case ISL_FORMAT_R64G64_PASSTHRU
:
410 case ISL_FORMAT_R64G64B64_PASSTHRU
:
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
414 unreachable("not reached");
419 * Returns the format that we are finally going to use when upload a vertex
420 * element. It will only change if we are using *64*PASSTHRU formats, as for
421 * gen < 8 they need to be splitted on two *32*FLOAT formats.
423 * @upload points in which upload we are. Valid values are [0,1]
426 downsize_format_if_needed(uint32_t format
,
429 assert(upload
== 0 || upload
== 1);
431 if (!is_passthru_format(format
))
434 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
435 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
436 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
437 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
438 * flagging that we want to fill with zeroes this second forced upload.
441 case ISL_FORMAT_R64_PASSTHRU
:
442 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
443 : ISL_FORMAT_R32_FLOAT
;
444 case ISL_FORMAT_R64G64_PASSTHRU
:
445 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
446 : ISL_FORMAT_R32_FLOAT
;
447 case ISL_FORMAT_R64G64B64_PASSTHRU
:
448 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
449 : ISL_FORMAT_R32G32_FLOAT
;
450 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
451 return ISL_FORMAT_R32G32B32A32_FLOAT
;
453 unreachable("not reached");
458 * Returns the number of componentes associated with a format that is used on
459 * a 64 to 32 format split. See downsize_format()
462 upload_format_size(uint32_t upload_format
)
464 switch (upload_format
) {
465 case ISL_FORMAT_R32_FLOAT
:
467 /* downsized_format has returned this one in order to flag that we are
468 * performing a second upload which we want to have filled with
469 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
470 * vertex shader input variables.
474 case ISL_FORMAT_R32G32_FLOAT
:
476 case ISL_FORMAT_R32G32B32A32_FLOAT
:
479 unreachable("not reached");
484 genX(emit_vertices
)(struct brw_context
*brw
)
486 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
489 brw_prepare_vertices(brw
);
490 brw_prepare_shader_draw_parameters(brw
);
493 brw_emit_query_begin(brw
);
496 const struct brw_vs_prog_data
*vs_prog_data
=
497 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
500 struct gl_context
*ctx
= &brw
->ctx
;
501 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
502 ctx
->Polygon
.BackMode
!= GL_FILL
);
504 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
505 unsigned vue
= brw
->vb
.nr_enabled
;
507 /* The element for the edge flags must always be last, so we have to
508 * insert the SGVS before it in that case.
510 if (uses_edge_flag
) {
516 "Trying to insert VID/IID past 33rd vertex element, "
517 "need to reorder the vertex attrbutes.");
519 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
520 if (vs_prog_data
->uses_vertexid
) {
521 vfs
.VertexIDEnable
= true;
522 vfs
.VertexIDComponentNumber
= 2;
523 vfs
.VertexIDElementOffset
= vue
;
526 if (vs_prog_data
->uses_instanceid
) {
527 vfs
.InstanceIDEnable
= true;
528 vfs
.InstanceIDComponentNumber
= 3;
529 vfs
.InstanceIDElementOffset
= vue
;
533 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
534 vfi
.InstancingEnable
= true;
535 vfi
.VertexElementIndex
= vue
;
538 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
542 const bool uses_draw_params
=
543 vs_prog_data
->uses_firstvertex
||
544 vs_prog_data
->uses_baseinstance
;
546 const bool uses_derived_draw_params
=
547 vs_prog_data
->uses_drawid
||
548 vs_prog_data
->uses_is_indexed_draw
;
550 const bool needs_sgvs_element
= (uses_draw_params
||
551 vs_prog_data
->uses_instanceid
||
552 vs_prog_data
->uses_vertexid
);
554 unsigned nr_elements
=
555 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ uses_derived_draw_params
;
558 /* If any of the formats of vb.enabled needs more that one upload, we need
559 * to add it to nr_elements
561 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
562 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
563 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
564 uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
566 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
571 /* If the VS doesn't read any inputs (calculating vertex position from
572 * a state variable for some reason, for example), emit a single pad
573 * VERTEX_ELEMENT struct and bail.
575 * The stale VB state stays in place, but they don't do anything unless
576 * a VE loads from them.
578 if (nr_elements
== 0) {
579 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
580 1 + GENX(VERTEX_ELEMENT_STATE_length
));
581 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
583 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
584 .Component0Control
= VFCOMP_STORE_0
,
585 .Component1Control
= VFCOMP_STORE_0
,
586 .Component2Control
= VFCOMP_STORE_0
,
587 .Component3Control
= VFCOMP_STORE_1_FP
,
589 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
593 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
594 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
595 uses_draw_params
+ uses_derived_draw_params
;
598 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
600 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
601 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
603 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
604 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
605 /* Prior to Haswell and Bay Trail we have to use 4-component formats
606 * to fake 3-component ones. In particular, we do this for
607 * half-float and 8 and 16-bit integer formats. This means that the
608 * vertex element may poke over the end of the buffer by 2 bytes.
610 const unsigned padding
=
611 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
612 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
613 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
620 if (uses_draw_params
) {
621 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
622 brw
->draw
.draw_params_bo
,
623 brw
->draw
.draw_params_offset
,
624 brw
->draw
.draw_params_bo
->size
,
629 if (uses_derived_draw_params
) {
630 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
631 brw
->draw
.derived_draw_params_bo
,
632 brw
->draw
.derived_draw_params_offset
,
633 brw
->draw
.derived_draw_params_bo
->size
,
639 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
640 * presumably for VertexID/InstanceID.
643 assert(nr_elements
<= 34);
644 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
646 assert(nr_elements
<= 18);
649 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
650 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
652 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
653 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
654 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
655 uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
656 uint32_t comp0
= VFCOMP_STORE_SRC
;
657 uint32_t comp1
= VFCOMP_STORE_SRC
;
658 uint32_t comp2
= VFCOMP_STORE_SRC
;
659 uint32_t comp3
= VFCOMP_STORE_SRC
;
660 const unsigned num_uploads
= GEN_GEN
< 8 ?
661 uploads_needed(format
, input
->is_dual_slot
) : 1;
664 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
665 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
666 * element which has edge flag enabled."
668 assert(!(is_passthru_format(format
) && uses_edge_flag
));
671 /* The gen4 driver expects edgeflag to come in as a float, and passes
672 * that float on to the tests in the clipper. Mesa's current vertex
673 * attribute value for EdgeFlag is stored as a float, which works out.
674 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
675 * integer ubyte. Just rewrite that to convert to a float.
677 * Gen6+ passes edgeflag as sideband along with the vertex, instead
678 * of in the VUE. We have to upload it sideband as the last vertex
679 * element according to the B-Spec.
682 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
683 gen6_edgeflag_input
= input
;
688 for (unsigned c
= 0; c
< num_uploads
; c
++) {
689 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
690 downsize_format_if_needed(format
, c
);
691 /* If we need more that one upload, the offset stride would be 128
692 * bits (16 bytes), as for previous uploads we are using the full
694 const unsigned offset
= input
->offset
+ c
* 16;
696 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
697 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
698 upload_format_size(upload_format
) : glattrib
->Size
;
701 case 0: comp0
= VFCOMP_STORE_0
;
702 case 1: comp1
= VFCOMP_STORE_0
;
703 case 2: comp2
= VFCOMP_STORE_0
;
705 if (GEN_GEN
>= 8 && glattrib
->Doubles
) {
706 comp3
= VFCOMP_STORE_0
;
707 } else if (glattrib
->Integer
) {
708 comp3
= VFCOMP_STORE_1_INT
;
710 comp3
= VFCOMP_STORE_1_FP
;
717 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
719 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
720 * formats, 64-bit components are stored in the URB without any
721 * conversion. In this case, vertex elements must be written as 128
722 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
723 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
724 * component into the URB, Component 1 must be specified as
725 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
726 * order to output a 128-bit vertex element, or Components 1-3 must
727 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
728 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
729 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
732 if (glattrib
->Doubles
&& !input
->is_dual_slot
) {
733 /* Store vertex elements which correspond to double and dvec2 vertex
734 * shader inputs as 128-bit vertex elements, instead of 256-bits.
736 comp2
= VFCOMP_NOSTORE
;
737 comp3
= VFCOMP_NOSTORE
;
741 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
742 .VertexBufferIndex
= input
->buffer
,
744 .SourceElementFormat
= upload_format
,
745 .SourceElementOffset
= offset
,
746 .Component0Control
= comp0
,
747 .Component1Control
= comp1
,
748 .Component2Control
= comp2
,
749 .Component3Control
= comp3
,
751 .DestinationElementOffset
= i
* 4,
755 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
756 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
760 if (needs_sgvs_element
) {
761 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
763 .Component0Control
= VFCOMP_STORE_0
,
764 .Component1Control
= VFCOMP_STORE_0
,
765 .Component2Control
= VFCOMP_STORE_0
,
766 .Component3Control
= VFCOMP_STORE_0
,
768 .DestinationElementOffset
= i
* 4,
773 if (uses_draw_params
) {
774 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
775 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
776 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
777 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
780 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
781 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
782 if (uses_draw_params
) {
783 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
784 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
787 if (vs_prog_data
->uses_vertexid
)
788 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
790 if (vs_prog_data
->uses_instanceid
)
791 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
794 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
795 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
798 if (uses_derived_draw_params
) {
799 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
801 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
802 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
803 .Component0Control
= VFCOMP_STORE_SRC
,
804 .Component1Control
= VFCOMP_STORE_SRC
,
805 .Component2Control
= VFCOMP_STORE_0
,
806 .Component3Control
= VFCOMP_STORE_0
,
808 .DestinationElementOffset
= i
* 4,
812 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
813 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
817 if (gen6_edgeflag_input
) {
818 const struct gl_array_attributes
*glattrib
= gen6_edgeflag_input
->glattrib
;
819 const uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
821 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
823 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
824 .EdgeFlagEnable
= true,
825 .SourceElementFormat
= format
,
826 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
827 .Component0Control
= VFCOMP_STORE_SRC
,
828 .Component1Control
= VFCOMP_STORE_0
,
829 .Component2Control
= VFCOMP_STORE_0
,
830 .Component3Control
= VFCOMP_STORE_0
,
833 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
834 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
839 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
840 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
841 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
842 unsigned element_index
;
844 /* The edge flag element is reordered to be the last one in the code
845 * above so we need to compensate for that in the element indices used
848 if (input
== gen6_edgeflag_input
)
849 element_index
= nr_elements
- 1;
853 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
854 vfi
.VertexElementIndex
= element_index
;
855 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
856 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
860 if (vs_prog_data
->uses_drawid
) {
861 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
863 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
864 vfi
.VertexElementIndex
= element
;
870 static const struct brw_tracked_state
genX(vertices
) = {
872 .mesa
= _NEW_POLYGON
,
873 .brw
= BRW_NEW_BATCH
|
876 BRW_NEW_VS_PROG_DATA
,
878 .emit
= genX(emit_vertices
),
882 genX(emit_index_buffer
)(struct brw_context
*brw
)
884 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
886 if (index_buffer
== NULL
)
889 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
890 #if GEN_GEN < 8 && !GEN_IS_HASWELL
891 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
893 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
895 /* The VF cache designers apparently cut corners, and made the cache
896 * only consider the bottom 32 bits of memory addresses. If you happen
897 * to have two index buffers which get placed exactly 4 GiB apart and
898 * use them in back-to-back draw calls, you can get collisions. To work
899 * around this problem, we restrict index buffers to the low 32 bits of
902 ib
.BufferStartingAddress
= ro_32_bo(brw
->ib
.bo
, 0);
904 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
905 ib
.BufferSize
= brw
->ib
.size
;
907 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
912 static const struct brw_tracked_state
genX(index_buffer
) = {
915 .brw
= BRW_NEW_BATCH
|
917 BRW_NEW_INDEX_BUFFER
,
919 .emit
= genX(emit_index_buffer
),
922 #if GEN_IS_HASWELL || GEN_GEN >= 8
924 genX(upload_cut_index
)(struct brw_context
*brw
)
926 const struct gl_context
*ctx
= &brw
->ctx
;
928 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
929 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
930 vf
.IndexedDrawCutIndexEnable
= true;
931 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
936 const struct brw_tracked_state
genX(cut_index
) = {
938 .mesa
= _NEW_TRANSFORM
,
939 .brw
= BRW_NEW_INDEX_BUFFER
,
941 .emit
= genX(upload_cut_index
),
947 * Determine the appropriate attribute override value to store into the
948 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
949 * override value contains two pieces of information: the location of the
950 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
951 * flag indicating whether to "swizzle" the attribute based on the direction
952 * the triangle is facing.
954 * If an attribute is "swizzled", then the given VUE location is used for
955 * front-facing triangles, and the VUE location that immediately follows is
956 * used for back-facing triangles. We use this to implement the mapping from
957 * gl_FrontColor/gl_BackColor to gl_Color.
959 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
960 * being instructed to begin reading attribute data. It can be set to a
961 * nonzero value to prevent the SF unit from wasting time reading elements of
962 * the VUE that are not needed by the fragment shader. It is measured in
963 * 256-bit increments.
966 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
967 const struct brw_vue_map
*vue_map
,
968 int urb_entry_read_offset
, int fs_attr
,
969 bool two_side_color
, uint32_t *max_source_attr
)
971 /* Find the VUE slot for this attribute. */
972 int slot
= vue_map
->varying_to_slot
[fs_attr
];
974 /* Viewport and Layer are stored in the VUE header. We need to override
975 * them to zero if earlier stages didn't write them, as GL requires that
976 * they read back as zero when not explicitly set.
978 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
979 attr
->ComponentOverrideX
= true;
980 attr
->ComponentOverrideW
= true;
981 attr
->ConstantSource
= CONST_0000
;
983 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
984 attr
->ComponentOverrideY
= true;
985 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
986 attr
->ComponentOverrideZ
= true;
991 /* If there was only a back color written but not front, use back
992 * as the color instead of undefined
994 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
995 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
996 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
997 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
1000 /* This attribute does not exist in the VUE--that means that the vertex
1001 * shader did not write to it. This means that either:
1003 * (a) This attribute is a texture coordinate, and it is going to be
1004 * replaced with point coordinates (as a consequence of a call to
1005 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
1006 * hardware will ignore whatever attribute override we supply.
1008 * (b) This attribute is read by the fragment shader but not written by
1009 * the vertex shader, so its value is undefined. Therefore the
1010 * attribute override we supply doesn't matter.
1012 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
1013 * previous shader stage.
1015 * Note that we don't have to worry about the cases where the attribute
1016 * is gl_PointCoord or is undergoing point sprite coordinate
1017 * replacement, because in those cases, this function isn't called.
1019 * In case (c), we need to program the attribute overrides so that the
1020 * primitive ID will be stored in this slot. In every other case, the
1021 * attribute override we supply doesn't matter. So just go ahead and
1022 * program primitive ID in every case.
1024 attr
->ComponentOverrideW
= true;
1025 attr
->ComponentOverrideX
= true;
1026 attr
->ComponentOverrideY
= true;
1027 attr
->ComponentOverrideZ
= true;
1028 attr
->ConstantSource
= PRIM_ID
;
1032 /* Compute the location of the attribute relative to urb_entry_read_offset.
1033 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1034 * it counts for two 128-bit VUE slots.
1036 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1037 assert(source_attr
>= 0 && source_attr
< 32);
1039 /* If we are doing two-sided color, and the VUE slot following this one
1040 * represents a back-facing color, then we need to instruct the SF unit to
1041 * do back-facing swizzling.
1043 bool swizzling
= two_side_color
&&
1044 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1045 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1046 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1047 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1049 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1050 if (*max_source_attr
< source_attr
+ swizzling
)
1051 *max_source_attr
= source_attr
+ swizzling
;
1053 attr
->SourceAttribute
= source_attr
;
1055 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1060 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1061 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1062 uint32_t *point_sprite_enables
,
1063 uint32_t *urb_entry_read_length
,
1064 uint32_t *urb_entry_read_offset
)
1066 const struct gl_context
*ctx
= &brw
->ctx
;
1069 const struct gl_point_attrib
*point
= &ctx
->Point
;
1071 /* BRW_NEW_FRAGMENT_PROGRAM */
1072 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1074 /* BRW_NEW_FS_PROG_DATA */
1075 const struct brw_wm_prog_data
*wm_prog_data
=
1076 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1077 uint32_t max_source_attr
= 0;
1079 *point_sprite_enables
= 0;
1082 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1083 &brw
->vue_map_geom_out
);
1085 /* Each URB offset packs two varying slots */
1086 assert(first_slot
% 2 == 0);
1087 *urb_entry_read_offset
= first_slot
/ 2;
1089 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1090 * description of dw10 Point Sprite Texture Coordinate Enable:
1092 * "This field must be programmed to zero when non-point primitives
1095 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1096 * must be programmed to zero when rendering non-point primitives, but
1097 * the IvyBridge PRM does, and if we don't, we get garbage.
1099 * This is not required on Haswell, as the hardware ignores this state
1100 * when drawing non-points -- although we do still need to be careful to
1101 * correctly set the attr overrides.
1104 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1106 bool drawing_points
= brw_is_drawing_points(brw
);
1108 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1109 int input_index
= wm_prog_data
->urb_setup
[attr
];
1111 if (input_index
< 0)
1115 bool point_sprite
= false;
1116 if (drawing_points
) {
1117 if (point
->PointSprite
&&
1118 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1119 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1120 point_sprite
= true;
1123 if (attr
== VARYING_SLOT_PNTC
)
1124 point_sprite
= true;
1127 *point_sprite_enables
|= (1 << input_index
);
1130 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1131 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1133 if (!point_sprite
) {
1134 genX(get_attr_override
)(&attribute
,
1135 &brw
->vue_map_geom_out
,
1136 *urb_entry_read_offset
, attr
,
1137 _mesa_vertex_program_two_side_enabled(ctx
),
1141 /* The hardware can only do the overrides on 16 overrides at a
1142 * time, and the other up to 16 have to be lined up so that the
1143 * input index = the output index. We'll need to do some
1144 * tweaking to make sure that's the case.
1146 if (input_index
< 16)
1147 attr_overrides
[input_index
] = attribute
;
1149 assert(attribute
.SourceAttribute
== input_index
);
1152 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1153 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1155 * "This field should be set to the minimum length required to read the
1156 * maximum source attribute. The maximum source attribute is indicated
1157 * by the maximum value of the enabled Attribute # Source Attribute if
1158 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1159 * enable is not set.
1160 * read_length = ceiling((max_source_attr + 1) / 2)
1162 * [errata] Corruption/Hang possible if length programmed larger than
1165 * Similar text exists for Ivy Bridge.
1167 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1171 /* ---------------------------------------------------------------------- */
1174 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1176 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1178 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1182 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1184 struct gl_context
*ctx
= &brw
->ctx
;
1187 struct intel_renderbuffer
*depth_irb
=
1188 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1191 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1194 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1195 const int b
= stencil
->_BackFace
;
1197 if (depth
->Test
&& depth_irb
) {
1198 ds
->DepthTestEnable
= true;
1199 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1200 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1203 if (brw
->stencil_enabled
) {
1204 ds
->StencilTestEnable
= true;
1205 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1206 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1208 ds
->StencilTestFunction
=
1209 intel_translate_compare_func(stencil
->Function
[0]);
1211 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1212 ds
->StencilPassDepthPassOp
=
1213 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1214 ds
->StencilPassDepthFailOp
=
1215 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1217 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1219 if (brw
->stencil_two_sided
) {
1220 ds
->DoubleSidedStencilEnable
= true;
1221 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1222 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1224 ds
->BackfaceStencilTestFunction
=
1225 intel_translate_compare_func(stencil
->Function
[b
]);
1226 ds
->BackfaceStencilFailOp
=
1227 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1228 ds
->BackfaceStencilPassDepthPassOp
=
1229 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1230 ds
->BackfaceStencilPassDepthFailOp
=
1231 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1234 #if GEN_GEN <= 5 || GEN_GEN >= 9
1235 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1236 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1243 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1246 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1247 set_depth_stencil_bits(brw
, &wmds
);
1251 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1252 set_depth_stencil_bits(brw
, &ds
);
1255 /* Now upload a pointer to the indirect state */
1257 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1258 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1259 ptr
.DEPTH_STENCIL_STATEChange
= true;
1262 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1263 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1269 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1271 .mesa
= _NEW_BUFFERS
|
1274 .brw
= BRW_NEW_BLORP
|
1275 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1277 BRW_NEW_STATE_BASE_ADDRESS
),
1279 .emit
= genX(upload_depth_stencil_state
),
1283 /* ---------------------------------------------------------------------- */
1288 genX(upload_clip_state
)(struct brw_context
*brw
)
1290 struct gl_context
*ctx
= &brw
->ctx
;
1292 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1293 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1294 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1295 clip
.GRFRegisterCount
=
1296 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1297 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1298 clip
.SingleProgramFlow
= true;
1299 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1300 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1302 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1303 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1304 clip
.DispatchGRFStartRegisterForURBData
= 1;
1305 clip
.VertexURBEntryReadOffset
= 0;
1307 /* BRW_NEW_URB_FENCE */
1308 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1309 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1311 if (brw
->urb
.nr_clip_entries
>= 10) {
1312 /* Half of the URB entries go to each thread, and it has to be an
1315 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1317 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1318 * only 2 threads can output VUEs at a time.
1320 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1322 assert(brw
->urb
.nr_clip_entries
>= 5);
1323 clip
.MaximumNumberofThreads
= 1 - 1;
1326 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1327 clip
.UserClipFlagsMustClipEnable
= true;
1328 clip
.GuardbandClipTestEnable
= true;
1330 clip
.ClipperViewportStatePointer
=
1331 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1333 clip
.ScreenSpaceViewportXMin
= -1;
1334 clip
.ScreenSpaceViewportXMax
= 1;
1335 clip
.ScreenSpaceViewportYMin
= -1;
1336 clip
.ScreenSpaceViewportYMax
= 1;
1338 clip
.ViewportXYClipTestEnable
= true;
1339 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1341 /* _NEW_TRANSFORM */
1342 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1343 clip
.UserClipDistanceClipTestEnableBitmask
=
1344 ctx
->Transform
.ClipPlanesEnabled
;
1346 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1349 clip
.UserClipDistanceClipTestEnableBitmask
=
1350 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1353 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1354 clip
.APIMode
= APIMODE_D3D
;
1356 clip
.APIMode
= APIMODE_OGL
;
1358 clip
.GuardbandClipTestEnable
= true;
1360 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1363 clip
.NegativeWClipTestEnable
= true;
1368 const struct brw_tracked_state
genX(clip_state
) = {
1370 .mesa
= _NEW_TRANSFORM
|
1372 .brw
= BRW_NEW_BATCH
|
1374 BRW_NEW_CLIP_PROG_DATA
|
1375 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1376 BRW_NEW_PROGRAM_CACHE
|
1379 .emit
= genX(upload_clip_state
),
1385 genX(upload_clip_state
)(struct brw_context
*brw
)
1387 struct gl_context
*ctx
= &brw
->ctx
;
1390 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1392 /* BRW_NEW_FS_PROG_DATA */
1393 struct brw_wm_prog_data
*wm_prog_data
=
1394 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1396 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1397 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1399 if (wm_prog_data
->barycentric_interp_modes
&
1400 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1401 clip
.NonPerspectiveBarycentricEnable
= true;
1404 clip
.EarlyCullEnable
= true;
1408 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1410 if (ctx
->Polygon
.CullFlag
) {
1411 switch (ctx
->Polygon
.CullFaceMode
) {
1413 clip
.CullMode
= CULLMODE_FRONT
;
1416 clip
.CullMode
= CULLMODE_BACK
;
1418 case GL_FRONT_AND_BACK
:
1419 clip
.CullMode
= CULLMODE_BOTH
;
1422 unreachable("Should not get here: invalid CullFlag");
1425 clip
.CullMode
= CULLMODE_NONE
;
1430 clip
.UserClipDistanceCullTestEnableBitmask
=
1431 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1433 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1437 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1438 clip
.TriangleStripListProvokingVertexSelect
= 0;
1439 clip
.TriangleFanProvokingVertexSelect
= 1;
1440 clip
.LineStripListProvokingVertexSelect
= 0;
1442 clip
.TriangleStripListProvokingVertexSelect
= 2;
1443 clip
.TriangleFanProvokingVertexSelect
= 2;
1444 clip
.LineStripListProvokingVertexSelect
= 1;
1447 /* _NEW_TRANSFORM */
1448 clip
.UserClipDistanceClipTestEnableBitmask
=
1449 ctx
->Transform
.ClipPlanesEnabled
;
1452 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1455 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1456 clip
.APIMode
= APIMODE_D3D
;
1458 clip
.APIMode
= APIMODE_OGL
;
1460 clip
.GuardbandClipTestEnable
= true;
1462 /* BRW_NEW_VIEWPORT_COUNT */
1463 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1465 if (ctx
->RasterDiscard
) {
1466 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1468 perf_debug("Rasterizer discard is currently implemented via the "
1469 "clipper; having the GS not write primitives would "
1470 "likely be faster.\n");
1473 clip
.ClipMode
= CLIPMODE_NORMAL
;
1476 clip
.ClipEnable
= true;
1479 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1481 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1482 clip
.ViewportXYClipTestEnable
= true;
1484 clip
.MinimumPointWidth
= 0.125;
1485 clip
.MaximumPointWidth
= 255.875;
1486 clip
.MaximumVPIndex
= viewport_count
- 1;
1487 if (_mesa_geometric_layers(fb
) == 0)
1488 clip
.ForceZeroRTAIndexEnable
= true;
1492 static const struct brw_tracked_state
genX(clip_state
) = {
1494 .mesa
= _NEW_BUFFERS
|
1498 .brw
= BRW_NEW_BLORP
|
1500 BRW_NEW_FS_PROG_DATA
|
1501 BRW_NEW_GS_PROG_DATA
|
1502 BRW_NEW_VS_PROG_DATA
|
1503 BRW_NEW_META_IN_PROGRESS
|
1505 BRW_NEW_RASTERIZER_DISCARD
|
1506 BRW_NEW_TES_PROG_DATA
|
1507 BRW_NEW_VIEWPORT_COUNT
,
1509 .emit
= genX(upload_clip_state
),
1513 /* ---------------------------------------------------------------------- */
1516 genX(upload_sf
)(struct brw_context
*brw
)
1518 struct gl_context
*ctx
= &brw
->ctx
;
1523 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1524 UNUSED
const bool multisampled_fbo
=
1525 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1529 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1531 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1533 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1534 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1535 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1536 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1537 sf
.DispatchGRFStartRegisterForURBData
= 3;
1538 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1539 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1540 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1541 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1543 /* STATE_PREFETCH command description describes this state as being
1544 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1547 sf
.SetupViewportStateOffset
=
1548 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1550 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1552 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1553 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1555 sf
.MaximumNumberofThreads
=
1556 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1558 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1560 sf
.DestinationOriginHorizontalBias
= 0.5;
1561 sf
.DestinationOriginVerticalBias
= 0.5;
1563 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1564 sf
.StatisticsEnable
= true;
1566 sf
.ViewportTransformEnable
= true;
1570 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1575 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1577 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1578 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1579 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1581 switch (ctx
->Polygon
.FrontMode
) {
1583 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1586 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1589 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1592 unreachable("not reached");
1595 switch (ctx
->Polygon
.BackMode
) {
1597 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1600 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1603 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1606 unreachable("not reached");
1609 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1610 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1612 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1613 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1614 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1617 sf
.ScissorRectangleEnable
= true;
1619 if (ctx
->Polygon
.CullFlag
) {
1620 switch (ctx
->Polygon
.CullFaceMode
) {
1622 sf
.CullMode
= CULLMODE_FRONT
;
1625 sf
.CullMode
= CULLMODE_BACK
;
1627 case GL_FRONT_AND_BACK
:
1628 sf
.CullMode
= CULLMODE_BOTH
;
1631 unreachable("not reached");
1634 sf
.CullMode
= CULLMODE_NONE
;
1638 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1645 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1647 if (devinfo
->is_cherryview
)
1648 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1650 sf
.LineWidth
= brw_get_line_width(brw
);
1652 sf
.LineWidth
= brw_get_line_width(brw
);
1655 if (ctx
->Line
.SmoothFlag
) {
1656 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1658 sf
.AntiAliasingEnable
= true;
1662 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1663 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1664 /* Clamp to the hardware limits */
1665 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1667 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1668 if (use_state_point_size(brw
))
1669 sf
.PointWidthSource
= State
;
1672 /* _NEW_POINT | _NEW_MULTISAMPLE */
1673 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1674 !ctx
->Point
.PointSprite
)
1675 sf
.SmoothPointEnable
= true;
1680 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1682 const bool multisampled_fbo
=
1683 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1684 if (multisampled_fbo
)
1685 sf
.SmoothPointEnable
= false;
1688 #if GEN_IS_G4X || GEN_GEN >= 5
1689 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1693 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1694 sf
.TriangleStripListProvokingVertexSelect
= 2;
1695 sf
.TriangleFanProvokingVertexSelect
= 2;
1696 sf
.LineStripListProvokingVertexSelect
= 1;
1698 sf
.TriangleFanProvokingVertexSelect
= 1;
1702 /* BRW_NEW_FS_PROG_DATA */
1703 const struct brw_wm_prog_data
*wm_prog_data
=
1704 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1706 sf
.AttributeSwizzleEnable
= true;
1707 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1710 * Window coordinates in an FBO are inverted, which means point
1711 * sprite origin must be inverted, too.
1713 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1714 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1716 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1719 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1720 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1722 uint32_t urb_entry_read_length
;
1723 uint32_t urb_entry_read_offset
;
1724 uint32_t point_sprite_enables
;
1725 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1726 &urb_entry_read_length
,
1727 &urb_entry_read_offset
);
1728 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1729 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1730 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1731 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1736 static const struct brw_tracked_state
genX(sf_state
) = {
1738 .mesa
= _NEW_LIGHT
|
1742 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1743 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1744 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1745 .brw
= BRW_NEW_BLORP
|
1746 BRW_NEW_VUE_MAP_GEOM_OUT
|
1747 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1748 BRW_NEW_PROGRAM_CACHE
|
1749 BRW_NEW_SF_PROG_DATA
|
1753 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1754 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1755 BRW_NEW_GS_PROG_DATA
|
1757 BRW_NEW_TES_PROG_DATA
1759 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1760 BRW_NEW_FRAGMENT_PROGRAM
1763 .emit
= genX(upload_sf
),
1766 /* ---------------------------------------------------------------------- */
1769 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1771 struct gl_context
*ctx
= &brw
->ctx
;
1772 /* BRW_NEW_FRAGMENT_PROGRAM */
1773 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1777 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1778 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1779 uint64_t outputs_written
= fp
->info
.outputs_written
;
1782 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1783 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1784 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1793 genX(upload_wm
)(struct brw_context
*brw
)
1795 struct gl_context
*ctx
= &brw
->ctx
;
1797 /* BRW_NEW_FS_PROG_DATA */
1798 const struct brw_wm_prog_data
*wm_prog_data
=
1799 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1801 UNUSED
bool writes_depth
=
1802 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1803 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1804 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1807 /* We can't fold this into gen6_upload_wm_push_constants(), because
1808 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1809 * (3DSTATE_CONSTANT_PS [DevSNB]):
1811 * "[DevSNB]: This packet must be followed by WM_STATE."
1813 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1814 if (wm_prog_data
->base
.nr_params
!= 0) {
1815 wmcp
.Buffer0Valid
= true;
1816 /* Pointer to the WM constant buffer. Covered by the set of
1817 * state flags from gen6_upload_wm_push_constants.
1819 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1820 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1826 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1827 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1828 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1830 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1831 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1833 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1834 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1835 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1836 /* These two fields should be the same pre-gen6, which is why we
1837 * only have one hardware field to program for both dispatch
1840 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1841 wm_prog_data
->dispatch_grf_start_reg_2
);
1844 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1845 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1847 if (stage_state
->sampler_count
)
1848 wm
.SamplerStatePointer
=
1849 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1851 if (wm_prog_data
->prog_offset_2
)
1852 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1855 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1856 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1857 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1858 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1859 wm
.EarlyDepthTestEnable
= true;
1860 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1861 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1864 if (ctx
->Polygon
.OffsetFill
) {
1865 wm
.GlobalDepthOffsetEnable
= true;
1866 /* Something weird going on with legacy_global_depth_bias,
1867 * offset_constant, scaling and MRD. This value passes glean
1868 * but gives some odd results elsewere (eg. the
1869 * quad-offset-units test).
1871 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1873 /* This is the only value that passes glean:
1875 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1878 wm
.DepthCoefficientURBReadOffset
= 1;
1881 /* BRW_NEW_STATS_WM */
1882 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1885 if (wm_prog_data
->base
.use_alt_mode
)
1886 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1888 wm
.SamplerCount
= GEN_GEN
== 5 ?
1889 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1891 wm
.BindingTableEntryCount
=
1892 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1893 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1894 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1895 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1896 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1897 wm_prog_data
->base
.dispatch_grf_start_reg
;
1899 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1900 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1904 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1905 wm
.KernelStartPointer2
=
1906 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1911 wm
.DualSourceBlendEnable
=
1912 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1913 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1914 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1915 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1917 /* From the SNB PRM, volume 2 part 1, page 281:
1918 * "If the PS kernel does not need the Position XY Offsets
1919 * to compute a Position XY value, then this field should be
1920 * programmed to POSOFFSET_NONE."
1922 * "SW Recommendation: If the PS kernel needs the Position Offsets
1923 * to compute a Position XY value, this field should match Position
1924 * ZW Interpolation Mode to ensure a consistent position.xyzw
1926 * We only require XY sample offsets. So, this recommendation doesn't
1927 * look useful at the moment. We might need this in future.
1929 if (wm_prog_data
->uses_pos_offset
)
1930 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1932 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1934 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1935 wm_prog_data
->dispatch_grf_start_reg_2
;
1938 if (wm_prog_data
->base
.total_scratch
) {
1939 wm
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
1940 wm
.PerThreadScratchSpace
=
1941 ffs(stage_state
->per_thread_scratch
) - 11;
1944 wm
.PixelShaderComputedDepth
= writes_depth
;
1948 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1951 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1956 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1959 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1961 if (multisampled_fbo
) {
1962 /* _NEW_MULTISAMPLE */
1963 if (ctx
->Multisample
.Enabled
)
1964 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1966 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1968 if (wm_prog_data
->persample_dispatch
)
1969 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1971 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1973 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1974 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1977 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1978 if (wm_prog_data
->uses_kill
||
1979 _mesa_is_alpha_test_enabled(ctx
) ||
1980 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1981 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1982 wm
.PixelShaderKillsPixel
= true;
1985 /* _NEW_BUFFERS | _NEW_COLOR */
1986 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1987 wm
.PixelShaderKillsPixel
||
1988 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1989 wm
.ThreadDispatchEnable
= true;
1993 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1994 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1997 /* The "UAV access enable" bits are unnecessary on HSW because they only
1998 * seem to have an effect on the HW-assisted coherency mechanism which we
1999 * don't need, and the rasterization-related UAV_ONLY flag and the
2000 * DISPATCH_ENABLE bit can be set independently from it.
2001 * C.f. gen8_upload_ps_extra().
2003 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
2007 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
2008 wm_prog_data
->has_side_effects
)
2014 /* BRW_NEW_FS_PROG_DATA */
2015 if (wm_prog_data
->early_fragment_tests
)
2016 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2017 else if (wm_prog_data
->has_side_effects
)
2018 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2023 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
2024 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
2025 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
2028 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
2033 static const struct brw_tracked_state
genX(wm_state
) = {
2037 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
2040 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2041 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2042 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2043 .brw
= BRW_NEW_BLORP
|
2044 BRW_NEW_FS_PROG_DATA
|
2045 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2046 BRW_NEW_FRAGMENT_PROGRAM
|
2047 BRW_NEW_PROGRAM_CACHE
|
2048 BRW_NEW_SAMPLER_STATE_TABLE
|
2051 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2053 .emit
= genX(upload_wm
),
2056 /* ---------------------------------------------------------------------- */
2058 /* We restrict scratch buffers to the bottom 32 bits of the address space
2059 * by using rw_32_bo().
2061 * General State Base Address is a bit broken. If the address + size as
2062 * seen by STATE_BASE_ADDRESS overflows 48 bits, the GPU appears to treat
2063 * all accesses to the buffer as being out of bounds and returns zero.
2066 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2067 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2068 pkt.SamplerCount = \
2069 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2070 pkt.BindingTableEntryCount = \
2071 stage_prog_data->binding_table.size_bytes / 4; \
2072 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2074 if (stage_prog_data->total_scratch) { \
2075 pkt.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0); \
2076 pkt.PerThreadScratchSpace = \
2077 ffs(stage_state->per_thread_scratch) - 11; \
2080 pkt.DispatchGRFStartRegisterForURBData = \
2081 stage_prog_data->dispatch_grf_start_reg; \
2082 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2083 pkt.prefix##URBEntryReadOffset = 0; \
2085 pkt.StatisticsEnable = true; \
2089 genX(upload_vs_state
)(struct brw_context
*brw
)
2091 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2092 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2093 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2095 /* BRW_NEW_VS_PROG_DATA */
2096 const struct brw_vue_prog_data
*vue_prog_data
=
2097 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2098 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2100 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2101 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2102 assert(GEN_GEN
< 11 ||
2103 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
2106 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2107 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2109 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2110 * command that causes the VS Function Enable to toggle. Pipeline
2111 * flush can be executed by sending a PIPE_CONTROL command with CS
2112 * stall bit set and a post sync operation.
2114 * We've already done such a flush at the start of state upload, so we
2115 * don't need to do another one here.
2117 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2118 if (stage_state
->push_const_size
!= 0) {
2119 cvs
.Buffer0Valid
= true;
2120 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2121 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2126 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2127 gen7_emit_vs_workaround_flush(brw
);
2130 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2132 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2133 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2135 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2137 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2140 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2141 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2142 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2144 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2145 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2147 vs
.MaximumNumberofThreads
=
2148 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2150 vs
.StatisticsEnable
= false;
2151 vs
.SamplerStatePointer
=
2152 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2156 /* Force single program flow on Ironlake. We cannot reliably get
2157 * all applications working without it. See:
2158 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2160 * The most notable and reliably failing application is the Humus
2163 vs
.SingleProgramFlow
= true;
2164 vs
.SamplerCount
= 0; /* hardware requirement */
2168 vs
.SIMD8DispatchEnable
=
2169 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2171 vs
.UserClipDistanceCullTestEnableBitmask
=
2172 vue_prog_data
->cull_distance_mask
;
2177 /* Based on my reading of the simulator, the VS constants don't get
2178 * pulled into the VS FF unit until an appropriate pipeline flush
2179 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2180 * references to them into a little FIFO. The flushes are common,
2181 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2182 * the primitive to use the wrong constants. Then the FIFO
2183 * containing the constant setup gets added to again on the next
2184 * constants change, and eventually when a flush does happen the
2185 * unit is overwhelmed by constant changes and dies.
2187 * To avoid this, send a PIPE_CONTROL down the line that will
2188 * update the unit immediately loading the constants. The flush
2189 * type bits here were those set by the STATE_BASE_ADDRESS whose
2190 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2191 * bug reports that led to this workaround, and may be more than
2192 * what is strictly required to avoid the issue.
2194 brw_emit_pipe_control_flush(brw
,
2195 PIPE_CONTROL_DEPTH_STALL
|
2196 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2197 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2201 static const struct brw_tracked_state
genX(vs_state
) = {
2203 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2204 .brw
= BRW_NEW_BATCH
|
2207 BRW_NEW_VS_PROG_DATA
|
2208 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2209 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2210 BRW_NEW_PROGRAM_CACHE
|
2211 BRW_NEW_SAMPLER_STATE_TABLE
|
2215 .emit
= genX(upload_vs_state
),
2218 /* ---------------------------------------------------------------------- */
2221 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2223 struct gl_context
*ctx
= &brw
->ctx
;
2225 /* BRW_NEW_VIEWPORT_COUNT */
2226 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2228 struct GENX(CC_VIEWPORT
) ccv
;
2229 uint32_t cc_vp_offset
;
2231 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2234 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2235 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2236 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2237 if (ctx
->Transform
.DepthClamp
) {
2238 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2239 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2241 ccv
.MinimumDepth
= 0.0;
2242 ccv
.MaximumDepth
= 1.0;
2244 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2245 cc_map
+= GENX(CC_VIEWPORT_length
);
2249 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2250 ptr
.CCViewportPointer
= cc_vp_offset
;
2253 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2254 vp
.CCViewportStateChange
= 1;
2255 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2258 brw
->cc
.vp_offset
= cc_vp_offset
;
2259 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2263 const struct brw_tracked_state
genX(cc_vp
) = {
2265 .mesa
= _NEW_TRANSFORM
|
2267 .brw
= BRW_NEW_BATCH
|
2269 BRW_NEW_VIEWPORT_COUNT
,
2271 .emit
= genX(upload_cc_viewport
)
2274 /* ---------------------------------------------------------------------- */
2277 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2278 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2279 struct GENX(SCISSOR_RECT
) *sc
)
2283 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2284 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2285 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2286 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2287 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2289 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2290 /* If the scissor was out of bounds and got clamped to 0 width/height
2291 * at the bounds, the subtraction of 1 from maximums could produce a
2292 * negative number and thus not clip anything. Instead, just provide
2293 * a min > max scissor inside the bounds, which produces the expected
2296 sc
->ScissorRectangleXMin
= 1;
2297 sc
->ScissorRectangleXMax
= 0;
2298 sc
->ScissorRectangleYMin
= 1;
2299 sc
->ScissorRectangleYMax
= 0;
2300 } else if (render_to_fbo
) {
2301 /* texmemory: Y=0=bottom */
2302 sc
->ScissorRectangleXMin
= bbox
[0];
2303 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2304 sc
->ScissorRectangleYMin
= bbox
[2];
2305 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2307 /* memory: Y=0=top */
2308 sc
->ScissorRectangleXMin
= bbox
[0];
2309 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2310 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2311 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2317 genX(upload_scissor_state
)(struct brw_context
*brw
)
2319 struct gl_context
*ctx
= &brw
->ctx
;
2320 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2321 struct GENX(SCISSOR_RECT
) scissor
;
2322 uint32_t scissor_state_offset
;
2323 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2324 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2325 uint32_t *scissor_map
;
2327 /* BRW_NEW_VIEWPORT_COUNT */
2328 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2330 scissor_map
= brw_state_batch(
2331 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2332 32, &scissor_state_offset
);
2334 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2336 /* The scissor only needs to handle the intersection of drawable and
2337 * scissor rect. Clipping to the boundaries of static shared buffers
2338 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2340 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2341 * inclusive but max is exclusive.
2343 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2344 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2345 GENX(SCISSOR_RECT_pack
)(
2346 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2349 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2350 ptr
.ScissorRectPointer
= scissor_state_offset
;
2354 static const struct brw_tracked_state
genX(scissor_state
) = {
2356 .mesa
= _NEW_BUFFERS
|
2359 .brw
= BRW_NEW_BATCH
|
2361 BRW_NEW_VIEWPORT_COUNT
,
2363 .emit
= genX(upload_scissor_state
),
2367 /* ---------------------------------------------------------------------- */
2370 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2371 float m00
, float m11
, float m30
, float m31
,
2372 float *xmin
, float *xmax
,
2373 float *ymin
, float *ymax
)
2375 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2376 * Strips and Fans documentation:
2378 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2379 * fixed-point "guardband" range supported by the rasterization hardware"
2383 * "In almost all circumstances, if an object’s vertices are actually
2384 * modified by this clamping (i.e., had X or Y coordinates outside of
2385 * the guardband extent the rendered object will not match the intended
2386 * result. Therefore software should take steps to ensure that this does
2387 * not happen - e.g., by clipping objects such that they do not exceed
2388 * these limits after the Drawing Rectangle is applied."
2390 * I believe the fundamental restriction is that the rasterizer (in
2391 * the SF/WM stages) have a limit on the number of pixels that can be
2392 * rasterized. We need to ensure any coordinates beyond the rasterizer
2393 * limit are handled by the clipper. So effectively that limit becomes
2394 * the clipper's guardband size.
2396 * It goes on to say:
2398 * "In addition, in order to be correctly rendered, objects must have a
2399 * screenspace bounding box not exceeding 8K in the X or Y direction.
2400 * This additional restriction must also be comprehended by software,
2401 * i.e., enforced by use of clipping."
2403 * This makes no sense. Gen7+ hardware supports 16K render targets,
2404 * and you definitely need to be able to draw polygons that fill the
2405 * surface. Our assumption is that the rasterizer was limited to 8K
2406 * on Sandybridge, which only supports 8K surfaces, and it was actually
2407 * increased to 16K on Ivybridge and later.
2409 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2411 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2413 if (m00
!= 0 && m11
!= 0) {
2414 /* First, we compute the screen-space render area */
2415 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2416 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2417 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2418 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2420 /* We want the guardband to be centered on that */
2421 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2422 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2423 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2424 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2426 /* Now we need it in native device coordinates */
2427 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2428 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2429 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2430 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2432 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2433 * flipped upside-down. X should be fine though.
2435 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2436 *xmin
= ndc_gb_xmin
;
2437 *xmax
= ndc_gb_xmax
;
2438 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2439 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2441 /* The viewport scales to 0, so nothing will be rendered. */
2450 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2452 struct gl_context
*ctx
= &brw
->ctx
;
2453 float y_scale
, y_bias
;
2455 /* BRW_NEW_VIEWPORT_COUNT */
2456 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2459 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2460 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2461 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2465 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2466 uint32_t sf_clip_vp_offset
;
2467 uint32_t *sf_clip_map
=
2468 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2469 64, &sf_clip_vp_offset
);
2471 struct GENX(SF_VIEWPORT
) sfv
;
2472 struct GENX(CLIP_VIEWPORT
) clv
;
2473 uint32_t sf_vp_offset
, clip_vp_offset
;
2475 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2477 uint32_t *clip_map
=
2478 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2479 32, &clip_vp_offset
);
2483 if (render_to_fbo
) {
2488 y_bias
= (float)fb_height
;
2491 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2492 /* _NEW_VIEWPORT: Guardband Clipping */
2493 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2494 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2496 sfv
.ViewportMatrixElementm00
= scale
[0];
2497 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2498 sfv
.ViewportMatrixElementm22
= scale
[2],
2499 sfv
.ViewportMatrixElementm30
= translate
[0],
2500 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2501 sfv
.ViewportMatrixElementm32
= translate
[2],
2502 brw_calculate_guardband_size(fb_width
, fb_height
,
2503 sfv
.ViewportMatrixElementm00
,
2504 sfv
.ViewportMatrixElementm11
,
2505 sfv
.ViewportMatrixElementm30
,
2506 sfv
.ViewportMatrixElementm31
,
2507 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2510 clv
.XMinClipGuardband
= gb_xmin
;
2511 clv
.XMaxClipGuardband
= gb_xmax
;
2512 clv
.YMinClipGuardband
= gb_ymin
;
2513 clv
.YMaxClipGuardband
= gb_ymax
;
2516 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2517 &sfv
.ScissorRectangle
);
2519 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2520 * The hardware will take the intersection of the drawing rectangle,
2521 * scissor rectangle, and the viewport extents. However, emitting
2522 * 3DSTATE_DRAWING_RECTANGLE is expensive since it requires a full
2523 * pipeline stall so we're better off just being a little more clever
2524 * with our viewport so we can emit it once at context creation time.
2526 const float viewport_Xmin
= MAX2(ctx
->ViewportArray
[i
].X
, 0);
2527 const float viewport_Ymin
= MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2528 const float viewport_Xmax
=
2529 MIN2(ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
, fb_width
);
2530 const float viewport_Ymax
=
2531 MIN2(ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
, fb_height
);
2533 if (render_to_fbo
) {
2534 sfv
.XMinViewPort
= viewport_Xmin
;
2535 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2536 sfv
.YMinViewPort
= viewport_Ymin
;
2537 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2539 sfv
.XMinViewPort
= viewport_Xmin
;
2540 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2541 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2542 sfv
.YMaxViewPort
= fb_height
- viewport_Ymin
- 1;
2547 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2548 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2550 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2551 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2552 sf_map
+= GENX(SF_VIEWPORT_length
);
2553 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2558 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2559 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2562 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2563 vp
.SFViewportStateChange
= 1;
2564 vp
.CLIPViewportStateChange
= 1;
2565 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2566 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2569 brw
->sf
.vp_offset
= sf_vp_offset
;
2570 brw
->clip
.vp_offset
= clip_vp_offset
;
2571 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2575 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2577 .mesa
= _NEW_BUFFERS
|
2579 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2580 .brw
= BRW_NEW_BATCH
|
2582 BRW_NEW_VIEWPORT_COUNT
,
2584 .emit
= genX(upload_sf_clip_viewport
),
2587 /* ---------------------------------------------------------------------- */
2590 genX(upload_gs_state
)(struct brw_context
*brw
)
2592 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2593 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2594 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2595 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2596 /* BRW_NEW_GEOMETRY_PROGRAM */
2597 bool active
= GEN_GEN
>= 6 && gs_prog
;
2599 /* BRW_NEW_GS_PROG_DATA */
2600 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2601 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2602 brw_vue_prog_data(stage_prog_data
);
2604 const struct brw_gs_prog_data
*gs_prog_data
=
2605 brw_gs_prog_data(stage_prog_data
);
2609 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2610 if (active
&& stage_state
->push_const_size
!= 0) {
2611 cgs
.Buffer0Valid
= true;
2612 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2613 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2618 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2620 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2621 * Geometry > Geometry Shader > State:
2623 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2624 * whole fixed function pipeline when the GS enable changes value in
2627 * The hardware architects have clarified that in this context "flush the
2628 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2631 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2632 gen7_emit_cs_stall_flush(brw
);
2636 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2638 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2639 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2644 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2647 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2648 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2649 gs
.ControlDataHeaderSize
=
2650 gs_prog_data
->control_data_header_size_hwords
;
2652 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2653 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2655 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2657 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2660 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2661 * Ivy Bridge and Haswell.
2663 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2664 * strip to be delivered to the geometry shader in an order that does
2665 * not strictly follow the OpenGL spec, but preserves triangle
2666 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2667 * the geometry shader sees triangles:
2669 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2671 * (Clearing the bit is even worse, because it fails to preserve
2674 * Triangle strips with adjacency always ordered in a way that preserves
2675 * triangle orientation but does not strictly follow the OpenGL spec,
2676 * regardless of the setting of this bit.
2678 * On Haswell, both triangle strips and triangle strips with adjacency
2679 * are always ordered in a way that preserves triangle orientation.
2680 * Setting this bit causes the ordering to strictly follow the OpenGL
2683 * So in either case we want to set the bit. Unfortunately on Ivy
2684 * Bridge this will get the order close to correct but not perfect.
2686 gs
.ReorderMode
= TRAILING
;
2687 gs
.MaximumNumberofThreads
=
2688 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2689 : (devinfo
->max_gs_threads
- 1);
2692 gs
.SOStatisticsEnable
= true;
2693 if (gs_prog
->info
.has_transform_feedback_varyings
)
2694 gs
.SVBIPayloadEnable
= true;
2696 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2697 * was previously done for gen6.
2699 * TODO: test with both disabled to see if the HW is behaving
2700 * as expected, like in gen7.
2702 gs
.SingleProgramFlow
= true;
2703 gs
.VectorMaskEnable
= true;
2707 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2709 if (gs_prog_data
->static_vertex_count
!= -1) {
2710 gs
.StaticOutput
= true;
2711 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2713 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2715 gs
.UserClipDistanceCullTestEnableBitmask
=
2716 vue_prog_data
->cull_distance_mask
;
2718 const int urb_entry_write_offset
= 1;
2719 const uint32_t urb_entry_output_length
=
2720 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2721 urb_entry_write_offset
;
2723 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2724 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2730 if (!active
&& brw
->ff_gs
.prog_active
) {
2731 /* In gen6, transform feedback for the VS stage is done with an
2732 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2735 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2736 gs
.SingleProgramFlow
= true;
2737 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2738 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2741 gs
.GRFRegisterCount
=
2742 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2743 /* BRW_NEW_URB_FENCE */
2744 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2745 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2746 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2747 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2750 gs
.VectorMaskEnable
= true;
2751 gs
.SVBIPayloadEnable
= true;
2752 gs
.SVBIPostIncrementEnable
= true;
2753 gs
.SVBIPostIncrementValue
=
2754 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2755 gs
.SOStatisticsEnable
= true;
2756 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2760 if (!active
&& !brw
->ff_gs
.prog_active
) {
2762 gs
.DispatchGRFStartRegisterForURBData
= 1;
2764 gs
.IncludeVertexHandles
= true;
2770 gs
.StatisticsEnable
= true;
2772 #if GEN_GEN == 5 || GEN_GEN == 6
2773 gs
.RenderingEnabled
= true;
2776 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2781 brw
->gs
.enabled
= active
;
2785 static const struct brw_tracked_state
genX(gs_state
) = {
2787 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2788 .brw
= BRW_NEW_BATCH
|
2790 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2791 BRW_NEW_PROGRAM_CACHE
|
2793 BRW_NEW_VIEWPORT_COUNT
2795 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2796 BRW_NEW_GEOMETRY_PROGRAM
|
2797 BRW_NEW_GS_PROG_DATA
2799 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2801 .emit
= genX(upload_gs_state
),
2804 /* ---------------------------------------------------------------------- */
2806 UNUSED
static GLenum
2807 fix_dual_blend_alpha_to_one(GLenum function
)
2813 case GL_ONE_MINUS_SRC1_ALPHA
:
2820 #define blend_factor(x) brw_translate_blend_factor(x)
2821 #define blend_eqn(x) brw_translate_blend_equation(x)
2824 * Modify blend function to force destination alpha to 1.0
2826 * If \c function specifies a blend function that uses destination alpha,
2827 * replace it with a function that hard-wires destination alpha to 1.0. This
2828 * is used when rendering to xRGB targets.
2831 brw_fix_xRGB_alpha(GLenum function
)
2837 case GL_ONE_MINUS_DST_ALPHA
:
2838 case GL_SRC_ALPHA_SATURATE
:
2846 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2848 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2852 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2855 struct gl_context
*ctx
= &brw
->ctx
;
2858 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2860 bool independent_alpha_blend
= false;
2862 /* Used for implementing the following bit of GL_EXT_texture_integer:
2863 * "Per-fragment operations that require floating-point color
2864 * components, including multisample alpha operations, alpha test,
2865 * blending, and dithering, have no effect when the corresponding
2866 * colors are written to an integer color buffer."
2868 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2870 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2871 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2874 if (ctx
->Color
.ColorLogicOpEnabled
) {
2875 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2876 : GL_UNSIGNED_NORMALIZED
;
2877 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2878 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2879 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2881 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2882 _mesa_enum_to_string(rb_type
));
2883 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2884 entry
->LogicOpEnable
= true;
2885 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2887 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2888 && (GEN_GEN
<= 5 || !integer
)) {
2889 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2890 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2891 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2892 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2893 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2894 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2896 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2897 srcRGB
= dstRGB
= GL_ONE
;
2899 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2900 srcA
= dstA
= GL_ONE
;
2902 /* Due to hardware limitations, the destination may have information
2903 * in an alpha channel even when the format specifies no alpha
2904 * channel. In order to avoid getting any incorrect blending due to
2905 * that alpha channel, coerce the blend factors to values that will
2906 * not read the alpha channel, but will instead use the correct
2907 * implicit value for alpha.
2909 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2910 GL_TEXTURE_ALPHA_TYPE
)) {
2911 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2912 srcA
= brw_fix_xRGB_alpha(srcA
);
2913 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2914 dstA
= brw_fix_xRGB_alpha(dstA
);
2917 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2918 * "If Dual Source Blending is enabled, this bit must be disabled."
2920 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2921 * and leave it enabled anyway.
2923 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2924 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2925 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2926 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2927 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2930 entry
->ColorBufferBlendEnable
= true;
2931 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2932 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2933 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2934 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2935 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2936 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2938 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2939 independent_alpha_blend
= true;
2942 return independent_alpha_blend
;
2947 genX(upload_blend_state
)(struct brw_context
*brw
)
2949 struct gl_context
*ctx
= &brw
->ctx
;
2952 /* We need at least one BLEND_STATE written, because we might do
2953 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2954 * for computed depth or alpha test), which will do an FB write
2955 * with render target 0, which will reference BLEND_STATE[0] for
2956 * alpha test enable.
2958 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2959 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2960 nr_draw_buffers
= 1;
2962 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2964 size
+= GENX(BLEND_STATE_length
) * 4;
2967 uint32_t *blend_map
;
2968 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2971 struct GENX(BLEND_STATE
) blend
= { 0 };
2974 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2975 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2978 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2979 * "If drawbuffer zero is not NONE and the buffer it references has an
2980 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2981 * operations are skipped."
2983 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2984 /* _NEW_MULTISAMPLE */
2985 if (_mesa_is_multisample_enabled(ctx
)) {
2986 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2987 blend
.AlphaToCoverageEnable
= true;
2988 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2990 if (ctx
->Multisample
.SampleAlphaToOne
)
2991 blend
.AlphaToOneEnable
= true;
2995 if (ctx
->Color
.AlphaEnabled
) {
2996 blend
.AlphaTestEnable
= true;
2997 blend
.AlphaTestFunction
=
2998 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3001 if (ctx
->Color
.DitherFlag
) {
3002 blend
.ColorDitherEnable
= true;
3007 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3008 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3012 blend
.IndependentAlphaBlendEnable
=
3013 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
3014 blend
.IndependentAlphaBlendEnable
;
3016 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
3017 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
3019 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
3020 * clamping in the fragment shader. For its clamping of
3021 * blending, the spec says:
3023 * "RESOLVED: For fixed-point color buffers, the inputs and
3024 * the result of the blending equation are clamped. For
3025 * floating-point color buffers, no clamping occurs."
3027 * So, generally, we want clamping to the render target's range.
3028 * And, good news, the hardware tables for both pre- and
3029 * post-blend color clamping are either ignored, or any are
3030 * allowed, or clamping is required but RT range clamping is a
3033 entry
.PreBlendColorClampEnable
= true;
3034 entry
.PostBlendColorClampEnable
= true;
3035 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
3037 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
3038 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
3039 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
3040 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
3043 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
3045 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3051 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3055 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3056 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3057 ptr
.BLEND_STATEChange
= true;
3060 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3061 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3063 ptr
.BlendStatePointerValid
= true;
3069 static const struct brw_tracked_state
genX(blend_state
) = {
3071 .mesa
= _NEW_BUFFERS
|
3074 .brw
= BRW_NEW_BATCH
|
3076 BRW_NEW_STATE_BASE_ADDRESS
,
3078 .emit
= genX(upload_blend_state
),
3082 /* ---------------------------------------------------------------------- */
3085 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3086 [MESA_SHADER_VERTEX
] = 21,
3087 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3088 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3089 [MESA_SHADER_GEOMETRY
] = 22,
3090 [MESA_SHADER_FRAGMENT
] = 23,
3091 [MESA_SHADER_COMPUTE
] = 0,
3095 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3097 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3098 struct gl_context
*ctx
= &brw
->ctx
;
3100 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3102 struct brw_stage_state
*stage_states
[] = {
3110 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3111 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3112 gen7_emit_vs_workaround_flush(brw
);
3114 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3115 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3116 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3118 if (!stage_state
->push_constants_dirty
)
3121 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3122 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3123 if (stage_state
->prog_data
) {
3124 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3125 /* The Skylake PRM contains the following restriction:
3127 * "The driver must ensure The following case does not occur
3128 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3129 * buffer 3 read length equal to zero committed followed by a
3130 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3133 * To avoid this, we program the buffers in the highest slots.
3134 * This way, slot 0 is only used if slot 3 is also used.
3138 for (int i
= 3; i
>= 0; i
--) {
3139 const struct brw_ubo_range
*range
=
3140 &stage_state
->prog_data
->ubo_ranges
[i
];
3142 if (range
->length
== 0)
3145 const struct gl_uniform_block
*block
=
3146 prog
->sh
.UniformBlocks
[range
->block
];
3147 const struct gl_buffer_binding
*binding
=
3148 &ctx
->UniformBufferBindings
[block
->Binding
];
3150 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3151 static unsigned msg_id
= 0;
3152 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3153 MESA_DEBUG_TYPE_UNDEFINED
,
3154 MESA_DEBUG_SEVERITY_HIGH
,
3155 "UBO %d unbound, %s shader uniform data "
3156 "will be undefined.",
3158 _mesa_shader_stage_to_string(stage
));
3162 assert(binding
->Offset
% 32 == 0);
3164 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3165 intel_buffer_object(binding
->BufferObject
),
3166 binding
->Offset
, range
->length
* 32, false);
3168 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3169 pkt
.ConstantBody
.Buffer
[n
] =
3170 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3174 if (stage_state
->push_const_size
> 0) {
3176 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3177 pkt
.ConstantBody
.Buffer
[n
] =
3178 ro_bo(stage_state
->push_const_bo
,
3179 stage_state
->push_const_offset
);
3182 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3183 pkt
.ConstantBody
.Buffer
[0].offset
=
3184 stage_state
->push_const_offset
| mocs
;
3189 stage_state
->push_constants_dirty
= false;
3190 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3194 const struct brw_tracked_state
genX(push_constant_packets
) = {
3197 .brw
= BRW_NEW_DRAW_CALL
,
3199 .emit
= genX(upload_push_constant_packets
),
3205 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3207 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3209 /* BRW_NEW_VERTEX_PROGRAM */
3210 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3211 /* BRW_NEW_VS_PROG_DATA */
3212 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3214 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3217 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3219 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3221 .brw
= BRW_NEW_BATCH
|
3223 BRW_NEW_VERTEX_PROGRAM
|
3224 BRW_NEW_VS_PROG_DATA
,
3226 .emit
= genX(upload_vs_push_constants
),
3230 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3232 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3234 /* BRW_NEW_GEOMETRY_PROGRAM */
3235 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3237 /* BRW_NEW_GS_PROG_DATA */
3238 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3240 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3243 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3245 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3247 .brw
= BRW_NEW_BATCH
|
3249 BRW_NEW_GEOMETRY_PROGRAM
|
3250 BRW_NEW_GS_PROG_DATA
,
3252 .emit
= genX(upload_gs_push_constants
),
3256 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3258 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3259 /* BRW_NEW_FRAGMENT_PROGRAM */
3260 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3261 /* BRW_NEW_FS_PROG_DATA */
3262 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3264 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3267 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3269 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3270 .brw
= BRW_NEW_BATCH
|
3272 BRW_NEW_FRAGMENT_PROGRAM
|
3273 BRW_NEW_FS_PROG_DATA
,
3275 .emit
= genX(upload_wm_push_constants
),
3279 /* ---------------------------------------------------------------------- */
3283 genX(determine_sample_mask
)(struct brw_context
*brw
)
3285 struct gl_context
*ctx
= &brw
->ctx
;
3286 float coverage
= 1.0f
;
3287 float coverage_invert
= false;
3288 unsigned sample_mask
= ~0u;
3290 /* BRW_NEW_NUM_SAMPLES */
3291 unsigned num_samples
= brw
->num_samples
;
3293 if (_mesa_is_multisample_enabled(ctx
)) {
3294 if (ctx
->Multisample
.SampleCoverage
) {
3295 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3296 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3298 if (ctx
->Multisample
.SampleMask
) {
3299 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3303 if (num_samples
> 1) {
3304 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3305 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3306 if (coverage_invert
)
3307 coverage_bits
^= (1 << num_samples
) - 1;
3308 return coverage_bits
& sample_mask
;
3315 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3316 unsigned num_samples
)
3318 unsigned log2_samples
= ffs(num_samples
) - 1;
3320 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3321 multi
.PixelLocation
= CENTER
;
3322 multi
.NumberofMultisamples
= log2_samples
;
3324 GEN_SAMPLE_POS_4X(multi
.Sample
);
3326 switch (num_samples
) {
3328 GEN_SAMPLE_POS_1X(multi
.Sample
);
3331 GEN_SAMPLE_POS_2X(multi
.Sample
);
3334 GEN_SAMPLE_POS_4X(multi
.Sample
);
3337 GEN_SAMPLE_POS_8X(multi
.Sample
);
3347 genX(upload_multisample_state
)(struct brw_context
*brw
)
3349 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3351 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3353 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3354 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3358 static const struct brw_tracked_state
genX(multisample_state
) = {
3360 .mesa
= _NEW_MULTISAMPLE
|
3361 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3362 .brw
= BRW_NEW_BLORP
|
3364 BRW_NEW_NUM_SAMPLES
,
3366 .emit
= genX(upload_multisample_state
)
3370 /* ---------------------------------------------------------------------- */
3373 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3375 struct gl_context
*ctx
= &brw
->ctx
;
3377 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3379 cc
.IndependentAlphaBlendEnable
=
3380 set_blend_entry_bits(brw
, &cc
, 0, false);
3381 set_depth_stencil_bits(brw
, &cc
);
3383 if (ctx
->Color
.AlphaEnabled
&&
3384 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3385 cc
.AlphaTestEnable
= true;
3386 cc
.AlphaTestFunction
=
3387 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3390 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3392 cc
.StatisticsEnable
= brw
->stats_wm
;
3394 cc
.CCViewportStatePointer
=
3395 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3398 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3399 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3400 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3401 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3405 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3406 cc
.BackfaceStencilReferenceValue
=
3407 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3413 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3414 ctx
->Color
.AlphaRef
);
3418 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3419 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3421 ptr
.ColorCalcStatePointerValid
= true;
3425 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3429 static const struct brw_tracked_state
genX(color_calc_state
) = {
3431 .mesa
= _NEW_COLOR
|
3433 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3436 .brw
= BRW_NEW_BATCH
|
3438 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3440 : BRW_NEW_CC_STATE
|
3441 BRW_NEW_STATE_BASE_ADDRESS
),
3443 .emit
= genX(upload_color_calc_state
),
3447 /* ---------------------------------------------------------------------- */
3451 genX(upload_sbe
)(struct brw_context
*brw
)
3453 struct gl_context
*ctx
= &brw
->ctx
;
3454 /* BRW_NEW_FRAGMENT_PROGRAM */
3455 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3456 /* BRW_NEW_FS_PROG_DATA */
3457 const struct brw_wm_prog_data
*wm_prog_data
=
3458 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3460 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3462 #define attr_overrides sbe.Attribute
3464 uint32_t urb_entry_read_length
;
3465 uint32_t urb_entry_read_offset
;
3466 uint32_t point_sprite_enables
;
3468 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3469 sbe
.AttributeSwizzleEnable
= true;
3470 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3473 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3477 * Window coordinates in an FBO are inverted, which means point
3478 * sprite origin must be inverted.
3480 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3481 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3483 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3485 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3486 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3487 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3488 * BRW_NEW_VUE_MAP_GEOM_OUT
3490 genX(calculate_attr_overrides
)(brw
,
3492 &point_sprite_enables
,
3493 &urb_entry_read_length
,
3494 &urb_entry_read_offset
);
3496 /* Typically, the URB entry read length and offset should be programmed
3497 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3498 * stage which produces geometry. However, we don't know the proper
3499 * value until we call calculate_attr_overrides().
3501 * To fit with our existing code, we override the inherited values and
3502 * specify it here directly, as we did on previous generations.
3504 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3505 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3506 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3507 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3510 sbe
.ForceVertexURBEntryReadLength
= true;
3511 sbe
.ForceVertexURBEntryReadOffset
= true;
3515 /* prepare the active component dwords */
3516 for (int i
= 0; i
< 32; i
++)
3517 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3522 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3523 for (int i
= 0; i
< 16; i
++)
3524 sbes
.Attribute
[i
] = attr_overrides
[i
];
3528 #undef attr_overrides
3531 static const struct brw_tracked_state
genX(sbe_state
) = {
3533 .mesa
= _NEW_BUFFERS
|
3538 .brw
= BRW_NEW_BLORP
|
3540 BRW_NEW_FRAGMENT_PROGRAM
|
3541 BRW_NEW_FS_PROG_DATA
|
3542 BRW_NEW_GS_PROG_DATA
|
3543 BRW_NEW_TES_PROG_DATA
|
3544 BRW_NEW_VUE_MAP_GEOM_OUT
|
3545 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3548 .emit
= genX(upload_sbe
),
3552 /* ---------------------------------------------------------------------- */
3556 * Outputs the 3DSTATE_SO_DECL_LIST command.
3558 * The data output is a series of 64-bit entries containing a SO_DECL per
3559 * stream. We only have one stream of rendering coming out of the GS unit, so
3560 * we only emit stream 0 (low 16 bits) SO_DECLs.
3563 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3564 const struct brw_vue_map
*vue_map
)
3566 struct gl_context
*ctx
= &brw
->ctx
;
3567 /* BRW_NEW_TRANSFORM_FEEDBACK */
3568 struct gl_transform_feedback_object
*xfb_obj
=
3569 ctx
->TransformFeedback
.CurrentObject
;
3570 const struct gl_transform_feedback_info
*linked_xfb_info
=
3571 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3572 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3573 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3574 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3575 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3577 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3579 memset(so_decl
, 0, sizeof(so_decl
));
3581 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3582 * command feels strange -- each dword pair contains a SO_DECL per stream.
3584 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3585 const struct gl_transform_feedback_output
*output
=
3586 &linked_xfb_info
->Outputs
[i
];
3587 const int buffer
= output
->OutputBuffer
;
3588 const int varying
= output
->OutputRegister
;
3589 const unsigned stream_id
= output
->StreamId
;
3590 assert(stream_id
< MAX_VERTEX_STREAMS
);
3592 buffer_mask
[stream_id
] |= 1 << buffer
;
3594 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3596 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3597 * array. Instead, it simply increments DstOffset for the following
3598 * input by the number of components that should be skipped.
3600 * Our hardware is unusual in that it requires us to program SO_DECLs
3601 * for fake "hole" components, rather than simply taking the offset
3602 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3603 * program as many size = 4 holes as we can, then a final hole to
3604 * accommodate the final 1, 2, or 3 remaining.
3606 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3608 while (skip_components
> 0) {
3609 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3611 .OutputBufferSlot
= output
->OutputBuffer
,
3612 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3614 skip_components
-= 4;
3617 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3619 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3620 .OutputBufferSlot
= output
->OutputBuffer
,
3621 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3623 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3626 if (decls
[stream_id
] > max_decls
)
3627 max_decls
= decls
[stream_id
];
3631 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3632 .StreamtoBufferSelects0
= buffer_mask
[0],
3633 .StreamtoBufferSelects1
= buffer_mask
[1],
3634 .StreamtoBufferSelects2
= buffer_mask
[2],
3635 .StreamtoBufferSelects3
= buffer_mask
[3],
3636 .NumEntries0
= decls
[0],
3637 .NumEntries1
= decls
[1],
3638 .NumEntries2
= decls
[2],
3639 .NumEntries3
= decls
[3]);
3641 for (int i
= 0; i
< max_decls
; i
++) {
3642 GENX(SO_DECL_ENTRY_pack
)(
3643 brw
, dw
+ 2 + i
* 2,
3644 &(struct GENX(SO_DECL_ENTRY
)) {
3645 .Stream0Decl
= so_decl
[0][i
],
3646 .Stream1Decl
= so_decl
[1][i
],
3647 .Stream2Decl
= so_decl
[2][i
],
3648 .Stream3Decl
= so_decl
[3][i
],
3654 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3656 struct gl_context
*ctx
= &brw
->ctx
;
3657 /* BRW_NEW_TRANSFORM_FEEDBACK */
3658 struct gl_transform_feedback_object
*xfb_obj
=
3659 ctx
->TransformFeedback
.CurrentObject
;
3661 const struct gl_transform_feedback_info
*linked_xfb_info
=
3662 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3664 struct brw_transform_feedback_object
*brw_obj
=
3665 (struct brw_transform_feedback_object
*) xfb_obj
;
3666 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3669 /* Set up the up to 4 output buffers. These are the ranges defined in the
3670 * gl_transform_feedback_object.
3672 for (int i
= 0; i
< 4; i
++) {
3673 struct intel_buffer_object
*bufferobj
=
3674 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3677 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3678 sob
.SOBufferIndex
= i
;
3683 uint32_t start
= xfb_obj
->Offset
[i
];
3684 assert(start
% 4 == 0);
3685 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3687 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3688 assert(end
<= bo
->size
);
3690 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3691 sob
.SOBufferIndex
= i
;
3693 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3695 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3696 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3698 sob
.SOBufferEnable
= true;
3699 sob
.StreamOffsetWriteEnable
= true;
3700 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3701 sob
.SOBufferMOCS
= mocs_wb
;
3703 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3704 sob
.StreamOutputBufferOffsetAddress
=
3705 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3707 if (brw_obj
->zero_offsets
) {
3708 /* Zero out the offset and write that to offset_bo */
3709 sob
.StreamOffset
= 0;
3711 /* Use offset_bo as the "Stream Offset." */
3712 sob
.StreamOffset
= 0xFFFFFFFF;
3719 brw_obj
->zero_offsets
= false;
3724 query_active(struct gl_query_object
*q
)
3726 return q
&& q
->Active
;
3730 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3731 const struct brw_vue_map
*vue_map
)
3733 struct gl_context
*ctx
= &brw
->ctx
;
3734 /* BRW_NEW_TRANSFORM_FEEDBACK */
3735 struct gl_transform_feedback_object
*xfb_obj
=
3736 ctx
->TransformFeedback
.CurrentObject
;
3738 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3740 int urb_entry_read_offset
= 0;
3741 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3742 urb_entry_read_offset
;
3744 sos
.SOFunctionEnable
= true;
3745 sos
.SOStatisticsEnable
= true;
3747 /* BRW_NEW_RASTERIZER_DISCARD */
3748 if (ctx
->RasterDiscard
) {
3749 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3750 sos
.RenderingDisable
= true;
3752 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3753 "query active relies on the clipper.\n");
3758 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3759 sos
.ReorderMode
= TRAILING
;
3762 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3763 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3764 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3765 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3767 const struct gl_transform_feedback_info
*linked_xfb_info
=
3768 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3769 /* Set buffer pitches; 0 means unbound. */
3770 if (xfb_obj
->Buffers
[0])
3771 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3772 if (xfb_obj
->Buffers
[1])
3773 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3774 if (xfb_obj
->Buffers
[2])
3775 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3776 if (xfb_obj
->Buffers
[3])
3777 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3780 /* We always read the whole vertex. This could be reduced at some
3781 * point by reading less and offsetting the register index in the
3784 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3785 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3786 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3787 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3788 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3789 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3790 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3791 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3797 genX(upload_sol
)(struct brw_context
*brw
)
3799 struct gl_context
*ctx
= &brw
->ctx
;
3800 /* BRW_NEW_TRANSFORM_FEEDBACK */
3801 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3804 genX(upload_3dstate_so_buffers
)(brw
);
3806 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3807 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3810 /* Finally, set up the SOL stage. This command must always follow updates to
3811 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3812 * MMIO register updates (current performed by the kernel at each batch
3815 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3818 static const struct brw_tracked_state
genX(sol_state
) = {
3821 .brw
= BRW_NEW_BATCH
|
3823 BRW_NEW_RASTERIZER_DISCARD
|
3824 BRW_NEW_VUE_MAP_GEOM_OUT
|
3825 BRW_NEW_TRANSFORM_FEEDBACK
,
3827 .emit
= genX(upload_sol
),
3831 /* ---------------------------------------------------------------------- */
3835 genX(upload_ps
)(struct brw_context
*brw
)
3837 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3838 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3840 /* BRW_NEW_FS_PROG_DATA */
3841 const struct brw_wm_prog_data
*prog_data
=
3842 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3843 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3848 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3849 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3850 * incorrect for subspans where some of the pixels are unlit. We believe
3851 * the bit just didn't take effect in previous generations.
3853 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3856 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3858 /* BRW_NEW_FS_PROG_DATA */
3859 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3861 if (prog_data
->base
.use_alt_mode
)
3862 ps
.FloatingPointMode
= Alternate
;
3864 /* Haswell requires the sample mask to be set in this packet as well as
3865 * in 3DSTATE_SAMPLE_MASK; the values should match.
3868 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3870 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3873 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
3874 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
3875 * k, it implies 2(k+1) threads. It implicitly scales for different GT
3876 * levels (which have some # of PSDs).
3878 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
3881 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3883 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3885 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3888 if (prog_data
->base
.nr_params
> 0 ||
3889 prog_data
->base
.ubo_ranges
[0].length
> 0)
3890 ps
.PushConstantEnable
= true;
3893 /* From the IVB PRM, volume 2 part 1, page 287:
3894 * "This bit is inserted in the PS payload header and made available to
3895 * the DataPort (either via the message header or via header bypass) to
3896 * indicate that oMask data (one or two phases) is included in Render
3897 * Target Write messages. If present, the oMask data is used to mask off
3900 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3902 /* The hardware wedges if you have this bit set but don't turn on any
3903 * dual source blend factors.
3905 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3907 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3908 (ctx
->Color
.BlendEnabled
& 1) &&
3909 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3911 /* BRW_NEW_FS_PROG_DATA */
3912 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3915 /* From the documentation for this packet:
3916 * "If the PS kernel does not need the Position XY Offsets to
3917 * compute a Position Value, then this field should be programmed
3918 * to POSOFFSET_NONE."
3920 * "SW Recommendation: If the PS kernel needs the Position Offsets
3921 * to compute a Position XY value, this field should match Position
3922 * ZW Interpolation Mode to ensure a consistent position.xyzw
3925 * We only require XY sample offsets. So, this recommendation doesn't
3926 * look useful at the moment. We might need this in future.
3928 if (prog_data
->uses_pos_offset
)
3929 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3931 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3933 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3934 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3935 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3936 prog_data
->base
.dispatch_grf_start_reg
;
3937 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3938 prog_data
->dispatch_grf_start_reg_2
;
3940 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3941 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3942 prog_data
->prog_offset_2
;
3944 if (prog_data
->base
.total_scratch
) {
3945 ps
.ScratchSpaceBasePointer
=
3946 rw_32_bo(stage_state
->scratch_bo
,
3947 ffs(stage_state
->per_thread_scratch
) - 11);
3952 static const struct brw_tracked_state
genX(ps_state
) = {
3954 .mesa
= _NEW_MULTISAMPLE
|
3955 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3958 .brw
= BRW_NEW_BATCH
|
3960 BRW_NEW_FS_PROG_DATA
,
3962 .emit
= genX(upload_ps
),
3966 /* ---------------------------------------------------------------------- */
3970 genX(upload_hs_state
)(struct brw_context
*brw
)
3972 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3973 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3974 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3975 const struct brw_vue_prog_data
*vue_prog_data
=
3976 brw_vue_prog_data(stage_prog_data
);
3978 /* BRW_NEW_TES_PROG_DATA */
3979 struct brw_tcs_prog_data
*tcs_prog_data
=
3980 brw_tcs_prog_data(stage_prog_data
);
3982 if (!tcs_prog_data
) {
3983 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3985 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3986 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3988 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3989 hs
.IncludeVertexHandles
= true;
3991 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3996 static const struct brw_tracked_state
genX(hs_state
) = {
3999 .brw
= BRW_NEW_BATCH
|
4001 BRW_NEW_TCS_PROG_DATA
|
4002 BRW_NEW_TESS_PROGRAMS
,
4004 .emit
= genX(upload_hs_state
),
4008 genX(upload_ds_state
)(struct brw_context
*brw
)
4010 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4011 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4012 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4014 /* BRW_NEW_TES_PROG_DATA */
4015 const struct brw_tes_prog_data
*tes_prog_data
=
4016 brw_tes_prog_data(stage_prog_data
);
4017 const struct brw_vue_prog_data
*vue_prog_data
=
4018 brw_vue_prog_data(stage_prog_data
);
4020 if (!tes_prog_data
) {
4021 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
4023 assert(GEN_GEN
< 11 ||
4024 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
4026 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
4027 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
4029 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4030 ds
.ComputeWCoordinateEnable
=
4031 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4034 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
4035 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4036 ds
.UserClipDistanceCullTestEnableBitmask
=
4037 vue_prog_data
->cull_distance_mask
;
4043 static const struct brw_tracked_state
genX(ds_state
) = {
4046 .brw
= BRW_NEW_BATCH
|
4048 BRW_NEW_TESS_PROGRAMS
|
4049 BRW_NEW_TES_PROG_DATA
,
4051 .emit
= genX(upload_ds_state
),
4054 /* ---------------------------------------------------------------------- */
4057 upload_te_state(struct brw_context
*brw
)
4059 /* BRW_NEW_TESS_PROGRAMS */
4060 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4062 /* BRW_NEW_TES_PROG_DATA */
4063 const struct brw_tes_prog_data
*tes_prog_data
=
4064 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4067 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4068 te
.Partitioning
= tes_prog_data
->partitioning
;
4069 te
.OutputTopology
= tes_prog_data
->output_topology
;
4070 te
.TEDomain
= tes_prog_data
->domain
;
4072 te
.MaximumTessellationFactorOdd
= 63.0;
4073 te
.MaximumTessellationFactorNotOdd
= 64.0;
4076 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4080 static const struct brw_tracked_state
genX(te_state
) = {
4083 .brw
= BRW_NEW_BLORP
|
4085 BRW_NEW_TES_PROG_DATA
|
4086 BRW_NEW_TESS_PROGRAMS
,
4088 .emit
= upload_te_state
,
4091 /* ---------------------------------------------------------------------- */
4094 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4096 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4097 /* BRW_NEW_TESS_PROGRAMS */
4098 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4100 /* BRW_NEW_TES_PROG_DATA */
4101 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4102 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4105 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4107 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4108 .brw
= BRW_NEW_BATCH
|
4110 BRW_NEW_TESS_PROGRAMS
|
4111 BRW_NEW_TES_PROG_DATA
,
4113 .emit
= genX(upload_tes_push_constants
),
4117 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4119 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4120 /* BRW_NEW_TESS_PROGRAMS */
4121 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4123 /* BRW_NEW_TCS_PROG_DATA */
4124 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4126 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4129 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4131 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4132 .brw
= BRW_NEW_BATCH
|
4134 BRW_NEW_DEFAULT_TESS_LEVELS
|
4135 BRW_NEW_TESS_PROGRAMS
|
4136 BRW_NEW_TCS_PROG_DATA
,
4138 .emit
= genX(upload_tcs_push_constants
),
4143 /* ---------------------------------------------------------------------- */
4147 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4149 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4151 /* BRW_NEW_COMPUTE_PROGRAM */
4152 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4155 /* BRW_NEW_CS_PROG_DATA */
4156 struct brw_cs_prog_data
*cs_prog_data
=
4157 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4159 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4160 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4164 const struct brw_tracked_state
genX(cs_push_constants
) = {
4166 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4167 .brw
= BRW_NEW_BATCH
|
4169 BRW_NEW_COMPUTE_PROGRAM
|
4170 BRW_NEW_CS_PROG_DATA
,
4172 .emit
= genX(upload_cs_push_constants
),
4176 * Creates a new CS constant buffer reflecting the current CS program's
4177 * constants, if needed by the CS program.
4180 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4182 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4184 /* BRW_NEW_COMPUTE_PROGRAM */
4185 struct brw_program
*cp
=
4186 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4188 /* BRW_NEW_CS_PROG_DATA */
4189 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4191 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4192 /* _NEW_PROGRAM_CONSTANTS */
4193 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4194 stage_state
, prog_data
);
4197 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4199 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4200 .brw
= BRW_NEW_BATCH
|
4202 BRW_NEW_COMPUTE_PROGRAM
|
4203 BRW_NEW_CS_PROG_DATA
,
4205 .emit
= genX(upload_cs_pull_constants
),
4209 genX(upload_cs_state
)(struct brw_context
*brw
)
4211 if (!brw
->cs
.base
.prog_data
)
4215 uint32_t *desc
= (uint32_t*) brw_state_batch(
4216 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4219 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4220 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4221 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4222 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4224 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4225 brw_emit_buffer_surface_state(
4226 brw
, &stage_state
->surf_offset
[
4227 prog_data
->binding_table
.shader_time_start
],
4228 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4229 brw
->shader_time
.bo
->size
, 1,
4233 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4234 32, &stage_state
->bind_bo_offset
);
4236 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4238 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4239 * the only bits that are changed are scoreboard related: Scoreboard
4240 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4241 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4243 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4244 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4246 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4248 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4249 if (prog_data
->total_scratch
) {
4250 uint32_t per_thread_scratch_value
;
4253 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4254 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4256 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4257 } else if (GEN_IS_HASWELL
) {
4258 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4259 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4261 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4263 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4264 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4266 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4268 vfe
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
4269 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4272 /* If brw->screen->subslice_total is greater than one, then
4273 * devinfo->max_cs_threads stores number of threads per sub-slice;
4274 * thus we need to multiply by that number by subslices to get
4275 * the actual maximum number of threads; the -1 is because the HW
4276 * has a bias of 1 (would not make sense to say the maximum number
4279 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4280 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4281 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4283 vfe
.ResetGatewayTimer
=
4284 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4287 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4293 /* We are uploading duplicated copies of push constant uniforms for each
4294 * thread. Although the local id data needs to vary per thread, it won't
4295 * change for other uniform data. Unfortunately this duplication is
4296 * required for gen7. As of Haswell, this duplication can be avoided,
4297 * but this older mechanism with duplicated data continues to work.
4299 * FINISHME: As of Haswell, we could make use of the
4300 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4301 * field to only store one copy of uniform data.
4303 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4304 * which is described in the GPGPU_WALKER command and in the Broadwell
4305 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4306 * Operations => GPGPU Mode => Indirect Payload Storage.
4308 * Note: The constant data is built in brw_upload_cs_push_constants
4311 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4313 const uint32_t vfe_curbe_allocation
=
4314 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4315 cs_prog_data
->push
.cross_thread
.regs
, 2);
4316 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4319 if (cs_prog_data
->push
.total
.size
> 0) {
4320 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4321 curbe
.CURBETotalDataLength
=
4322 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4323 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4327 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4328 memcpy(bind
, stage_state
->surf_offset
,
4329 prog_data
->binding_table
.size_bytes
);
4330 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4331 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4332 .SamplerStatePointer
= stage_state
->sampler_offset
,
4333 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4334 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4335 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4336 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4337 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4338 prog_data
->total_shared
),
4339 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4340 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4341 .CrossThreadConstantDataReadLength
=
4342 cs_prog_data
->push
.cross_thread
.regs
,
4346 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4348 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4349 load
.InterfaceDescriptorTotalLength
=
4350 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4351 load
.InterfaceDescriptorDataStartAddress
= offset
;
4355 static const struct brw_tracked_state
genX(cs_state
) = {
4357 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4358 .brw
= BRW_NEW_BATCH
|
4360 BRW_NEW_CS_PROG_DATA
|
4361 BRW_NEW_SAMPLER_STATE_TABLE
|
4364 .emit
= genX(upload_cs_state
)
4369 /* ---------------------------------------------------------------------- */
4373 genX(upload_raster
)(struct brw_context
*brw
)
4375 const struct gl_context
*ctx
= &brw
->ctx
;
4378 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4381 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4384 const struct gl_point_attrib
*point
= &ctx
->Point
;
4386 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4387 if (brw
->polygon_front_bit
== render_to_fbo
)
4388 raster
.FrontWinding
= CounterClockwise
;
4390 if (polygon
->CullFlag
) {
4391 switch (polygon
->CullFaceMode
) {
4393 raster
.CullMode
= CULLMODE_FRONT
;
4396 raster
.CullMode
= CULLMODE_BACK
;
4398 case GL_FRONT_AND_BACK
:
4399 raster
.CullMode
= CULLMODE_BOTH
;
4402 unreachable("not reached");
4405 raster
.CullMode
= CULLMODE_NONE
;
4408 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4410 raster
.DXMultisampleRasterizationEnable
=
4411 _mesa_is_multisample_enabled(ctx
);
4413 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4414 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4415 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4417 switch (polygon
->FrontMode
) {
4419 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4422 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4425 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4428 unreachable("not reached");
4431 switch (polygon
->BackMode
) {
4433 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4436 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4439 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4442 unreachable("not reached");
4446 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4450 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4452 const bool multisampled_fbo
=
4453 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4454 if (multisampled_fbo
)
4455 raster
.AntialiasingEnable
= false;
4459 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4461 /* _NEW_TRANSFORM */
4462 if (!ctx
->Transform
.DepthClamp
) {
4464 raster
.ViewportZFarClipTestEnable
= true;
4465 raster
.ViewportZNearClipTestEnable
= true;
4467 raster
.ViewportZClipTestEnable
= true;
4471 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4473 raster
.ConservativeRasterizationEnable
=
4474 ctx
->IntelConservativeRasterization
;
4477 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4478 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4480 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4484 static const struct brw_tracked_state
genX(raster_state
) = {
4486 .mesa
= _NEW_BUFFERS
|
4493 .brw
= BRW_NEW_BLORP
|
4495 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4497 .emit
= genX(upload_raster
),
4501 /* ---------------------------------------------------------------------- */
4505 genX(upload_ps_extra
)(struct brw_context
*brw
)
4507 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4509 const struct brw_wm_prog_data
*prog_data
=
4510 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4512 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4513 psx
.PixelShaderValid
= true;
4514 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4515 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4516 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4517 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4518 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4519 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4521 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4522 if (prog_data
->uses_sample_mask
) {
4524 if (prog_data
->post_depth_coverage
)
4525 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4526 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4527 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4529 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4531 psx
.PixelShaderUsesInputCoverageMask
= true;
4535 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4537 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4538 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4541 /* The stricter cross-primitive coherency guarantees that the hardware
4542 * gives us with the "Accesses UAV" bit set for at least one shader stage
4543 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4544 * are redundant within the current image, atomic counter and SSBO GL
4545 * APIs, which all have very loose ordering and coherency requirements
4546 * and generally rely on the application to insert explicit barriers when
4547 * a shader invocation is expected to see the memory writes performed by
4548 * the invocations of some previous primitive. Regardless of the value
4549 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4550 * cause an in most cases useless DC flush when the lowermost stage with
4551 * the bit set finishes execution.
4553 * It would be nice to disable it, but in some cases we can't because on
4554 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4555 * signal (which could be set independently from the coherency mechanism
4556 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4557 * determine whether the hardware skips execution of the fragment shader
4558 * or not via the ThreadDispatchEnable signal. However if we know that
4559 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4560 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4561 * difference so we may just disable it here.
4563 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4564 * take into account KillPixels when no depth or stencil writes are
4565 * enabled. In order for occlusion queries to work correctly with no
4566 * attachments, we need to force-enable here.
4568 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4571 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4572 !brw_color_buffer_write_enabled(brw
))
4573 psx
.PixelShaderHasUAV
= true;
4577 const struct brw_tracked_state
genX(ps_extra
) = {
4579 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4580 .brw
= BRW_NEW_BLORP
|
4582 BRW_NEW_FRAGMENT_PROGRAM
|
4583 BRW_NEW_FS_PROG_DATA
|
4584 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4586 .emit
= genX(upload_ps_extra
),
4590 /* ---------------------------------------------------------------------- */
4594 genX(upload_ps_blend
)(struct brw_context
*brw
)
4596 struct gl_context
*ctx
= &brw
->ctx
;
4599 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4600 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4603 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4605 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4606 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4607 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4609 bool alpha_to_one
= false;
4611 if (!buffer0_is_integer
) {
4612 /* _NEW_MULTISAMPLE */
4614 if (_mesa_is_multisample_enabled(ctx
)) {
4615 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4616 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4619 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4622 /* Used for implementing the following bit of GL_EXT_texture_integer:
4623 * "Per-fragment operations that require floating-point color
4624 * components, including multisample alpha operations, alpha test,
4625 * blending, and dithering, have no effect when the corresponding
4626 * colors are written to an integer color buffer."
4628 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4629 * "If drawbuffer zero is not NONE and the buffer it references has an
4630 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4631 * operations are skipped."
4633 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4634 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4635 GLenum eqA
= color
->Blend
[0].EquationA
;
4636 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4637 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4638 GLenum srcA
= color
->Blend
[0].SrcA
;
4639 GLenum dstA
= color
->Blend
[0].DstA
;
4641 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4642 srcRGB
= dstRGB
= GL_ONE
;
4644 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4645 srcA
= dstA
= GL_ONE
;
4647 /* Due to hardware limitations, the destination may have information
4648 * in an alpha channel even when the format specifies no alpha
4649 * channel. In order to avoid getting any incorrect blending due to
4650 * that alpha channel, coerce the blend factors to values that will
4651 * not read the alpha channel, but will instead use the correct
4652 * implicit value for alpha.
4654 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4655 GL_TEXTURE_ALPHA_TYPE
)) {
4656 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4657 srcA
= brw_fix_xRGB_alpha(srcA
);
4658 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4659 dstA
= brw_fix_xRGB_alpha(dstA
);
4662 /* Alpha to One doesn't work with Dual Color Blending. Override
4663 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4665 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4666 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4667 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4668 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4669 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4672 pb
.ColorBufferBlendEnable
= true;
4673 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4674 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4675 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4676 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4678 pb
.IndependentAlphaBlendEnable
=
4679 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4684 static const struct brw_tracked_state
genX(ps_blend
) = {
4686 .mesa
= _NEW_BUFFERS
|
4689 .brw
= BRW_NEW_BLORP
|
4691 BRW_NEW_FRAGMENT_PROGRAM
,
4693 .emit
= genX(upload_ps_blend
)
4697 /* ---------------------------------------------------------------------- */
4701 genX(emit_vf_topology
)(struct brw_context
*brw
)
4703 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4704 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4708 static const struct brw_tracked_state
genX(vf_topology
) = {
4711 .brw
= BRW_NEW_BLORP
|
4714 .emit
= genX(emit_vf_topology
),
4718 /* ---------------------------------------------------------------------- */
4722 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4724 uint32_t offset_in_bytes
,
4727 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4728 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4729 mi_rpc
.ReportID
= report_id
;
4734 /* ---------------------------------------------------------------------- */
4737 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4740 genX(emit_sampler_state_pointers_xs
)(MAYBE_UNUSED
struct brw_context
*brw
,
4741 MAYBE_UNUSED
struct brw_stage_state
*stage_state
)
4744 static const uint16_t packet_headers
[] = {
4745 [MESA_SHADER_VERTEX
] = 43,
4746 [MESA_SHADER_TESS_CTRL
] = 44,
4747 [MESA_SHADER_TESS_EVAL
] = 45,
4748 [MESA_SHADER_GEOMETRY
] = 46,
4749 [MESA_SHADER_FRAGMENT
] = 47,
4752 /* Ivybridge requires a workaround flush before VS packets. */
4753 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4754 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4755 gen7_emit_vs_workaround_flush(brw
);
4758 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4759 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4760 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4766 has_component(mesa_format format
, int i
)
4768 if (_mesa_is_format_color_format(format
))
4769 return _mesa_format_has_color_component(format
, i
);
4771 /* depth and stencil have only one component */
4776 * Upload SAMPLER_BORDER_COLOR_STATE.
4779 genX(upload_default_color
)(struct brw_context
*brw
,
4780 const struct gl_sampler_object
*sampler
,
4781 MAYBE_UNUSED mesa_format format
, GLenum base_format
,
4782 bool is_integer_format
, bool is_stencil_sampling
,
4783 uint32_t *sdc_offset
)
4785 union gl_color_union color
;
4787 switch (base_format
) {
4788 case GL_DEPTH_COMPONENT
:
4789 /* GL specs that border color for depth textures is taken from the
4790 * R channel, while the hardware uses A. Spam R into all the
4791 * channels for safety.
4793 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4794 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4795 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4796 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4802 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4805 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4806 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4807 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4808 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4811 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4812 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4813 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4814 color
.ui
[3] = float_as_int(1.0);
4816 case GL_LUMINANCE_ALPHA
:
4817 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4818 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4819 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4820 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4823 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4824 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4825 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4826 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4830 /* In some cases we use an RGBA surface format for GL RGB textures,
4831 * where we've initialized the A channel to 1.0. We also have to set
4832 * the border color alpha to 1.0 in that case.
4834 if (base_format
== GL_RGB
)
4835 color
.ui
[3] = float_as_int(1.0);
4840 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4844 uint32_t *sdc
= brw_state_batch(
4845 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4846 alignment
, sdc_offset
);
4848 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4850 #define ASSIGN(dst, src) \
4855 #define ASSIGNu16(dst, src) \
4857 dst = (uint16_t)src; \
4860 #define ASSIGNu8(dst, src) \
4862 dst = (uint8_t)src; \
4865 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4866 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4867 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4868 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4869 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4872 /* On Broadwell, the border color is represented as four 32-bit floats,
4873 * integers, or unsigned values, interpreted according to the surface
4874 * format. This matches the sampler->BorderColor union exactly; just
4875 * memcpy the values.
4877 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4878 #elif GEN_IS_HASWELL
4879 if (is_integer_format
|| is_stencil_sampling
) {
4880 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4881 const int bits_per_channel
=
4882 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4884 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4885 * "If any color channel is missing from the surface format,
4886 * corresponding border color should be programmed as zero and if
4887 * alpha channel is missing, corresponding Alpha border color should
4888 * be programmed as 1."
4890 unsigned c
[4] = { 0, 0, 0, 1 };
4891 for (int i
= 0; i
< 4; i
++) {
4892 if (has_component(format
, i
))
4896 switch (bits_per_channel
) {
4898 /* Copy RGBA in order. */
4899 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4902 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4904 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4907 if (base_format
== GL_RG
) {
4908 /* Careful inspection of the tables reveals that for RG32 formats,
4909 * the green channel needs to go where blue normally belongs.
4911 state
.BorderColor32bitRed
= c
[0];
4912 state
.BorderColor32bitBlue
= c
[1];
4913 state
.BorderColor32bitAlpha
= 1;
4915 /* Copy RGBA in order. */
4916 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4920 assert(!"Invalid number of bits per channel in integer format.");
4924 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4926 #elif GEN_GEN == 5 || GEN_GEN == 6
4927 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4928 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4929 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4931 #define MESA_FLOAT_TO_HALF(dst, src) \
4932 dst = _mesa_float_to_half(src);
4934 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4936 #undef MESA_FLOAT_TO_HALF
4938 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4939 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4940 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4941 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4943 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4945 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4947 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4951 #undef BORDER_COLOR_ATTR
4953 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4957 translate_wrap_mode(GLenum wrap
, MAYBE_UNUSED
bool using_nearest
)
4964 /* GL_CLAMP is the weird mode where coordinates are clamped to
4965 * [0.0, 1.0], so linear filtering of coordinates outside of
4966 * [0.0, 1.0] give you half edge texel value and half border
4969 * Gen8+ supports this natively.
4971 return TCM_HALF_BORDER
;
4973 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4974 * and set clamp_border here, which gets the result desired.
4975 * We just use clamp(_to_edge) for nearest, because for nearest
4976 * clamping to 1.0 gives border color instead of the desired
4982 return TCM_CLAMP_BORDER
;
4984 case GL_CLAMP_TO_EDGE
:
4986 case GL_CLAMP_TO_BORDER
:
4987 return TCM_CLAMP_BORDER
;
4988 case GL_MIRRORED_REPEAT
:
4990 case GL_MIRROR_CLAMP_TO_EDGE
:
4991 return TCM_MIRROR_ONCE
;
4998 * Return true if the given wrap mode requires the border color to exist.
5001 wrap_mode_needs_border_color(unsigned wrap_mode
)
5004 return wrap_mode
== TCM_CLAMP_BORDER
||
5005 wrap_mode
== TCM_HALF_BORDER
;
5007 return wrap_mode
== TCM_CLAMP_BORDER
;
5012 * Sets the sampler state for a single unit based off of the sampler key
5016 genX(update_sampler_state
)(struct brw_context
*brw
,
5017 GLenum target
, bool tex_cube_map_seamless
,
5018 GLfloat tex_unit_lod_bias
,
5019 mesa_format format
, GLenum base_format
,
5020 const struct gl_texture_object
*texObj
,
5021 const struct gl_sampler_object
*sampler
,
5022 uint32_t *sampler_state
)
5024 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
5026 /* Select min and mip filters. */
5027 switch (sampler
->MinFilter
) {
5029 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5030 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5033 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5034 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5036 case GL_NEAREST_MIPMAP_NEAREST
:
5037 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5038 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5040 case GL_LINEAR_MIPMAP_NEAREST
:
5041 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5042 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5044 case GL_NEAREST_MIPMAP_LINEAR
:
5045 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5046 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5048 case GL_LINEAR_MIPMAP_LINEAR
:
5049 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5050 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5053 unreachable("not reached");
5056 /* Select mag filter. */
5057 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5058 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5060 /* Enable anisotropic filtering if desired. */
5061 samp_st
.MaximumAnisotropy
= RATIO21
;
5063 if (sampler
->MaxAnisotropy
> 1.0f
) {
5064 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5065 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5066 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5067 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5069 if (sampler
->MaxAnisotropy
> 2.0f
) {
5070 samp_st
.MaximumAnisotropy
=
5071 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5075 /* Set address rounding bits if not using nearest filtering. */
5076 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5077 samp_st
.UAddressMinFilterRoundingEnable
= true;
5078 samp_st
.VAddressMinFilterRoundingEnable
= true;
5079 samp_st
.RAddressMinFilterRoundingEnable
= true;
5082 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5083 samp_st
.UAddressMagFilterRoundingEnable
= true;
5084 samp_st
.VAddressMagFilterRoundingEnable
= true;
5085 samp_st
.RAddressMagFilterRoundingEnable
= true;
5088 bool either_nearest
=
5089 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5090 unsigned wrap_s
= translate_wrap_mode(sampler
->WrapS
, either_nearest
);
5091 unsigned wrap_t
= translate_wrap_mode(sampler
->WrapT
, either_nearest
);
5092 unsigned wrap_r
= translate_wrap_mode(sampler
->WrapR
, either_nearest
);
5094 if (target
== GL_TEXTURE_CUBE_MAP
||
5095 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5096 /* Cube maps must use the same wrap mode for all three coordinate
5097 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5099 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5100 * integer formats. Fall back to CLAMP for now.
5102 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5103 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5112 } else if (target
== GL_TEXTURE_1D
) {
5113 /* There's a bug in 1D texture sampling - it actually pays
5114 * attention to the wrap_t value, though it should not.
5115 * Override the wrap_t value here to GL_REPEAT to keep
5116 * any nonexistent border pixels from floating in.
5121 samp_st
.TCXAddressControlMode
= wrap_s
;
5122 samp_st
.TCYAddressControlMode
= wrap_t
;
5123 samp_st
.TCZAddressControlMode
= wrap_r
;
5125 samp_st
.ShadowFunction
=
5126 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5127 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5130 /* Set shadow function. */
5131 samp_st
.AnisotropicAlgorithm
=
5132 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5133 EWAApproximation
: LEGACY
;
5137 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5140 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5141 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5142 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5143 samp_st
.TextureLODBias
=
5144 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5147 samp_st
.BaseMipLevel
=
5148 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5149 samp_st
.MinandMagStateNotEqual
=
5150 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5153 /* Upload the border color if necessary. If not, just point it at
5154 * offset 0 (the start of the batch) - the color should be ignored,
5155 * but that address won't fault in case something reads it anyway.
5157 uint32_t border_color_offset
= 0;
5158 if (wrap_mode_needs_border_color(wrap_s
) ||
5159 wrap_mode_needs_border_color(wrap_t
) ||
5160 wrap_mode_needs_border_color(wrap_r
)) {
5161 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5162 texObj
->_IsIntegerFormat
,
5163 texObj
->StencilSampling
,
5164 &border_color_offset
);
5167 samp_st
.BorderColorPointer
=
5168 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5170 samp_st
.BorderColorPointer
= border_color_offset
;
5174 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5176 samp_st
.LODPreClampEnable
= true;
5179 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5183 update_sampler_state(struct brw_context
*brw
,
5185 uint32_t *sampler_state
)
5187 struct gl_context
*ctx
= &brw
->ctx
;
5188 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5189 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5190 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5192 /* These don't use samplers at all. */
5193 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5196 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5197 genX(update_sampler_state
)(brw
, texObj
->Target
,
5198 ctx
->Texture
.CubeMapSeamless
,
5200 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5206 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5207 struct gl_program
*prog
,
5208 struct brw_stage_state
*stage_state
)
5210 struct gl_context
*ctx
= &brw
->ctx
;
5211 uint32_t sampler_count
= stage_state
->sampler_count
;
5213 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5215 if (sampler_count
== 0)
5218 /* SAMPLER_STATE is 4 DWords on all platforms. */
5219 const int dwords
= GENX(SAMPLER_STATE_length
);
5220 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5222 uint32_t *sampler_state
= brw_state_batch(brw
,
5223 sampler_count
* size_in_bytes
,
5224 32, &stage_state
->sampler_offset
);
5225 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5227 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5228 if (SamplersUsed
& (1 << s
)) {
5229 const unsigned unit
= prog
->SamplerUnits
[s
];
5230 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5231 update_sampler_state(brw
, unit
, sampler_state
);
5235 sampler_state
+= dwords
;
5238 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5239 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5240 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5242 /* Flag that the sampler state table pointer has changed; later atoms
5245 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5250 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5252 /* BRW_NEW_FRAGMENT_PROGRAM */
5253 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5254 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5257 static const struct brw_tracked_state
genX(fs_samplers
) = {
5259 .mesa
= _NEW_TEXTURE
,
5260 .brw
= BRW_NEW_BATCH
|
5262 BRW_NEW_FRAGMENT_PROGRAM
,
5264 .emit
= genX(upload_fs_samplers
),
5268 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5270 /* BRW_NEW_VERTEX_PROGRAM */
5271 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5272 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5275 static const struct brw_tracked_state
genX(vs_samplers
) = {
5277 .mesa
= _NEW_TEXTURE
,
5278 .brw
= BRW_NEW_BATCH
|
5280 BRW_NEW_VERTEX_PROGRAM
,
5282 .emit
= genX(upload_vs_samplers
),
5287 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5289 /* BRW_NEW_GEOMETRY_PROGRAM */
5290 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5294 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5298 static const struct brw_tracked_state
genX(gs_samplers
) = {
5300 .mesa
= _NEW_TEXTURE
,
5301 .brw
= BRW_NEW_BATCH
|
5303 BRW_NEW_GEOMETRY_PROGRAM
,
5305 .emit
= genX(upload_gs_samplers
),
5311 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5313 /* BRW_NEW_TESS_PROGRAMS */
5314 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5318 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5321 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5323 .mesa
= _NEW_TEXTURE
,
5324 .brw
= BRW_NEW_BATCH
|
5326 BRW_NEW_TESS_PROGRAMS
,
5328 .emit
= genX(upload_tcs_samplers
),
5334 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5336 /* BRW_NEW_TESS_PROGRAMS */
5337 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5341 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5344 static const struct brw_tracked_state
genX(tes_samplers
) = {
5346 .mesa
= _NEW_TEXTURE
,
5347 .brw
= BRW_NEW_BATCH
|
5349 BRW_NEW_TESS_PROGRAMS
,
5351 .emit
= genX(upload_tes_samplers
),
5357 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5359 /* BRW_NEW_COMPUTE_PROGRAM */
5360 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5364 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5367 const struct brw_tracked_state
genX(cs_samplers
) = {
5369 .mesa
= _NEW_TEXTURE
,
5370 .brw
= BRW_NEW_BATCH
|
5372 BRW_NEW_COMPUTE_PROGRAM
,
5374 .emit
= genX(upload_cs_samplers
),
5378 /* ---------------------------------------------------------------------- */
5382 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5384 struct gl_context
*ctx
= &brw
->ctx
;
5386 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5387 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5388 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5389 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5390 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5394 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5397 .brw
= BRW_NEW_CONTEXT
|
5400 .emit
= genX(upload_blend_constant_color
)
5404 /* ---------------------------------------------------------------------- */
5407 genX(init_atoms
)(struct brw_context
*brw
)
5410 static const struct brw_tracked_state
*render_atoms
[] =
5412 /* Once all the programs are done, we know how large urb entry
5413 * sizes need to be and can decide if we need to change the urb
5417 &brw_recalculate_urb_fence
,
5420 &genX(color_calc_state
),
5422 /* Surface state setup. Must come before the VS/WM unit. The binding
5423 * table upload must be last.
5425 &brw_vs_pull_constants
,
5426 &brw_wm_pull_constants
,
5427 &brw_renderbuffer_surfaces
,
5428 &brw_renderbuffer_read_surfaces
,
5429 &brw_texture_surfaces
,
5430 &brw_vs_binding_table
,
5431 &brw_wm_binding_table
,
5436 /* These set up state for brw_psp_urb_cbs */
5438 &genX(sf_clip_viewport
),
5440 &genX(vs_state
), /* always required, enabled or not */
5446 &brw_binding_table_pointers
,
5447 &genX(blend_constant_color
),
5451 &genX(polygon_stipple
),
5452 &genX(polygon_stipple_offset
),
5454 &genX(line_stipple
),
5458 &genX(drawing_rect
),
5459 &brw_indices
, /* must come before brw_vertices */
5460 &genX(index_buffer
),
5463 &brw_constant_buffer
5466 static const struct brw_tracked_state
*render_atoms
[] =
5468 &genX(sf_clip_viewport
),
5470 /* Command packets: */
5475 &genX(blend_state
), /* must do before cc unit */
5476 &genX(color_calc_state
), /* must do before cc unit */
5477 &genX(depth_stencil_state
), /* must do before cc unit */
5479 &genX(vs_push_constants
), /* Before vs_state */
5480 &genX(gs_push_constants
), /* Before gs_state */
5481 &genX(wm_push_constants
), /* Before wm_state */
5483 /* Surface state setup. Must come before the VS/WM unit. The binding
5484 * table upload must be last.
5486 &brw_vs_pull_constants
,
5487 &brw_vs_ubo_surfaces
,
5488 &brw_gs_pull_constants
,
5489 &brw_gs_ubo_surfaces
,
5490 &brw_wm_pull_constants
,
5491 &brw_wm_ubo_surfaces
,
5492 &gen6_renderbuffer_surfaces
,
5493 &brw_renderbuffer_read_surfaces
,
5494 &brw_texture_surfaces
,
5496 &brw_vs_binding_table
,
5497 &gen6_gs_binding_table
,
5498 &brw_wm_binding_table
,
5503 &gen6_sampler_state
,
5504 &genX(multisample_state
),
5512 &genX(scissor_state
),
5514 &gen6_binding_table_pointers
,
5518 &genX(polygon_stipple
),
5519 &genX(polygon_stipple_offset
),
5521 &genX(line_stipple
),
5523 &genX(drawing_rect
),
5525 &brw_indices
, /* must come before brw_vertices */
5526 &genX(index_buffer
),
5530 static const struct brw_tracked_state
*render_atoms
[] =
5532 /* Command packets: */
5535 &genX(sf_clip_viewport
),
5538 &gen7_push_constant_space
,
5540 &genX(blend_state
), /* must do before cc unit */
5541 &genX(color_calc_state
), /* must do before cc unit */
5542 &genX(depth_stencil_state
), /* must do before cc unit */
5544 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5545 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5546 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5547 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5548 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5550 &genX(vs_push_constants
), /* Before vs_state */
5551 &genX(tcs_push_constants
),
5552 &genX(tes_push_constants
),
5553 &genX(gs_push_constants
), /* Before gs_state */
5554 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5556 /* Surface state setup. Must come before the VS/WM unit. The binding
5557 * table upload must be last.
5559 &brw_vs_pull_constants
,
5560 &brw_vs_ubo_surfaces
,
5561 &brw_tcs_pull_constants
,
5562 &brw_tcs_ubo_surfaces
,
5563 &brw_tes_pull_constants
,
5564 &brw_tes_ubo_surfaces
,
5565 &brw_gs_pull_constants
,
5566 &brw_gs_ubo_surfaces
,
5567 &brw_wm_pull_constants
,
5568 &brw_wm_ubo_surfaces
,
5569 &gen6_renderbuffer_surfaces
,
5570 &brw_renderbuffer_read_surfaces
,
5571 &brw_texture_surfaces
,
5573 &genX(push_constant_packets
),
5575 &brw_vs_binding_table
,
5576 &brw_tcs_binding_table
,
5577 &brw_tes_binding_table
,
5578 &brw_gs_binding_table
,
5579 &brw_wm_binding_table
,
5583 &genX(tcs_samplers
),
5584 &genX(tes_samplers
),
5586 &genX(multisample_state
),
5600 &genX(scissor_state
),
5604 &genX(polygon_stipple
),
5605 &genX(polygon_stipple_offset
),
5607 &genX(line_stipple
),
5609 &genX(drawing_rect
),
5611 &brw_indices
, /* must come before brw_vertices */
5612 &genX(index_buffer
),
5620 static const struct brw_tracked_state
*render_atoms
[] =
5623 &genX(sf_clip_viewport
),
5626 &gen7_push_constant_space
,
5629 &genX(color_calc_state
),
5631 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5632 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5633 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5634 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5635 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5637 &genX(vs_push_constants
), /* Before vs_state */
5638 &genX(tcs_push_constants
),
5639 &genX(tes_push_constants
),
5640 &genX(gs_push_constants
), /* Before gs_state */
5641 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5643 /* Surface state setup. Must come before the VS/WM unit. The binding
5644 * table upload must be last.
5646 &brw_vs_pull_constants
,
5647 &brw_vs_ubo_surfaces
,
5648 &brw_tcs_pull_constants
,
5649 &brw_tcs_ubo_surfaces
,
5650 &brw_tes_pull_constants
,
5651 &brw_tes_ubo_surfaces
,
5652 &brw_gs_pull_constants
,
5653 &brw_gs_ubo_surfaces
,
5654 &brw_wm_pull_constants
,
5655 &brw_wm_ubo_surfaces
,
5656 &gen6_renderbuffer_surfaces
,
5657 &brw_renderbuffer_read_surfaces
,
5658 &brw_texture_surfaces
,
5660 &genX(push_constant_packets
),
5662 &brw_vs_binding_table
,
5663 &brw_tcs_binding_table
,
5664 &brw_tes_binding_table
,
5665 &brw_gs_binding_table
,
5666 &brw_wm_binding_table
,
5670 &genX(tcs_samplers
),
5671 &genX(tes_samplers
),
5673 &genX(multisample_state
),
5682 &genX(raster_state
),
5688 &genX(depth_stencil_state
),
5691 &genX(scissor_state
),
5695 &genX(polygon_stipple
),
5696 &genX(polygon_stipple_offset
),
5698 &genX(line_stipple
),
5700 &genX(drawing_rect
),
5705 &genX(index_buffer
),
5713 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5714 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5715 render_atoms
, ARRAY_SIZE(render_atoms
));
5718 static const struct brw_tracked_state
*compute_atoms
[] =
5721 &brw_cs_image_surfaces
,
5722 &genX(cs_push_constants
),
5723 &genX(cs_pull_constants
),
5724 &brw_cs_ubo_surfaces
,
5725 &brw_cs_texture_surfaces
,
5726 &brw_cs_work_groups_surface
,
5731 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5732 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5733 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5735 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);