2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "dev/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 UNUSED
static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 static struct brw_address
124 rw_32_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_32BIT
,
133 static struct brw_address
134 ro_32_bo(struct brw_bo
*bo
, uint32_t offset
)
136 return (struct brw_address
) {
139 .reloc_flags
= RELOC_32BIT
,
143 UNUSED
static struct brw_address
144 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
146 return (struct brw_address
) {
149 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
154 static struct brw_address
155 KSP(struct brw_context
*brw
, uint32_t offset
)
157 return ro_bo(brw
->cache
.bo
, offset
);
161 KSP(UNUSED
struct brw_context
*brw
, uint32_t offset
)
167 #include "genxml/genX_pack.h"
169 #define _brw_cmd_length(cmd) cmd ## _length
170 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
171 #define _brw_cmd_header(cmd) cmd ## _header
172 #define _brw_cmd_pack(cmd) cmd ## _pack
174 #define brw_batch_emit(brw, cmd, name) \
175 for (struct cmd name = { _brw_cmd_header(cmd) }, \
176 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
177 __builtin_expect(_dst != NULL, 1); \
178 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
182 uint32_t *_dw = emit_dwords(brw, n); \
183 struct cmd template = { \
184 _brw_cmd_header(cmd), \
185 .DWordLength = n - _brw_cmd_length_bias(cmd), \
188 _brw_cmd_pack(cmd)(brw, _dw, &template); \
189 _dw + 1; /* Array starts at dw[1] */ \
192 #define brw_state_emit(brw, cmd, align, offset, name) \
193 for (struct cmd name = {}, \
194 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
196 __builtin_expect(_dst != NULL, 1); \
197 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
201 * Polygon stipple packet
204 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
206 struct gl_context
*ctx
= &brw
->ctx
;
209 if (!ctx
->Polygon
.StippleFlag
)
212 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
213 /* Polygon stipple is provided in OpenGL order, i.e. bottom
214 * row first. If we're rendering to a window (i.e. the
215 * default frame buffer object, 0), then we need to invert
216 * it to match our pixel layout. But if we're rendering
217 * to a FBO (i.e. any named frame buffer object), we *don't*
218 * need to invert - we already match the layout.
220 if (ctx
->DrawBuffer
->FlipY
) {
221 for (unsigned i
= 0; i
< 32; i
++)
222 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
224 for (unsigned i
= 0; i
< 32; i
++)
225 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
230 static const struct brw_tracked_state
genX(polygon_stipple
) = {
232 .mesa
= _NEW_POLYGON
|
234 .brw
= BRW_NEW_CONTEXT
,
236 .emit
= genX(upload_polygon_stipple
),
240 * Polygon stipple offset packet
243 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
245 struct gl_context
*ctx
= &brw
->ctx
;
248 if (!ctx
->Polygon
.StippleFlag
)
251 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
254 * If we're drawing to a system window we have to invert the Y axis
255 * in order to match the OpenGL pixel coordinate system, and our
256 * offset must be matched to the window position. If we're drawing
257 * to a user-created FBO then our native pixel coordinate system
258 * works just fine, and there's no window system to worry about.
260 if (ctx
->DrawBuffer
->FlipY
) {
261 poly
.PolygonStippleYOffset
=
262 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
267 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
269 .mesa
= _NEW_BUFFERS
|
271 .brw
= BRW_NEW_CONTEXT
,
273 .emit
= genX(upload_polygon_stipple_offset
),
277 * Line stipple packet
280 genX(upload_line_stipple
)(struct brw_context
*brw
)
282 struct gl_context
*ctx
= &brw
->ctx
;
284 if (!ctx
->Line
.StippleFlag
)
287 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
288 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
290 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
291 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
295 static const struct brw_tracked_state
genX(line_stipple
) = {
298 .brw
= BRW_NEW_CONTEXT
,
300 .emit
= genX(upload_line_stipple
),
303 /* Constant single cliprect for framebuffer object or DRI2 drawing */
305 genX(upload_drawing_rect
)(struct brw_context
*brw
)
307 struct gl_context
*ctx
= &brw
->ctx
;
308 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
309 const unsigned int fb_width
= _mesa_geometric_width(fb
);
310 const unsigned int fb_height
= _mesa_geometric_height(fb
);
312 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
313 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
314 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
318 static const struct brw_tracked_state
genX(drawing_rect
) = {
320 .mesa
= _NEW_BUFFERS
,
321 .brw
= BRW_NEW_BLORP
|
324 .emit
= genX(upload_drawing_rect
),
328 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
332 unsigned start_offset
,
333 MAYBE_UNUSED
unsigned end_offset
,
335 MAYBE_UNUSED
unsigned step_rate
)
337 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
338 .VertexBufferIndex
= buffer_nr
,
339 .BufferPitch
= stride
,
341 /* The VF cache designers apparently cut corners, and made the cache
342 * only consider the bottom 32 bits of memory addresses. If you happen
343 * to have two vertex buffers which get placed exactly 4 GiB apart and
344 * use them in back-to-back draw calls, you can get collisions. To work
345 * around this problem, we restrict vertex buffers to the low 32 bits of
348 .BufferStartingAddress
= ro_32_bo(bo
, start_offset
),
350 .BufferSize
= end_offset
- start_offset
,
354 .AddressModifyEnable
= true,
358 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
359 .InstanceDataStepRate
= step_rate
,
361 .EndAddress
= ro_bo(bo
, end_offset
- 1),
366 .VertexBufferMOCS
= ICL_MOCS_WB
,
368 .VertexBufferMOCS
= CNL_MOCS_WB
,
370 .VertexBufferMOCS
= SKL_MOCS_WB
,
372 .VertexBufferMOCS
= BDW_MOCS_WB
,
374 .VertexBufferMOCS
= GEN7_MOCS_L3
,
378 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
379 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
383 is_passthru_format(uint32_t format
)
386 case ISL_FORMAT_R64_PASSTHRU
:
387 case ISL_FORMAT_R64G64_PASSTHRU
:
388 case ISL_FORMAT_R64G64B64_PASSTHRU
:
389 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
397 uploads_needed(uint32_t format
,
400 if (!is_passthru_format(format
))
407 case ISL_FORMAT_R64_PASSTHRU
:
408 case ISL_FORMAT_R64G64_PASSTHRU
:
410 case ISL_FORMAT_R64G64B64_PASSTHRU
:
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
414 unreachable("not reached");
419 * Returns the format that we are finally going to use when upload a vertex
420 * element. It will only change if we are using *64*PASSTHRU formats, as for
421 * gen < 8 they need to be splitted on two *32*FLOAT formats.
423 * @upload points in which upload we are. Valid values are [0,1]
426 downsize_format_if_needed(uint32_t format
,
429 assert(upload
== 0 || upload
== 1);
431 if (!is_passthru_format(format
))
434 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
435 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
436 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
437 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
438 * flagging that we want to fill with zeroes this second forced upload.
441 case ISL_FORMAT_R64_PASSTHRU
:
442 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
443 : ISL_FORMAT_R32_FLOAT
;
444 case ISL_FORMAT_R64G64_PASSTHRU
:
445 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
446 : ISL_FORMAT_R32_FLOAT
;
447 case ISL_FORMAT_R64G64B64_PASSTHRU
:
448 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
449 : ISL_FORMAT_R32G32_FLOAT
;
450 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
451 return ISL_FORMAT_R32G32B32A32_FLOAT
;
453 unreachable("not reached");
458 * Returns the number of componentes associated with a format that is used on
459 * a 64 to 32 format split. See downsize_format()
462 upload_format_size(uint32_t upload_format
)
464 switch (upload_format
) {
465 case ISL_FORMAT_R32_FLOAT
:
467 /* downsized_format has returned this one in order to flag that we are
468 * performing a second upload which we want to have filled with
469 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
470 * vertex shader input variables.
474 case ISL_FORMAT_R32G32_FLOAT
:
476 case ISL_FORMAT_R32G32B32A32_FLOAT
:
479 unreachable("not reached");
483 static UNUSED
uint16_t
484 pinned_bo_high_bits(struct brw_bo
*bo
)
486 return (bo
->kflags
& EXEC_OBJECT_PINNED
) ? bo
->gtt_offset
>> 32ull : 0;
489 /* The VF cache designers apparently cut corners, and made the cache key's
490 * <VertexBufferIndex, Memory Address> tuple only consider the bottom 32 bits
491 * of the address. If you happen to have two vertex buffers which get placed
492 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
493 * collisions. (These collisions can happen within a single batch.)
495 * In the soft-pin world, we'd like to assign addresses up front, and never
496 * move buffers. So, we need to do a VF cache invalidate if the buffer for
497 * a particular VB slot has different [48:32] address bits than the last one.
499 * In the relocation world, we have no idea what the addresses will be, so
500 * we can't apply this workaround. Instead, we tell the kernel to move it
501 * to the low 4GB regardless.
504 vf_invalidate_for_vb_48bit_transitions(struct brw_context
*brw
)
507 bool need_invalidate
= false;
510 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
511 uint16_t high_bits
= pinned_bo_high_bits(brw
->vb
.buffers
[i
].bo
);
513 if (high_bits
!= brw
->vb
.last_bo_high_bits
[i
]) {
514 need_invalidate
= true;
515 brw
->vb
.last_bo_high_bits
[i
] = high_bits
;
519 /* Don't bother with draw parameter buffers - those are generated by
520 * the driver so we can select a consistent memory zone.
523 if (need_invalidate
) {
524 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
530 vf_invalidate_for_ib_48bit_transition(struct brw_context
*brw
)
533 uint16_t high_bits
= pinned_bo_high_bits(brw
->ib
.bo
);
535 if (high_bits
!= brw
->ib
.last_bo_high_bits
) {
536 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
537 brw
->ib
.last_bo_high_bits
= high_bits
;
543 genX(emit_vertices
)(struct brw_context
*brw
)
545 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
548 brw_prepare_vertices(brw
);
549 brw_prepare_shader_draw_parameters(brw
);
552 brw_emit_query_begin(brw
);
555 const struct brw_vs_prog_data
*vs_prog_data
=
556 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
559 struct gl_context
*ctx
= &brw
->ctx
;
560 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
561 ctx
->Polygon
.BackMode
!= GL_FILL
);
563 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
564 unsigned vue
= brw
->vb
.nr_enabled
;
566 /* The element for the edge flags must always be last, so we have to
567 * insert the SGVS before it in that case.
569 if (uses_edge_flag
) {
575 "Trying to insert VID/IID past 33rd vertex element, "
576 "need to reorder the vertex attrbutes.");
578 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
579 if (vs_prog_data
->uses_vertexid
) {
580 vfs
.VertexIDEnable
= true;
581 vfs
.VertexIDComponentNumber
= 2;
582 vfs
.VertexIDElementOffset
= vue
;
585 if (vs_prog_data
->uses_instanceid
) {
586 vfs
.InstanceIDEnable
= true;
587 vfs
.InstanceIDComponentNumber
= 3;
588 vfs
.InstanceIDElementOffset
= vue
;
592 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
593 vfi
.InstancingEnable
= true;
594 vfi
.VertexElementIndex
= vue
;
597 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
601 const bool uses_draw_params
=
602 vs_prog_data
->uses_firstvertex
||
603 vs_prog_data
->uses_baseinstance
;
605 const bool uses_derived_draw_params
=
606 vs_prog_data
->uses_drawid
||
607 vs_prog_data
->uses_is_indexed_draw
;
609 const bool needs_sgvs_element
= (uses_draw_params
||
610 vs_prog_data
->uses_instanceid
||
611 vs_prog_data
->uses_vertexid
);
613 unsigned nr_elements
=
614 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ uses_derived_draw_params
;
617 /* If any of the formats of vb.enabled needs more that one upload, we need
618 * to add it to nr_elements
620 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
621 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
622 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
623 uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
625 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
630 /* If the VS doesn't read any inputs (calculating vertex position from
631 * a state variable for some reason, for example), emit a single pad
632 * VERTEX_ELEMENT struct and bail.
634 * The stale VB state stays in place, but they don't do anything unless
635 * a VE loads from them.
637 if (nr_elements
== 0) {
638 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
639 1 + GENX(VERTEX_ELEMENT_STATE_length
));
640 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
642 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
643 .Component0Control
= VFCOMP_STORE_0
,
644 .Component1Control
= VFCOMP_STORE_0
,
645 .Component2Control
= VFCOMP_STORE_0
,
646 .Component3Control
= VFCOMP_STORE_1_FP
,
648 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
652 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
653 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
654 uses_draw_params
+ uses_derived_draw_params
;
656 vf_invalidate_for_vb_48bit_transitions(brw
);
659 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
661 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
662 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
664 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
665 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
666 /* Prior to Haswell and Bay Trail we have to use 4-component formats
667 * to fake 3-component ones. In particular, we do this for
668 * half-float and 8 and 16-bit integer formats. This means that the
669 * vertex element may poke over the end of the buffer by 2 bytes.
671 const unsigned padding
=
672 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
673 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
674 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
681 if (uses_draw_params
) {
682 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
683 brw
->draw
.draw_params_bo
,
684 brw
->draw
.draw_params_offset
,
685 brw
->draw
.draw_params_bo
->size
,
690 if (uses_derived_draw_params
) {
691 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
692 brw
->draw
.derived_draw_params_bo
,
693 brw
->draw
.derived_draw_params_offset
,
694 brw
->draw
.derived_draw_params_bo
->size
,
700 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
701 * presumably for VertexID/InstanceID.
704 assert(nr_elements
<= 34);
705 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
707 assert(nr_elements
<= 18);
710 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
711 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
713 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
714 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
715 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
716 uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
717 uint32_t comp0
= VFCOMP_STORE_SRC
;
718 uint32_t comp1
= VFCOMP_STORE_SRC
;
719 uint32_t comp2
= VFCOMP_STORE_SRC
;
720 uint32_t comp3
= VFCOMP_STORE_SRC
;
721 const unsigned num_uploads
= GEN_GEN
< 8 ?
722 uploads_needed(format
, input
->is_dual_slot
) : 1;
725 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
726 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
727 * element which has edge flag enabled."
729 assert(!(is_passthru_format(format
) && uses_edge_flag
));
732 /* The gen4 driver expects edgeflag to come in as a float, and passes
733 * that float on to the tests in the clipper. Mesa's current vertex
734 * attribute value for EdgeFlag is stored as a float, which works out.
735 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
736 * integer ubyte. Just rewrite that to convert to a float.
738 * Gen6+ passes edgeflag as sideband along with the vertex, instead
739 * of in the VUE. We have to upload it sideband as the last vertex
740 * element according to the B-Spec.
743 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
744 gen6_edgeflag_input
= input
;
749 for (unsigned c
= 0; c
< num_uploads
; c
++) {
750 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
751 downsize_format_if_needed(format
, c
);
752 /* If we need more that one upload, the offset stride would be 128
753 * bits (16 bytes), as for previous uploads we are using the full
755 const unsigned offset
= input
->offset
+ c
* 16;
757 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
758 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
759 upload_format_size(upload_format
) : glattrib
->Size
;
762 case 0: comp0
= VFCOMP_STORE_0
;
763 case 1: comp1
= VFCOMP_STORE_0
;
764 case 2: comp2
= VFCOMP_STORE_0
;
766 if (GEN_GEN
>= 8 && glattrib
->Doubles
) {
767 comp3
= VFCOMP_STORE_0
;
768 } else if (glattrib
->Integer
) {
769 comp3
= VFCOMP_STORE_1_INT
;
771 comp3
= VFCOMP_STORE_1_FP
;
778 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
780 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
781 * formats, 64-bit components are stored in the URB without any
782 * conversion. In this case, vertex elements must be written as 128
783 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
784 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
785 * component into the URB, Component 1 must be specified as
786 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
787 * order to output a 128-bit vertex element, or Components 1-3 must
788 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
789 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
790 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
793 if (glattrib
->Doubles
&& !input
->is_dual_slot
) {
794 /* Store vertex elements which correspond to double and dvec2 vertex
795 * shader inputs as 128-bit vertex elements, instead of 256-bits.
797 comp2
= VFCOMP_NOSTORE
;
798 comp3
= VFCOMP_NOSTORE
;
802 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
803 .VertexBufferIndex
= input
->buffer
,
805 .SourceElementFormat
= upload_format
,
806 .SourceElementOffset
= offset
,
807 .Component0Control
= comp0
,
808 .Component1Control
= comp1
,
809 .Component2Control
= comp2
,
810 .Component3Control
= comp3
,
812 .DestinationElementOffset
= i
* 4,
816 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
817 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
821 if (needs_sgvs_element
) {
822 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
824 .Component0Control
= VFCOMP_STORE_0
,
825 .Component1Control
= VFCOMP_STORE_0
,
826 .Component2Control
= VFCOMP_STORE_0
,
827 .Component3Control
= VFCOMP_STORE_0
,
829 .DestinationElementOffset
= i
* 4,
834 if (uses_draw_params
) {
835 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
836 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
837 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
838 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
841 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
842 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
843 if (uses_draw_params
) {
844 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
845 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
848 if (vs_prog_data
->uses_vertexid
)
849 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
851 if (vs_prog_data
->uses_instanceid
)
852 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
855 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
856 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
859 if (uses_derived_draw_params
) {
860 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
862 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
863 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
864 .Component0Control
= VFCOMP_STORE_SRC
,
865 .Component1Control
= VFCOMP_STORE_SRC
,
866 .Component2Control
= VFCOMP_STORE_0
,
867 .Component3Control
= VFCOMP_STORE_0
,
869 .DestinationElementOffset
= i
* 4,
873 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
874 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
878 if (gen6_edgeflag_input
) {
879 const struct gl_array_attributes
*glattrib
= gen6_edgeflag_input
->glattrib
;
880 const uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
882 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
884 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
885 .EdgeFlagEnable
= true,
886 .SourceElementFormat
= format
,
887 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
888 .Component0Control
= VFCOMP_STORE_SRC
,
889 .Component1Control
= VFCOMP_STORE_0
,
890 .Component2Control
= VFCOMP_STORE_0
,
891 .Component3Control
= VFCOMP_STORE_0
,
894 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
895 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
900 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
901 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
902 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
903 unsigned element_index
;
905 /* The edge flag element is reordered to be the last one in the code
906 * above so we need to compensate for that in the element indices used
909 if (input
== gen6_edgeflag_input
)
910 element_index
= nr_elements
- 1;
914 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
915 vfi
.VertexElementIndex
= element_index
;
916 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
917 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
921 if (vs_prog_data
->uses_drawid
) {
922 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
924 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
925 vfi
.VertexElementIndex
= element
;
931 static const struct brw_tracked_state
genX(vertices
) = {
933 .mesa
= _NEW_POLYGON
,
934 .brw
= BRW_NEW_BATCH
|
936 BRW_NEW_VERTEX_PROGRAM
|
938 BRW_NEW_VS_PROG_DATA
,
940 .emit
= genX(emit_vertices
),
944 genX(emit_index_buffer
)(struct brw_context
*brw
)
946 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
948 if (index_buffer
== NULL
)
951 vf_invalidate_for_ib_48bit_transition(brw
);
953 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
954 #if GEN_GEN < 8 && !GEN_IS_HASWELL
955 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
957 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
959 /* The VF cache designers apparently cut corners, and made the cache
960 * only consider the bottom 32 bits of memory addresses. If you happen
961 * to have two index buffers which get placed exactly 4 GiB apart and
962 * use them in back-to-back draw calls, you can get collisions. To work
963 * around this problem, we restrict index buffers to the low 32 bits of
966 ib
.BufferStartingAddress
= ro_32_bo(brw
->ib
.bo
, 0);
968 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
969 ib
.BufferSize
= brw
->ib
.size
;
971 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
976 static const struct brw_tracked_state
genX(index_buffer
) = {
979 .brw
= BRW_NEW_BATCH
|
981 BRW_NEW_INDEX_BUFFER
,
983 .emit
= genX(emit_index_buffer
),
986 #if GEN_IS_HASWELL || GEN_GEN >= 8
988 genX(upload_cut_index
)(struct brw_context
*brw
)
990 const struct gl_context
*ctx
= &brw
->ctx
;
992 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
993 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
994 vf
.IndexedDrawCutIndexEnable
= true;
995 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
1000 const struct brw_tracked_state
genX(cut_index
) = {
1002 .mesa
= _NEW_TRANSFORM
,
1003 .brw
= BRW_NEW_INDEX_BUFFER
,
1005 .emit
= genX(upload_cut_index
),
1011 * Determine the appropriate attribute override value to store into the
1012 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
1013 * override value contains two pieces of information: the location of the
1014 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
1015 * flag indicating whether to "swizzle" the attribute based on the direction
1016 * the triangle is facing.
1018 * If an attribute is "swizzled", then the given VUE location is used for
1019 * front-facing triangles, and the VUE location that immediately follows is
1020 * used for back-facing triangles. We use this to implement the mapping from
1021 * gl_FrontColor/gl_BackColor to gl_Color.
1023 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
1024 * being instructed to begin reading attribute data. It can be set to a
1025 * nonzero value to prevent the SF unit from wasting time reading elements of
1026 * the VUE that are not needed by the fragment shader. It is measured in
1027 * 256-bit increments.
1030 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
1031 const struct brw_vue_map
*vue_map
,
1032 int urb_entry_read_offset
, int fs_attr
,
1033 bool two_side_color
, uint32_t *max_source_attr
)
1035 /* Find the VUE slot for this attribute. */
1036 int slot
= vue_map
->varying_to_slot
[fs_attr
];
1038 /* Viewport and Layer are stored in the VUE header. We need to override
1039 * them to zero if earlier stages didn't write them, as GL requires that
1040 * they read back as zero when not explicitly set.
1042 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
1043 attr
->ComponentOverrideX
= true;
1044 attr
->ComponentOverrideW
= true;
1045 attr
->ConstantSource
= CONST_0000
;
1047 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
1048 attr
->ComponentOverrideY
= true;
1049 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
1050 attr
->ComponentOverrideZ
= true;
1055 /* If there was only a back color written but not front, use back
1056 * as the color instead of undefined
1058 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
1059 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
1060 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
1061 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
1064 /* This attribute does not exist in the VUE--that means that the vertex
1065 * shader did not write to it. This means that either:
1067 * (a) This attribute is a texture coordinate, and it is going to be
1068 * replaced with point coordinates (as a consequence of a call to
1069 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
1070 * hardware will ignore whatever attribute override we supply.
1072 * (b) This attribute is read by the fragment shader but not written by
1073 * the vertex shader, so its value is undefined. Therefore the
1074 * attribute override we supply doesn't matter.
1076 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
1077 * previous shader stage.
1079 * Note that we don't have to worry about the cases where the attribute
1080 * is gl_PointCoord or is undergoing point sprite coordinate
1081 * replacement, because in those cases, this function isn't called.
1083 * In case (c), we need to program the attribute overrides so that the
1084 * primitive ID will be stored in this slot. In every other case, the
1085 * attribute override we supply doesn't matter. So just go ahead and
1086 * program primitive ID in every case.
1088 attr
->ComponentOverrideW
= true;
1089 attr
->ComponentOverrideX
= true;
1090 attr
->ComponentOverrideY
= true;
1091 attr
->ComponentOverrideZ
= true;
1092 attr
->ConstantSource
= PRIM_ID
;
1096 /* Compute the location of the attribute relative to urb_entry_read_offset.
1097 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1098 * it counts for two 128-bit VUE slots.
1100 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1101 assert(source_attr
>= 0 && source_attr
< 32);
1103 /* If we are doing two-sided color, and the VUE slot following this one
1104 * represents a back-facing color, then we need to instruct the SF unit to
1105 * do back-facing swizzling.
1107 bool swizzling
= two_side_color
&&
1108 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1109 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1110 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1111 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1113 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1114 if (*max_source_attr
< source_attr
+ swizzling
)
1115 *max_source_attr
= source_attr
+ swizzling
;
1117 attr
->SourceAttribute
= source_attr
;
1119 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1124 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1125 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1126 uint32_t *point_sprite_enables
,
1127 uint32_t *urb_entry_read_length
,
1128 uint32_t *urb_entry_read_offset
)
1130 const struct gl_context
*ctx
= &brw
->ctx
;
1133 const struct gl_point_attrib
*point
= &ctx
->Point
;
1135 /* BRW_NEW_FRAGMENT_PROGRAM */
1136 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1138 /* BRW_NEW_FS_PROG_DATA */
1139 const struct brw_wm_prog_data
*wm_prog_data
=
1140 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1141 uint32_t max_source_attr
= 0;
1143 *point_sprite_enables
= 0;
1146 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1147 &brw
->vue_map_geom_out
);
1149 /* Each URB offset packs two varying slots */
1150 assert(first_slot
% 2 == 0);
1151 *urb_entry_read_offset
= first_slot
/ 2;
1153 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1154 * description of dw10 Point Sprite Texture Coordinate Enable:
1156 * "This field must be programmed to zero when non-point primitives
1159 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1160 * must be programmed to zero when rendering non-point primitives, but
1161 * the IvyBridge PRM does, and if we don't, we get garbage.
1163 * This is not required on Haswell, as the hardware ignores this state
1164 * when drawing non-points -- although we do still need to be careful to
1165 * correctly set the attr overrides.
1168 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1170 bool drawing_points
= brw_is_drawing_points(brw
);
1172 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1173 int input_index
= wm_prog_data
->urb_setup
[attr
];
1175 if (input_index
< 0)
1179 bool point_sprite
= false;
1180 if (drawing_points
) {
1181 if (point
->PointSprite
&&
1182 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1183 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1184 point_sprite
= true;
1187 if (attr
== VARYING_SLOT_PNTC
)
1188 point_sprite
= true;
1191 *point_sprite_enables
|= (1 << input_index
);
1194 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1195 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1197 if (!point_sprite
) {
1198 genX(get_attr_override
)(&attribute
,
1199 &brw
->vue_map_geom_out
,
1200 *urb_entry_read_offset
, attr
,
1201 _mesa_vertex_program_two_side_enabled(ctx
),
1205 /* The hardware can only do the overrides on 16 overrides at a
1206 * time, and the other up to 16 have to be lined up so that the
1207 * input index = the output index. We'll need to do some
1208 * tweaking to make sure that's the case.
1210 if (input_index
< 16)
1211 attr_overrides
[input_index
] = attribute
;
1213 assert(attribute
.SourceAttribute
== input_index
);
1216 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1217 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1219 * "This field should be set to the minimum length required to read the
1220 * maximum source attribute. The maximum source attribute is indicated
1221 * by the maximum value of the enabled Attribute # Source Attribute if
1222 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1223 * enable is not set.
1224 * read_length = ceiling((max_source_attr + 1) / 2)
1226 * [errata] Corruption/Hang possible if length programmed larger than
1229 * Similar text exists for Ivy Bridge.
1231 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1235 /* ---------------------------------------------------------------------- */
1238 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1240 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1242 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1246 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1248 struct gl_context
*ctx
= &brw
->ctx
;
1251 struct intel_renderbuffer
*depth_irb
=
1252 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1255 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1258 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1259 const int b
= stencil
->_BackFace
;
1261 if (depth
->Test
&& depth_irb
) {
1262 ds
->DepthTestEnable
= true;
1263 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1264 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1267 if (brw
->stencil_enabled
) {
1268 ds
->StencilTestEnable
= true;
1269 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1270 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1272 ds
->StencilTestFunction
=
1273 intel_translate_compare_func(stencil
->Function
[0]);
1275 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1276 ds
->StencilPassDepthPassOp
=
1277 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1278 ds
->StencilPassDepthFailOp
=
1279 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1281 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1283 if (brw
->stencil_two_sided
) {
1284 ds
->DoubleSidedStencilEnable
= true;
1285 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1286 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1288 ds
->BackfaceStencilTestFunction
=
1289 intel_translate_compare_func(stencil
->Function
[b
]);
1290 ds
->BackfaceStencilFailOp
=
1291 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1292 ds
->BackfaceStencilPassDepthPassOp
=
1293 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1294 ds
->BackfaceStencilPassDepthFailOp
=
1295 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1298 #if GEN_GEN <= 5 || GEN_GEN >= 9
1299 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1300 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1307 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1310 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1311 set_depth_stencil_bits(brw
, &wmds
);
1315 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1316 set_depth_stencil_bits(brw
, &ds
);
1319 /* Now upload a pointer to the indirect state */
1321 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1322 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1323 ptr
.DEPTH_STENCIL_STATEChange
= true;
1326 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1327 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1333 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1335 .mesa
= _NEW_BUFFERS
|
1338 .brw
= BRW_NEW_BLORP
|
1339 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1341 BRW_NEW_STATE_BASE_ADDRESS
),
1343 .emit
= genX(upload_depth_stencil_state
),
1347 /* ---------------------------------------------------------------------- */
1352 genX(upload_clip_state
)(struct brw_context
*brw
)
1354 struct gl_context
*ctx
= &brw
->ctx
;
1356 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1357 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1358 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1359 clip
.GRFRegisterCount
=
1360 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1361 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1362 clip
.SingleProgramFlow
= true;
1363 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1364 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1366 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1367 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1368 clip
.DispatchGRFStartRegisterForURBData
= 1;
1369 clip
.VertexURBEntryReadOffset
= 0;
1371 /* BRW_NEW_URB_FENCE */
1372 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1373 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1375 if (brw
->urb
.nr_clip_entries
>= 10) {
1376 /* Half of the URB entries go to each thread, and it has to be an
1379 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1381 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1382 * only 2 threads can output VUEs at a time.
1384 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1386 assert(brw
->urb
.nr_clip_entries
>= 5);
1387 clip
.MaximumNumberofThreads
= 1 - 1;
1390 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1391 clip
.UserClipFlagsMustClipEnable
= true;
1392 clip
.GuardbandClipTestEnable
= true;
1394 clip
.ClipperViewportStatePointer
=
1395 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1397 clip
.ScreenSpaceViewportXMin
= -1;
1398 clip
.ScreenSpaceViewportXMax
= 1;
1399 clip
.ScreenSpaceViewportYMin
= -1;
1400 clip
.ScreenSpaceViewportYMax
= 1;
1402 clip
.ViewportXYClipTestEnable
= true;
1403 clip
.ViewportZClipTestEnable
= !(ctx
->Transform
.DepthClampNear
&&
1404 ctx
->Transform
.DepthClampFar
);
1406 /* _NEW_TRANSFORM */
1407 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1408 clip
.UserClipDistanceClipTestEnableBitmask
=
1409 ctx
->Transform
.ClipPlanesEnabled
;
1411 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1414 clip
.UserClipDistanceClipTestEnableBitmask
=
1415 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1418 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1419 clip
.APIMode
= APIMODE_D3D
;
1421 clip
.APIMode
= APIMODE_OGL
;
1423 clip
.GuardbandClipTestEnable
= true;
1425 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1428 clip
.NegativeWClipTestEnable
= true;
1433 const struct brw_tracked_state
genX(clip_state
) = {
1435 .mesa
= _NEW_TRANSFORM
|
1437 .brw
= BRW_NEW_BATCH
|
1439 BRW_NEW_CLIP_PROG_DATA
|
1440 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1441 BRW_NEW_PROGRAM_CACHE
|
1444 .emit
= genX(upload_clip_state
),
1450 genX(upload_clip_state
)(struct brw_context
*brw
)
1452 struct gl_context
*ctx
= &brw
->ctx
;
1455 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1457 /* BRW_NEW_FS_PROG_DATA */
1458 struct brw_wm_prog_data
*wm_prog_data
=
1459 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1461 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1462 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1464 if (wm_prog_data
->barycentric_interp_modes
&
1465 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1466 clip
.NonPerspectiveBarycentricEnable
= true;
1469 clip
.EarlyCullEnable
= true;
1473 clip
.FrontWinding
= brw
->polygon_front_bit
!= fb
->FlipY
;
1475 if (ctx
->Polygon
.CullFlag
) {
1476 switch (ctx
->Polygon
.CullFaceMode
) {
1478 clip
.CullMode
= CULLMODE_FRONT
;
1481 clip
.CullMode
= CULLMODE_BACK
;
1483 case GL_FRONT_AND_BACK
:
1484 clip
.CullMode
= CULLMODE_BOTH
;
1487 unreachable("Should not get here: invalid CullFlag");
1490 clip
.CullMode
= CULLMODE_NONE
;
1495 clip
.UserClipDistanceCullTestEnableBitmask
=
1496 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1498 clip
.ViewportZClipTestEnable
= !(ctx
->Transform
.DepthClampNear
&&
1499 ctx
->Transform
.DepthClampFar
);
1503 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1504 clip
.TriangleStripListProvokingVertexSelect
= 0;
1505 clip
.TriangleFanProvokingVertexSelect
= 1;
1506 clip
.LineStripListProvokingVertexSelect
= 0;
1508 clip
.TriangleStripListProvokingVertexSelect
= 2;
1509 clip
.TriangleFanProvokingVertexSelect
= 2;
1510 clip
.LineStripListProvokingVertexSelect
= 1;
1513 /* _NEW_TRANSFORM */
1514 clip
.UserClipDistanceClipTestEnableBitmask
=
1515 ctx
->Transform
.ClipPlanesEnabled
;
1518 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1521 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1522 clip
.APIMode
= APIMODE_D3D
;
1524 clip
.APIMode
= APIMODE_OGL
;
1526 clip
.GuardbandClipTestEnable
= true;
1528 /* BRW_NEW_VIEWPORT_COUNT */
1529 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1531 if (ctx
->RasterDiscard
) {
1532 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1534 perf_debug("Rasterizer discard is currently implemented via the "
1535 "clipper; having the GS not write primitives would "
1536 "likely be faster.\n");
1539 clip
.ClipMode
= CLIPMODE_NORMAL
;
1542 clip
.ClipEnable
= true;
1545 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1547 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1548 clip
.ViewportXYClipTestEnable
= true;
1550 clip
.MinimumPointWidth
= 0.125;
1551 clip
.MaximumPointWidth
= 255.875;
1552 clip
.MaximumVPIndex
= viewport_count
- 1;
1553 if (_mesa_geometric_layers(fb
) == 0)
1554 clip
.ForceZeroRTAIndexEnable
= true;
1558 static const struct brw_tracked_state
genX(clip_state
) = {
1560 .mesa
= _NEW_BUFFERS
|
1564 .brw
= BRW_NEW_BLORP
|
1566 BRW_NEW_FS_PROG_DATA
|
1567 BRW_NEW_GS_PROG_DATA
|
1568 BRW_NEW_VS_PROG_DATA
|
1569 BRW_NEW_META_IN_PROGRESS
|
1571 BRW_NEW_RASTERIZER_DISCARD
|
1572 BRW_NEW_TES_PROG_DATA
|
1573 BRW_NEW_VIEWPORT_COUNT
,
1575 .emit
= genX(upload_clip_state
),
1579 /* ---------------------------------------------------------------------- */
1582 genX(upload_sf
)(struct brw_context
*brw
)
1584 struct gl_context
*ctx
= &brw
->ctx
;
1589 bool flip_y
= ctx
->DrawBuffer
->FlipY
;
1590 UNUSED
const bool multisampled_fbo
=
1591 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1595 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1597 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1599 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1600 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1601 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1602 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1603 sf
.DispatchGRFStartRegisterForURBData
= 3;
1604 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1605 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1606 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1607 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1609 /* STATE_PREFETCH command description describes this state as being
1610 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1613 sf
.SetupViewportStateOffset
=
1614 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1616 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1618 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1619 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1621 sf
.MaximumNumberofThreads
=
1622 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1624 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1626 sf
.DestinationOriginHorizontalBias
= 0.5;
1627 sf
.DestinationOriginVerticalBias
= 0.5;
1629 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1630 sf
.StatisticsEnable
= true;
1632 sf
.ViewportTransformEnable
= true;
1636 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1641 sf
.FrontWinding
= brw
->polygon_front_bit
!= flip_y
;
1643 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1644 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1645 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1647 switch (ctx
->Polygon
.FrontMode
) {
1649 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1652 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1655 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1658 unreachable("not reached");
1661 switch (ctx
->Polygon
.BackMode
) {
1663 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1666 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1669 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1672 unreachable("not reached");
1675 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1676 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1678 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1679 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1680 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1683 sf
.ScissorRectangleEnable
= true;
1685 if (ctx
->Polygon
.CullFlag
) {
1686 switch (ctx
->Polygon
.CullFaceMode
) {
1688 sf
.CullMode
= CULLMODE_FRONT
;
1691 sf
.CullMode
= CULLMODE_BACK
;
1693 case GL_FRONT_AND_BACK
:
1694 sf
.CullMode
= CULLMODE_BOTH
;
1697 unreachable("not reached");
1700 sf
.CullMode
= CULLMODE_NONE
;
1704 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1711 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1713 if (devinfo
->is_cherryview
)
1714 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1716 sf
.LineWidth
= brw_get_line_width(brw
);
1718 sf
.LineWidth
= brw_get_line_width(brw
);
1721 if (ctx
->Line
.SmoothFlag
) {
1722 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1724 sf
.AntiAliasingEnable
= true;
1728 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1729 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1730 /* Clamp to the hardware limits */
1731 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1733 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1734 if (use_state_point_size(brw
))
1735 sf
.PointWidthSource
= State
;
1738 /* _NEW_POINT | _NEW_MULTISAMPLE */
1739 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1740 !ctx
->Point
.PointSprite
)
1741 sf
.SmoothPointEnable
= true;
1746 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1748 const bool multisampled_fbo
=
1749 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1750 if (multisampled_fbo
)
1751 sf
.SmoothPointEnable
= false;
1754 #if GEN_IS_G4X || GEN_GEN >= 5
1755 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1759 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1760 sf
.TriangleStripListProvokingVertexSelect
= 2;
1761 sf
.TriangleFanProvokingVertexSelect
= 2;
1762 sf
.LineStripListProvokingVertexSelect
= 1;
1764 sf
.TriangleFanProvokingVertexSelect
= 1;
1768 /* BRW_NEW_FS_PROG_DATA */
1769 const struct brw_wm_prog_data
*wm_prog_data
=
1770 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1772 sf
.AttributeSwizzleEnable
= true;
1773 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1776 * Window coordinates in an FBO are inverted, which means point
1777 * sprite origin must be inverted, too.
1779 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) == flip_y
) {
1780 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1782 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1785 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1786 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1788 uint32_t urb_entry_read_length
;
1789 uint32_t urb_entry_read_offset
;
1790 uint32_t point_sprite_enables
;
1791 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1792 &urb_entry_read_length
,
1793 &urb_entry_read_offset
);
1794 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1795 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1796 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1797 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1802 static const struct brw_tracked_state
genX(sf_state
) = {
1804 .mesa
= _NEW_LIGHT
|
1808 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1809 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1810 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1811 .brw
= BRW_NEW_BLORP
|
1812 BRW_NEW_VUE_MAP_GEOM_OUT
|
1813 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1814 BRW_NEW_PROGRAM_CACHE
|
1815 BRW_NEW_SF_PROG_DATA
|
1819 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1820 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1821 BRW_NEW_GS_PROG_DATA
|
1823 BRW_NEW_TES_PROG_DATA
1825 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1826 BRW_NEW_FRAGMENT_PROGRAM
1829 .emit
= genX(upload_sf
),
1832 /* ---------------------------------------------------------------------- */
1835 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1837 struct gl_context
*ctx
= &brw
->ctx
;
1838 /* BRW_NEW_FRAGMENT_PROGRAM */
1839 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1843 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1844 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1845 uint64_t outputs_written
= fp
->info
.outputs_written
;
1848 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1849 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1850 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1859 genX(upload_wm
)(struct brw_context
*brw
)
1861 struct gl_context
*ctx
= &brw
->ctx
;
1863 /* BRW_NEW_FS_PROG_DATA */
1864 const struct brw_wm_prog_data
*wm_prog_data
=
1865 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1867 UNUSED
bool writes_depth
=
1868 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1869 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1870 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1873 /* We can't fold this into gen6_upload_wm_push_constants(), because
1874 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1875 * (3DSTATE_CONSTANT_PS [DevSNB]):
1877 * "[DevSNB]: This packet must be followed by WM_STATE."
1879 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1880 if (wm_prog_data
->base
.nr_params
!= 0) {
1881 wmcp
.Buffer0Valid
= true;
1882 /* Pointer to the WM constant buffer. Covered by the set of
1883 * state flags from gen6_upload_wm_push_constants.
1885 wmcp
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
1886 wmcp
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1892 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1894 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1895 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1899 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1900 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1901 wm
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1905 /* On gen4, we only have one shader kernel */
1906 if (brw_wm_state_has_ksp(wm
, 0)) {
1907 assert(brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0) == 0);
1908 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1909 wm
.GRFRegisterCount0
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 0);
1910 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1911 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 0);
1914 /* On gen5, we have multiple shader kernels but only one GRF start
1915 * register for all kernels
1917 wm
.KernelStartPointer0
= stage_state
->prog_offset
+
1918 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0);
1919 wm
.KernelStartPointer1
= stage_state
->prog_offset
+
1920 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 1);
1921 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1922 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 2);
1924 wm
.GRFRegisterCount0
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 0);
1925 wm
.GRFRegisterCount1
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 1);
1926 wm
.GRFRegisterCount2
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 2);
1928 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1929 wm_prog_data
->base
.dispatch_grf_start_reg
;
1931 /* Dispatch GRF Start should be the same for all shaders on gen5 */
1932 if (brw_wm_state_has_ksp(wm
, 1)) {
1933 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1934 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 1));
1936 if (brw_wm_state_has_ksp(wm
, 2)) {
1937 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1938 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 2));
1941 /* On gen6, we have multiple shader kernels and we no longer specify a
1942 * register count for each one.
1944 wm
.KernelStartPointer0
= stage_state
->prog_offset
+
1945 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0);
1946 wm
.KernelStartPointer1
= stage_state
->prog_offset
+
1947 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 1);
1948 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1949 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 2);
1951 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1952 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 0);
1953 wm
.DispatchGRFStartRegisterForConstantSetupData1
=
1954 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 1);
1955 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1956 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 2);
1960 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1961 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1962 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1963 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1964 wm
.SetupURBEntryReadOffset
= 0;
1965 wm
.EarlyDepthTestEnable
= true;
1969 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1970 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1972 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1973 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1975 if (stage_state
->sampler_count
)
1976 wm
.SamplerStatePointer
=
1977 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1979 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1980 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1983 if (ctx
->Polygon
.OffsetFill
) {
1984 wm
.GlobalDepthOffsetEnable
= true;
1985 /* Something weird going on with legacy_global_depth_bias,
1986 * offset_constant, scaling and MRD. This value passes glean
1987 * but gives some odd results elsewere (eg. the
1988 * quad-offset-units test).
1990 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1992 /* This is the only value that passes glean:
1994 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1997 wm
.DepthCoefficientURBReadOffset
= 1;
2000 /* BRW_NEW_STATS_WM */
2001 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
2004 if (wm_prog_data
->base
.use_alt_mode
)
2005 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2007 wm
.SamplerCount
= GEN_GEN
== 5 ?
2008 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
2010 wm
.BindingTableEntryCount
=
2011 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
2012 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
2015 wm
.DualSourceBlendEnable
=
2016 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
2017 ctx
->Color
.Blend
[0]._UsesDualSrc
;
2018 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2019 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2021 /* From the SNB PRM, volume 2 part 1, page 281:
2022 * "If the PS kernel does not need the Position XY Offsets
2023 * to compute a Position XY value, then this field should be
2024 * programmed to POSOFFSET_NONE."
2026 * "SW Recommendation: If the PS kernel needs the Position Offsets
2027 * to compute a Position XY value, this field should match Position
2028 * ZW Interpolation Mode to ensure a consistent position.xyzw
2030 * We only require XY sample offsets. So, this recommendation doesn't
2031 * look useful at the moment. We might need this in future.
2033 if (wm_prog_data
->uses_pos_offset
)
2034 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
2036 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
2039 if (wm_prog_data
->base
.total_scratch
) {
2040 wm
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
2041 wm
.PerThreadScratchSpace
=
2042 ffs(stage_state
->per_thread_scratch
) - 11;
2045 wm
.PixelShaderComputedDepth
= writes_depth
;
2049 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
2052 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
2057 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2060 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
2062 if (multisampled_fbo
) {
2063 /* _NEW_MULTISAMPLE */
2064 if (ctx
->Multisample
.Enabled
)
2065 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
2067 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
2069 if (wm_prog_data
->persample_dispatch
)
2070 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
2072 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
2074 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
2075 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
2078 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2079 if (wm_prog_data
->uses_kill
||
2080 _mesa_is_alpha_test_enabled(ctx
) ||
2081 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
2082 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
2083 wm
.PixelShaderKillsPixel
= true;
2086 /* _NEW_BUFFERS | _NEW_COLOR */
2087 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
2088 wm
.PixelShaderKillsPixel
||
2089 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
2090 wm
.ThreadDispatchEnable
= true;
2094 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2095 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
2098 /* The "UAV access enable" bits are unnecessary on HSW because they only
2099 * seem to have an effect on the HW-assisted coherency mechanism which we
2100 * don't need, and the rasterization-related UAV_ONLY flag and the
2101 * DISPATCH_ENABLE bit can be set independently from it.
2102 * C.f. gen8_upload_ps_extra().
2104 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
2108 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
2109 wm_prog_data
->has_side_effects
)
2115 /* BRW_NEW_FS_PROG_DATA */
2116 if (wm_prog_data
->early_fragment_tests
)
2117 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2118 else if (wm_prog_data
->has_side_effects
)
2119 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2124 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
2125 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
2126 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
2129 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
2134 static const struct brw_tracked_state
genX(wm_state
) = {
2138 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
2141 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2142 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2143 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2144 .brw
= BRW_NEW_BLORP
|
2145 BRW_NEW_FS_PROG_DATA
|
2146 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2147 BRW_NEW_FRAGMENT_PROGRAM
|
2148 BRW_NEW_PROGRAM_CACHE
|
2149 BRW_NEW_SAMPLER_STATE_TABLE
|
2152 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2154 .emit
= genX(upload_wm
),
2157 /* ---------------------------------------------------------------------- */
2159 /* We restrict scratch buffers to the bottom 32 bits of the address space
2160 * by using rw_32_bo().
2162 * General State Base Address is a bit broken. If the address + size as
2163 * seen by STATE_BASE_ADDRESS overflows 48 bits, the GPU appears to treat
2164 * all accesses to the buffer as being out of bounds and returns zero.
2167 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2168 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2169 pkt.SamplerCount = \
2170 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2171 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to \
2172 * disable prefetching of binding tables in A0 and B0 steppings. \
2173 * TODO: Revisit this WA on C0 stepping. \
2175 pkt.BindingTableEntryCount = \
2178 stage_prog_data->binding_table.size_bytes / 4; \
2179 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2181 if (stage_prog_data->total_scratch) { \
2182 pkt.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0); \
2183 pkt.PerThreadScratchSpace = \
2184 ffs(stage_state->per_thread_scratch) - 11; \
2187 pkt.DispatchGRFStartRegisterForURBData = \
2188 stage_prog_data->dispatch_grf_start_reg; \
2189 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2190 pkt.prefix##URBEntryReadOffset = 0; \
2192 pkt.StatisticsEnable = true; \
2196 genX(upload_vs_state
)(struct brw_context
*brw
)
2198 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2199 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2200 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2202 /* BRW_NEW_VS_PROG_DATA */
2203 const struct brw_vue_prog_data
*vue_prog_data
=
2204 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2205 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2207 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2208 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2209 assert(GEN_GEN
< 11 ||
2210 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
2213 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2214 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2216 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2217 * command that causes the VS Function Enable to toggle. Pipeline
2218 * flush can be executed by sending a PIPE_CONTROL command with CS
2219 * stall bit set and a post sync operation.
2221 * We've already done such a flush at the start of state upload, so we
2222 * don't need to do another one here.
2224 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2225 if (stage_state
->push_const_size
!= 0) {
2226 cvs
.Buffer0Valid
= true;
2227 cvs
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
2228 cvs
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2233 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2234 gen7_emit_vs_workaround_flush(brw
);
2237 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2239 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2240 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2242 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2244 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2247 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2248 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2249 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2251 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2252 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2254 vs
.MaximumNumberofThreads
=
2255 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2257 vs
.StatisticsEnable
= false;
2258 vs
.SamplerStatePointer
=
2259 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2263 /* Force single program flow on Ironlake. We cannot reliably get
2264 * all applications working without it. See:
2265 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2267 * The most notable and reliably failing application is the Humus
2270 vs
.SingleProgramFlow
= true;
2271 vs
.SamplerCount
= 0; /* hardware requirement */
2275 vs
.SIMD8DispatchEnable
=
2276 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2278 vs
.UserClipDistanceCullTestEnableBitmask
=
2279 vue_prog_data
->cull_distance_mask
;
2284 /* Based on my reading of the simulator, the VS constants don't get
2285 * pulled into the VS FF unit until an appropriate pipeline flush
2286 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2287 * references to them into a little FIFO. The flushes are common,
2288 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2289 * the primitive to use the wrong constants. Then the FIFO
2290 * containing the constant setup gets added to again on the next
2291 * constants change, and eventually when a flush does happen the
2292 * unit is overwhelmed by constant changes and dies.
2294 * To avoid this, send a PIPE_CONTROL down the line that will
2295 * update the unit immediately loading the constants. The flush
2296 * type bits here were those set by the STATE_BASE_ADDRESS whose
2297 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2298 * bug reports that led to this workaround, and may be more than
2299 * what is strictly required to avoid the issue.
2301 brw_emit_pipe_control_flush(brw
,
2302 PIPE_CONTROL_DEPTH_STALL
|
2303 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2304 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2308 static const struct brw_tracked_state
genX(vs_state
) = {
2310 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2311 .brw
= BRW_NEW_BATCH
|
2314 BRW_NEW_VS_PROG_DATA
|
2315 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2316 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2317 BRW_NEW_PROGRAM_CACHE
|
2318 BRW_NEW_SAMPLER_STATE_TABLE
|
2322 .emit
= genX(upload_vs_state
),
2325 /* ---------------------------------------------------------------------- */
2328 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2330 struct gl_context
*ctx
= &brw
->ctx
;
2332 /* BRW_NEW_VIEWPORT_COUNT */
2333 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2335 struct GENX(CC_VIEWPORT
) ccv
;
2336 uint32_t cc_vp_offset
;
2338 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2341 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2342 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2343 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2344 if (ctx
->Transform
.DepthClampNear
&& ctx
->Transform
.DepthClampFar
) {
2345 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2346 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2347 } else if (ctx
->Transform
.DepthClampNear
) {
2348 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2349 ccv
.MaximumDepth
= 0.0;
2350 } else if (ctx
->Transform
.DepthClampFar
) {
2351 ccv
.MinimumDepth
= 0.0;
2352 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2354 ccv
.MinimumDepth
= 0.0;
2355 ccv
.MaximumDepth
= 1.0;
2357 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2358 cc_map
+= GENX(CC_VIEWPORT_length
);
2362 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2363 ptr
.CCViewportPointer
= cc_vp_offset
;
2366 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2367 vp
.CCViewportStateChange
= 1;
2368 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2371 brw
->cc
.vp_offset
= cc_vp_offset
;
2372 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2376 const struct brw_tracked_state
genX(cc_vp
) = {
2378 .mesa
= _NEW_TRANSFORM
|
2380 .brw
= BRW_NEW_BATCH
|
2382 BRW_NEW_VIEWPORT_COUNT
,
2384 .emit
= genX(upload_cc_viewport
)
2387 /* ---------------------------------------------------------------------- */
2390 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2391 bool flip_y
, unsigned fb_width
, unsigned fb_height
,
2392 struct GENX(SCISSOR_RECT
) *sc
)
2396 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2397 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2398 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2399 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2400 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2402 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2403 /* If the scissor was out of bounds and got clamped to 0 width/height
2404 * at the bounds, the subtraction of 1 from maximums could produce a
2405 * negative number and thus not clip anything. Instead, just provide
2406 * a min > max scissor inside the bounds, which produces the expected
2409 sc
->ScissorRectangleXMin
= 1;
2410 sc
->ScissorRectangleXMax
= 0;
2411 sc
->ScissorRectangleYMin
= 1;
2412 sc
->ScissorRectangleYMax
= 0;
2413 } else if (!flip_y
) {
2414 /* texmemory: Y=0=bottom */
2415 sc
->ScissorRectangleXMin
= bbox
[0];
2416 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2417 sc
->ScissorRectangleYMin
= bbox
[2];
2418 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2420 /* memory: Y=0=top */
2421 sc
->ScissorRectangleXMin
= bbox
[0];
2422 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2423 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2424 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2430 genX(upload_scissor_state
)(struct brw_context
*brw
)
2432 struct gl_context
*ctx
= &brw
->ctx
;
2433 const bool flip_y
= ctx
->DrawBuffer
->FlipY
;
2434 struct GENX(SCISSOR_RECT
) scissor
;
2435 uint32_t scissor_state_offset
;
2436 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2437 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2438 uint32_t *scissor_map
;
2440 /* BRW_NEW_VIEWPORT_COUNT */
2441 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2443 scissor_map
= brw_state_batch(
2444 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2445 32, &scissor_state_offset
);
2447 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2449 /* The scissor only needs to handle the intersection of drawable and
2450 * scissor rect. Clipping to the boundaries of static shared buffers
2451 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2453 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2454 * inclusive but max is exclusive.
2456 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2457 set_scissor_bits(ctx
, i
, flip_y
, fb_width
, fb_height
, &scissor
);
2458 GENX(SCISSOR_RECT_pack
)(
2459 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2462 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2463 ptr
.ScissorRectPointer
= scissor_state_offset
;
2467 static const struct brw_tracked_state
genX(scissor_state
) = {
2469 .mesa
= _NEW_BUFFERS
|
2472 .brw
= BRW_NEW_BATCH
|
2474 BRW_NEW_VIEWPORT_COUNT
,
2476 .emit
= genX(upload_scissor_state
),
2480 /* ---------------------------------------------------------------------- */
2483 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2484 float m00
, float m11
, float m30
, float m31
,
2485 float *xmin
, float *xmax
,
2486 float *ymin
, float *ymax
)
2488 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2489 * Strips and Fans documentation:
2491 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2492 * fixed-point "guardband" range supported by the rasterization hardware"
2496 * "In almost all circumstances, if an object’s vertices are actually
2497 * modified by this clamping (i.e., had X or Y coordinates outside of
2498 * the guardband extent the rendered object will not match the intended
2499 * result. Therefore software should take steps to ensure that this does
2500 * not happen - e.g., by clipping objects such that they do not exceed
2501 * these limits after the Drawing Rectangle is applied."
2503 * I believe the fundamental restriction is that the rasterizer (in
2504 * the SF/WM stages) have a limit on the number of pixels that can be
2505 * rasterized. We need to ensure any coordinates beyond the rasterizer
2506 * limit are handled by the clipper. So effectively that limit becomes
2507 * the clipper's guardband size.
2509 * It goes on to say:
2511 * "In addition, in order to be correctly rendered, objects must have a
2512 * screenspace bounding box not exceeding 8K in the X or Y direction.
2513 * This additional restriction must also be comprehended by software,
2514 * i.e., enforced by use of clipping."
2516 * This makes no sense. Gen7+ hardware supports 16K render targets,
2517 * and you definitely need to be able to draw polygons that fill the
2518 * surface. Our assumption is that the rasterizer was limited to 8K
2519 * on Sandybridge, which only supports 8K surfaces, and it was actually
2520 * increased to 16K on Ivybridge and later.
2522 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2524 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2526 /* Workaround: prevent gpu hangs on SandyBridge
2527 * by disabling guardband clipping for odd dimensions.
2529 if (GEN_GEN
== 6 && (fb_width
& 1 || fb_height
& 1)) {
2537 if (m00
!= 0 && m11
!= 0) {
2538 /* First, we compute the screen-space render area */
2539 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2540 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2541 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2542 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2544 /* We want the guardband to be centered on that */
2545 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2546 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2547 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2548 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2550 /* Now we need it in native device coordinates */
2551 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2552 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2553 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2554 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2556 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2557 * flipped upside-down. X should be fine though.
2559 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2560 *xmin
= ndc_gb_xmin
;
2561 *xmax
= ndc_gb_xmax
;
2562 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2563 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2565 /* The viewport scales to 0, so nothing will be rendered. */
2574 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2576 struct gl_context
*ctx
= &brw
->ctx
;
2577 float y_scale
, y_bias
;
2579 /* BRW_NEW_VIEWPORT_COUNT */
2580 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2583 const bool flip_y
= ctx
->DrawBuffer
->FlipY
;
2584 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2585 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2589 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2590 uint32_t sf_clip_vp_offset
;
2591 uint32_t *sf_clip_map
=
2592 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2593 64, &sf_clip_vp_offset
);
2595 struct GENX(SF_VIEWPORT
) sfv
;
2596 struct GENX(CLIP_VIEWPORT
) clv
;
2597 uint32_t sf_vp_offset
, clip_vp_offset
;
2599 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2601 uint32_t *clip_map
=
2602 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2603 32, &clip_vp_offset
);
2609 y_bias
= (float)fb_height
;
2615 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2616 /* _NEW_VIEWPORT: Guardband Clipping */
2617 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2618 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2620 sfv
.ViewportMatrixElementm00
= scale
[0];
2621 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2622 sfv
.ViewportMatrixElementm22
= scale
[2],
2623 sfv
.ViewportMatrixElementm30
= translate
[0],
2624 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2625 sfv
.ViewportMatrixElementm32
= translate
[2],
2626 brw_calculate_guardband_size(fb_width
, fb_height
,
2627 sfv
.ViewportMatrixElementm00
,
2628 sfv
.ViewportMatrixElementm11
,
2629 sfv
.ViewportMatrixElementm30
,
2630 sfv
.ViewportMatrixElementm31
,
2631 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2634 clv
.XMinClipGuardband
= gb_xmin
;
2635 clv
.XMaxClipGuardband
= gb_xmax
;
2636 clv
.YMinClipGuardband
= gb_ymin
;
2637 clv
.YMaxClipGuardband
= gb_ymax
;
2640 set_scissor_bits(ctx
, i
, flip_y
, fb_width
, fb_height
,
2641 &sfv
.ScissorRectangle
);
2643 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2644 * The hardware will take the intersection of the drawing rectangle,
2645 * scissor rectangle, and the viewport extents. However, emitting
2646 * 3DSTATE_DRAWING_RECTANGLE is expensive since it requires a full
2647 * pipeline stall so we're better off just being a little more clever
2648 * with our viewport so we can emit it once at context creation time.
2650 const float viewport_Xmin
= MAX2(ctx
->ViewportArray
[i
].X
, 0);
2651 const float viewport_Ymin
= MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2652 const float viewport_Xmax
=
2653 MIN2(ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
, fb_width
);
2654 const float viewport_Ymax
=
2655 MIN2(ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
, fb_height
);
2658 sfv
.XMinViewPort
= viewport_Xmin
;
2659 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2660 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2661 sfv
.YMaxViewPort
= fb_height
- viewport_Ymin
- 1;
2663 sfv
.XMinViewPort
= viewport_Xmin
;
2664 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2665 sfv
.YMinViewPort
= viewport_Ymin
;
2666 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2671 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2672 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2674 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2675 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2676 sf_map
+= GENX(SF_VIEWPORT_length
);
2677 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2682 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2683 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2686 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2687 vp
.SFViewportStateChange
= 1;
2688 vp
.CLIPViewportStateChange
= 1;
2689 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2690 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2693 brw
->sf
.vp_offset
= sf_vp_offset
;
2694 brw
->clip
.vp_offset
= clip_vp_offset
;
2695 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2699 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2701 .mesa
= _NEW_BUFFERS
|
2703 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2704 .brw
= BRW_NEW_BATCH
|
2706 BRW_NEW_VIEWPORT_COUNT
,
2708 .emit
= genX(upload_sf_clip_viewport
),
2711 /* ---------------------------------------------------------------------- */
2714 genX(upload_gs_state
)(struct brw_context
*brw
)
2716 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2717 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2718 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2719 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2720 /* BRW_NEW_GEOMETRY_PROGRAM */
2721 bool active
= GEN_GEN
>= 6 && gs_prog
;
2723 /* BRW_NEW_GS_PROG_DATA */
2724 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2725 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2726 brw_vue_prog_data(stage_prog_data
);
2728 const struct brw_gs_prog_data
*gs_prog_data
=
2729 brw_gs_prog_data(stage_prog_data
);
2733 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2734 if (active
&& stage_state
->push_const_size
!= 0) {
2735 cgs
.Buffer0Valid
= true;
2736 cgs
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
2737 cgs
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2742 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2744 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2745 * Geometry > Geometry Shader > State:
2747 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2748 * whole fixed function pipeline when the GS enable changes value in
2751 * The hardware architects have clarified that in this context "flush the
2752 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2755 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2756 gen7_emit_cs_stall_flush(brw
);
2760 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2762 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2763 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2768 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2771 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2772 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2773 gs
.ControlDataHeaderSize
=
2774 gs_prog_data
->control_data_header_size_hwords
;
2776 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2777 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2779 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2781 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2784 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2785 * Ivy Bridge and Haswell.
2787 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2788 * strip to be delivered to the geometry shader in an order that does
2789 * not strictly follow the OpenGL spec, but preserves triangle
2790 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2791 * the geometry shader sees triangles:
2793 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2795 * (Clearing the bit is even worse, because it fails to preserve
2798 * Triangle strips with adjacency always ordered in a way that preserves
2799 * triangle orientation but does not strictly follow the OpenGL spec,
2800 * regardless of the setting of this bit.
2802 * On Haswell, both triangle strips and triangle strips with adjacency
2803 * are always ordered in a way that preserves triangle orientation.
2804 * Setting this bit causes the ordering to strictly follow the OpenGL
2807 * So in either case we want to set the bit. Unfortunately on Ivy
2808 * Bridge this will get the order close to correct but not perfect.
2810 gs
.ReorderMode
= TRAILING
;
2811 gs
.MaximumNumberofThreads
=
2812 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2813 : (devinfo
->max_gs_threads
- 1);
2816 gs
.SOStatisticsEnable
= true;
2817 if (gs_prog
->info
.has_transform_feedback_varyings
)
2818 gs
.SVBIPayloadEnable
= _mesa_is_xfb_active_and_unpaused(ctx
);
2820 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2821 * was previously done for gen6.
2823 * TODO: test with both disabled to see if the HW is behaving
2824 * as expected, like in gen7.
2826 gs
.SingleProgramFlow
= true;
2827 gs
.VectorMaskEnable
= true;
2831 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2833 if (gs_prog_data
->static_vertex_count
!= -1) {
2834 gs
.StaticOutput
= true;
2835 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2837 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2839 gs
.UserClipDistanceCullTestEnableBitmask
=
2840 vue_prog_data
->cull_distance_mask
;
2842 const int urb_entry_write_offset
= 1;
2843 const uint32_t urb_entry_output_length
=
2844 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2845 urb_entry_write_offset
;
2847 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2848 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2854 if (!active
&& brw
->ff_gs
.prog_active
) {
2855 /* In gen6, transform feedback for the VS stage is done with an
2856 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2859 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2860 gs
.SingleProgramFlow
= true;
2861 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2862 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2865 gs
.GRFRegisterCount
=
2866 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2867 /* BRW_NEW_URB_FENCE */
2868 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2869 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2870 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2871 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2874 gs
.VectorMaskEnable
= true;
2875 gs
.SVBIPayloadEnable
= true;
2876 gs
.SVBIPostIncrementEnable
= true;
2877 gs
.SVBIPostIncrementValue
=
2878 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2879 gs
.SOStatisticsEnable
= true;
2880 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2884 if (!active
&& !brw
->ff_gs
.prog_active
) {
2886 gs
.DispatchGRFStartRegisterForURBData
= 1;
2888 gs
.IncludeVertexHandles
= true;
2894 gs
.StatisticsEnable
= true;
2896 #if GEN_GEN == 5 || GEN_GEN == 6
2897 gs
.RenderingEnabled
= true;
2900 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2905 brw
->gs
.enabled
= active
;
2909 static const struct brw_tracked_state
genX(gs_state
) = {
2911 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2912 .brw
= BRW_NEW_BATCH
|
2914 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2915 BRW_NEW_PROGRAM_CACHE
|
2917 BRW_NEW_VIEWPORT_COUNT
2919 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2920 BRW_NEW_GEOMETRY_PROGRAM
|
2921 BRW_NEW_GS_PROG_DATA
2923 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2925 .emit
= genX(upload_gs_state
),
2928 /* ---------------------------------------------------------------------- */
2930 UNUSED
static GLenum
2931 fix_dual_blend_alpha_to_one(GLenum function
)
2937 case GL_ONE_MINUS_SRC1_ALPHA
:
2944 #define blend_factor(x) brw_translate_blend_factor(x)
2945 #define blend_eqn(x) brw_translate_blend_equation(x)
2948 * Modify blend function to force destination alpha to 1.0
2950 * If \c function specifies a blend function that uses destination alpha,
2951 * replace it with a function that hard-wires destination alpha to 1.0. This
2952 * is used when rendering to xRGB targets.
2955 brw_fix_xRGB_alpha(GLenum function
)
2961 case GL_ONE_MINUS_DST_ALPHA
:
2962 case GL_SRC_ALPHA_SATURATE
:
2970 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2972 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2976 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2979 struct gl_context
*ctx
= &brw
->ctx
;
2982 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2984 bool independent_alpha_blend
= false;
2986 /* Used for implementing the following bit of GL_EXT_texture_integer:
2987 * "Per-fragment operations that require floating-point color
2988 * components, including multisample alpha operations, alpha test,
2989 * blending, and dithering, have no effect when the corresponding
2990 * colors are written to an integer color buffer."
2992 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2994 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2995 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2998 if (ctx
->Color
.ColorLogicOpEnabled
) {
2999 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
3000 : GL_UNSIGNED_NORMALIZED
;
3001 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
3002 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
3003 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
3005 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
3006 _mesa_enum_to_string(rb_type
));
3007 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
3008 entry
->LogicOpEnable
= true;
3009 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
3011 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
3012 && (GEN_GEN
<= 5 || !integer
)) {
3013 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
3014 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
3015 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
3016 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
3017 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
3018 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
3020 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
3021 srcRGB
= dstRGB
= GL_ONE
;
3023 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
3024 srcA
= dstA
= GL_ONE
;
3026 /* Due to hardware limitations, the destination may have information
3027 * in an alpha channel even when the format specifies no alpha
3028 * channel. In order to avoid getting any incorrect blending due to
3029 * that alpha channel, coerce the blend factors to values that will
3030 * not read the alpha channel, but will instead use the correct
3031 * implicit value for alpha.
3033 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
3034 GL_TEXTURE_ALPHA_TYPE
)) {
3035 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
3036 srcA
= brw_fix_xRGB_alpha(srcA
);
3037 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
3038 dstA
= brw_fix_xRGB_alpha(dstA
);
3041 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
3042 * "If Dual Source Blending is enabled, this bit must be disabled."
3044 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
3045 * and leave it enabled anyway.
3047 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
3048 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
3049 srcA
= fix_dual_blend_alpha_to_one(srcA
);
3050 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
3051 dstA
= fix_dual_blend_alpha_to_one(dstA
);
3054 entry
->ColorBufferBlendEnable
= true;
3055 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
3056 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
3057 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
3058 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
3059 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
3060 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
3062 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
3063 independent_alpha_blend
= true;
3066 return independent_alpha_blend
;
3071 genX(upload_blend_state
)(struct brw_context
*brw
)
3073 struct gl_context
*ctx
= &brw
->ctx
;
3076 /* We need at least one BLEND_STATE written, because we might do
3077 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
3078 * for computed depth or alpha test), which will do an FB write
3079 * with render target 0, which will reference BLEND_STATE[0] for
3080 * alpha test enable.
3082 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
3083 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
3084 nr_draw_buffers
= 1;
3086 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
3088 size
+= GENX(BLEND_STATE_length
) * 4;
3091 uint32_t *blend_map
;
3092 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
3095 struct GENX(BLEND_STATE
) blend
= { 0 };
3098 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3099 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3102 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
3103 * "If drawbuffer zero is not NONE and the buffer it references has an
3104 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
3105 * operations are skipped."
3107 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
3108 /* _NEW_MULTISAMPLE */
3109 if (_mesa_is_multisample_enabled(ctx
)) {
3110 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
3111 blend
.AlphaToCoverageEnable
= true;
3112 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
3114 if (ctx
->Multisample
.SampleAlphaToOne
)
3115 blend
.AlphaToOneEnable
= true;
3119 if (ctx
->Color
.AlphaEnabled
) {
3120 blend
.AlphaTestEnable
= true;
3121 blend
.AlphaTestFunction
=
3122 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3125 if (ctx
->Color
.DitherFlag
) {
3126 blend
.ColorDitherEnable
= true;
3131 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3132 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3136 blend
.IndependentAlphaBlendEnable
=
3137 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
3138 blend
.IndependentAlphaBlendEnable
;
3140 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
3141 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
3143 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
3144 * clamping in the fragment shader. For its clamping of
3145 * blending, the spec says:
3147 * "RESOLVED: For fixed-point color buffers, the inputs and
3148 * the result of the blending equation are clamped. For
3149 * floating-point color buffers, no clamping occurs."
3151 * So, generally, we want clamping to the render target's range.
3152 * And, good news, the hardware tables for both pre- and
3153 * post-blend color clamping are either ignored, or any are
3154 * allowed, or clamping is required but RT range clamping is a
3157 entry
.PreBlendColorClampEnable
= true;
3158 entry
.PostBlendColorClampEnable
= true;
3159 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
3161 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
3162 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
3163 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
3164 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
3167 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
3169 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3175 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3179 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3180 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3181 ptr
.BLEND_STATEChange
= true;
3184 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3185 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3187 ptr
.BlendStatePointerValid
= true;
3193 static const struct brw_tracked_state
genX(blend_state
) = {
3195 .mesa
= _NEW_BUFFERS
|
3198 .brw
= BRW_NEW_BATCH
|
3200 BRW_NEW_STATE_BASE_ADDRESS
,
3202 .emit
= genX(upload_blend_state
),
3206 /* ---------------------------------------------------------------------- */
3209 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3210 [MESA_SHADER_VERTEX
] = 21,
3211 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3212 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3213 [MESA_SHADER_GEOMETRY
] = 22,
3214 [MESA_SHADER_FRAGMENT
] = 23,
3215 [MESA_SHADER_COMPUTE
] = 0,
3219 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3221 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3222 struct gl_context
*ctx
= &brw
->ctx
;
3224 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3226 struct brw_stage_state
*stage_states
[] = {
3234 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3235 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3236 gen7_emit_vs_workaround_flush(brw
);
3238 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3239 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3240 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3242 if (!stage_state
->push_constants_dirty
)
3245 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3246 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3247 if (stage_state
->prog_data
) {
3248 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3249 /* The Skylake PRM contains the following restriction:
3251 * "The driver must ensure The following case does not occur
3252 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3253 * buffer 3 read length equal to zero committed followed by a
3254 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3257 * To avoid this, we program the buffers in the highest slots.
3258 * This way, slot 0 is only used if slot 3 is also used.
3262 for (int i
= 3; i
>= 0; i
--) {
3263 const struct brw_ubo_range
*range
=
3264 &stage_state
->prog_data
->ubo_ranges
[i
];
3266 if (range
->length
== 0)
3269 const struct gl_uniform_block
*block
=
3270 prog
->sh
.UniformBlocks
[range
->block
];
3271 const struct gl_buffer_binding
*binding
=
3272 &ctx
->UniformBufferBindings
[block
->Binding
];
3274 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3275 static unsigned msg_id
= 0;
3276 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3277 MESA_DEBUG_TYPE_UNDEFINED
,
3278 MESA_DEBUG_SEVERITY_HIGH
,
3279 "UBO %d unbound, %s shader uniform data "
3280 "will be undefined.",
3282 _mesa_shader_stage_to_string(stage
));
3286 assert(binding
->Offset
% 32 == 0);
3288 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3289 intel_buffer_object(binding
->BufferObject
),
3290 binding
->Offset
, range
->length
* 32, false);
3292 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3293 pkt
.ConstantBody
.Buffer
[n
] =
3294 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3298 if (stage_state
->push_const_size
> 0) {
3300 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3301 pkt
.ConstantBody
.Buffer
[n
] =
3302 ro_bo(stage_state
->push_const_bo
,
3303 stage_state
->push_const_offset
);
3306 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3307 pkt
.ConstantBody
.Buffer
[0].offset
=
3308 stage_state
->push_const_offset
| mocs
;
3313 stage_state
->push_constants_dirty
= false;
3314 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3318 const struct brw_tracked_state
genX(push_constant_packets
) = {
3321 .brw
= BRW_NEW_DRAW_CALL
,
3323 .emit
= genX(upload_push_constant_packets
),
3329 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3331 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3333 /* BRW_NEW_VERTEX_PROGRAM */
3334 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3335 /* BRW_NEW_VS_PROG_DATA */
3336 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3338 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3341 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3343 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3345 .brw
= BRW_NEW_BATCH
|
3347 BRW_NEW_VERTEX_PROGRAM
|
3348 BRW_NEW_VS_PROG_DATA
,
3350 .emit
= genX(upload_vs_push_constants
),
3354 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3356 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3358 /* BRW_NEW_GEOMETRY_PROGRAM */
3359 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3361 /* BRW_NEW_GS_PROG_DATA */
3362 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3364 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3367 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3369 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3371 .brw
= BRW_NEW_BATCH
|
3373 BRW_NEW_GEOMETRY_PROGRAM
|
3374 BRW_NEW_GS_PROG_DATA
,
3376 .emit
= genX(upload_gs_push_constants
),
3380 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3382 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3383 /* BRW_NEW_FRAGMENT_PROGRAM */
3384 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3385 /* BRW_NEW_FS_PROG_DATA */
3386 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3388 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3391 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3393 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3394 .brw
= BRW_NEW_BATCH
|
3396 BRW_NEW_FRAGMENT_PROGRAM
|
3397 BRW_NEW_FS_PROG_DATA
,
3399 .emit
= genX(upload_wm_push_constants
),
3403 /* ---------------------------------------------------------------------- */
3407 genX(determine_sample_mask
)(struct brw_context
*brw
)
3409 struct gl_context
*ctx
= &brw
->ctx
;
3410 float coverage
= 1.0f
;
3411 float coverage_invert
= false;
3412 unsigned sample_mask
= ~0u;
3414 /* BRW_NEW_NUM_SAMPLES */
3415 unsigned num_samples
= brw
->num_samples
;
3417 if (_mesa_is_multisample_enabled(ctx
)) {
3418 if (ctx
->Multisample
.SampleCoverage
) {
3419 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3420 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3422 if (ctx
->Multisample
.SampleMask
) {
3423 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3427 if (num_samples
> 1) {
3428 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3429 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3430 if (coverage_invert
)
3431 coverage_bits
^= (1 << num_samples
) - 1;
3432 return coverage_bits
& sample_mask
;
3439 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3440 unsigned num_samples
)
3442 unsigned log2_samples
= ffs(num_samples
) - 1;
3444 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3445 multi
.PixelLocation
= CENTER
;
3446 multi
.NumberofMultisamples
= log2_samples
;
3448 GEN_SAMPLE_POS_4X(multi
.Sample
);
3450 switch (num_samples
) {
3452 GEN_SAMPLE_POS_1X(multi
.Sample
);
3455 GEN_SAMPLE_POS_2X(multi
.Sample
);
3458 GEN_SAMPLE_POS_4X(multi
.Sample
);
3461 GEN_SAMPLE_POS_8X(multi
.Sample
);
3471 genX(upload_multisample_state
)(struct brw_context
*brw
)
3473 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3475 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3477 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3478 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3482 static const struct brw_tracked_state
genX(multisample_state
) = {
3484 .mesa
= _NEW_MULTISAMPLE
|
3485 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3486 .brw
= BRW_NEW_BLORP
|
3488 BRW_NEW_NUM_SAMPLES
,
3490 .emit
= genX(upload_multisample_state
)
3494 /* ---------------------------------------------------------------------- */
3497 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3499 struct gl_context
*ctx
= &brw
->ctx
;
3501 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3503 cc
.IndependentAlphaBlendEnable
=
3504 set_blend_entry_bits(brw
, &cc
, 0, false);
3505 set_depth_stencil_bits(brw
, &cc
);
3507 if (ctx
->Color
.AlphaEnabled
&&
3508 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3509 cc
.AlphaTestEnable
= true;
3510 cc
.AlphaTestFunction
=
3511 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3514 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3516 cc
.StatisticsEnable
= brw
->stats_wm
;
3518 cc
.CCViewportStatePointer
=
3519 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3522 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3523 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3524 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3525 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3529 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3530 cc
.BackfaceStencilReferenceValue
=
3531 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3537 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3538 ctx
->Color
.AlphaRef
);
3542 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3543 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3545 ptr
.ColorCalcStatePointerValid
= true;
3549 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3553 static const struct brw_tracked_state
genX(color_calc_state
) = {
3555 .mesa
= _NEW_COLOR
|
3557 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3560 .brw
= BRW_NEW_BATCH
|
3562 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3564 : BRW_NEW_CC_STATE
|
3565 BRW_NEW_STATE_BASE_ADDRESS
),
3567 .emit
= genX(upload_color_calc_state
),
3571 /* ---------------------------------------------------------------------- */
3575 genX(upload_sbe
)(struct brw_context
*brw
)
3577 struct gl_context
*ctx
= &brw
->ctx
;
3578 /* BRW_NEW_FRAGMENT_PROGRAM */
3579 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3580 /* BRW_NEW_FS_PROG_DATA */
3581 const struct brw_wm_prog_data
*wm_prog_data
=
3582 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3584 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3586 #define attr_overrides sbe.Attribute
3588 uint32_t urb_entry_read_length
;
3589 uint32_t urb_entry_read_offset
;
3590 uint32_t point_sprite_enables
;
3592 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3593 sbe
.AttributeSwizzleEnable
= true;
3594 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3597 bool flip_y
= ctx
->DrawBuffer
->FlipY
;
3601 * Window coordinates in an FBO are inverted, which means point
3602 * sprite origin must be inverted.
3604 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) == flip_y
)
3605 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3607 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3609 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3610 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3611 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3612 * BRW_NEW_VUE_MAP_GEOM_OUT
3614 genX(calculate_attr_overrides
)(brw
,
3616 &point_sprite_enables
,
3617 &urb_entry_read_length
,
3618 &urb_entry_read_offset
);
3620 /* Typically, the URB entry read length and offset should be programmed
3621 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3622 * stage which produces geometry. However, we don't know the proper
3623 * value until we call calculate_attr_overrides().
3625 * To fit with our existing code, we override the inherited values and
3626 * specify it here directly, as we did on previous generations.
3628 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3629 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3630 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3631 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3634 sbe
.ForceVertexURBEntryReadLength
= true;
3635 sbe
.ForceVertexURBEntryReadOffset
= true;
3639 /* prepare the active component dwords */
3640 for (int i
= 0; i
< 32; i
++)
3641 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3646 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3647 for (int i
= 0; i
< 16; i
++)
3648 sbes
.Attribute
[i
] = attr_overrides
[i
];
3652 #undef attr_overrides
3655 static const struct brw_tracked_state
genX(sbe_state
) = {
3657 .mesa
= _NEW_BUFFERS
|
3662 .brw
= BRW_NEW_BLORP
|
3664 BRW_NEW_FRAGMENT_PROGRAM
|
3665 BRW_NEW_FS_PROG_DATA
|
3666 BRW_NEW_GS_PROG_DATA
|
3667 BRW_NEW_TES_PROG_DATA
|
3668 BRW_NEW_VUE_MAP_GEOM_OUT
|
3669 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3672 .emit
= genX(upload_sbe
),
3676 /* ---------------------------------------------------------------------- */
3680 * Outputs the 3DSTATE_SO_DECL_LIST command.
3682 * The data output is a series of 64-bit entries containing a SO_DECL per
3683 * stream. We only have one stream of rendering coming out of the GS unit, so
3684 * we only emit stream 0 (low 16 bits) SO_DECLs.
3687 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3688 const struct brw_vue_map
*vue_map
)
3690 struct gl_context
*ctx
= &brw
->ctx
;
3691 /* BRW_NEW_TRANSFORM_FEEDBACK */
3692 struct gl_transform_feedback_object
*xfb_obj
=
3693 ctx
->TransformFeedback
.CurrentObject
;
3694 const struct gl_transform_feedback_info
*linked_xfb_info
=
3695 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3696 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3697 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3698 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3699 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3701 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3703 memset(so_decl
, 0, sizeof(so_decl
));
3705 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3706 * command feels strange -- each dword pair contains a SO_DECL per stream.
3708 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3709 const struct gl_transform_feedback_output
*output
=
3710 &linked_xfb_info
->Outputs
[i
];
3711 const int buffer
= output
->OutputBuffer
;
3712 const int varying
= output
->OutputRegister
;
3713 const unsigned stream_id
= output
->StreamId
;
3714 assert(stream_id
< MAX_VERTEX_STREAMS
);
3716 buffer_mask
[stream_id
] |= 1 << buffer
;
3718 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3720 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3721 * array. Instead, it simply increments DstOffset for the following
3722 * input by the number of components that should be skipped.
3724 * Our hardware is unusual in that it requires us to program SO_DECLs
3725 * for fake "hole" components, rather than simply taking the offset
3726 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3727 * program as many size = 4 holes as we can, then a final hole to
3728 * accommodate the final 1, 2, or 3 remaining.
3730 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3732 while (skip_components
> 0) {
3733 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3735 .OutputBufferSlot
= output
->OutputBuffer
,
3736 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3738 skip_components
-= 4;
3741 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3743 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3744 .OutputBufferSlot
= output
->OutputBuffer
,
3745 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3747 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3750 if (decls
[stream_id
] > max_decls
)
3751 max_decls
= decls
[stream_id
];
3755 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3756 .StreamtoBufferSelects0
= buffer_mask
[0],
3757 .StreamtoBufferSelects1
= buffer_mask
[1],
3758 .StreamtoBufferSelects2
= buffer_mask
[2],
3759 .StreamtoBufferSelects3
= buffer_mask
[3],
3760 .NumEntries0
= decls
[0],
3761 .NumEntries1
= decls
[1],
3762 .NumEntries2
= decls
[2],
3763 .NumEntries3
= decls
[3]);
3765 for (int i
= 0; i
< max_decls
; i
++) {
3766 GENX(SO_DECL_ENTRY_pack
)(
3767 brw
, dw
+ 2 + i
* 2,
3768 &(struct GENX(SO_DECL_ENTRY
)) {
3769 .Stream0Decl
= so_decl
[0][i
],
3770 .Stream1Decl
= so_decl
[1][i
],
3771 .Stream2Decl
= so_decl
[2][i
],
3772 .Stream3Decl
= so_decl
[3][i
],
3778 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3780 struct gl_context
*ctx
= &brw
->ctx
;
3781 /* BRW_NEW_TRANSFORM_FEEDBACK */
3782 struct gl_transform_feedback_object
*xfb_obj
=
3783 ctx
->TransformFeedback
.CurrentObject
;
3785 const struct gl_transform_feedback_info
*linked_xfb_info
=
3786 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3788 struct brw_transform_feedback_object
*brw_obj
=
3789 (struct brw_transform_feedback_object
*) xfb_obj
;
3790 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3793 /* Set up the up to 4 output buffers. These are the ranges defined in the
3794 * gl_transform_feedback_object.
3796 for (int i
= 0; i
< 4; i
++) {
3797 struct intel_buffer_object
*bufferobj
=
3798 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3799 uint32_t start
= xfb_obj
->Offset
[i
];
3800 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3801 uint32_t const size
= end
- start
;
3803 if (!bufferobj
|| !size
) {
3804 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3805 sob
.SOBufferIndex
= i
;
3810 assert(start
% 4 == 0);
3812 intel_bufferobj_buffer(brw
, bufferobj
, start
, size
, true);
3813 assert(end
<= bo
->size
);
3815 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3816 sob
.SOBufferIndex
= i
;
3818 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3820 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3821 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3823 sob
.SOBufferEnable
= true;
3824 sob
.StreamOffsetWriteEnable
= true;
3825 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3826 sob
.SOBufferMOCS
= mocs_wb
;
3828 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3829 sob
.StreamOutputBufferOffsetAddress
=
3830 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3832 if (brw_obj
->zero_offsets
) {
3833 /* Zero out the offset and write that to offset_bo */
3834 sob
.StreamOffset
= 0;
3836 /* Use offset_bo as the "Stream Offset." */
3837 sob
.StreamOffset
= 0xFFFFFFFF;
3844 brw_obj
->zero_offsets
= false;
3849 query_active(struct gl_query_object
*q
)
3851 return q
&& q
->Active
;
3855 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3856 const struct brw_vue_map
*vue_map
)
3858 struct gl_context
*ctx
= &brw
->ctx
;
3859 /* BRW_NEW_TRANSFORM_FEEDBACK */
3860 struct gl_transform_feedback_object
*xfb_obj
=
3861 ctx
->TransformFeedback
.CurrentObject
;
3863 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3865 int urb_entry_read_offset
= 0;
3866 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3867 urb_entry_read_offset
;
3869 sos
.SOFunctionEnable
= true;
3870 sos
.SOStatisticsEnable
= true;
3872 /* BRW_NEW_RASTERIZER_DISCARD */
3873 if (ctx
->RasterDiscard
) {
3874 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3875 sos
.RenderingDisable
= true;
3877 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3878 "query active relies on the clipper.\n");
3883 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3884 sos
.ReorderMode
= TRAILING
;
3887 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3888 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3889 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3890 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3892 const struct gl_transform_feedback_info
*linked_xfb_info
=
3893 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3894 /* Set buffer pitches; 0 means unbound. */
3895 if (xfb_obj
->Buffers
[0])
3896 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3897 if (xfb_obj
->Buffers
[1])
3898 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3899 if (xfb_obj
->Buffers
[2])
3900 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3901 if (xfb_obj
->Buffers
[3])
3902 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3905 /* We always read the whole vertex. This could be reduced at some
3906 * point by reading less and offsetting the register index in the
3909 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3910 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3911 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3912 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3913 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3914 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3915 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3916 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3922 genX(upload_sol
)(struct brw_context
*brw
)
3924 struct gl_context
*ctx
= &brw
->ctx
;
3925 /* BRW_NEW_TRANSFORM_FEEDBACK */
3926 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3929 genX(upload_3dstate_so_buffers
)(brw
);
3931 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3932 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3935 /* Finally, set up the SOL stage. This command must always follow updates to
3936 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3937 * MMIO register updates (current performed by the kernel at each batch
3940 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3943 static const struct brw_tracked_state
genX(sol_state
) = {
3946 .brw
= BRW_NEW_BATCH
|
3948 BRW_NEW_RASTERIZER_DISCARD
|
3949 BRW_NEW_VUE_MAP_GEOM_OUT
|
3950 BRW_NEW_TRANSFORM_FEEDBACK
,
3952 .emit
= genX(upload_sol
),
3956 /* ---------------------------------------------------------------------- */
3960 genX(upload_ps
)(struct brw_context
*brw
)
3962 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3963 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3965 /* BRW_NEW_FS_PROG_DATA */
3966 const struct brw_wm_prog_data
*prog_data
=
3967 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3968 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3973 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3974 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3975 * incorrect for subspans where some of the pixels are unlit. We believe
3976 * the bit just didn't take effect in previous generations.
3978 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3981 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3983 /* BRW_NEW_FS_PROG_DATA */
3984 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to disable
3985 * prefetching of binding tables in A0 and B0 steppings.
3986 * TODO: Revisit this workaround on C0 stepping.
3988 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ?
3990 prog_data
->base
.binding_table
.size_bytes
/ 4;
3992 if (prog_data
->base
.use_alt_mode
)
3993 ps
.FloatingPointMode
= Alternate
;
3995 /* Haswell requires the sample mask to be set in this packet as well as
3996 * in 3DSTATE_SAMPLE_MASK; the values should match.
3999 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
4001 ps
.SampleMask
= genX(determine_sample_mask(brw
));
4004 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
4005 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
4006 * k, it implies 2(k+1) threads. It implicitly scales for different GT
4007 * levels (which have some # of PSDs).
4009 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
4012 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
4014 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
4016 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
4019 if (prog_data
->base
.nr_params
> 0 ||
4020 prog_data
->base
.ubo_ranges
[0].length
> 0)
4021 ps
.PushConstantEnable
= true;
4024 /* From the IVB PRM, volume 2 part 1, page 287:
4025 * "This bit is inserted in the PS payload header and made available to
4026 * the DataPort (either via the message header or via header bypass) to
4027 * indicate that oMask data (one or two phases) is included in Render
4028 * Target Write messages. If present, the oMask data is used to mask off
4031 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4033 /* The hardware wedges if you have this bit set but don't turn on any
4034 * dual source blend factors.
4036 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
4038 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
4039 (ctx
->Color
.BlendEnabled
& 1) &&
4040 ctx
->Color
.Blend
[0]._UsesDualSrc
;
4042 /* BRW_NEW_FS_PROG_DATA */
4043 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
4046 /* From the documentation for this packet:
4047 * "If the PS kernel does not need the Position XY Offsets to
4048 * compute a Position Value, then this field should be programmed
4049 * to POSOFFSET_NONE."
4051 * "SW Recommendation: If the PS kernel needs the Position Offsets
4052 * to compute a Position XY value, this field should match Position
4053 * ZW Interpolation Mode to ensure a consistent position.xyzw
4056 * We only require XY sample offsets. So, this recommendation doesn't
4057 * look useful at the moment. We might need this in future.
4059 if (prog_data
->uses_pos_offset
)
4060 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
4062 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
4064 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
4065 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
4066 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
4068 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
4070 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
4071 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
4073 * Since 16x MSAA is first introduced on SKL, we don't need to apply
4074 * the workaround on any older hardware.
4076 * BRW_NEW_NUM_SAMPLES
4078 if (GEN_GEN
>= 9 && !prog_data
->persample_dispatch
&&
4079 brw
->num_samples
== 16) {
4080 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
4081 ps
._32PixelDispatchEnable
= false;
4084 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
4085 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
4086 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
4087 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
4088 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
4089 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
4091 ps
.KernelStartPointer0
= stage_state
->prog_offset
+
4092 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
4093 ps
.KernelStartPointer1
= stage_state
->prog_offset
+
4094 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
4095 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
4096 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
4098 if (prog_data
->base
.total_scratch
) {
4099 ps
.ScratchSpaceBasePointer
=
4100 rw_32_bo(stage_state
->scratch_bo
,
4101 ffs(stage_state
->per_thread_scratch
) - 11);
4106 static const struct brw_tracked_state
genX(ps_state
) = {
4108 .mesa
= _NEW_MULTISAMPLE
|
4109 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
4112 .brw
= BRW_NEW_BATCH
|
4114 BRW_NEW_FS_PROG_DATA
|
4115 (GEN_GEN
>= 9 ? BRW_NEW_NUM_SAMPLES
: 0),
4117 .emit
= genX(upload_ps
),
4121 /* ---------------------------------------------------------------------- */
4125 genX(upload_hs_state
)(struct brw_context
*brw
)
4127 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4128 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4129 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4130 const struct brw_vue_prog_data
*vue_prog_data
=
4131 brw_vue_prog_data(stage_prog_data
);
4133 /* BRW_NEW_TES_PROG_DATA */
4134 struct brw_tcs_prog_data
*tcs_prog_data
=
4135 brw_tcs_prog_data(stage_prog_data
);
4137 if (!tcs_prog_data
) {
4138 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
4140 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
4141 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
4143 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
4144 hs
.IncludeVertexHandles
= true;
4146 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
4151 static const struct brw_tracked_state
genX(hs_state
) = {
4154 .brw
= BRW_NEW_BATCH
|
4156 BRW_NEW_TCS_PROG_DATA
|
4157 BRW_NEW_TESS_PROGRAMS
,
4159 .emit
= genX(upload_hs_state
),
4163 genX(upload_ds_state
)(struct brw_context
*brw
)
4165 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4166 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4167 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4169 /* BRW_NEW_TES_PROG_DATA */
4170 const struct brw_tes_prog_data
*tes_prog_data
=
4171 brw_tes_prog_data(stage_prog_data
);
4172 const struct brw_vue_prog_data
*vue_prog_data
=
4173 brw_vue_prog_data(stage_prog_data
);
4175 if (!tes_prog_data
) {
4176 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
4178 assert(GEN_GEN
< 11 ||
4179 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
4181 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
4182 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
4184 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4185 ds
.ComputeWCoordinateEnable
=
4186 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4189 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
4190 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4191 ds
.UserClipDistanceCullTestEnableBitmask
=
4192 vue_prog_data
->cull_distance_mask
;
4198 static const struct brw_tracked_state
genX(ds_state
) = {
4201 .brw
= BRW_NEW_BATCH
|
4203 BRW_NEW_TESS_PROGRAMS
|
4204 BRW_NEW_TES_PROG_DATA
,
4206 .emit
= genX(upload_ds_state
),
4209 /* ---------------------------------------------------------------------- */
4212 upload_te_state(struct brw_context
*brw
)
4214 /* BRW_NEW_TESS_PROGRAMS */
4215 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4217 /* BRW_NEW_TES_PROG_DATA */
4218 const struct brw_tes_prog_data
*tes_prog_data
=
4219 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4222 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4223 te
.Partitioning
= tes_prog_data
->partitioning
;
4224 te
.OutputTopology
= tes_prog_data
->output_topology
;
4225 te
.TEDomain
= tes_prog_data
->domain
;
4227 te
.MaximumTessellationFactorOdd
= 63.0;
4228 te
.MaximumTessellationFactorNotOdd
= 64.0;
4231 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4235 static const struct brw_tracked_state
genX(te_state
) = {
4238 .brw
= BRW_NEW_BLORP
|
4240 BRW_NEW_TES_PROG_DATA
|
4241 BRW_NEW_TESS_PROGRAMS
,
4243 .emit
= upload_te_state
,
4246 /* ---------------------------------------------------------------------- */
4249 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4251 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4252 /* BRW_NEW_TESS_PROGRAMS */
4253 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4255 /* BRW_NEW_TES_PROG_DATA */
4256 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4257 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4260 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4262 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4263 .brw
= BRW_NEW_BATCH
|
4265 BRW_NEW_TESS_PROGRAMS
|
4266 BRW_NEW_TES_PROG_DATA
,
4268 .emit
= genX(upload_tes_push_constants
),
4272 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4274 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4275 /* BRW_NEW_TESS_PROGRAMS */
4276 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4278 /* BRW_NEW_TCS_PROG_DATA */
4279 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4281 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4284 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4286 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4287 .brw
= BRW_NEW_BATCH
|
4289 BRW_NEW_DEFAULT_TESS_LEVELS
|
4290 BRW_NEW_TESS_PROGRAMS
|
4291 BRW_NEW_TCS_PROG_DATA
,
4293 .emit
= genX(upload_tcs_push_constants
),
4298 /* ---------------------------------------------------------------------- */
4302 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4304 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4306 /* BRW_NEW_COMPUTE_PROGRAM */
4307 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4310 /* BRW_NEW_CS_PROG_DATA */
4311 struct brw_cs_prog_data
*cs_prog_data
=
4312 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4314 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4315 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4319 const struct brw_tracked_state
genX(cs_push_constants
) = {
4321 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4322 .brw
= BRW_NEW_BATCH
|
4324 BRW_NEW_COMPUTE_PROGRAM
|
4325 BRW_NEW_CS_PROG_DATA
,
4327 .emit
= genX(upload_cs_push_constants
),
4331 * Creates a new CS constant buffer reflecting the current CS program's
4332 * constants, if needed by the CS program.
4335 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4337 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4339 /* BRW_NEW_COMPUTE_PROGRAM */
4340 struct brw_program
*cp
=
4341 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4343 /* BRW_NEW_CS_PROG_DATA */
4344 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4346 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4347 /* _NEW_PROGRAM_CONSTANTS */
4348 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4349 stage_state
, prog_data
);
4352 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4354 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4355 .brw
= BRW_NEW_BATCH
|
4357 BRW_NEW_COMPUTE_PROGRAM
|
4358 BRW_NEW_CS_PROG_DATA
,
4360 .emit
= genX(upload_cs_pull_constants
),
4364 genX(upload_cs_state
)(struct brw_context
*brw
)
4366 if (!brw
->cs
.base
.prog_data
)
4370 uint32_t *desc
= (uint32_t*) brw_state_batch(
4371 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4374 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4375 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4376 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4377 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4379 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4380 brw_emit_buffer_surface_state(
4381 brw
, &stage_state
->surf_offset
[
4382 prog_data
->binding_table
.shader_time_start
],
4383 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4384 brw
->shader_time
.bo
->size
, 1,
4388 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4389 32, &stage_state
->bind_bo_offset
);
4391 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4393 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4394 * the only bits that are changed are scoreboard related: Scoreboard
4395 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4396 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4398 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4399 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4401 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4403 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4404 if (prog_data
->total_scratch
) {
4405 uint32_t per_thread_scratch_value
;
4408 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4409 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4411 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4412 } else if (GEN_IS_HASWELL
) {
4413 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4414 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4416 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4418 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4419 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4421 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4423 vfe
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
4424 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4427 /* If brw->screen->subslice_total is greater than one, then
4428 * devinfo->max_cs_threads stores number of threads per sub-slice;
4429 * thus we need to multiply by that number by subslices to get
4430 * the actual maximum number of threads; the -1 is because the HW
4431 * has a bias of 1 (would not make sense to say the maximum number
4434 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4435 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4436 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4438 vfe
.ResetGatewayTimer
=
4439 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4442 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4448 /* We are uploading duplicated copies of push constant uniforms for each
4449 * thread. Although the local id data needs to vary per thread, it won't
4450 * change for other uniform data. Unfortunately this duplication is
4451 * required for gen7. As of Haswell, this duplication can be avoided,
4452 * but this older mechanism with duplicated data continues to work.
4454 * FINISHME: As of Haswell, we could make use of the
4455 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4456 * field to only store one copy of uniform data.
4458 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4459 * which is described in the GPGPU_WALKER command and in the Broadwell
4460 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4461 * Operations => GPGPU Mode => Indirect Payload Storage.
4463 * Note: The constant data is built in brw_upload_cs_push_constants
4466 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4468 const uint32_t vfe_curbe_allocation
=
4469 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4470 cs_prog_data
->push
.cross_thread
.regs
, 2);
4471 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4474 if (cs_prog_data
->push
.total
.size
> 0) {
4475 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4476 curbe
.CURBETotalDataLength
=
4477 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4478 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4482 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4483 memcpy(bind
, stage_state
->surf_offset
,
4484 prog_data
->binding_table
.size_bytes
);
4485 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4486 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4487 .SamplerStatePointer
= stage_state
->sampler_offset
,
4488 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4489 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4490 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4491 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4492 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4493 prog_data
->total_shared
),
4494 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4495 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4496 .CrossThreadConstantDataReadLength
=
4497 cs_prog_data
->push
.cross_thread
.regs
,
4501 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4503 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4504 load
.InterfaceDescriptorTotalLength
=
4505 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4506 load
.InterfaceDescriptorDataStartAddress
= offset
;
4510 static const struct brw_tracked_state
genX(cs_state
) = {
4512 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4513 .brw
= BRW_NEW_BATCH
|
4515 BRW_NEW_CS_PROG_DATA
|
4516 BRW_NEW_SAMPLER_STATE_TABLE
|
4519 .emit
= genX(upload_cs_state
)
4524 /* ---------------------------------------------------------------------- */
4528 genX(upload_raster
)(struct brw_context
*brw
)
4530 const struct gl_context
*ctx
= &brw
->ctx
;
4533 const bool flip_y
= ctx
->DrawBuffer
->FlipY
;
4536 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4539 const struct gl_point_attrib
*point
= &ctx
->Point
;
4541 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4542 if (brw
->polygon_front_bit
!= flip_y
)
4543 raster
.FrontWinding
= CounterClockwise
;
4545 if (polygon
->CullFlag
) {
4546 switch (polygon
->CullFaceMode
) {
4548 raster
.CullMode
= CULLMODE_FRONT
;
4551 raster
.CullMode
= CULLMODE_BACK
;
4553 case GL_FRONT_AND_BACK
:
4554 raster
.CullMode
= CULLMODE_BOTH
;
4557 unreachable("not reached");
4560 raster
.CullMode
= CULLMODE_NONE
;
4563 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4565 raster
.DXMultisampleRasterizationEnable
=
4566 _mesa_is_multisample_enabled(ctx
);
4568 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4569 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4570 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4572 switch (polygon
->FrontMode
) {
4574 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4577 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4580 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4583 unreachable("not reached");
4586 switch (polygon
->BackMode
) {
4588 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4591 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4594 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4597 unreachable("not reached");
4601 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4605 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4607 const bool multisampled_fbo
=
4608 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4609 if (multisampled_fbo
)
4610 raster
.AntialiasingEnable
= false;
4614 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4616 /* _NEW_TRANSFORM */
4618 if (!(ctx
->Transform
.DepthClampNear
&&
4619 ctx
->Transform
.DepthClampFar
))
4620 raster
.ViewportZClipTestEnable
= true;
4624 if (!ctx
->Transform
.DepthClampNear
)
4625 raster
.ViewportZNearClipTestEnable
= true;
4627 if (!ctx
->Transform
.DepthClampFar
)
4628 raster
.ViewportZFarClipTestEnable
= true;
4631 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4633 raster
.ConservativeRasterizationEnable
=
4634 ctx
->IntelConservativeRasterization
;
4637 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4638 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4640 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4644 static const struct brw_tracked_state
genX(raster_state
) = {
4646 .mesa
= _NEW_BUFFERS
|
4653 .brw
= BRW_NEW_BLORP
|
4655 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4657 .emit
= genX(upload_raster
),
4661 /* ---------------------------------------------------------------------- */
4665 genX(upload_ps_extra
)(struct brw_context
*brw
)
4667 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4669 const struct brw_wm_prog_data
*prog_data
=
4670 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4672 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4673 psx
.PixelShaderValid
= true;
4674 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4675 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4676 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4677 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4678 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4679 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4681 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4682 if (prog_data
->uses_sample_mask
) {
4684 if (prog_data
->post_depth_coverage
)
4685 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4686 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4687 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4689 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4691 psx
.PixelShaderUsesInputCoverageMask
= true;
4695 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4697 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4698 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4701 /* The stricter cross-primitive coherency guarantees that the hardware
4702 * gives us with the "Accesses UAV" bit set for at least one shader stage
4703 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4704 * are redundant within the current image, atomic counter and SSBO GL
4705 * APIs, which all have very loose ordering and coherency requirements
4706 * and generally rely on the application to insert explicit barriers when
4707 * a shader invocation is expected to see the memory writes performed by
4708 * the invocations of some previous primitive. Regardless of the value
4709 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4710 * cause an in most cases useless DC flush when the lowermost stage with
4711 * the bit set finishes execution.
4713 * It would be nice to disable it, but in some cases we can't because on
4714 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4715 * signal (which could be set independently from the coherency mechanism
4716 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4717 * determine whether the hardware skips execution of the fragment shader
4718 * or not via the ThreadDispatchEnable signal. However if we know that
4719 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4720 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4721 * difference so we may just disable it here.
4723 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4724 * take into account KillPixels when no depth or stencil writes are
4725 * enabled. In order for occlusion queries to work correctly with no
4726 * attachments, we need to force-enable here.
4728 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4731 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4732 !brw_color_buffer_write_enabled(brw
))
4733 psx
.PixelShaderHasUAV
= true;
4737 const struct brw_tracked_state
genX(ps_extra
) = {
4739 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4740 .brw
= BRW_NEW_BLORP
|
4742 BRW_NEW_FRAGMENT_PROGRAM
|
4743 BRW_NEW_FS_PROG_DATA
|
4744 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4746 .emit
= genX(upload_ps_extra
),
4750 /* ---------------------------------------------------------------------- */
4754 genX(upload_ps_blend
)(struct brw_context
*brw
)
4756 struct gl_context
*ctx
= &brw
->ctx
;
4759 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4760 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4763 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4765 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4766 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4767 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4769 bool alpha_to_one
= false;
4771 if (!buffer0_is_integer
) {
4772 /* _NEW_MULTISAMPLE */
4774 if (_mesa_is_multisample_enabled(ctx
)) {
4775 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4776 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4779 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4782 /* Used for implementing the following bit of GL_EXT_texture_integer:
4783 * "Per-fragment operations that require floating-point color
4784 * components, including multisample alpha operations, alpha test,
4785 * blending, and dithering, have no effect when the corresponding
4786 * colors are written to an integer color buffer."
4788 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4789 * "If drawbuffer zero is not NONE and the buffer it references has an
4790 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4791 * operations are skipped."
4793 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4794 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4795 GLenum eqA
= color
->Blend
[0].EquationA
;
4796 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4797 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4798 GLenum srcA
= color
->Blend
[0].SrcA
;
4799 GLenum dstA
= color
->Blend
[0].DstA
;
4801 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4802 srcRGB
= dstRGB
= GL_ONE
;
4804 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4805 srcA
= dstA
= GL_ONE
;
4807 /* Due to hardware limitations, the destination may have information
4808 * in an alpha channel even when the format specifies no alpha
4809 * channel. In order to avoid getting any incorrect blending due to
4810 * that alpha channel, coerce the blend factors to values that will
4811 * not read the alpha channel, but will instead use the correct
4812 * implicit value for alpha.
4814 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4815 GL_TEXTURE_ALPHA_TYPE
)) {
4816 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4817 srcA
= brw_fix_xRGB_alpha(srcA
);
4818 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4819 dstA
= brw_fix_xRGB_alpha(dstA
);
4822 /* Alpha to One doesn't work with Dual Color Blending. Override
4823 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4825 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4826 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4827 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4828 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4829 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4832 pb
.ColorBufferBlendEnable
= true;
4833 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4834 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4835 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4836 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4838 pb
.IndependentAlphaBlendEnable
=
4839 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4844 static const struct brw_tracked_state
genX(ps_blend
) = {
4846 .mesa
= _NEW_BUFFERS
|
4849 .brw
= BRW_NEW_BLORP
|
4851 BRW_NEW_FRAGMENT_PROGRAM
,
4853 .emit
= genX(upload_ps_blend
)
4857 /* ---------------------------------------------------------------------- */
4861 genX(emit_vf_topology
)(struct brw_context
*brw
)
4863 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4864 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4868 static const struct brw_tracked_state
genX(vf_topology
) = {
4871 .brw
= BRW_NEW_BLORP
|
4874 .emit
= genX(emit_vf_topology
),
4878 /* ---------------------------------------------------------------------- */
4882 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4884 uint32_t offset_in_bytes
,
4887 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4888 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4889 mi_rpc
.ReportID
= report_id
;
4894 /* ---------------------------------------------------------------------- */
4897 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4900 genX(emit_sampler_state_pointers_xs
)(MAYBE_UNUSED
struct brw_context
*brw
,
4901 MAYBE_UNUSED
struct brw_stage_state
*stage_state
)
4904 static const uint16_t packet_headers
[] = {
4905 [MESA_SHADER_VERTEX
] = 43,
4906 [MESA_SHADER_TESS_CTRL
] = 44,
4907 [MESA_SHADER_TESS_EVAL
] = 45,
4908 [MESA_SHADER_GEOMETRY
] = 46,
4909 [MESA_SHADER_FRAGMENT
] = 47,
4912 /* Ivybridge requires a workaround flush before VS packets. */
4913 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4914 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4915 gen7_emit_vs_workaround_flush(brw
);
4918 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4919 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4920 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4926 has_component(mesa_format format
, int i
)
4928 if (_mesa_is_format_color_format(format
))
4929 return _mesa_format_has_color_component(format
, i
);
4931 /* depth and stencil have only one component */
4936 * Upload SAMPLER_BORDER_COLOR_STATE.
4939 genX(upload_default_color
)(struct brw_context
*brw
,
4940 const struct gl_sampler_object
*sampler
,
4941 MAYBE_UNUSED mesa_format format
, GLenum base_format
,
4942 bool is_integer_format
, bool is_stencil_sampling
,
4943 uint32_t *sdc_offset
)
4945 union gl_color_union color
;
4947 switch (base_format
) {
4948 case GL_DEPTH_COMPONENT
:
4949 /* GL specs that border color for depth textures is taken from the
4950 * R channel, while the hardware uses A. Spam R into all the
4951 * channels for safety.
4953 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4954 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4955 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4956 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4962 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4965 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4966 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4967 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4968 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4971 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4972 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4973 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4974 color
.ui
[3] = float_as_int(1.0);
4976 case GL_LUMINANCE_ALPHA
:
4977 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4978 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4979 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4980 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4983 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4984 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4985 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4986 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4990 /* In some cases we use an RGBA surface format for GL RGB textures,
4991 * where we've initialized the A channel to 1.0. We also have to set
4992 * the border color alpha to 1.0 in that case.
4994 if (base_format
== GL_RGB
)
4995 color
.ui
[3] = float_as_int(1.0);
5000 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
5004 uint32_t *sdc
= brw_state_batch(
5005 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
5006 alignment
, sdc_offset
);
5008 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
5010 #define ASSIGN(dst, src) \
5015 #define ASSIGNu16(dst, src) \
5017 dst = (uint16_t)src; \
5020 #define ASSIGNu8(dst, src) \
5022 dst = (uint8_t)src; \
5025 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
5026 macro(state.BorderColor ## _color_type ## Red, src[0]); \
5027 macro(state.BorderColor ## _color_type ## Green, src[1]); \
5028 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
5029 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
5032 /* On Broadwell, the border color is represented as four 32-bit floats,
5033 * integers, or unsigned values, interpreted according to the surface
5034 * format. This matches the sampler->BorderColor union exactly; just
5035 * memcpy the values.
5037 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
5038 #elif GEN_IS_HASWELL
5039 if (is_integer_format
|| is_stencil_sampling
) {
5040 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
5041 const int bits_per_channel
=
5042 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
5044 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
5045 * "If any color channel is missing from the surface format,
5046 * corresponding border color should be programmed as zero and if
5047 * alpha channel is missing, corresponding Alpha border color should
5048 * be programmed as 1."
5050 unsigned c
[4] = { 0, 0, 0, 1 };
5051 for (int i
= 0; i
< 4; i
++) {
5052 if (has_component(format
, i
))
5056 switch (bits_per_channel
) {
5058 /* Copy RGBA in order. */
5059 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
5062 /* R10G10B10A2_UINT is treated like a 16-bit format. */
5064 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
5067 if (base_format
== GL_RG
) {
5068 /* Careful inspection of the tables reveals that for RG32 formats,
5069 * the green channel needs to go where blue normally belongs.
5071 state
.BorderColor32bitRed
= c
[0];
5072 state
.BorderColor32bitBlue
= c
[1];
5073 state
.BorderColor32bitAlpha
= 1;
5075 /* Copy RGBA in order. */
5076 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
5080 assert(!"Invalid number of bits per channel in integer format.");
5084 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5086 #elif GEN_GEN == 5 || GEN_GEN == 6
5087 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
5088 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
5089 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
5091 #define MESA_FLOAT_TO_HALF(dst, src) \
5092 dst = _mesa_float_to_half(src);
5094 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
5096 #undef MESA_FLOAT_TO_HALF
5098 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
5099 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
5100 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
5101 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
5103 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5105 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
5107 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5111 #undef BORDER_COLOR_ATTR
5113 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
5117 translate_wrap_mode(GLenum wrap
, MAYBE_UNUSED
bool using_nearest
)
5124 /* GL_CLAMP is the weird mode where coordinates are clamped to
5125 * [0.0, 1.0], so linear filtering of coordinates outside of
5126 * [0.0, 1.0] give you half edge texel value and half border
5129 * Gen8+ supports this natively.
5131 return TCM_HALF_BORDER
;
5133 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
5134 * and set clamp_border here, which gets the result desired.
5135 * We just use clamp(_to_edge) for nearest, because for nearest
5136 * clamping to 1.0 gives border color instead of the desired
5142 return TCM_CLAMP_BORDER
;
5144 case GL_CLAMP_TO_EDGE
:
5146 case GL_CLAMP_TO_BORDER
:
5147 return TCM_CLAMP_BORDER
;
5148 case GL_MIRRORED_REPEAT
:
5150 case GL_MIRROR_CLAMP_TO_EDGE
:
5151 return TCM_MIRROR_ONCE
;
5158 * Return true if the given wrap mode requires the border color to exist.
5161 wrap_mode_needs_border_color(unsigned wrap_mode
)
5164 return wrap_mode
== TCM_CLAMP_BORDER
||
5165 wrap_mode
== TCM_HALF_BORDER
;
5167 return wrap_mode
== TCM_CLAMP_BORDER
;
5172 * Sets the sampler state for a single unit based off of the sampler key
5176 genX(update_sampler_state
)(struct brw_context
*brw
,
5177 GLenum target
, bool tex_cube_map_seamless
,
5178 GLfloat tex_unit_lod_bias
,
5179 mesa_format format
, GLenum base_format
,
5180 const struct gl_texture_object
*texObj
,
5181 const struct gl_sampler_object
*sampler
,
5182 uint32_t *sampler_state
)
5184 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
5186 /* Select min and mip filters. */
5187 switch (sampler
->MinFilter
) {
5189 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5190 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5193 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5194 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5196 case GL_NEAREST_MIPMAP_NEAREST
:
5197 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5198 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5200 case GL_LINEAR_MIPMAP_NEAREST
:
5201 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5202 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5204 case GL_NEAREST_MIPMAP_LINEAR
:
5205 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5206 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5208 case GL_LINEAR_MIPMAP_LINEAR
:
5209 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5210 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5213 unreachable("not reached");
5216 /* Select mag filter. */
5217 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5218 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5220 /* Enable anisotropic filtering if desired. */
5221 samp_st
.MaximumAnisotropy
= RATIO21
;
5223 if (sampler
->MaxAnisotropy
> 1.0f
) {
5224 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5225 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5226 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5227 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5229 if (sampler
->MaxAnisotropy
> 2.0f
) {
5230 samp_st
.MaximumAnisotropy
=
5231 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5235 /* Set address rounding bits if not using nearest filtering. */
5236 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5237 samp_st
.UAddressMinFilterRoundingEnable
= true;
5238 samp_st
.VAddressMinFilterRoundingEnable
= true;
5239 samp_st
.RAddressMinFilterRoundingEnable
= true;
5242 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5243 samp_st
.UAddressMagFilterRoundingEnable
= true;
5244 samp_st
.VAddressMagFilterRoundingEnable
= true;
5245 samp_st
.RAddressMagFilterRoundingEnable
= true;
5248 bool either_nearest
=
5249 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5250 unsigned wrap_s
= translate_wrap_mode(sampler
->WrapS
, either_nearest
);
5251 unsigned wrap_t
= translate_wrap_mode(sampler
->WrapT
, either_nearest
);
5252 unsigned wrap_r
= translate_wrap_mode(sampler
->WrapR
, either_nearest
);
5254 if (target
== GL_TEXTURE_CUBE_MAP
||
5255 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5256 /* Cube maps must use the same wrap mode for all three coordinate
5257 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5259 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5260 * integer formats. Fall back to CLAMP for now.
5262 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5263 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5272 } else if (target
== GL_TEXTURE_1D
) {
5273 /* There's a bug in 1D texture sampling - it actually pays
5274 * attention to the wrap_t value, though it should not.
5275 * Override the wrap_t value here to GL_REPEAT to keep
5276 * any nonexistent border pixels from floating in.
5281 samp_st
.TCXAddressControlMode
= wrap_s
;
5282 samp_st
.TCYAddressControlMode
= wrap_t
;
5283 samp_st
.TCZAddressControlMode
= wrap_r
;
5285 samp_st
.ShadowFunction
=
5286 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5287 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5290 /* Set shadow function. */
5291 samp_st
.AnisotropicAlgorithm
=
5292 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5293 EWAApproximation
: LEGACY
;
5297 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5300 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5301 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5302 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5303 samp_st
.TextureLODBias
=
5304 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5307 samp_st
.BaseMipLevel
=
5308 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5309 samp_st
.MinandMagStateNotEqual
=
5310 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5313 /* Upload the border color if necessary. If not, just point it at
5314 * offset 0 (the start of the batch) - the color should be ignored,
5315 * but that address won't fault in case something reads it anyway.
5317 uint32_t border_color_offset
= 0;
5318 if (wrap_mode_needs_border_color(wrap_s
) ||
5319 wrap_mode_needs_border_color(wrap_t
) ||
5320 wrap_mode_needs_border_color(wrap_r
)) {
5321 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5322 texObj
->_IsIntegerFormat
,
5323 texObj
->StencilSampling
,
5324 &border_color_offset
);
5327 samp_st
.BorderColorPointer
=
5328 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5330 samp_st
.BorderColorPointer
= border_color_offset
;
5334 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5336 samp_st
.LODPreClampEnable
= true;
5339 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5343 update_sampler_state(struct brw_context
*brw
,
5345 uint32_t *sampler_state
)
5347 struct gl_context
*ctx
= &brw
->ctx
;
5348 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5349 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5350 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5352 /* These don't use samplers at all. */
5353 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5356 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5357 genX(update_sampler_state
)(brw
, texObj
->Target
,
5358 ctx
->Texture
.CubeMapSeamless
,
5360 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5366 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5367 struct gl_program
*prog
,
5368 struct brw_stage_state
*stage_state
)
5370 struct gl_context
*ctx
= &brw
->ctx
;
5371 uint32_t sampler_count
= stage_state
->sampler_count
;
5373 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5375 if (sampler_count
== 0)
5378 /* SAMPLER_STATE is 4 DWords on all platforms. */
5379 const int dwords
= GENX(SAMPLER_STATE_length
);
5380 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5382 uint32_t *sampler_state
= brw_state_batch(brw
,
5383 sampler_count
* size_in_bytes
,
5384 32, &stage_state
->sampler_offset
);
5385 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5387 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5388 if (SamplersUsed
& (1 << s
)) {
5389 const unsigned unit
= prog
->SamplerUnits
[s
];
5390 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5391 update_sampler_state(brw
, unit
, sampler_state
);
5395 sampler_state
+= dwords
;
5398 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5399 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5400 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5402 /* Flag that the sampler state table pointer has changed; later atoms
5405 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5410 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5412 /* BRW_NEW_FRAGMENT_PROGRAM */
5413 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5414 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5417 static const struct brw_tracked_state
genX(fs_samplers
) = {
5419 .mesa
= _NEW_TEXTURE
,
5420 .brw
= BRW_NEW_BATCH
|
5422 BRW_NEW_FRAGMENT_PROGRAM
,
5424 .emit
= genX(upload_fs_samplers
),
5428 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5430 /* BRW_NEW_VERTEX_PROGRAM */
5431 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5432 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5435 static const struct brw_tracked_state
genX(vs_samplers
) = {
5437 .mesa
= _NEW_TEXTURE
,
5438 .brw
= BRW_NEW_BATCH
|
5440 BRW_NEW_VERTEX_PROGRAM
,
5442 .emit
= genX(upload_vs_samplers
),
5447 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5449 /* BRW_NEW_GEOMETRY_PROGRAM */
5450 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5454 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5458 static const struct brw_tracked_state
genX(gs_samplers
) = {
5460 .mesa
= _NEW_TEXTURE
,
5461 .brw
= BRW_NEW_BATCH
|
5463 BRW_NEW_GEOMETRY_PROGRAM
,
5465 .emit
= genX(upload_gs_samplers
),
5471 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5473 /* BRW_NEW_TESS_PROGRAMS */
5474 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5478 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5481 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5483 .mesa
= _NEW_TEXTURE
,
5484 .brw
= BRW_NEW_BATCH
|
5486 BRW_NEW_TESS_PROGRAMS
,
5488 .emit
= genX(upload_tcs_samplers
),
5494 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5496 /* BRW_NEW_TESS_PROGRAMS */
5497 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5501 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5504 static const struct brw_tracked_state
genX(tes_samplers
) = {
5506 .mesa
= _NEW_TEXTURE
,
5507 .brw
= BRW_NEW_BATCH
|
5509 BRW_NEW_TESS_PROGRAMS
,
5511 .emit
= genX(upload_tes_samplers
),
5517 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5519 /* BRW_NEW_COMPUTE_PROGRAM */
5520 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5524 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5527 const struct brw_tracked_state
genX(cs_samplers
) = {
5529 .mesa
= _NEW_TEXTURE
,
5530 .brw
= BRW_NEW_BATCH
|
5532 BRW_NEW_COMPUTE_PROGRAM
,
5534 .emit
= genX(upload_cs_samplers
),
5538 /* ---------------------------------------------------------------------- */
5542 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5544 struct gl_context
*ctx
= &brw
->ctx
;
5546 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5547 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5548 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5549 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5550 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5554 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5557 .brw
= BRW_NEW_CONTEXT
|
5560 .emit
= genX(upload_blend_constant_color
)
5564 /* ---------------------------------------------------------------------- */
5567 genX(init_atoms
)(struct brw_context
*brw
)
5570 static const struct brw_tracked_state
*render_atoms
[] =
5572 /* Once all the programs are done, we know how large urb entry
5573 * sizes need to be and can decide if we need to change the urb
5577 &brw_recalculate_urb_fence
,
5580 &genX(color_calc_state
),
5582 /* Surface state setup. Must come before the VS/WM unit. The binding
5583 * table upload must be last.
5585 &brw_vs_pull_constants
,
5586 &brw_wm_pull_constants
,
5587 &brw_renderbuffer_surfaces
,
5588 &brw_renderbuffer_read_surfaces
,
5589 &brw_texture_surfaces
,
5590 &brw_vs_binding_table
,
5591 &brw_wm_binding_table
,
5596 /* These set up state for brw_psp_urb_cbs */
5598 &genX(sf_clip_viewport
),
5600 &genX(vs_state
), /* always required, enabled or not */
5606 &brw_binding_table_pointers
,
5607 &genX(blend_constant_color
),
5611 &genX(polygon_stipple
),
5612 &genX(polygon_stipple_offset
),
5614 &genX(line_stipple
),
5618 &genX(drawing_rect
),
5619 &brw_indices
, /* must come before brw_vertices */
5620 &genX(index_buffer
),
5623 &brw_constant_buffer
5626 static const struct brw_tracked_state
*render_atoms
[] =
5628 &genX(sf_clip_viewport
),
5630 /* Command packets: */
5635 &genX(blend_state
), /* must do before cc unit */
5636 &genX(color_calc_state
), /* must do before cc unit */
5637 &genX(depth_stencil_state
), /* must do before cc unit */
5639 &genX(vs_push_constants
), /* Before vs_state */
5640 &genX(gs_push_constants
), /* Before gs_state */
5641 &genX(wm_push_constants
), /* Before wm_state */
5643 /* Surface state setup. Must come before the VS/WM unit. The binding
5644 * table upload must be last.
5646 &brw_vs_pull_constants
,
5647 &brw_vs_ubo_surfaces
,
5648 &brw_gs_pull_constants
,
5649 &brw_gs_ubo_surfaces
,
5650 &brw_wm_pull_constants
,
5651 &brw_wm_ubo_surfaces
,
5652 &gen6_renderbuffer_surfaces
,
5653 &brw_renderbuffer_read_surfaces
,
5654 &brw_texture_surfaces
,
5656 &brw_vs_binding_table
,
5657 &gen6_gs_binding_table
,
5658 &brw_wm_binding_table
,
5663 &gen6_sampler_state
,
5664 &genX(multisample_state
),
5672 &genX(scissor_state
),
5674 &gen6_binding_table_pointers
,
5678 &genX(polygon_stipple
),
5679 &genX(polygon_stipple_offset
),
5681 &genX(line_stipple
),
5683 &genX(drawing_rect
),
5685 &brw_indices
, /* must come before brw_vertices */
5686 &genX(index_buffer
),
5690 static const struct brw_tracked_state
*render_atoms
[] =
5692 /* Command packets: */
5695 &genX(sf_clip_viewport
),
5698 &gen7_push_constant_space
,
5700 &genX(blend_state
), /* must do before cc unit */
5701 &genX(color_calc_state
), /* must do before cc unit */
5702 &genX(depth_stencil_state
), /* must do before cc unit */
5704 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5705 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5706 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5707 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5708 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5710 &genX(vs_push_constants
), /* Before vs_state */
5711 &genX(tcs_push_constants
),
5712 &genX(tes_push_constants
),
5713 &genX(gs_push_constants
), /* Before gs_state */
5714 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5716 /* Surface state setup. Must come before the VS/WM unit. The binding
5717 * table upload must be last.
5719 &brw_vs_pull_constants
,
5720 &brw_vs_ubo_surfaces
,
5721 &brw_tcs_pull_constants
,
5722 &brw_tcs_ubo_surfaces
,
5723 &brw_tes_pull_constants
,
5724 &brw_tes_ubo_surfaces
,
5725 &brw_gs_pull_constants
,
5726 &brw_gs_ubo_surfaces
,
5727 &brw_wm_pull_constants
,
5728 &brw_wm_ubo_surfaces
,
5729 &gen6_renderbuffer_surfaces
,
5730 &brw_renderbuffer_read_surfaces
,
5731 &brw_texture_surfaces
,
5733 &genX(push_constant_packets
),
5735 &brw_vs_binding_table
,
5736 &brw_tcs_binding_table
,
5737 &brw_tes_binding_table
,
5738 &brw_gs_binding_table
,
5739 &brw_wm_binding_table
,
5743 &genX(tcs_samplers
),
5744 &genX(tes_samplers
),
5746 &genX(multisample_state
),
5760 &genX(scissor_state
),
5764 &genX(polygon_stipple
),
5765 &genX(polygon_stipple_offset
),
5767 &genX(line_stipple
),
5769 &genX(drawing_rect
),
5771 &brw_indices
, /* must come before brw_vertices */
5772 &genX(index_buffer
),
5780 static const struct brw_tracked_state
*render_atoms
[] =
5783 &genX(sf_clip_viewport
),
5786 &gen7_push_constant_space
,
5789 &genX(color_calc_state
),
5791 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5792 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5793 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5794 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5795 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5797 &genX(vs_push_constants
), /* Before vs_state */
5798 &genX(tcs_push_constants
),
5799 &genX(tes_push_constants
),
5800 &genX(gs_push_constants
), /* Before gs_state */
5801 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5803 /* Surface state setup. Must come before the VS/WM unit. The binding
5804 * table upload must be last.
5806 &brw_vs_pull_constants
,
5807 &brw_vs_ubo_surfaces
,
5808 &brw_tcs_pull_constants
,
5809 &brw_tcs_ubo_surfaces
,
5810 &brw_tes_pull_constants
,
5811 &brw_tes_ubo_surfaces
,
5812 &brw_gs_pull_constants
,
5813 &brw_gs_ubo_surfaces
,
5814 &brw_wm_pull_constants
,
5815 &brw_wm_ubo_surfaces
,
5816 &gen6_renderbuffer_surfaces
,
5817 &brw_renderbuffer_read_surfaces
,
5818 &brw_texture_surfaces
,
5820 &genX(push_constant_packets
),
5822 &brw_vs_binding_table
,
5823 &brw_tcs_binding_table
,
5824 &brw_tes_binding_table
,
5825 &brw_gs_binding_table
,
5826 &brw_wm_binding_table
,
5830 &genX(tcs_samplers
),
5831 &genX(tes_samplers
),
5833 &genX(multisample_state
),
5842 &genX(raster_state
),
5848 &genX(depth_stencil_state
),
5851 &genX(scissor_state
),
5855 &genX(polygon_stipple
),
5856 &genX(polygon_stipple_offset
),
5858 &genX(line_stipple
),
5860 &genX(drawing_rect
),
5865 &genX(index_buffer
),
5873 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5874 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5875 render_atoms
, ARRAY_SIZE(render_atoms
));
5878 static const struct brw_tracked_state
*compute_atoms
[] =
5881 &brw_cs_image_surfaces
,
5882 &genX(cs_push_constants
),
5883 &genX(cs_pull_constants
),
5884 &brw_cs_ubo_surfaces
,
5885 &brw_cs_texture_surfaces
,
5886 &brw_cs_work_groups_surface
,
5891 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5892 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5893 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5895 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);