2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "dev/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 UNUSED
static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 static struct brw_address
124 rw_32_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_32BIT
,
133 static struct brw_address
134 ro_32_bo(struct brw_bo
*bo
, uint32_t offset
)
136 return (struct brw_address
) {
139 .reloc_flags
= RELOC_32BIT
,
143 UNUSED
static struct brw_address
144 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
146 return (struct brw_address
) {
149 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
154 static struct brw_address
155 KSP(struct brw_context
*brw
, uint32_t offset
)
157 return ro_bo(brw
->cache
.bo
, offset
);
161 KSP(UNUSED
struct brw_context
*brw
, uint32_t offset
)
167 #include "genxml/genX_pack.h"
169 #define _brw_cmd_length(cmd) cmd ## _length
170 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
171 #define _brw_cmd_header(cmd) cmd ## _header
172 #define _brw_cmd_pack(cmd) cmd ## _pack
174 #define brw_batch_emit(brw, cmd, name) \
175 for (struct cmd name = { _brw_cmd_header(cmd) }, \
176 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
177 __builtin_expect(_dst != NULL, 1); \
178 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
182 uint32_t *_dw = emit_dwords(brw, n); \
183 struct cmd template = { \
184 _brw_cmd_header(cmd), \
185 .DWordLength = n - _brw_cmd_length_bias(cmd), \
188 _brw_cmd_pack(cmd)(brw, _dw, &template); \
189 _dw + 1; /* Array starts at dw[1] */ \
192 #define brw_state_emit(brw, cmd, align, offset, name) \
193 for (struct cmd name = {}, \
194 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
196 __builtin_expect(_dst != NULL, 1); \
197 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
201 * Polygon stipple packet
204 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
206 struct gl_context
*ctx
= &brw
->ctx
;
209 if (!ctx
->Polygon
.StippleFlag
)
212 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
213 /* Polygon stipple is provided in OpenGL order, i.e. bottom
214 * row first. If we're rendering to a window (i.e. the
215 * default frame buffer object, 0), then we need to invert
216 * it to match our pixel layout. But if we're rendering
217 * to a FBO (i.e. any named frame buffer object), we *don't*
218 * need to invert - we already match the layout.
220 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
221 for (unsigned i
= 0; i
< 32; i
++)
222 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
224 for (unsigned i
= 0; i
< 32; i
++)
225 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
230 static const struct brw_tracked_state
genX(polygon_stipple
) = {
232 .mesa
= _NEW_POLYGON
|
234 .brw
= BRW_NEW_CONTEXT
,
236 .emit
= genX(upload_polygon_stipple
),
240 * Polygon stipple offset packet
243 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
245 struct gl_context
*ctx
= &brw
->ctx
;
248 if (!ctx
->Polygon
.StippleFlag
)
251 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
254 * If we're drawing to a system window we have to invert the Y axis
255 * in order to match the OpenGL pixel coordinate system, and our
256 * offset must be matched to the window position. If we're drawing
257 * to a user-created FBO then our native pixel coordinate system
258 * works just fine, and there's no window system to worry about.
260 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
261 poly
.PolygonStippleYOffset
=
262 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
267 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
269 .mesa
= _NEW_BUFFERS
|
271 .brw
= BRW_NEW_CONTEXT
,
273 .emit
= genX(upload_polygon_stipple_offset
),
277 * Line stipple packet
280 genX(upload_line_stipple
)(struct brw_context
*brw
)
282 struct gl_context
*ctx
= &brw
->ctx
;
284 if (!ctx
->Line
.StippleFlag
)
287 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
288 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
290 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
291 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
295 static const struct brw_tracked_state
genX(line_stipple
) = {
298 .brw
= BRW_NEW_CONTEXT
,
300 .emit
= genX(upload_line_stipple
),
303 /* Constant single cliprect for framebuffer object or DRI2 drawing */
305 genX(upload_drawing_rect
)(struct brw_context
*brw
)
307 struct gl_context
*ctx
= &brw
->ctx
;
308 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
309 const unsigned int fb_width
= _mesa_geometric_width(fb
);
310 const unsigned int fb_height
= _mesa_geometric_height(fb
);
312 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
313 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
314 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
318 static const struct brw_tracked_state
genX(drawing_rect
) = {
320 .mesa
= _NEW_BUFFERS
,
321 .brw
= BRW_NEW_BLORP
|
324 .emit
= genX(upload_drawing_rect
),
328 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
332 unsigned start_offset
,
333 MAYBE_UNUSED
unsigned end_offset
,
335 MAYBE_UNUSED
unsigned step_rate
)
337 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
338 .VertexBufferIndex
= buffer_nr
,
339 .BufferPitch
= stride
,
341 /* The VF cache designers apparently cut corners, and made the cache
342 * only consider the bottom 32 bits of memory addresses. If you happen
343 * to have two vertex buffers which get placed exactly 4 GiB apart and
344 * use them in back-to-back draw calls, you can get collisions. To work
345 * around this problem, we restrict vertex buffers to the low 32 bits of
348 .BufferStartingAddress
= ro_32_bo(bo
, start_offset
),
350 .BufferSize
= end_offset
- start_offset
,
354 .AddressModifyEnable
= true,
358 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
359 .InstanceDataStepRate
= step_rate
,
361 .EndAddress
= ro_bo(bo
, end_offset
- 1),
366 .VertexBufferMOCS
= ICL_MOCS_WB
,
368 .VertexBufferMOCS
= CNL_MOCS_WB
,
370 .VertexBufferMOCS
= SKL_MOCS_WB
,
372 .VertexBufferMOCS
= BDW_MOCS_WB
,
374 .VertexBufferMOCS
= GEN7_MOCS_L3
,
378 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
379 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
383 is_passthru_format(uint32_t format
)
386 case ISL_FORMAT_R64_PASSTHRU
:
387 case ISL_FORMAT_R64G64_PASSTHRU
:
388 case ISL_FORMAT_R64G64B64_PASSTHRU
:
389 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
397 uploads_needed(uint32_t format
,
400 if (!is_passthru_format(format
))
407 case ISL_FORMAT_R64_PASSTHRU
:
408 case ISL_FORMAT_R64G64_PASSTHRU
:
410 case ISL_FORMAT_R64G64B64_PASSTHRU
:
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
414 unreachable("not reached");
419 * Returns the format that we are finally going to use when upload a vertex
420 * element. It will only change if we are using *64*PASSTHRU formats, as for
421 * gen < 8 they need to be splitted on two *32*FLOAT formats.
423 * @upload points in which upload we are. Valid values are [0,1]
426 downsize_format_if_needed(uint32_t format
,
429 assert(upload
== 0 || upload
== 1);
431 if (!is_passthru_format(format
))
434 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
435 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
436 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
437 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
438 * flagging that we want to fill with zeroes this second forced upload.
441 case ISL_FORMAT_R64_PASSTHRU
:
442 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
443 : ISL_FORMAT_R32_FLOAT
;
444 case ISL_FORMAT_R64G64_PASSTHRU
:
445 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
446 : ISL_FORMAT_R32_FLOAT
;
447 case ISL_FORMAT_R64G64B64_PASSTHRU
:
448 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
449 : ISL_FORMAT_R32G32_FLOAT
;
450 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
451 return ISL_FORMAT_R32G32B32A32_FLOAT
;
453 unreachable("not reached");
458 * Returns the number of componentes associated with a format that is used on
459 * a 64 to 32 format split. See downsize_format()
462 upload_format_size(uint32_t upload_format
)
464 switch (upload_format
) {
465 case ISL_FORMAT_R32_FLOAT
:
467 /* downsized_format has returned this one in order to flag that we are
468 * performing a second upload which we want to have filled with
469 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
470 * vertex shader input variables.
474 case ISL_FORMAT_R32G32_FLOAT
:
476 case ISL_FORMAT_R32G32B32A32_FLOAT
:
479 unreachable("not reached");
483 static UNUSED
uint16_t
484 pinned_bo_high_bits(struct brw_bo
*bo
)
486 return (bo
->kflags
& EXEC_OBJECT_PINNED
) ? bo
->gtt_offset
>> 32ull : 0;
489 /* The VF cache designers apparently cut corners, and made the cache key's
490 * <VertexBufferIndex, Memory Address> tuple only consider the bottom 32 bits
491 * of the address. If you happen to have two vertex buffers which get placed
492 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
493 * collisions. (These collisions can happen within a single batch.)
495 * In the soft-pin world, we'd like to assign addresses up front, and never
496 * move buffers. So, we need to do a VF cache invalidate if the buffer for
497 * a particular VB slot has different [48:32] address bits than the last one.
499 * In the relocation world, we have no idea what the addresses will be, so
500 * we can't apply this workaround. Instead, we tell the kernel to move it
501 * to the low 4GB regardless.
504 vf_invalidate_for_vb_48bit_transitions(struct brw_context
*brw
)
507 bool need_invalidate
= false;
510 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
511 uint16_t high_bits
= pinned_bo_high_bits(brw
->vb
.buffers
[i
].bo
);
513 if (high_bits
!= brw
->vb
.last_bo_high_bits
[i
]) {
514 need_invalidate
= true;
515 brw
->vb
.last_bo_high_bits
[i
] = high_bits
;
519 /* Don't bother with draw parameter buffers - those are generated by
520 * the driver so we can select a consistent memory zone.
523 if (need_invalidate
) {
524 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
530 vf_invalidate_for_ib_48bit_transition(struct brw_context
*brw
)
533 uint16_t high_bits
= pinned_bo_high_bits(brw
->ib
.bo
);
535 if (high_bits
!= brw
->ib
.last_bo_high_bits
) {
536 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
537 brw
->ib
.last_bo_high_bits
= high_bits
;
543 genX(emit_vertices
)(struct brw_context
*brw
)
545 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
548 brw_prepare_vertices(brw
);
549 brw_prepare_shader_draw_parameters(brw
);
552 brw_emit_query_begin(brw
);
555 const struct brw_vs_prog_data
*vs_prog_data
=
556 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
559 struct gl_context
*ctx
= &brw
->ctx
;
560 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
561 ctx
->Polygon
.BackMode
!= GL_FILL
);
563 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
564 unsigned vue
= brw
->vb
.nr_enabled
;
566 /* The element for the edge flags must always be last, so we have to
567 * insert the SGVS before it in that case.
569 if (uses_edge_flag
) {
575 "Trying to insert VID/IID past 33rd vertex element, "
576 "need to reorder the vertex attrbutes.");
578 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
579 if (vs_prog_data
->uses_vertexid
) {
580 vfs
.VertexIDEnable
= true;
581 vfs
.VertexIDComponentNumber
= 2;
582 vfs
.VertexIDElementOffset
= vue
;
585 if (vs_prog_data
->uses_instanceid
) {
586 vfs
.InstanceIDEnable
= true;
587 vfs
.InstanceIDComponentNumber
= 3;
588 vfs
.InstanceIDElementOffset
= vue
;
592 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
593 vfi
.InstancingEnable
= true;
594 vfi
.VertexElementIndex
= vue
;
597 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
601 const bool uses_draw_params
=
602 vs_prog_data
->uses_firstvertex
||
603 vs_prog_data
->uses_baseinstance
;
605 const bool uses_derived_draw_params
=
606 vs_prog_data
->uses_drawid
||
607 vs_prog_data
->uses_is_indexed_draw
;
609 const bool needs_sgvs_element
= (uses_draw_params
||
610 vs_prog_data
->uses_instanceid
||
611 vs_prog_data
->uses_vertexid
);
613 unsigned nr_elements
=
614 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ uses_derived_draw_params
;
617 /* If any of the formats of vb.enabled needs more that one upload, we need
618 * to add it to nr_elements
620 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
621 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
622 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
623 uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
625 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
630 /* If the VS doesn't read any inputs (calculating vertex position from
631 * a state variable for some reason, for example), emit a single pad
632 * VERTEX_ELEMENT struct and bail.
634 * The stale VB state stays in place, but they don't do anything unless
635 * a VE loads from them.
637 if (nr_elements
== 0) {
638 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
639 1 + GENX(VERTEX_ELEMENT_STATE_length
));
640 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
642 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
643 .Component0Control
= VFCOMP_STORE_0
,
644 .Component1Control
= VFCOMP_STORE_0
,
645 .Component2Control
= VFCOMP_STORE_0
,
646 .Component3Control
= VFCOMP_STORE_1_FP
,
648 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
652 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
653 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
654 uses_draw_params
+ uses_derived_draw_params
;
656 vf_invalidate_for_vb_48bit_transitions(brw
);
659 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
661 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
662 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
664 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
665 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
666 /* Prior to Haswell and Bay Trail we have to use 4-component formats
667 * to fake 3-component ones. In particular, we do this for
668 * half-float and 8 and 16-bit integer formats. This means that the
669 * vertex element may poke over the end of the buffer by 2 bytes.
671 const unsigned padding
=
672 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
673 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
674 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
681 if (uses_draw_params
) {
682 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
683 brw
->draw
.draw_params_bo
,
684 brw
->draw
.draw_params_offset
,
685 brw
->draw
.draw_params_bo
->size
,
690 if (uses_derived_draw_params
) {
691 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
692 brw
->draw
.derived_draw_params_bo
,
693 brw
->draw
.derived_draw_params_offset
,
694 brw
->draw
.derived_draw_params_bo
->size
,
700 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
701 * presumably for VertexID/InstanceID.
704 assert(nr_elements
<= 34);
705 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
707 assert(nr_elements
<= 18);
710 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
711 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
713 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
714 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
715 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
716 uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
717 uint32_t comp0
= VFCOMP_STORE_SRC
;
718 uint32_t comp1
= VFCOMP_STORE_SRC
;
719 uint32_t comp2
= VFCOMP_STORE_SRC
;
720 uint32_t comp3
= VFCOMP_STORE_SRC
;
721 const unsigned num_uploads
= GEN_GEN
< 8 ?
722 uploads_needed(format
, input
->is_dual_slot
) : 1;
725 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
726 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
727 * element which has edge flag enabled."
729 assert(!(is_passthru_format(format
) && uses_edge_flag
));
732 /* The gen4 driver expects edgeflag to come in as a float, and passes
733 * that float on to the tests in the clipper. Mesa's current vertex
734 * attribute value for EdgeFlag is stored as a float, which works out.
735 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
736 * integer ubyte. Just rewrite that to convert to a float.
738 * Gen6+ passes edgeflag as sideband along with the vertex, instead
739 * of in the VUE. We have to upload it sideband as the last vertex
740 * element according to the B-Spec.
743 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
744 gen6_edgeflag_input
= input
;
749 for (unsigned c
= 0; c
< num_uploads
; c
++) {
750 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
751 downsize_format_if_needed(format
, c
);
752 /* If we need more that one upload, the offset stride would be 128
753 * bits (16 bytes), as for previous uploads we are using the full
755 const unsigned offset
= input
->offset
+ c
* 16;
757 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
758 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
759 upload_format_size(upload_format
) : glattrib
->Size
;
762 case 0: comp0
= VFCOMP_STORE_0
;
763 case 1: comp1
= VFCOMP_STORE_0
;
764 case 2: comp2
= VFCOMP_STORE_0
;
766 if (GEN_GEN
>= 8 && glattrib
->Doubles
) {
767 comp3
= VFCOMP_STORE_0
;
768 } else if (glattrib
->Integer
) {
769 comp3
= VFCOMP_STORE_1_INT
;
771 comp3
= VFCOMP_STORE_1_FP
;
778 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
780 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
781 * formats, 64-bit components are stored in the URB without any
782 * conversion. In this case, vertex elements must be written as 128
783 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
784 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
785 * component into the URB, Component 1 must be specified as
786 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
787 * order to output a 128-bit vertex element, or Components 1-3 must
788 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
789 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
790 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
793 if (glattrib
->Doubles
&& !input
->is_dual_slot
) {
794 /* Store vertex elements which correspond to double and dvec2 vertex
795 * shader inputs as 128-bit vertex elements, instead of 256-bits.
797 comp2
= VFCOMP_NOSTORE
;
798 comp3
= VFCOMP_NOSTORE
;
802 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
803 .VertexBufferIndex
= input
->buffer
,
805 .SourceElementFormat
= upload_format
,
806 .SourceElementOffset
= offset
,
807 .Component0Control
= comp0
,
808 .Component1Control
= comp1
,
809 .Component2Control
= comp2
,
810 .Component3Control
= comp3
,
812 .DestinationElementOffset
= i
* 4,
816 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
817 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
821 if (needs_sgvs_element
) {
822 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
824 .Component0Control
= VFCOMP_STORE_0
,
825 .Component1Control
= VFCOMP_STORE_0
,
826 .Component2Control
= VFCOMP_STORE_0
,
827 .Component3Control
= VFCOMP_STORE_0
,
829 .DestinationElementOffset
= i
* 4,
834 if (uses_draw_params
) {
835 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
836 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
837 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
838 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
841 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
842 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
843 if (uses_draw_params
) {
844 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
845 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
848 if (vs_prog_data
->uses_vertexid
)
849 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
851 if (vs_prog_data
->uses_instanceid
)
852 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
855 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
856 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
859 if (uses_derived_draw_params
) {
860 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
862 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
863 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
864 .Component0Control
= VFCOMP_STORE_SRC
,
865 .Component1Control
= VFCOMP_STORE_SRC
,
866 .Component2Control
= VFCOMP_STORE_0
,
867 .Component3Control
= VFCOMP_STORE_0
,
869 .DestinationElementOffset
= i
* 4,
873 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
874 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
878 if (gen6_edgeflag_input
) {
879 const struct gl_array_attributes
*glattrib
= gen6_edgeflag_input
->glattrib
;
880 const uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
882 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
884 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
885 .EdgeFlagEnable
= true,
886 .SourceElementFormat
= format
,
887 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
888 .Component0Control
= VFCOMP_STORE_SRC
,
889 .Component1Control
= VFCOMP_STORE_0
,
890 .Component2Control
= VFCOMP_STORE_0
,
891 .Component3Control
= VFCOMP_STORE_0
,
894 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
895 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
900 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
901 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
902 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
903 unsigned element_index
;
905 /* The edge flag element is reordered to be the last one in the code
906 * above so we need to compensate for that in the element indices used
909 if (input
== gen6_edgeflag_input
)
910 element_index
= nr_elements
- 1;
914 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
915 vfi
.VertexElementIndex
= element_index
;
916 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
917 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
921 if (vs_prog_data
->uses_drawid
) {
922 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
924 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
925 vfi
.VertexElementIndex
= element
;
931 static const struct brw_tracked_state
genX(vertices
) = {
933 .mesa
= _NEW_POLYGON
,
934 .brw
= BRW_NEW_BATCH
|
937 BRW_NEW_VS_PROG_DATA
,
939 .emit
= genX(emit_vertices
),
943 genX(emit_index_buffer
)(struct brw_context
*brw
)
945 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
947 if (index_buffer
== NULL
)
950 vf_invalidate_for_ib_48bit_transition(brw
);
952 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
953 #if GEN_GEN < 8 && !GEN_IS_HASWELL
954 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
956 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
958 /* The VF cache designers apparently cut corners, and made the cache
959 * only consider the bottom 32 bits of memory addresses. If you happen
960 * to have two index buffers which get placed exactly 4 GiB apart and
961 * use them in back-to-back draw calls, you can get collisions. To work
962 * around this problem, we restrict index buffers to the low 32 bits of
965 ib
.BufferStartingAddress
= ro_32_bo(brw
->ib
.bo
, 0);
967 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
968 ib
.BufferSize
= brw
->ib
.size
;
970 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
975 static const struct brw_tracked_state
genX(index_buffer
) = {
978 .brw
= BRW_NEW_BATCH
|
980 BRW_NEW_INDEX_BUFFER
,
982 .emit
= genX(emit_index_buffer
),
985 #if GEN_IS_HASWELL || GEN_GEN >= 8
987 genX(upload_cut_index
)(struct brw_context
*brw
)
989 const struct gl_context
*ctx
= &brw
->ctx
;
991 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
992 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
993 vf
.IndexedDrawCutIndexEnable
= true;
994 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
999 const struct brw_tracked_state
genX(cut_index
) = {
1001 .mesa
= _NEW_TRANSFORM
,
1002 .brw
= BRW_NEW_INDEX_BUFFER
,
1004 .emit
= genX(upload_cut_index
),
1010 * Determine the appropriate attribute override value to store into the
1011 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
1012 * override value contains two pieces of information: the location of the
1013 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
1014 * flag indicating whether to "swizzle" the attribute based on the direction
1015 * the triangle is facing.
1017 * If an attribute is "swizzled", then the given VUE location is used for
1018 * front-facing triangles, and the VUE location that immediately follows is
1019 * used for back-facing triangles. We use this to implement the mapping from
1020 * gl_FrontColor/gl_BackColor to gl_Color.
1022 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
1023 * being instructed to begin reading attribute data. It can be set to a
1024 * nonzero value to prevent the SF unit from wasting time reading elements of
1025 * the VUE that are not needed by the fragment shader. It is measured in
1026 * 256-bit increments.
1029 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
1030 const struct brw_vue_map
*vue_map
,
1031 int urb_entry_read_offset
, int fs_attr
,
1032 bool two_side_color
, uint32_t *max_source_attr
)
1034 /* Find the VUE slot for this attribute. */
1035 int slot
= vue_map
->varying_to_slot
[fs_attr
];
1037 /* Viewport and Layer are stored in the VUE header. We need to override
1038 * them to zero if earlier stages didn't write them, as GL requires that
1039 * they read back as zero when not explicitly set.
1041 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
1042 attr
->ComponentOverrideX
= true;
1043 attr
->ComponentOverrideW
= true;
1044 attr
->ConstantSource
= CONST_0000
;
1046 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
1047 attr
->ComponentOverrideY
= true;
1048 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
1049 attr
->ComponentOverrideZ
= true;
1054 /* If there was only a back color written but not front, use back
1055 * as the color instead of undefined
1057 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
1058 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
1059 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
1060 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
1063 /* This attribute does not exist in the VUE--that means that the vertex
1064 * shader did not write to it. This means that either:
1066 * (a) This attribute is a texture coordinate, and it is going to be
1067 * replaced with point coordinates (as a consequence of a call to
1068 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
1069 * hardware will ignore whatever attribute override we supply.
1071 * (b) This attribute is read by the fragment shader but not written by
1072 * the vertex shader, so its value is undefined. Therefore the
1073 * attribute override we supply doesn't matter.
1075 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
1076 * previous shader stage.
1078 * Note that we don't have to worry about the cases where the attribute
1079 * is gl_PointCoord or is undergoing point sprite coordinate
1080 * replacement, because in those cases, this function isn't called.
1082 * In case (c), we need to program the attribute overrides so that the
1083 * primitive ID will be stored in this slot. In every other case, the
1084 * attribute override we supply doesn't matter. So just go ahead and
1085 * program primitive ID in every case.
1087 attr
->ComponentOverrideW
= true;
1088 attr
->ComponentOverrideX
= true;
1089 attr
->ComponentOverrideY
= true;
1090 attr
->ComponentOverrideZ
= true;
1091 attr
->ConstantSource
= PRIM_ID
;
1095 /* Compute the location of the attribute relative to urb_entry_read_offset.
1096 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1097 * it counts for two 128-bit VUE slots.
1099 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1100 assert(source_attr
>= 0 && source_attr
< 32);
1102 /* If we are doing two-sided color, and the VUE slot following this one
1103 * represents a back-facing color, then we need to instruct the SF unit to
1104 * do back-facing swizzling.
1106 bool swizzling
= two_side_color
&&
1107 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1108 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1109 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1110 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1112 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1113 if (*max_source_attr
< source_attr
+ swizzling
)
1114 *max_source_attr
= source_attr
+ swizzling
;
1116 attr
->SourceAttribute
= source_attr
;
1118 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1123 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1124 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1125 uint32_t *point_sprite_enables
,
1126 uint32_t *urb_entry_read_length
,
1127 uint32_t *urb_entry_read_offset
)
1129 const struct gl_context
*ctx
= &brw
->ctx
;
1132 const struct gl_point_attrib
*point
= &ctx
->Point
;
1134 /* BRW_NEW_FRAGMENT_PROGRAM */
1135 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1137 /* BRW_NEW_FS_PROG_DATA */
1138 const struct brw_wm_prog_data
*wm_prog_data
=
1139 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1140 uint32_t max_source_attr
= 0;
1142 *point_sprite_enables
= 0;
1145 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1146 &brw
->vue_map_geom_out
);
1148 /* Each URB offset packs two varying slots */
1149 assert(first_slot
% 2 == 0);
1150 *urb_entry_read_offset
= first_slot
/ 2;
1152 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1153 * description of dw10 Point Sprite Texture Coordinate Enable:
1155 * "This field must be programmed to zero when non-point primitives
1158 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1159 * must be programmed to zero when rendering non-point primitives, but
1160 * the IvyBridge PRM does, and if we don't, we get garbage.
1162 * This is not required on Haswell, as the hardware ignores this state
1163 * when drawing non-points -- although we do still need to be careful to
1164 * correctly set the attr overrides.
1167 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1169 bool drawing_points
= brw_is_drawing_points(brw
);
1171 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1172 int input_index
= wm_prog_data
->urb_setup
[attr
];
1174 if (input_index
< 0)
1178 bool point_sprite
= false;
1179 if (drawing_points
) {
1180 if (point
->PointSprite
&&
1181 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1182 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1183 point_sprite
= true;
1186 if (attr
== VARYING_SLOT_PNTC
)
1187 point_sprite
= true;
1190 *point_sprite_enables
|= (1 << input_index
);
1193 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1194 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1196 if (!point_sprite
) {
1197 genX(get_attr_override
)(&attribute
,
1198 &brw
->vue_map_geom_out
,
1199 *urb_entry_read_offset
, attr
,
1200 _mesa_vertex_program_two_side_enabled(ctx
),
1204 /* The hardware can only do the overrides on 16 overrides at a
1205 * time, and the other up to 16 have to be lined up so that the
1206 * input index = the output index. We'll need to do some
1207 * tweaking to make sure that's the case.
1209 if (input_index
< 16)
1210 attr_overrides
[input_index
] = attribute
;
1212 assert(attribute
.SourceAttribute
== input_index
);
1215 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1216 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1218 * "This field should be set to the minimum length required to read the
1219 * maximum source attribute. The maximum source attribute is indicated
1220 * by the maximum value of the enabled Attribute # Source Attribute if
1221 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1222 * enable is not set.
1223 * read_length = ceiling((max_source_attr + 1) / 2)
1225 * [errata] Corruption/Hang possible if length programmed larger than
1228 * Similar text exists for Ivy Bridge.
1230 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1234 /* ---------------------------------------------------------------------- */
1237 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1239 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1241 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1245 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1247 struct gl_context
*ctx
= &brw
->ctx
;
1250 struct intel_renderbuffer
*depth_irb
=
1251 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1254 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1257 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1258 const int b
= stencil
->_BackFace
;
1260 if (depth
->Test
&& depth_irb
) {
1261 ds
->DepthTestEnable
= true;
1262 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1263 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1266 if (brw
->stencil_enabled
) {
1267 ds
->StencilTestEnable
= true;
1268 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1269 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1271 ds
->StencilTestFunction
=
1272 intel_translate_compare_func(stencil
->Function
[0]);
1274 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1275 ds
->StencilPassDepthPassOp
=
1276 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1277 ds
->StencilPassDepthFailOp
=
1278 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1280 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1282 if (brw
->stencil_two_sided
) {
1283 ds
->DoubleSidedStencilEnable
= true;
1284 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1285 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1287 ds
->BackfaceStencilTestFunction
=
1288 intel_translate_compare_func(stencil
->Function
[b
]);
1289 ds
->BackfaceStencilFailOp
=
1290 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1291 ds
->BackfaceStencilPassDepthPassOp
=
1292 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1293 ds
->BackfaceStencilPassDepthFailOp
=
1294 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1297 #if GEN_GEN <= 5 || GEN_GEN >= 9
1298 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1299 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1306 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1309 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1310 set_depth_stencil_bits(brw
, &wmds
);
1314 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1315 set_depth_stencil_bits(brw
, &ds
);
1318 /* Now upload a pointer to the indirect state */
1320 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1321 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1322 ptr
.DEPTH_STENCIL_STATEChange
= true;
1325 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1326 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1332 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1334 .mesa
= _NEW_BUFFERS
|
1337 .brw
= BRW_NEW_BLORP
|
1338 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1340 BRW_NEW_STATE_BASE_ADDRESS
),
1342 .emit
= genX(upload_depth_stencil_state
),
1346 /* ---------------------------------------------------------------------- */
1351 genX(upload_clip_state
)(struct brw_context
*brw
)
1353 struct gl_context
*ctx
= &brw
->ctx
;
1355 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1356 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1357 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1358 clip
.GRFRegisterCount
=
1359 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1360 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1361 clip
.SingleProgramFlow
= true;
1362 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1363 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1365 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1366 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1367 clip
.DispatchGRFStartRegisterForURBData
= 1;
1368 clip
.VertexURBEntryReadOffset
= 0;
1370 /* BRW_NEW_URB_FENCE */
1371 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1372 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1374 if (brw
->urb
.nr_clip_entries
>= 10) {
1375 /* Half of the URB entries go to each thread, and it has to be an
1378 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1380 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1381 * only 2 threads can output VUEs at a time.
1383 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1385 assert(brw
->urb
.nr_clip_entries
>= 5);
1386 clip
.MaximumNumberofThreads
= 1 - 1;
1389 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1390 clip
.UserClipFlagsMustClipEnable
= true;
1391 clip
.GuardbandClipTestEnable
= true;
1393 clip
.ClipperViewportStatePointer
=
1394 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1396 clip
.ScreenSpaceViewportXMin
= -1;
1397 clip
.ScreenSpaceViewportXMax
= 1;
1398 clip
.ScreenSpaceViewportYMin
= -1;
1399 clip
.ScreenSpaceViewportYMax
= 1;
1401 clip
.ViewportXYClipTestEnable
= true;
1402 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1404 /* _NEW_TRANSFORM */
1405 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1406 clip
.UserClipDistanceClipTestEnableBitmask
=
1407 ctx
->Transform
.ClipPlanesEnabled
;
1409 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1412 clip
.UserClipDistanceClipTestEnableBitmask
=
1413 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1416 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1417 clip
.APIMode
= APIMODE_D3D
;
1419 clip
.APIMode
= APIMODE_OGL
;
1421 clip
.GuardbandClipTestEnable
= true;
1423 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1426 clip
.NegativeWClipTestEnable
= true;
1431 const struct brw_tracked_state
genX(clip_state
) = {
1433 .mesa
= _NEW_TRANSFORM
|
1435 .brw
= BRW_NEW_BATCH
|
1437 BRW_NEW_CLIP_PROG_DATA
|
1438 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1439 BRW_NEW_PROGRAM_CACHE
|
1442 .emit
= genX(upload_clip_state
),
1448 genX(upload_clip_state
)(struct brw_context
*brw
)
1450 struct gl_context
*ctx
= &brw
->ctx
;
1453 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1455 /* BRW_NEW_FS_PROG_DATA */
1456 struct brw_wm_prog_data
*wm_prog_data
=
1457 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1459 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1460 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1462 if (wm_prog_data
->barycentric_interp_modes
&
1463 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1464 clip
.NonPerspectiveBarycentricEnable
= true;
1467 clip
.EarlyCullEnable
= true;
1471 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1473 if (ctx
->Polygon
.CullFlag
) {
1474 switch (ctx
->Polygon
.CullFaceMode
) {
1476 clip
.CullMode
= CULLMODE_FRONT
;
1479 clip
.CullMode
= CULLMODE_BACK
;
1481 case GL_FRONT_AND_BACK
:
1482 clip
.CullMode
= CULLMODE_BOTH
;
1485 unreachable("Should not get here: invalid CullFlag");
1488 clip
.CullMode
= CULLMODE_NONE
;
1493 clip
.UserClipDistanceCullTestEnableBitmask
=
1494 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1496 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1500 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1501 clip
.TriangleStripListProvokingVertexSelect
= 0;
1502 clip
.TriangleFanProvokingVertexSelect
= 1;
1503 clip
.LineStripListProvokingVertexSelect
= 0;
1505 clip
.TriangleStripListProvokingVertexSelect
= 2;
1506 clip
.TriangleFanProvokingVertexSelect
= 2;
1507 clip
.LineStripListProvokingVertexSelect
= 1;
1510 /* _NEW_TRANSFORM */
1511 clip
.UserClipDistanceClipTestEnableBitmask
=
1512 ctx
->Transform
.ClipPlanesEnabled
;
1515 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1518 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1519 clip
.APIMode
= APIMODE_D3D
;
1521 clip
.APIMode
= APIMODE_OGL
;
1523 clip
.GuardbandClipTestEnable
= true;
1525 /* BRW_NEW_VIEWPORT_COUNT */
1526 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1528 if (ctx
->RasterDiscard
) {
1529 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1531 perf_debug("Rasterizer discard is currently implemented via the "
1532 "clipper; having the GS not write primitives would "
1533 "likely be faster.\n");
1536 clip
.ClipMode
= CLIPMODE_NORMAL
;
1539 clip
.ClipEnable
= true;
1542 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1544 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1545 clip
.ViewportXYClipTestEnable
= true;
1547 clip
.MinimumPointWidth
= 0.125;
1548 clip
.MaximumPointWidth
= 255.875;
1549 clip
.MaximumVPIndex
= viewport_count
- 1;
1550 if (_mesa_geometric_layers(fb
) == 0)
1551 clip
.ForceZeroRTAIndexEnable
= true;
1555 static const struct brw_tracked_state
genX(clip_state
) = {
1557 .mesa
= _NEW_BUFFERS
|
1561 .brw
= BRW_NEW_BLORP
|
1563 BRW_NEW_FS_PROG_DATA
|
1564 BRW_NEW_GS_PROG_DATA
|
1565 BRW_NEW_VS_PROG_DATA
|
1566 BRW_NEW_META_IN_PROGRESS
|
1568 BRW_NEW_RASTERIZER_DISCARD
|
1569 BRW_NEW_TES_PROG_DATA
|
1570 BRW_NEW_VIEWPORT_COUNT
,
1572 .emit
= genX(upload_clip_state
),
1576 /* ---------------------------------------------------------------------- */
1579 genX(upload_sf
)(struct brw_context
*brw
)
1581 struct gl_context
*ctx
= &brw
->ctx
;
1586 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1587 UNUSED
const bool multisampled_fbo
=
1588 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1592 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1594 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1596 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1597 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1598 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1599 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1600 sf
.DispatchGRFStartRegisterForURBData
= 3;
1601 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1602 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1603 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1604 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1606 /* STATE_PREFETCH command description describes this state as being
1607 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1610 sf
.SetupViewportStateOffset
=
1611 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1613 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1615 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1616 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1618 sf
.MaximumNumberofThreads
=
1619 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1621 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1623 sf
.DestinationOriginHorizontalBias
= 0.5;
1624 sf
.DestinationOriginVerticalBias
= 0.5;
1626 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1627 sf
.StatisticsEnable
= true;
1629 sf
.ViewportTransformEnable
= true;
1633 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1638 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1640 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1641 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1642 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1644 switch (ctx
->Polygon
.FrontMode
) {
1646 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1649 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1652 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1655 unreachable("not reached");
1658 switch (ctx
->Polygon
.BackMode
) {
1660 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1663 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1666 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1669 unreachable("not reached");
1672 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1673 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1675 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1676 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1677 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1680 sf
.ScissorRectangleEnable
= true;
1682 if (ctx
->Polygon
.CullFlag
) {
1683 switch (ctx
->Polygon
.CullFaceMode
) {
1685 sf
.CullMode
= CULLMODE_FRONT
;
1688 sf
.CullMode
= CULLMODE_BACK
;
1690 case GL_FRONT_AND_BACK
:
1691 sf
.CullMode
= CULLMODE_BOTH
;
1694 unreachable("not reached");
1697 sf
.CullMode
= CULLMODE_NONE
;
1701 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1708 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1710 if (devinfo
->is_cherryview
)
1711 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1713 sf
.LineWidth
= brw_get_line_width(brw
);
1715 sf
.LineWidth
= brw_get_line_width(brw
);
1718 if (ctx
->Line
.SmoothFlag
) {
1719 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1721 sf
.AntiAliasingEnable
= true;
1725 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1726 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1727 /* Clamp to the hardware limits */
1728 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1730 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1731 if (use_state_point_size(brw
))
1732 sf
.PointWidthSource
= State
;
1735 /* _NEW_POINT | _NEW_MULTISAMPLE */
1736 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1737 !ctx
->Point
.PointSprite
)
1738 sf
.SmoothPointEnable
= true;
1743 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1745 const bool multisampled_fbo
=
1746 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1747 if (multisampled_fbo
)
1748 sf
.SmoothPointEnable
= false;
1751 #if GEN_IS_G4X || GEN_GEN >= 5
1752 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1756 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1757 sf
.TriangleStripListProvokingVertexSelect
= 2;
1758 sf
.TriangleFanProvokingVertexSelect
= 2;
1759 sf
.LineStripListProvokingVertexSelect
= 1;
1761 sf
.TriangleFanProvokingVertexSelect
= 1;
1765 /* BRW_NEW_FS_PROG_DATA */
1766 const struct brw_wm_prog_data
*wm_prog_data
=
1767 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1769 sf
.AttributeSwizzleEnable
= true;
1770 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1773 * Window coordinates in an FBO are inverted, which means point
1774 * sprite origin must be inverted, too.
1776 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1777 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1779 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1782 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1783 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1785 uint32_t urb_entry_read_length
;
1786 uint32_t urb_entry_read_offset
;
1787 uint32_t point_sprite_enables
;
1788 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1789 &urb_entry_read_length
,
1790 &urb_entry_read_offset
);
1791 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1792 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1793 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1794 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1799 static const struct brw_tracked_state
genX(sf_state
) = {
1801 .mesa
= _NEW_LIGHT
|
1805 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1806 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1807 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1808 .brw
= BRW_NEW_BLORP
|
1809 BRW_NEW_VUE_MAP_GEOM_OUT
|
1810 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1811 BRW_NEW_PROGRAM_CACHE
|
1812 BRW_NEW_SF_PROG_DATA
|
1816 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1817 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1818 BRW_NEW_GS_PROG_DATA
|
1820 BRW_NEW_TES_PROG_DATA
1822 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1823 BRW_NEW_FRAGMENT_PROGRAM
1826 .emit
= genX(upload_sf
),
1829 /* ---------------------------------------------------------------------- */
1832 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1834 struct gl_context
*ctx
= &brw
->ctx
;
1835 /* BRW_NEW_FRAGMENT_PROGRAM */
1836 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1840 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1841 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1842 uint64_t outputs_written
= fp
->info
.outputs_written
;
1845 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1846 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1847 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1856 genX(upload_wm
)(struct brw_context
*brw
)
1858 struct gl_context
*ctx
= &brw
->ctx
;
1860 /* BRW_NEW_FS_PROG_DATA */
1861 const struct brw_wm_prog_data
*wm_prog_data
=
1862 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1864 UNUSED
bool writes_depth
=
1865 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1866 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1867 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1870 /* We can't fold this into gen6_upload_wm_push_constants(), because
1871 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1872 * (3DSTATE_CONSTANT_PS [DevSNB]):
1874 * "[DevSNB]: This packet must be followed by WM_STATE."
1876 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1877 if (wm_prog_data
->base
.nr_params
!= 0) {
1878 wmcp
.Buffer0Valid
= true;
1879 /* Pointer to the WM constant buffer. Covered by the set of
1880 * state flags from gen6_upload_wm_push_constants.
1882 wmcp
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
1883 wmcp
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1889 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1891 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1892 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1896 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1897 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1898 wm
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1902 /* On gen4, we only have one shader kernel */
1903 if (brw_wm_state_has_ksp(wm
, 0)) {
1904 assert(brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0) == 0);
1905 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1906 wm
.GRFRegisterCount0
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 0);
1907 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1908 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 0);
1911 /* On gen5, we have multiple shader kernels but only one GRF start
1912 * register for all kernels
1914 wm
.KernelStartPointer0
= stage_state
->prog_offset
+
1915 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0);
1916 wm
.KernelStartPointer1
= stage_state
->prog_offset
+
1917 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 1);
1918 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1919 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 2);
1921 wm
.GRFRegisterCount0
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 0);
1922 wm
.GRFRegisterCount1
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 1);
1923 wm
.GRFRegisterCount2
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 2);
1925 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1926 wm_prog_data
->base
.dispatch_grf_start_reg
;
1928 /* Dispatch GRF Start should be the same for all shaders on gen5 */
1929 if (brw_wm_state_has_ksp(wm
, 1)) {
1930 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1931 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 1));
1933 if (brw_wm_state_has_ksp(wm
, 2)) {
1934 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1935 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 2));
1938 /* On gen6, we have multiple shader kernels and we no longer specify a
1939 * register count for each one.
1941 wm
.KernelStartPointer0
= stage_state
->prog_offset
+
1942 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0);
1943 wm
.KernelStartPointer1
= stage_state
->prog_offset
+
1944 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 1);
1945 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1946 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 2);
1948 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1949 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 0);
1950 wm
.DispatchGRFStartRegisterForConstantSetupData1
=
1951 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 1);
1952 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1953 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 2);
1957 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1958 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1959 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1960 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1961 wm
.SetupURBEntryReadOffset
= 0;
1962 wm
.EarlyDepthTestEnable
= true;
1966 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1967 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1969 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1970 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1972 if (stage_state
->sampler_count
)
1973 wm
.SamplerStatePointer
=
1974 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1976 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1977 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1980 if (ctx
->Polygon
.OffsetFill
) {
1981 wm
.GlobalDepthOffsetEnable
= true;
1982 /* Something weird going on with legacy_global_depth_bias,
1983 * offset_constant, scaling and MRD. This value passes glean
1984 * but gives some odd results elsewere (eg. the
1985 * quad-offset-units test).
1987 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1989 /* This is the only value that passes glean:
1991 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1994 wm
.DepthCoefficientURBReadOffset
= 1;
1997 /* BRW_NEW_STATS_WM */
1998 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
2001 if (wm_prog_data
->base
.use_alt_mode
)
2002 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2004 wm
.SamplerCount
= GEN_GEN
== 5 ?
2005 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
2007 wm
.BindingTableEntryCount
=
2008 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
2009 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
2012 wm
.DualSourceBlendEnable
=
2013 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
2014 ctx
->Color
.Blend
[0]._UsesDualSrc
;
2015 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2016 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2018 /* From the SNB PRM, volume 2 part 1, page 281:
2019 * "If the PS kernel does not need the Position XY Offsets
2020 * to compute a Position XY value, then this field should be
2021 * programmed to POSOFFSET_NONE."
2023 * "SW Recommendation: If the PS kernel needs the Position Offsets
2024 * to compute a Position XY value, this field should match Position
2025 * ZW Interpolation Mode to ensure a consistent position.xyzw
2027 * We only require XY sample offsets. So, this recommendation doesn't
2028 * look useful at the moment. We might need this in future.
2030 if (wm_prog_data
->uses_pos_offset
)
2031 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
2033 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
2036 if (wm_prog_data
->base
.total_scratch
) {
2037 wm
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
2038 wm
.PerThreadScratchSpace
=
2039 ffs(stage_state
->per_thread_scratch
) - 11;
2042 wm
.PixelShaderComputedDepth
= writes_depth
;
2046 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
2049 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
2054 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2057 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
2059 if (multisampled_fbo
) {
2060 /* _NEW_MULTISAMPLE */
2061 if (ctx
->Multisample
.Enabled
)
2062 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
2064 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
2066 if (wm_prog_data
->persample_dispatch
)
2067 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
2069 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
2071 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
2072 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
2075 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2076 if (wm_prog_data
->uses_kill
||
2077 _mesa_is_alpha_test_enabled(ctx
) ||
2078 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
2079 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
2080 wm
.PixelShaderKillsPixel
= true;
2083 /* _NEW_BUFFERS | _NEW_COLOR */
2084 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
2085 wm
.PixelShaderKillsPixel
||
2086 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
2087 wm
.ThreadDispatchEnable
= true;
2091 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2092 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
2095 /* The "UAV access enable" bits are unnecessary on HSW because they only
2096 * seem to have an effect on the HW-assisted coherency mechanism which we
2097 * don't need, and the rasterization-related UAV_ONLY flag and the
2098 * DISPATCH_ENABLE bit can be set independently from it.
2099 * C.f. gen8_upload_ps_extra().
2101 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
2105 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
2106 wm_prog_data
->has_side_effects
)
2112 /* BRW_NEW_FS_PROG_DATA */
2113 if (wm_prog_data
->early_fragment_tests
)
2114 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2115 else if (wm_prog_data
->has_side_effects
)
2116 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2121 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
2122 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
2123 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
2126 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
2131 static const struct brw_tracked_state
genX(wm_state
) = {
2135 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
2138 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2139 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2140 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2141 .brw
= BRW_NEW_BLORP
|
2142 BRW_NEW_FS_PROG_DATA
|
2143 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2144 BRW_NEW_FRAGMENT_PROGRAM
|
2145 BRW_NEW_PROGRAM_CACHE
|
2146 BRW_NEW_SAMPLER_STATE_TABLE
|
2149 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2151 .emit
= genX(upload_wm
),
2154 /* ---------------------------------------------------------------------- */
2156 /* We restrict scratch buffers to the bottom 32 bits of the address space
2157 * by using rw_32_bo().
2159 * General State Base Address is a bit broken. If the address + size as
2160 * seen by STATE_BASE_ADDRESS overflows 48 bits, the GPU appears to treat
2161 * all accesses to the buffer as being out of bounds and returns zero.
2164 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2165 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2166 pkt.SamplerCount = \
2167 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2168 pkt.BindingTableEntryCount = \
2169 stage_prog_data->binding_table.size_bytes / 4; \
2170 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2172 if (stage_prog_data->total_scratch) { \
2173 pkt.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0); \
2174 pkt.PerThreadScratchSpace = \
2175 ffs(stage_state->per_thread_scratch) - 11; \
2178 pkt.DispatchGRFStartRegisterForURBData = \
2179 stage_prog_data->dispatch_grf_start_reg; \
2180 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2181 pkt.prefix##URBEntryReadOffset = 0; \
2183 pkt.StatisticsEnable = true; \
2187 genX(upload_vs_state
)(struct brw_context
*brw
)
2189 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2190 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2191 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2193 /* BRW_NEW_VS_PROG_DATA */
2194 const struct brw_vue_prog_data
*vue_prog_data
=
2195 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2196 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2198 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2199 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2200 assert(GEN_GEN
< 11 ||
2201 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
2204 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2205 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2207 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2208 * command that causes the VS Function Enable to toggle. Pipeline
2209 * flush can be executed by sending a PIPE_CONTROL command with CS
2210 * stall bit set and a post sync operation.
2212 * We've already done such a flush at the start of state upload, so we
2213 * don't need to do another one here.
2215 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2216 if (stage_state
->push_const_size
!= 0) {
2217 cvs
.Buffer0Valid
= true;
2218 cvs
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
2219 cvs
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2224 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2225 gen7_emit_vs_workaround_flush(brw
);
2228 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2230 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2231 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2233 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2235 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2238 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2239 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2240 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2242 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2243 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2245 vs
.MaximumNumberofThreads
=
2246 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2248 vs
.StatisticsEnable
= false;
2249 vs
.SamplerStatePointer
=
2250 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2254 /* Force single program flow on Ironlake. We cannot reliably get
2255 * all applications working without it. See:
2256 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2258 * The most notable and reliably failing application is the Humus
2261 vs
.SingleProgramFlow
= true;
2262 vs
.SamplerCount
= 0; /* hardware requirement */
2266 vs
.SIMD8DispatchEnable
=
2267 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2269 vs
.UserClipDistanceCullTestEnableBitmask
=
2270 vue_prog_data
->cull_distance_mask
;
2275 /* Based on my reading of the simulator, the VS constants don't get
2276 * pulled into the VS FF unit until an appropriate pipeline flush
2277 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2278 * references to them into a little FIFO. The flushes are common,
2279 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2280 * the primitive to use the wrong constants. Then the FIFO
2281 * containing the constant setup gets added to again on the next
2282 * constants change, and eventually when a flush does happen the
2283 * unit is overwhelmed by constant changes and dies.
2285 * To avoid this, send a PIPE_CONTROL down the line that will
2286 * update the unit immediately loading the constants. The flush
2287 * type bits here were those set by the STATE_BASE_ADDRESS whose
2288 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2289 * bug reports that led to this workaround, and may be more than
2290 * what is strictly required to avoid the issue.
2292 brw_emit_pipe_control_flush(brw
,
2293 PIPE_CONTROL_DEPTH_STALL
|
2294 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2295 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2299 static const struct brw_tracked_state
genX(vs_state
) = {
2301 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2302 .brw
= BRW_NEW_BATCH
|
2305 BRW_NEW_VS_PROG_DATA
|
2306 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2307 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2308 BRW_NEW_PROGRAM_CACHE
|
2309 BRW_NEW_SAMPLER_STATE_TABLE
|
2313 .emit
= genX(upload_vs_state
),
2316 /* ---------------------------------------------------------------------- */
2319 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2321 struct gl_context
*ctx
= &brw
->ctx
;
2323 /* BRW_NEW_VIEWPORT_COUNT */
2324 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2326 struct GENX(CC_VIEWPORT
) ccv
;
2327 uint32_t cc_vp_offset
;
2329 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2332 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2333 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2334 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2335 if (ctx
->Transform
.DepthClamp
) {
2336 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2337 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2339 ccv
.MinimumDepth
= 0.0;
2340 ccv
.MaximumDepth
= 1.0;
2342 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2343 cc_map
+= GENX(CC_VIEWPORT_length
);
2347 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2348 ptr
.CCViewportPointer
= cc_vp_offset
;
2351 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2352 vp
.CCViewportStateChange
= 1;
2353 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2356 brw
->cc
.vp_offset
= cc_vp_offset
;
2357 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2361 const struct brw_tracked_state
genX(cc_vp
) = {
2363 .mesa
= _NEW_TRANSFORM
|
2365 .brw
= BRW_NEW_BATCH
|
2367 BRW_NEW_VIEWPORT_COUNT
,
2369 .emit
= genX(upload_cc_viewport
)
2372 /* ---------------------------------------------------------------------- */
2375 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2376 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2377 struct GENX(SCISSOR_RECT
) *sc
)
2381 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2382 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2383 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2384 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2385 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2387 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2388 /* If the scissor was out of bounds and got clamped to 0 width/height
2389 * at the bounds, the subtraction of 1 from maximums could produce a
2390 * negative number and thus not clip anything. Instead, just provide
2391 * a min > max scissor inside the bounds, which produces the expected
2394 sc
->ScissorRectangleXMin
= 1;
2395 sc
->ScissorRectangleXMax
= 0;
2396 sc
->ScissorRectangleYMin
= 1;
2397 sc
->ScissorRectangleYMax
= 0;
2398 } else if (render_to_fbo
) {
2399 /* texmemory: Y=0=bottom */
2400 sc
->ScissorRectangleXMin
= bbox
[0];
2401 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2402 sc
->ScissorRectangleYMin
= bbox
[2];
2403 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2405 /* memory: Y=0=top */
2406 sc
->ScissorRectangleXMin
= bbox
[0];
2407 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2408 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2409 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2415 genX(upload_scissor_state
)(struct brw_context
*brw
)
2417 struct gl_context
*ctx
= &brw
->ctx
;
2418 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2419 struct GENX(SCISSOR_RECT
) scissor
;
2420 uint32_t scissor_state_offset
;
2421 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2422 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2423 uint32_t *scissor_map
;
2425 /* BRW_NEW_VIEWPORT_COUNT */
2426 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2428 scissor_map
= brw_state_batch(
2429 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2430 32, &scissor_state_offset
);
2432 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2434 /* The scissor only needs to handle the intersection of drawable and
2435 * scissor rect. Clipping to the boundaries of static shared buffers
2436 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2438 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2439 * inclusive but max is exclusive.
2441 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2442 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2443 GENX(SCISSOR_RECT_pack
)(
2444 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2447 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2448 ptr
.ScissorRectPointer
= scissor_state_offset
;
2452 static const struct brw_tracked_state
genX(scissor_state
) = {
2454 .mesa
= _NEW_BUFFERS
|
2457 .brw
= BRW_NEW_BATCH
|
2459 BRW_NEW_VIEWPORT_COUNT
,
2461 .emit
= genX(upload_scissor_state
),
2465 /* ---------------------------------------------------------------------- */
2468 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2469 float m00
, float m11
, float m30
, float m31
,
2470 float *xmin
, float *xmax
,
2471 float *ymin
, float *ymax
)
2473 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2474 * Strips and Fans documentation:
2476 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2477 * fixed-point "guardband" range supported by the rasterization hardware"
2481 * "In almost all circumstances, if an object’s vertices are actually
2482 * modified by this clamping (i.e., had X or Y coordinates outside of
2483 * the guardband extent the rendered object will not match the intended
2484 * result. Therefore software should take steps to ensure that this does
2485 * not happen - e.g., by clipping objects such that they do not exceed
2486 * these limits after the Drawing Rectangle is applied."
2488 * I believe the fundamental restriction is that the rasterizer (in
2489 * the SF/WM stages) have a limit on the number of pixels that can be
2490 * rasterized. We need to ensure any coordinates beyond the rasterizer
2491 * limit are handled by the clipper. So effectively that limit becomes
2492 * the clipper's guardband size.
2494 * It goes on to say:
2496 * "In addition, in order to be correctly rendered, objects must have a
2497 * screenspace bounding box not exceeding 8K in the X or Y direction.
2498 * This additional restriction must also be comprehended by software,
2499 * i.e., enforced by use of clipping."
2501 * This makes no sense. Gen7+ hardware supports 16K render targets,
2502 * and you definitely need to be able to draw polygons that fill the
2503 * surface. Our assumption is that the rasterizer was limited to 8K
2504 * on Sandybridge, which only supports 8K surfaces, and it was actually
2505 * increased to 16K on Ivybridge and later.
2507 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2509 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2511 if (m00
!= 0 && m11
!= 0) {
2512 /* First, we compute the screen-space render area */
2513 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2514 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2515 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2516 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2518 /* We want the guardband to be centered on that */
2519 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2520 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2521 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2522 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2524 /* Now we need it in native device coordinates */
2525 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2526 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2527 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2528 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2530 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2531 * flipped upside-down. X should be fine though.
2533 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2534 *xmin
= ndc_gb_xmin
;
2535 *xmax
= ndc_gb_xmax
;
2536 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2537 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2539 /* The viewport scales to 0, so nothing will be rendered. */
2548 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2550 struct gl_context
*ctx
= &brw
->ctx
;
2551 float y_scale
, y_bias
;
2553 /* BRW_NEW_VIEWPORT_COUNT */
2554 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2557 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2558 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2559 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2563 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2564 uint32_t sf_clip_vp_offset
;
2565 uint32_t *sf_clip_map
=
2566 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2567 64, &sf_clip_vp_offset
);
2569 struct GENX(SF_VIEWPORT
) sfv
;
2570 struct GENX(CLIP_VIEWPORT
) clv
;
2571 uint32_t sf_vp_offset
, clip_vp_offset
;
2573 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2575 uint32_t *clip_map
=
2576 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2577 32, &clip_vp_offset
);
2581 if (render_to_fbo
) {
2586 y_bias
= (float)fb_height
;
2589 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2590 /* _NEW_VIEWPORT: Guardband Clipping */
2591 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2592 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2594 sfv
.ViewportMatrixElementm00
= scale
[0];
2595 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2596 sfv
.ViewportMatrixElementm22
= scale
[2],
2597 sfv
.ViewportMatrixElementm30
= translate
[0],
2598 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2599 sfv
.ViewportMatrixElementm32
= translate
[2],
2600 brw_calculate_guardband_size(fb_width
, fb_height
,
2601 sfv
.ViewportMatrixElementm00
,
2602 sfv
.ViewportMatrixElementm11
,
2603 sfv
.ViewportMatrixElementm30
,
2604 sfv
.ViewportMatrixElementm31
,
2605 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2608 clv
.XMinClipGuardband
= gb_xmin
;
2609 clv
.XMaxClipGuardband
= gb_xmax
;
2610 clv
.YMinClipGuardband
= gb_ymin
;
2611 clv
.YMaxClipGuardband
= gb_ymax
;
2614 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2615 &sfv
.ScissorRectangle
);
2617 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2618 * The hardware will take the intersection of the drawing rectangle,
2619 * scissor rectangle, and the viewport extents. However, emitting
2620 * 3DSTATE_DRAWING_RECTANGLE is expensive since it requires a full
2621 * pipeline stall so we're better off just being a little more clever
2622 * with our viewport so we can emit it once at context creation time.
2624 const float viewport_Xmin
= MAX2(ctx
->ViewportArray
[i
].X
, 0);
2625 const float viewport_Ymin
= MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2626 const float viewport_Xmax
=
2627 MIN2(ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
, fb_width
);
2628 const float viewport_Ymax
=
2629 MIN2(ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
, fb_height
);
2631 if (render_to_fbo
) {
2632 sfv
.XMinViewPort
= viewport_Xmin
;
2633 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2634 sfv
.YMinViewPort
= viewport_Ymin
;
2635 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2637 sfv
.XMinViewPort
= viewport_Xmin
;
2638 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2639 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2640 sfv
.YMaxViewPort
= fb_height
- viewport_Ymin
- 1;
2645 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2646 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2648 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2649 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2650 sf_map
+= GENX(SF_VIEWPORT_length
);
2651 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2656 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2657 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2660 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2661 vp
.SFViewportStateChange
= 1;
2662 vp
.CLIPViewportStateChange
= 1;
2663 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2664 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2667 brw
->sf
.vp_offset
= sf_vp_offset
;
2668 brw
->clip
.vp_offset
= clip_vp_offset
;
2669 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2673 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2675 .mesa
= _NEW_BUFFERS
|
2677 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2678 .brw
= BRW_NEW_BATCH
|
2680 BRW_NEW_VIEWPORT_COUNT
,
2682 .emit
= genX(upload_sf_clip_viewport
),
2685 /* ---------------------------------------------------------------------- */
2688 genX(upload_gs_state
)(struct brw_context
*brw
)
2690 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2691 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2692 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2693 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2694 /* BRW_NEW_GEOMETRY_PROGRAM */
2695 bool active
= GEN_GEN
>= 6 && gs_prog
;
2697 /* BRW_NEW_GS_PROG_DATA */
2698 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2699 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2700 brw_vue_prog_data(stage_prog_data
);
2702 const struct brw_gs_prog_data
*gs_prog_data
=
2703 brw_gs_prog_data(stage_prog_data
);
2707 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2708 if (active
&& stage_state
->push_const_size
!= 0) {
2709 cgs
.Buffer0Valid
= true;
2710 cgs
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
2711 cgs
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2716 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2718 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2719 * Geometry > Geometry Shader > State:
2721 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2722 * whole fixed function pipeline when the GS enable changes value in
2725 * The hardware architects have clarified that in this context "flush the
2726 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2729 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2730 gen7_emit_cs_stall_flush(brw
);
2734 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2736 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2737 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2742 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2745 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2746 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2747 gs
.ControlDataHeaderSize
=
2748 gs_prog_data
->control_data_header_size_hwords
;
2750 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2751 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2753 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2755 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2758 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2759 * Ivy Bridge and Haswell.
2761 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2762 * strip to be delivered to the geometry shader in an order that does
2763 * not strictly follow the OpenGL spec, but preserves triangle
2764 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2765 * the geometry shader sees triangles:
2767 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2769 * (Clearing the bit is even worse, because it fails to preserve
2772 * Triangle strips with adjacency always ordered in a way that preserves
2773 * triangle orientation but does not strictly follow the OpenGL spec,
2774 * regardless of the setting of this bit.
2776 * On Haswell, both triangle strips and triangle strips with adjacency
2777 * are always ordered in a way that preserves triangle orientation.
2778 * Setting this bit causes the ordering to strictly follow the OpenGL
2781 * So in either case we want to set the bit. Unfortunately on Ivy
2782 * Bridge this will get the order close to correct but not perfect.
2784 gs
.ReorderMode
= TRAILING
;
2785 gs
.MaximumNumberofThreads
=
2786 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2787 : (devinfo
->max_gs_threads
- 1);
2790 gs
.SOStatisticsEnable
= true;
2791 if (gs_prog
->info
.has_transform_feedback_varyings
)
2792 gs
.SVBIPayloadEnable
= true;
2794 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2795 * was previously done for gen6.
2797 * TODO: test with both disabled to see if the HW is behaving
2798 * as expected, like in gen7.
2800 gs
.SingleProgramFlow
= true;
2801 gs
.VectorMaskEnable
= true;
2805 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2807 if (gs_prog_data
->static_vertex_count
!= -1) {
2808 gs
.StaticOutput
= true;
2809 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2811 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2813 gs
.UserClipDistanceCullTestEnableBitmask
=
2814 vue_prog_data
->cull_distance_mask
;
2816 const int urb_entry_write_offset
= 1;
2817 const uint32_t urb_entry_output_length
=
2818 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2819 urb_entry_write_offset
;
2821 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2822 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2828 if (!active
&& brw
->ff_gs
.prog_active
) {
2829 /* In gen6, transform feedback for the VS stage is done with an
2830 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2833 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2834 gs
.SingleProgramFlow
= true;
2835 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2836 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2839 gs
.GRFRegisterCount
=
2840 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2841 /* BRW_NEW_URB_FENCE */
2842 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2843 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2844 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2845 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2848 gs
.VectorMaskEnable
= true;
2849 gs
.SVBIPayloadEnable
= true;
2850 gs
.SVBIPostIncrementEnable
= true;
2851 gs
.SVBIPostIncrementValue
=
2852 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2853 gs
.SOStatisticsEnable
= true;
2854 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2858 if (!active
&& !brw
->ff_gs
.prog_active
) {
2860 gs
.DispatchGRFStartRegisterForURBData
= 1;
2862 gs
.IncludeVertexHandles
= true;
2868 gs
.StatisticsEnable
= true;
2870 #if GEN_GEN == 5 || GEN_GEN == 6
2871 gs
.RenderingEnabled
= true;
2874 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2879 brw
->gs
.enabled
= active
;
2883 static const struct brw_tracked_state
genX(gs_state
) = {
2885 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2886 .brw
= BRW_NEW_BATCH
|
2888 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2889 BRW_NEW_PROGRAM_CACHE
|
2891 BRW_NEW_VIEWPORT_COUNT
2893 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2894 BRW_NEW_GEOMETRY_PROGRAM
|
2895 BRW_NEW_GS_PROG_DATA
2897 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2899 .emit
= genX(upload_gs_state
),
2902 /* ---------------------------------------------------------------------- */
2904 UNUSED
static GLenum
2905 fix_dual_blend_alpha_to_one(GLenum function
)
2911 case GL_ONE_MINUS_SRC1_ALPHA
:
2918 #define blend_factor(x) brw_translate_blend_factor(x)
2919 #define blend_eqn(x) brw_translate_blend_equation(x)
2922 * Modify blend function to force destination alpha to 1.0
2924 * If \c function specifies a blend function that uses destination alpha,
2925 * replace it with a function that hard-wires destination alpha to 1.0. This
2926 * is used when rendering to xRGB targets.
2929 brw_fix_xRGB_alpha(GLenum function
)
2935 case GL_ONE_MINUS_DST_ALPHA
:
2936 case GL_SRC_ALPHA_SATURATE
:
2944 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2946 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2950 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2953 struct gl_context
*ctx
= &brw
->ctx
;
2956 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2958 bool independent_alpha_blend
= false;
2960 /* Used for implementing the following bit of GL_EXT_texture_integer:
2961 * "Per-fragment operations that require floating-point color
2962 * components, including multisample alpha operations, alpha test,
2963 * blending, and dithering, have no effect when the corresponding
2964 * colors are written to an integer color buffer."
2966 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2968 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2969 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2972 if (ctx
->Color
.ColorLogicOpEnabled
) {
2973 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2974 : GL_UNSIGNED_NORMALIZED
;
2975 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2976 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2977 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2979 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2980 _mesa_enum_to_string(rb_type
));
2981 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2982 entry
->LogicOpEnable
= true;
2983 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2985 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2986 && (GEN_GEN
<= 5 || !integer
)) {
2987 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2988 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2989 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2990 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2991 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2992 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2994 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2995 srcRGB
= dstRGB
= GL_ONE
;
2997 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2998 srcA
= dstA
= GL_ONE
;
3000 /* Due to hardware limitations, the destination may have information
3001 * in an alpha channel even when the format specifies no alpha
3002 * channel. In order to avoid getting any incorrect blending due to
3003 * that alpha channel, coerce the blend factors to values that will
3004 * not read the alpha channel, but will instead use the correct
3005 * implicit value for alpha.
3007 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
3008 GL_TEXTURE_ALPHA_TYPE
)) {
3009 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
3010 srcA
= brw_fix_xRGB_alpha(srcA
);
3011 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
3012 dstA
= brw_fix_xRGB_alpha(dstA
);
3015 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
3016 * "If Dual Source Blending is enabled, this bit must be disabled."
3018 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
3019 * and leave it enabled anyway.
3021 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
3022 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
3023 srcA
= fix_dual_blend_alpha_to_one(srcA
);
3024 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
3025 dstA
= fix_dual_blend_alpha_to_one(dstA
);
3028 entry
->ColorBufferBlendEnable
= true;
3029 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
3030 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
3031 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
3032 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
3033 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
3034 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
3036 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
3037 independent_alpha_blend
= true;
3040 return independent_alpha_blend
;
3045 genX(upload_blend_state
)(struct brw_context
*brw
)
3047 struct gl_context
*ctx
= &brw
->ctx
;
3050 /* We need at least one BLEND_STATE written, because we might do
3051 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
3052 * for computed depth or alpha test), which will do an FB write
3053 * with render target 0, which will reference BLEND_STATE[0] for
3054 * alpha test enable.
3056 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
3057 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
3058 nr_draw_buffers
= 1;
3060 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
3062 size
+= GENX(BLEND_STATE_length
) * 4;
3065 uint32_t *blend_map
;
3066 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
3069 struct GENX(BLEND_STATE
) blend
= { 0 };
3072 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3073 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3076 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
3077 * "If drawbuffer zero is not NONE and the buffer it references has an
3078 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
3079 * operations are skipped."
3081 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
3082 /* _NEW_MULTISAMPLE */
3083 if (_mesa_is_multisample_enabled(ctx
)) {
3084 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
3085 blend
.AlphaToCoverageEnable
= true;
3086 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
3088 if (ctx
->Multisample
.SampleAlphaToOne
)
3089 blend
.AlphaToOneEnable
= true;
3093 if (ctx
->Color
.AlphaEnabled
) {
3094 blend
.AlphaTestEnable
= true;
3095 blend
.AlphaTestFunction
=
3096 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3099 if (ctx
->Color
.DitherFlag
) {
3100 blend
.ColorDitherEnable
= true;
3105 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3106 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3110 blend
.IndependentAlphaBlendEnable
=
3111 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
3112 blend
.IndependentAlphaBlendEnable
;
3114 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
3115 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
3117 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
3118 * clamping in the fragment shader. For its clamping of
3119 * blending, the spec says:
3121 * "RESOLVED: For fixed-point color buffers, the inputs and
3122 * the result of the blending equation are clamped. For
3123 * floating-point color buffers, no clamping occurs."
3125 * So, generally, we want clamping to the render target's range.
3126 * And, good news, the hardware tables for both pre- and
3127 * post-blend color clamping are either ignored, or any are
3128 * allowed, or clamping is required but RT range clamping is a
3131 entry
.PreBlendColorClampEnable
= true;
3132 entry
.PostBlendColorClampEnable
= true;
3133 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
3135 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
3136 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
3137 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
3138 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
3141 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
3143 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3149 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3153 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3154 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3155 ptr
.BLEND_STATEChange
= true;
3158 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3159 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3161 ptr
.BlendStatePointerValid
= true;
3167 static const struct brw_tracked_state
genX(blend_state
) = {
3169 .mesa
= _NEW_BUFFERS
|
3172 .brw
= BRW_NEW_BATCH
|
3174 BRW_NEW_STATE_BASE_ADDRESS
,
3176 .emit
= genX(upload_blend_state
),
3180 /* ---------------------------------------------------------------------- */
3183 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3184 [MESA_SHADER_VERTEX
] = 21,
3185 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3186 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3187 [MESA_SHADER_GEOMETRY
] = 22,
3188 [MESA_SHADER_FRAGMENT
] = 23,
3189 [MESA_SHADER_COMPUTE
] = 0,
3193 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3195 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3196 struct gl_context
*ctx
= &brw
->ctx
;
3198 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3200 struct brw_stage_state
*stage_states
[] = {
3208 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3209 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3210 gen7_emit_vs_workaround_flush(brw
);
3212 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3213 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3214 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3216 if (!stage_state
->push_constants_dirty
)
3219 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3220 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3221 if (stage_state
->prog_data
) {
3222 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3223 /* The Skylake PRM contains the following restriction:
3225 * "The driver must ensure The following case does not occur
3226 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3227 * buffer 3 read length equal to zero committed followed by a
3228 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3231 * To avoid this, we program the buffers in the highest slots.
3232 * This way, slot 0 is only used if slot 3 is also used.
3236 for (int i
= 3; i
>= 0; i
--) {
3237 const struct brw_ubo_range
*range
=
3238 &stage_state
->prog_data
->ubo_ranges
[i
];
3240 if (range
->length
== 0)
3243 const struct gl_uniform_block
*block
=
3244 prog
->sh
.UniformBlocks
[range
->block
];
3245 const struct gl_buffer_binding
*binding
=
3246 &ctx
->UniformBufferBindings
[block
->Binding
];
3248 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3249 static unsigned msg_id
= 0;
3250 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3251 MESA_DEBUG_TYPE_UNDEFINED
,
3252 MESA_DEBUG_SEVERITY_HIGH
,
3253 "UBO %d unbound, %s shader uniform data "
3254 "will be undefined.",
3256 _mesa_shader_stage_to_string(stage
));
3260 assert(binding
->Offset
% 32 == 0);
3262 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3263 intel_buffer_object(binding
->BufferObject
),
3264 binding
->Offset
, range
->length
* 32, false);
3266 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3267 pkt
.ConstantBody
.Buffer
[n
] =
3268 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3272 if (stage_state
->push_const_size
> 0) {
3274 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3275 pkt
.ConstantBody
.Buffer
[n
] =
3276 ro_bo(stage_state
->push_const_bo
,
3277 stage_state
->push_const_offset
);
3280 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3281 pkt
.ConstantBody
.Buffer
[0].offset
=
3282 stage_state
->push_const_offset
| mocs
;
3287 stage_state
->push_constants_dirty
= false;
3288 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3292 const struct brw_tracked_state
genX(push_constant_packets
) = {
3295 .brw
= BRW_NEW_DRAW_CALL
,
3297 .emit
= genX(upload_push_constant_packets
),
3303 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3305 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3307 /* BRW_NEW_VERTEX_PROGRAM */
3308 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3309 /* BRW_NEW_VS_PROG_DATA */
3310 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3312 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3315 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3317 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3319 .brw
= BRW_NEW_BATCH
|
3321 BRW_NEW_VERTEX_PROGRAM
|
3322 BRW_NEW_VS_PROG_DATA
,
3324 .emit
= genX(upload_vs_push_constants
),
3328 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3330 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3332 /* BRW_NEW_GEOMETRY_PROGRAM */
3333 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3335 /* BRW_NEW_GS_PROG_DATA */
3336 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3338 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3341 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3343 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3345 .brw
= BRW_NEW_BATCH
|
3347 BRW_NEW_GEOMETRY_PROGRAM
|
3348 BRW_NEW_GS_PROG_DATA
,
3350 .emit
= genX(upload_gs_push_constants
),
3354 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3356 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3357 /* BRW_NEW_FRAGMENT_PROGRAM */
3358 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3359 /* BRW_NEW_FS_PROG_DATA */
3360 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3362 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3365 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3367 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3368 .brw
= BRW_NEW_BATCH
|
3370 BRW_NEW_FRAGMENT_PROGRAM
|
3371 BRW_NEW_FS_PROG_DATA
,
3373 .emit
= genX(upload_wm_push_constants
),
3377 /* ---------------------------------------------------------------------- */
3381 genX(determine_sample_mask
)(struct brw_context
*brw
)
3383 struct gl_context
*ctx
= &brw
->ctx
;
3384 float coverage
= 1.0f
;
3385 float coverage_invert
= false;
3386 unsigned sample_mask
= ~0u;
3388 /* BRW_NEW_NUM_SAMPLES */
3389 unsigned num_samples
= brw
->num_samples
;
3391 if (_mesa_is_multisample_enabled(ctx
)) {
3392 if (ctx
->Multisample
.SampleCoverage
) {
3393 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3394 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3396 if (ctx
->Multisample
.SampleMask
) {
3397 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3401 if (num_samples
> 1) {
3402 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3403 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3404 if (coverage_invert
)
3405 coverage_bits
^= (1 << num_samples
) - 1;
3406 return coverage_bits
& sample_mask
;
3413 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3414 unsigned num_samples
)
3416 unsigned log2_samples
= ffs(num_samples
) - 1;
3418 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3419 multi
.PixelLocation
= CENTER
;
3420 multi
.NumberofMultisamples
= log2_samples
;
3422 GEN_SAMPLE_POS_4X(multi
.Sample
);
3424 switch (num_samples
) {
3426 GEN_SAMPLE_POS_1X(multi
.Sample
);
3429 GEN_SAMPLE_POS_2X(multi
.Sample
);
3432 GEN_SAMPLE_POS_4X(multi
.Sample
);
3435 GEN_SAMPLE_POS_8X(multi
.Sample
);
3445 genX(upload_multisample_state
)(struct brw_context
*brw
)
3447 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3449 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3451 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3452 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3456 static const struct brw_tracked_state
genX(multisample_state
) = {
3458 .mesa
= _NEW_MULTISAMPLE
|
3459 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3460 .brw
= BRW_NEW_BLORP
|
3462 BRW_NEW_NUM_SAMPLES
,
3464 .emit
= genX(upload_multisample_state
)
3468 /* ---------------------------------------------------------------------- */
3471 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3473 struct gl_context
*ctx
= &brw
->ctx
;
3475 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3477 cc
.IndependentAlphaBlendEnable
=
3478 set_blend_entry_bits(brw
, &cc
, 0, false);
3479 set_depth_stencil_bits(brw
, &cc
);
3481 if (ctx
->Color
.AlphaEnabled
&&
3482 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3483 cc
.AlphaTestEnable
= true;
3484 cc
.AlphaTestFunction
=
3485 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3488 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3490 cc
.StatisticsEnable
= brw
->stats_wm
;
3492 cc
.CCViewportStatePointer
=
3493 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3496 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3497 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3498 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3499 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3503 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3504 cc
.BackfaceStencilReferenceValue
=
3505 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3511 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3512 ctx
->Color
.AlphaRef
);
3516 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3517 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3519 ptr
.ColorCalcStatePointerValid
= true;
3523 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3527 static const struct brw_tracked_state
genX(color_calc_state
) = {
3529 .mesa
= _NEW_COLOR
|
3531 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3534 .brw
= BRW_NEW_BATCH
|
3536 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3538 : BRW_NEW_CC_STATE
|
3539 BRW_NEW_STATE_BASE_ADDRESS
),
3541 .emit
= genX(upload_color_calc_state
),
3545 /* ---------------------------------------------------------------------- */
3549 genX(upload_sbe
)(struct brw_context
*brw
)
3551 struct gl_context
*ctx
= &brw
->ctx
;
3552 /* BRW_NEW_FRAGMENT_PROGRAM */
3553 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3554 /* BRW_NEW_FS_PROG_DATA */
3555 const struct brw_wm_prog_data
*wm_prog_data
=
3556 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3558 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3560 #define attr_overrides sbe.Attribute
3562 uint32_t urb_entry_read_length
;
3563 uint32_t urb_entry_read_offset
;
3564 uint32_t point_sprite_enables
;
3566 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3567 sbe
.AttributeSwizzleEnable
= true;
3568 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3571 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3575 * Window coordinates in an FBO are inverted, which means point
3576 * sprite origin must be inverted.
3578 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3579 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3581 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3583 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3584 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3585 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3586 * BRW_NEW_VUE_MAP_GEOM_OUT
3588 genX(calculate_attr_overrides
)(brw
,
3590 &point_sprite_enables
,
3591 &urb_entry_read_length
,
3592 &urb_entry_read_offset
);
3594 /* Typically, the URB entry read length and offset should be programmed
3595 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3596 * stage which produces geometry. However, we don't know the proper
3597 * value until we call calculate_attr_overrides().
3599 * To fit with our existing code, we override the inherited values and
3600 * specify it here directly, as we did on previous generations.
3602 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3603 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3604 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3605 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3608 sbe
.ForceVertexURBEntryReadLength
= true;
3609 sbe
.ForceVertexURBEntryReadOffset
= true;
3613 /* prepare the active component dwords */
3614 for (int i
= 0; i
< 32; i
++)
3615 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3620 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3621 for (int i
= 0; i
< 16; i
++)
3622 sbes
.Attribute
[i
] = attr_overrides
[i
];
3626 #undef attr_overrides
3629 static const struct brw_tracked_state
genX(sbe_state
) = {
3631 .mesa
= _NEW_BUFFERS
|
3636 .brw
= BRW_NEW_BLORP
|
3638 BRW_NEW_FRAGMENT_PROGRAM
|
3639 BRW_NEW_FS_PROG_DATA
|
3640 BRW_NEW_GS_PROG_DATA
|
3641 BRW_NEW_TES_PROG_DATA
|
3642 BRW_NEW_VUE_MAP_GEOM_OUT
|
3643 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3646 .emit
= genX(upload_sbe
),
3650 /* ---------------------------------------------------------------------- */
3654 * Outputs the 3DSTATE_SO_DECL_LIST command.
3656 * The data output is a series of 64-bit entries containing a SO_DECL per
3657 * stream. We only have one stream of rendering coming out of the GS unit, so
3658 * we only emit stream 0 (low 16 bits) SO_DECLs.
3661 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3662 const struct brw_vue_map
*vue_map
)
3664 struct gl_context
*ctx
= &brw
->ctx
;
3665 /* BRW_NEW_TRANSFORM_FEEDBACK */
3666 struct gl_transform_feedback_object
*xfb_obj
=
3667 ctx
->TransformFeedback
.CurrentObject
;
3668 const struct gl_transform_feedback_info
*linked_xfb_info
=
3669 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3670 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3671 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3672 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3673 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3675 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3677 memset(so_decl
, 0, sizeof(so_decl
));
3679 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3680 * command feels strange -- each dword pair contains a SO_DECL per stream.
3682 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3683 const struct gl_transform_feedback_output
*output
=
3684 &linked_xfb_info
->Outputs
[i
];
3685 const int buffer
= output
->OutputBuffer
;
3686 const int varying
= output
->OutputRegister
;
3687 const unsigned stream_id
= output
->StreamId
;
3688 assert(stream_id
< MAX_VERTEX_STREAMS
);
3690 buffer_mask
[stream_id
] |= 1 << buffer
;
3692 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3694 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3695 * array. Instead, it simply increments DstOffset for the following
3696 * input by the number of components that should be skipped.
3698 * Our hardware is unusual in that it requires us to program SO_DECLs
3699 * for fake "hole" components, rather than simply taking the offset
3700 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3701 * program as many size = 4 holes as we can, then a final hole to
3702 * accommodate the final 1, 2, or 3 remaining.
3704 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3706 while (skip_components
> 0) {
3707 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3709 .OutputBufferSlot
= output
->OutputBuffer
,
3710 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3712 skip_components
-= 4;
3715 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3717 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3718 .OutputBufferSlot
= output
->OutputBuffer
,
3719 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3721 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3724 if (decls
[stream_id
] > max_decls
)
3725 max_decls
= decls
[stream_id
];
3729 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3730 .StreamtoBufferSelects0
= buffer_mask
[0],
3731 .StreamtoBufferSelects1
= buffer_mask
[1],
3732 .StreamtoBufferSelects2
= buffer_mask
[2],
3733 .StreamtoBufferSelects3
= buffer_mask
[3],
3734 .NumEntries0
= decls
[0],
3735 .NumEntries1
= decls
[1],
3736 .NumEntries2
= decls
[2],
3737 .NumEntries3
= decls
[3]);
3739 for (int i
= 0; i
< max_decls
; i
++) {
3740 GENX(SO_DECL_ENTRY_pack
)(
3741 brw
, dw
+ 2 + i
* 2,
3742 &(struct GENX(SO_DECL_ENTRY
)) {
3743 .Stream0Decl
= so_decl
[0][i
],
3744 .Stream1Decl
= so_decl
[1][i
],
3745 .Stream2Decl
= so_decl
[2][i
],
3746 .Stream3Decl
= so_decl
[3][i
],
3752 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3754 struct gl_context
*ctx
= &brw
->ctx
;
3755 /* BRW_NEW_TRANSFORM_FEEDBACK */
3756 struct gl_transform_feedback_object
*xfb_obj
=
3757 ctx
->TransformFeedback
.CurrentObject
;
3759 const struct gl_transform_feedback_info
*linked_xfb_info
=
3760 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3762 struct brw_transform_feedback_object
*brw_obj
=
3763 (struct brw_transform_feedback_object
*) xfb_obj
;
3764 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3767 /* Set up the up to 4 output buffers. These are the ranges defined in the
3768 * gl_transform_feedback_object.
3770 for (int i
= 0; i
< 4; i
++) {
3771 struct intel_buffer_object
*bufferobj
=
3772 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3775 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3776 sob
.SOBufferIndex
= i
;
3781 uint32_t start
= xfb_obj
->Offset
[i
];
3782 assert(start
% 4 == 0);
3783 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3785 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3786 assert(end
<= bo
->size
);
3788 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3789 sob
.SOBufferIndex
= i
;
3791 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3793 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3794 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3796 sob
.SOBufferEnable
= true;
3797 sob
.StreamOffsetWriteEnable
= true;
3798 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3799 sob
.SOBufferMOCS
= mocs_wb
;
3801 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3802 sob
.StreamOutputBufferOffsetAddress
=
3803 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3805 if (brw_obj
->zero_offsets
) {
3806 /* Zero out the offset and write that to offset_bo */
3807 sob
.StreamOffset
= 0;
3809 /* Use offset_bo as the "Stream Offset." */
3810 sob
.StreamOffset
= 0xFFFFFFFF;
3817 brw_obj
->zero_offsets
= false;
3822 query_active(struct gl_query_object
*q
)
3824 return q
&& q
->Active
;
3828 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3829 const struct brw_vue_map
*vue_map
)
3831 struct gl_context
*ctx
= &brw
->ctx
;
3832 /* BRW_NEW_TRANSFORM_FEEDBACK */
3833 struct gl_transform_feedback_object
*xfb_obj
=
3834 ctx
->TransformFeedback
.CurrentObject
;
3836 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3838 int urb_entry_read_offset
= 0;
3839 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3840 urb_entry_read_offset
;
3842 sos
.SOFunctionEnable
= true;
3843 sos
.SOStatisticsEnable
= true;
3845 /* BRW_NEW_RASTERIZER_DISCARD */
3846 if (ctx
->RasterDiscard
) {
3847 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3848 sos
.RenderingDisable
= true;
3850 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3851 "query active relies on the clipper.\n");
3856 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3857 sos
.ReorderMode
= TRAILING
;
3860 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3861 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3862 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3863 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3865 const struct gl_transform_feedback_info
*linked_xfb_info
=
3866 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3867 /* Set buffer pitches; 0 means unbound. */
3868 if (xfb_obj
->Buffers
[0])
3869 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3870 if (xfb_obj
->Buffers
[1])
3871 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3872 if (xfb_obj
->Buffers
[2])
3873 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3874 if (xfb_obj
->Buffers
[3])
3875 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3878 /* We always read the whole vertex. This could be reduced at some
3879 * point by reading less and offsetting the register index in the
3882 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3883 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3884 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3885 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3886 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3887 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3888 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3889 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3895 genX(upload_sol
)(struct brw_context
*brw
)
3897 struct gl_context
*ctx
= &brw
->ctx
;
3898 /* BRW_NEW_TRANSFORM_FEEDBACK */
3899 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3902 genX(upload_3dstate_so_buffers
)(brw
);
3904 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3905 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3908 /* Finally, set up the SOL stage. This command must always follow updates to
3909 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3910 * MMIO register updates (current performed by the kernel at each batch
3913 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3916 static const struct brw_tracked_state
genX(sol_state
) = {
3919 .brw
= BRW_NEW_BATCH
|
3921 BRW_NEW_RASTERIZER_DISCARD
|
3922 BRW_NEW_VUE_MAP_GEOM_OUT
|
3923 BRW_NEW_TRANSFORM_FEEDBACK
,
3925 .emit
= genX(upload_sol
),
3929 /* ---------------------------------------------------------------------- */
3933 genX(upload_ps
)(struct brw_context
*brw
)
3935 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3936 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3938 /* BRW_NEW_FS_PROG_DATA */
3939 const struct brw_wm_prog_data
*prog_data
=
3940 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3941 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3946 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3947 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3948 * incorrect for subspans where some of the pixels are unlit. We believe
3949 * the bit just didn't take effect in previous generations.
3951 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3954 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3956 /* BRW_NEW_FS_PROG_DATA */
3957 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3959 if (prog_data
->base
.use_alt_mode
)
3960 ps
.FloatingPointMode
= Alternate
;
3962 /* Haswell requires the sample mask to be set in this packet as well as
3963 * in 3DSTATE_SAMPLE_MASK; the values should match.
3966 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3968 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3971 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
3972 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
3973 * k, it implies 2(k+1) threads. It implicitly scales for different GT
3974 * levels (which have some # of PSDs).
3976 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
3979 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3981 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3983 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3986 if (prog_data
->base
.nr_params
> 0 ||
3987 prog_data
->base
.ubo_ranges
[0].length
> 0)
3988 ps
.PushConstantEnable
= true;
3991 /* From the IVB PRM, volume 2 part 1, page 287:
3992 * "This bit is inserted in the PS payload header and made available to
3993 * the DataPort (either via the message header or via header bypass) to
3994 * indicate that oMask data (one or two phases) is included in Render
3995 * Target Write messages. If present, the oMask data is used to mask off
3998 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4000 /* The hardware wedges if you have this bit set but don't turn on any
4001 * dual source blend factors.
4003 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
4005 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
4006 (ctx
->Color
.BlendEnabled
& 1) &&
4007 ctx
->Color
.Blend
[0]._UsesDualSrc
;
4009 /* BRW_NEW_FS_PROG_DATA */
4010 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
4013 /* From the documentation for this packet:
4014 * "If the PS kernel does not need the Position XY Offsets to
4015 * compute a Position Value, then this field should be programmed
4016 * to POSOFFSET_NONE."
4018 * "SW Recommendation: If the PS kernel needs the Position Offsets
4019 * to compute a Position XY value, this field should match Position
4020 * ZW Interpolation Mode to ensure a consistent position.xyzw
4023 * We only require XY sample offsets. So, this recommendation doesn't
4024 * look useful at the moment. We might need this in future.
4026 if (prog_data
->uses_pos_offset
)
4027 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
4029 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
4031 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
4032 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
4033 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
4035 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
4037 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
4038 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
4040 * Since 16x MSAA is first introduced on SKL, we don't need to apply
4041 * the workaround on any older hardware.
4043 * BRW_NEW_NUM_SAMPLES
4045 if (GEN_GEN
>= 9 && !prog_data
->persample_dispatch
&&
4046 brw
->num_samples
== 16) {
4047 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
4048 ps
._32PixelDispatchEnable
= false;
4051 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
4052 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
4053 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
4054 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
4055 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
4056 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
4058 ps
.KernelStartPointer0
= stage_state
->prog_offset
+
4059 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
4060 ps
.KernelStartPointer1
= stage_state
->prog_offset
+
4061 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
4062 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
4063 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
4065 if (prog_data
->base
.total_scratch
) {
4066 ps
.ScratchSpaceBasePointer
=
4067 rw_32_bo(stage_state
->scratch_bo
,
4068 ffs(stage_state
->per_thread_scratch
) - 11);
4073 static const struct brw_tracked_state
genX(ps_state
) = {
4075 .mesa
= _NEW_MULTISAMPLE
|
4076 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
4079 .brw
= BRW_NEW_BATCH
|
4081 BRW_NEW_FS_PROG_DATA
|
4082 (GEN_GEN
>= 9 ? BRW_NEW_NUM_SAMPLES
: 0),
4084 .emit
= genX(upload_ps
),
4088 /* ---------------------------------------------------------------------- */
4092 genX(upload_hs_state
)(struct brw_context
*brw
)
4094 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4095 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4096 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4097 const struct brw_vue_prog_data
*vue_prog_data
=
4098 brw_vue_prog_data(stage_prog_data
);
4100 /* BRW_NEW_TES_PROG_DATA */
4101 struct brw_tcs_prog_data
*tcs_prog_data
=
4102 brw_tcs_prog_data(stage_prog_data
);
4104 if (!tcs_prog_data
) {
4105 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
4107 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
4108 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
4110 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
4111 hs
.IncludeVertexHandles
= true;
4113 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
4118 static const struct brw_tracked_state
genX(hs_state
) = {
4121 .brw
= BRW_NEW_BATCH
|
4123 BRW_NEW_TCS_PROG_DATA
|
4124 BRW_NEW_TESS_PROGRAMS
,
4126 .emit
= genX(upload_hs_state
),
4130 genX(upload_ds_state
)(struct brw_context
*brw
)
4132 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4133 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4134 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4136 /* BRW_NEW_TES_PROG_DATA */
4137 const struct brw_tes_prog_data
*tes_prog_data
=
4138 brw_tes_prog_data(stage_prog_data
);
4139 const struct brw_vue_prog_data
*vue_prog_data
=
4140 brw_vue_prog_data(stage_prog_data
);
4142 if (!tes_prog_data
) {
4143 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
4145 assert(GEN_GEN
< 11 ||
4146 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
4148 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
4149 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
4151 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4152 ds
.ComputeWCoordinateEnable
=
4153 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4156 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
4157 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4158 ds
.UserClipDistanceCullTestEnableBitmask
=
4159 vue_prog_data
->cull_distance_mask
;
4165 static const struct brw_tracked_state
genX(ds_state
) = {
4168 .brw
= BRW_NEW_BATCH
|
4170 BRW_NEW_TESS_PROGRAMS
|
4171 BRW_NEW_TES_PROG_DATA
,
4173 .emit
= genX(upload_ds_state
),
4176 /* ---------------------------------------------------------------------- */
4179 upload_te_state(struct brw_context
*brw
)
4181 /* BRW_NEW_TESS_PROGRAMS */
4182 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4184 /* BRW_NEW_TES_PROG_DATA */
4185 const struct brw_tes_prog_data
*tes_prog_data
=
4186 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4189 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4190 te
.Partitioning
= tes_prog_data
->partitioning
;
4191 te
.OutputTopology
= tes_prog_data
->output_topology
;
4192 te
.TEDomain
= tes_prog_data
->domain
;
4194 te
.MaximumTessellationFactorOdd
= 63.0;
4195 te
.MaximumTessellationFactorNotOdd
= 64.0;
4198 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4202 static const struct brw_tracked_state
genX(te_state
) = {
4205 .brw
= BRW_NEW_BLORP
|
4207 BRW_NEW_TES_PROG_DATA
|
4208 BRW_NEW_TESS_PROGRAMS
,
4210 .emit
= upload_te_state
,
4213 /* ---------------------------------------------------------------------- */
4216 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4218 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4219 /* BRW_NEW_TESS_PROGRAMS */
4220 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4222 /* BRW_NEW_TES_PROG_DATA */
4223 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4224 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4227 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4229 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4230 .brw
= BRW_NEW_BATCH
|
4232 BRW_NEW_TESS_PROGRAMS
|
4233 BRW_NEW_TES_PROG_DATA
,
4235 .emit
= genX(upload_tes_push_constants
),
4239 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4241 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4242 /* BRW_NEW_TESS_PROGRAMS */
4243 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4245 /* BRW_NEW_TCS_PROG_DATA */
4246 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4248 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4251 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4253 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4254 .brw
= BRW_NEW_BATCH
|
4256 BRW_NEW_DEFAULT_TESS_LEVELS
|
4257 BRW_NEW_TESS_PROGRAMS
|
4258 BRW_NEW_TCS_PROG_DATA
,
4260 .emit
= genX(upload_tcs_push_constants
),
4265 /* ---------------------------------------------------------------------- */
4269 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4271 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4273 /* BRW_NEW_COMPUTE_PROGRAM */
4274 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4277 /* BRW_NEW_CS_PROG_DATA */
4278 struct brw_cs_prog_data
*cs_prog_data
=
4279 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4281 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4282 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4286 const struct brw_tracked_state
genX(cs_push_constants
) = {
4288 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4289 .brw
= BRW_NEW_BATCH
|
4291 BRW_NEW_COMPUTE_PROGRAM
|
4292 BRW_NEW_CS_PROG_DATA
,
4294 .emit
= genX(upload_cs_push_constants
),
4298 * Creates a new CS constant buffer reflecting the current CS program's
4299 * constants, if needed by the CS program.
4302 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4304 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4306 /* BRW_NEW_COMPUTE_PROGRAM */
4307 struct brw_program
*cp
=
4308 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4310 /* BRW_NEW_CS_PROG_DATA */
4311 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4313 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4314 /* _NEW_PROGRAM_CONSTANTS */
4315 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4316 stage_state
, prog_data
);
4319 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4321 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4322 .brw
= BRW_NEW_BATCH
|
4324 BRW_NEW_COMPUTE_PROGRAM
|
4325 BRW_NEW_CS_PROG_DATA
,
4327 .emit
= genX(upload_cs_pull_constants
),
4331 genX(upload_cs_state
)(struct brw_context
*brw
)
4333 if (!brw
->cs
.base
.prog_data
)
4337 uint32_t *desc
= (uint32_t*) brw_state_batch(
4338 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4341 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4342 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4343 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4344 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4346 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4347 brw_emit_buffer_surface_state(
4348 brw
, &stage_state
->surf_offset
[
4349 prog_data
->binding_table
.shader_time_start
],
4350 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4351 brw
->shader_time
.bo
->size
, 1,
4355 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4356 32, &stage_state
->bind_bo_offset
);
4358 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4360 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4361 * the only bits that are changed are scoreboard related: Scoreboard
4362 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4363 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4365 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4366 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4368 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4370 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4371 if (prog_data
->total_scratch
) {
4372 uint32_t per_thread_scratch_value
;
4375 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4376 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4378 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4379 } else if (GEN_IS_HASWELL
) {
4380 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4381 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4383 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4385 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4386 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4388 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4390 vfe
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
4391 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4394 /* If brw->screen->subslice_total is greater than one, then
4395 * devinfo->max_cs_threads stores number of threads per sub-slice;
4396 * thus we need to multiply by that number by subslices to get
4397 * the actual maximum number of threads; the -1 is because the HW
4398 * has a bias of 1 (would not make sense to say the maximum number
4401 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4402 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4403 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4405 vfe
.ResetGatewayTimer
=
4406 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4409 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4415 /* We are uploading duplicated copies of push constant uniforms for each
4416 * thread. Although the local id data needs to vary per thread, it won't
4417 * change for other uniform data. Unfortunately this duplication is
4418 * required for gen7. As of Haswell, this duplication can be avoided,
4419 * but this older mechanism with duplicated data continues to work.
4421 * FINISHME: As of Haswell, we could make use of the
4422 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4423 * field to only store one copy of uniform data.
4425 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4426 * which is described in the GPGPU_WALKER command and in the Broadwell
4427 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4428 * Operations => GPGPU Mode => Indirect Payload Storage.
4430 * Note: The constant data is built in brw_upload_cs_push_constants
4433 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4435 const uint32_t vfe_curbe_allocation
=
4436 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4437 cs_prog_data
->push
.cross_thread
.regs
, 2);
4438 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4441 if (cs_prog_data
->push
.total
.size
> 0) {
4442 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4443 curbe
.CURBETotalDataLength
=
4444 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4445 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4449 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4450 memcpy(bind
, stage_state
->surf_offset
,
4451 prog_data
->binding_table
.size_bytes
);
4452 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4453 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4454 .SamplerStatePointer
= stage_state
->sampler_offset
,
4455 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4456 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4457 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4458 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4459 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4460 prog_data
->total_shared
),
4461 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4462 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4463 .CrossThreadConstantDataReadLength
=
4464 cs_prog_data
->push
.cross_thread
.regs
,
4468 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4470 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4471 load
.InterfaceDescriptorTotalLength
=
4472 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4473 load
.InterfaceDescriptorDataStartAddress
= offset
;
4477 static const struct brw_tracked_state
genX(cs_state
) = {
4479 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4480 .brw
= BRW_NEW_BATCH
|
4482 BRW_NEW_CS_PROG_DATA
|
4483 BRW_NEW_SAMPLER_STATE_TABLE
|
4486 .emit
= genX(upload_cs_state
)
4491 /* ---------------------------------------------------------------------- */
4495 genX(upload_raster
)(struct brw_context
*brw
)
4497 const struct gl_context
*ctx
= &brw
->ctx
;
4500 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4503 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4506 const struct gl_point_attrib
*point
= &ctx
->Point
;
4508 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4509 if (brw
->polygon_front_bit
== render_to_fbo
)
4510 raster
.FrontWinding
= CounterClockwise
;
4512 if (polygon
->CullFlag
) {
4513 switch (polygon
->CullFaceMode
) {
4515 raster
.CullMode
= CULLMODE_FRONT
;
4518 raster
.CullMode
= CULLMODE_BACK
;
4520 case GL_FRONT_AND_BACK
:
4521 raster
.CullMode
= CULLMODE_BOTH
;
4524 unreachable("not reached");
4527 raster
.CullMode
= CULLMODE_NONE
;
4530 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4532 raster
.DXMultisampleRasterizationEnable
=
4533 _mesa_is_multisample_enabled(ctx
);
4535 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4536 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4537 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4539 switch (polygon
->FrontMode
) {
4541 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4544 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4547 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4550 unreachable("not reached");
4553 switch (polygon
->BackMode
) {
4555 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4558 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4561 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4564 unreachable("not reached");
4568 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4572 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4574 const bool multisampled_fbo
=
4575 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4576 if (multisampled_fbo
)
4577 raster
.AntialiasingEnable
= false;
4581 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4583 /* _NEW_TRANSFORM */
4584 if (!ctx
->Transform
.DepthClamp
) {
4586 raster
.ViewportZFarClipTestEnable
= true;
4587 raster
.ViewportZNearClipTestEnable
= true;
4589 raster
.ViewportZClipTestEnable
= true;
4593 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4595 raster
.ConservativeRasterizationEnable
=
4596 ctx
->IntelConservativeRasterization
;
4599 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4600 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4602 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4606 static const struct brw_tracked_state
genX(raster_state
) = {
4608 .mesa
= _NEW_BUFFERS
|
4615 .brw
= BRW_NEW_BLORP
|
4617 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4619 .emit
= genX(upload_raster
),
4623 /* ---------------------------------------------------------------------- */
4627 genX(upload_ps_extra
)(struct brw_context
*brw
)
4629 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4631 const struct brw_wm_prog_data
*prog_data
=
4632 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4634 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4635 psx
.PixelShaderValid
= true;
4636 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4637 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4638 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4639 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4640 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4641 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4643 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4644 if (prog_data
->uses_sample_mask
) {
4646 if (prog_data
->post_depth_coverage
)
4647 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4648 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4649 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4651 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4653 psx
.PixelShaderUsesInputCoverageMask
= true;
4657 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4659 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4660 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4663 /* The stricter cross-primitive coherency guarantees that the hardware
4664 * gives us with the "Accesses UAV" bit set for at least one shader stage
4665 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4666 * are redundant within the current image, atomic counter and SSBO GL
4667 * APIs, which all have very loose ordering and coherency requirements
4668 * and generally rely on the application to insert explicit barriers when
4669 * a shader invocation is expected to see the memory writes performed by
4670 * the invocations of some previous primitive. Regardless of the value
4671 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4672 * cause an in most cases useless DC flush when the lowermost stage with
4673 * the bit set finishes execution.
4675 * It would be nice to disable it, but in some cases we can't because on
4676 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4677 * signal (which could be set independently from the coherency mechanism
4678 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4679 * determine whether the hardware skips execution of the fragment shader
4680 * or not via the ThreadDispatchEnable signal. However if we know that
4681 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4682 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4683 * difference so we may just disable it here.
4685 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4686 * take into account KillPixels when no depth or stencil writes are
4687 * enabled. In order for occlusion queries to work correctly with no
4688 * attachments, we need to force-enable here.
4690 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4693 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4694 !brw_color_buffer_write_enabled(brw
))
4695 psx
.PixelShaderHasUAV
= true;
4699 const struct brw_tracked_state
genX(ps_extra
) = {
4701 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4702 .brw
= BRW_NEW_BLORP
|
4704 BRW_NEW_FRAGMENT_PROGRAM
|
4705 BRW_NEW_FS_PROG_DATA
|
4706 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4708 .emit
= genX(upload_ps_extra
),
4712 /* ---------------------------------------------------------------------- */
4716 genX(upload_ps_blend
)(struct brw_context
*brw
)
4718 struct gl_context
*ctx
= &brw
->ctx
;
4721 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4722 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4725 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4727 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4728 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4729 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4731 bool alpha_to_one
= false;
4733 if (!buffer0_is_integer
) {
4734 /* _NEW_MULTISAMPLE */
4736 if (_mesa_is_multisample_enabled(ctx
)) {
4737 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4738 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4741 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4744 /* Used for implementing the following bit of GL_EXT_texture_integer:
4745 * "Per-fragment operations that require floating-point color
4746 * components, including multisample alpha operations, alpha test,
4747 * blending, and dithering, have no effect when the corresponding
4748 * colors are written to an integer color buffer."
4750 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4751 * "If drawbuffer zero is not NONE and the buffer it references has an
4752 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4753 * operations are skipped."
4755 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4756 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4757 GLenum eqA
= color
->Blend
[0].EquationA
;
4758 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4759 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4760 GLenum srcA
= color
->Blend
[0].SrcA
;
4761 GLenum dstA
= color
->Blend
[0].DstA
;
4763 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4764 srcRGB
= dstRGB
= GL_ONE
;
4766 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4767 srcA
= dstA
= GL_ONE
;
4769 /* Due to hardware limitations, the destination may have information
4770 * in an alpha channel even when the format specifies no alpha
4771 * channel. In order to avoid getting any incorrect blending due to
4772 * that alpha channel, coerce the blend factors to values that will
4773 * not read the alpha channel, but will instead use the correct
4774 * implicit value for alpha.
4776 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4777 GL_TEXTURE_ALPHA_TYPE
)) {
4778 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4779 srcA
= brw_fix_xRGB_alpha(srcA
);
4780 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4781 dstA
= brw_fix_xRGB_alpha(dstA
);
4784 /* Alpha to One doesn't work with Dual Color Blending. Override
4785 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4787 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4788 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4789 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4790 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4791 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4794 pb
.ColorBufferBlendEnable
= true;
4795 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4796 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4797 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4798 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4800 pb
.IndependentAlphaBlendEnable
=
4801 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4806 static const struct brw_tracked_state
genX(ps_blend
) = {
4808 .mesa
= _NEW_BUFFERS
|
4811 .brw
= BRW_NEW_BLORP
|
4813 BRW_NEW_FRAGMENT_PROGRAM
,
4815 .emit
= genX(upload_ps_blend
)
4819 /* ---------------------------------------------------------------------- */
4823 genX(emit_vf_topology
)(struct brw_context
*brw
)
4825 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4826 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4830 static const struct brw_tracked_state
genX(vf_topology
) = {
4833 .brw
= BRW_NEW_BLORP
|
4836 .emit
= genX(emit_vf_topology
),
4840 /* ---------------------------------------------------------------------- */
4844 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4846 uint32_t offset_in_bytes
,
4849 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4850 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4851 mi_rpc
.ReportID
= report_id
;
4856 /* ---------------------------------------------------------------------- */
4859 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4862 genX(emit_sampler_state_pointers_xs
)(MAYBE_UNUSED
struct brw_context
*brw
,
4863 MAYBE_UNUSED
struct brw_stage_state
*stage_state
)
4866 static const uint16_t packet_headers
[] = {
4867 [MESA_SHADER_VERTEX
] = 43,
4868 [MESA_SHADER_TESS_CTRL
] = 44,
4869 [MESA_SHADER_TESS_EVAL
] = 45,
4870 [MESA_SHADER_GEOMETRY
] = 46,
4871 [MESA_SHADER_FRAGMENT
] = 47,
4874 /* Ivybridge requires a workaround flush before VS packets. */
4875 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4876 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4877 gen7_emit_vs_workaround_flush(brw
);
4880 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4881 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4882 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4888 has_component(mesa_format format
, int i
)
4890 if (_mesa_is_format_color_format(format
))
4891 return _mesa_format_has_color_component(format
, i
);
4893 /* depth and stencil have only one component */
4898 * Upload SAMPLER_BORDER_COLOR_STATE.
4901 genX(upload_default_color
)(struct brw_context
*brw
,
4902 const struct gl_sampler_object
*sampler
,
4903 MAYBE_UNUSED mesa_format format
, GLenum base_format
,
4904 bool is_integer_format
, bool is_stencil_sampling
,
4905 uint32_t *sdc_offset
)
4907 union gl_color_union color
;
4909 switch (base_format
) {
4910 case GL_DEPTH_COMPONENT
:
4911 /* GL specs that border color for depth textures is taken from the
4912 * R channel, while the hardware uses A. Spam R into all the
4913 * channels for safety.
4915 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4916 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4917 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4918 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4924 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4927 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4928 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4929 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4930 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4933 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4934 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4935 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4936 color
.ui
[3] = float_as_int(1.0);
4938 case GL_LUMINANCE_ALPHA
:
4939 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4940 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4941 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4942 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4945 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4946 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4947 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4948 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4952 /* In some cases we use an RGBA surface format for GL RGB textures,
4953 * where we've initialized the A channel to 1.0. We also have to set
4954 * the border color alpha to 1.0 in that case.
4956 if (base_format
== GL_RGB
)
4957 color
.ui
[3] = float_as_int(1.0);
4962 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4966 uint32_t *sdc
= brw_state_batch(
4967 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4968 alignment
, sdc_offset
);
4970 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4972 #define ASSIGN(dst, src) \
4977 #define ASSIGNu16(dst, src) \
4979 dst = (uint16_t)src; \
4982 #define ASSIGNu8(dst, src) \
4984 dst = (uint8_t)src; \
4987 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4988 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4989 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4990 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4991 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4994 /* On Broadwell, the border color is represented as four 32-bit floats,
4995 * integers, or unsigned values, interpreted according to the surface
4996 * format. This matches the sampler->BorderColor union exactly; just
4997 * memcpy the values.
4999 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
5000 #elif GEN_IS_HASWELL
5001 if (is_integer_format
|| is_stencil_sampling
) {
5002 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
5003 const int bits_per_channel
=
5004 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
5006 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
5007 * "If any color channel is missing from the surface format,
5008 * corresponding border color should be programmed as zero and if
5009 * alpha channel is missing, corresponding Alpha border color should
5010 * be programmed as 1."
5012 unsigned c
[4] = { 0, 0, 0, 1 };
5013 for (int i
= 0; i
< 4; i
++) {
5014 if (has_component(format
, i
))
5018 switch (bits_per_channel
) {
5020 /* Copy RGBA in order. */
5021 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
5024 /* R10G10B10A2_UINT is treated like a 16-bit format. */
5026 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
5029 if (base_format
== GL_RG
) {
5030 /* Careful inspection of the tables reveals that for RG32 formats,
5031 * the green channel needs to go where blue normally belongs.
5033 state
.BorderColor32bitRed
= c
[0];
5034 state
.BorderColor32bitBlue
= c
[1];
5035 state
.BorderColor32bitAlpha
= 1;
5037 /* Copy RGBA in order. */
5038 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
5042 assert(!"Invalid number of bits per channel in integer format.");
5046 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5048 #elif GEN_GEN == 5 || GEN_GEN == 6
5049 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
5050 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
5051 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
5053 #define MESA_FLOAT_TO_HALF(dst, src) \
5054 dst = _mesa_float_to_half(src);
5056 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
5058 #undef MESA_FLOAT_TO_HALF
5060 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
5061 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
5062 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
5063 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
5065 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5067 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
5069 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5073 #undef BORDER_COLOR_ATTR
5075 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
5079 translate_wrap_mode(GLenum wrap
, MAYBE_UNUSED
bool using_nearest
)
5086 /* GL_CLAMP is the weird mode where coordinates are clamped to
5087 * [0.0, 1.0], so linear filtering of coordinates outside of
5088 * [0.0, 1.0] give you half edge texel value and half border
5091 * Gen8+ supports this natively.
5093 return TCM_HALF_BORDER
;
5095 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
5096 * and set clamp_border here, which gets the result desired.
5097 * We just use clamp(_to_edge) for nearest, because for nearest
5098 * clamping to 1.0 gives border color instead of the desired
5104 return TCM_CLAMP_BORDER
;
5106 case GL_CLAMP_TO_EDGE
:
5108 case GL_CLAMP_TO_BORDER
:
5109 return TCM_CLAMP_BORDER
;
5110 case GL_MIRRORED_REPEAT
:
5112 case GL_MIRROR_CLAMP_TO_EDGE
:
5113 return TCM_MIRROR_ONCE
;
5120 * Return true if the given wrap mode requires the border color to exist.
5123 wrap_mode_needs_border_color(unsigned wrap_mode
)
5126 return wrap_mode
== TCM_CLAMP_BORDER
||
5127 wrap_mode
== TCM_HALF_BORDER
;
5129 return wrap_mode
== TCM_CLAMP_BORDER
;
5134 * Sets the sampler state for a single unit based off of the sampler key
5138 genX(update_sampler_state
)(struct brw_context
*brw
,
5139 GLenum target
, bool tex_cube_map_seamless
,
5140 GLfloat tex_unit_lod_bias
,
5141 mesa_format format
, GLenum base_format
,
5142 const struct gl_texture_object
*texObj
,
5143 const struct gl_sampler_object
*sampler
,
5144 uint32_t *sampler_state
)
5146 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
5148 /* Select min and mip filters. */
5149 switch (sampler
->MinFilter
) {
5151 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5152 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5155 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5156 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5158 case GL_NEAREST_MIPMAP_NEAREST
:
5159 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5160 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5162 case GL_LINEAR_MIPMAP_NEAREST
:
5163 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5164 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5166 case GL_NEAREST_MIPMAP_LINEAR
:
5167 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5168 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5170 case GL_LINEAR_MIPMAP_LINEAR
:
5171 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5172 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5175 unreachable("not reached");
5178 /* Select mag filter. */
5179 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5180 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5182 /* Enable anisotropic filtering if desired. */
5183 samp_st
.MaximumAnisotropy
= RATIO21
;
5185 if (sampler
->MaxAnisotropy
> 1.0f
) {
5186 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5187 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5188 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5189 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5191 if (sampler
->MaxAnisotropy
> 2.0f
) {
5192 samp_st
.MaximumAnisotropy
=
5193 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5197 /* Set address rounding bits if not using nearest filtering. */
5198 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5199 samp_st
.UAddressMinFilterRoundingEnable
= true;
5200 samp_st
.VAddressMinFilterRoundingEnable
= true;
5201 samp_st
.RAddressMinFilterRoundingEnable
= true;
5204 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5205 samp_st
.UAddressMagFilterRoundingEnable
= true;
5206 samp_st
.VAddressMagFilterRoundingEnable
= true;
5207 samp_st
.RAddressMagFilterRoundingEnable
= true;
5210 bool either_nearest
=
5211 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5212 unsigned wrap_s
= translate_wrap_mode(sampler
->WrapS
, either_nearest
);
5213 unsigned wrap_t
= translate_wrap_mode(sampler
->WrapT
, either_nearest
);
5214 unsigned wrap_r
= translate_wrap_mode(sampler
->WrapR
, either_nearest
);
5216 if (target
== GL_TEXTURE_CUBE_MAP
||
5217 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5218 /* Cube maps must use the same wrap mode for all three coordinate
5219 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5221 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5222 * integer formats. Fall back to CLAMP for now.
5224 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5225 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5234 } else if (target
== GL_TEXTURE_1D
) {
5235 /* There's a bug in 1D texture sampling - it actually pays
5236 * attention to the wrap_t value, though it should not.
5237 * Override the wrap_t value here to GL_REPEAT to keep
5238 * any nonexistent border pixels from floating in.
5243 samp_st
.TCXAddressControlMode
= wrap_s
;
5244 samp_st
.TCYAddressControlMode
= wrap_t
;
5245 samp_st
.TCZAddressControlMode
= wrap_r
;
5247 samp_st
.ShadowFunction
=
5248 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5249 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5252 /* Set shadow function. */
5253 samp_st
.AnisotropicAlgorithm
=
5254 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5255 EWAApproximation
: LEGACY
;
5259 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5262 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5263 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5264 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5265 samp_st
.TextureLODBias
=
5266 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5269 samp_st
.BaseMipLevel
=
5270 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5271 samp_st
.MinandMagStateNotEqual
=
5272 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5275 /* Upload the border color if necessary. If not, just point it at
5276 * offset 0 (the start of the batch) - the color should be ignored,
5277 * but that address won't fault in case something reads it anyway.
5279 uint32_t border_color_offset
= 0;
5280 if (wrap_mode_needs_border_color(wrap_s
) ||
5281 wrap_mode_needs_border_color(wrap_t
) ||
5282 wrap_mode_needs_border_color(wrap_r
)) {
5283 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5284 texObj
->_IsIntegerFormat
,
5285 texObj
->StencilSampling
,
5286 &border_color_offset
);
5289 samp_st
.BorderColorPointer
=
5290 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5292 samp_st
.BorderColorPointer
= border_color_offset
;
5296 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5298 samp_st
.LODPreClampEnable
= true;
5301 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5305 update_sampler_state(struct brw_context
*brw
,
5307 uint32_t *sampler_state
)
5309 struct gl_context
*ctx
= &brw
->ctx
;
5310 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5311 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5312 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5314 /* These don't use samplers at all. */
5315 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5318 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5319 genX(update_sampler_state
)(brw
, texObj
->Target
,
5320 ctx
->Texture
.CubeMapSeamless
,
5322 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5328 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5329 struct gl_program
*prog
,
5330 struct brw_stage_state
*stage_state
)
5332 struct gl_context
*ctx
= &brw
->ctx
;
5333 uint32_t sampler_count
= stage_state
->sampler_count
;
5335 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5337 if (sampler_count
== 0)
5340 /* SAMPLER_STATE is 4 DWords on all platforms. */
5341 const int dwords
= GENX(SAMPLER_STATE_length
);
5342 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5344 uint32_t *sampler_state
= brw_state_batch(brw
,
5345 sampler_count
* size_in_bytes
,
5346 32, &stage_state
->sampler_offset
);
5347 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5349 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5350 if (SamplersUsed
& (1 << s
)) {
5351 const unsigned unit
= prog
->SamplerUnits
[s
];
5352 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5353 update_sampler_state(brw
, unit
, sampler_state
);
5357 sampler_state
+= dwords
;
5360 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5361 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5362 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5364 /* Flag that the sampler state table pointer has changed; later atoms
5367 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5372 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5374 /* BRW_NEW_FRAGMENT_PROGRAM */
5375 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5376 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5379 static const struct brw_tracked_state
genX(fs_samplers
) = {
5381 .mesa
= _NEW_TEXTURE
,
5382 .brw
= BRW_NEW_BATCH
|
5384 BRW_NEW_FRAGMENT_PROGRAM
,
5386 .emit
= genX(upload_fs_samplers
),
5390 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5392 /* BRW_NEW_VERTEX_PROGRAM */
5393 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5394 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5397 static const struct brw_tracked_state
genX(vs_samplers
) = {
5399 .mesa
= _NEW_TEXTURE
,
5400 .brw
= BRW_NEW_BATCH
|
5402 BRW_NEW_VERTEX_PROGRAM
,
5404 .emit
= genX(upload_vs_samplers
),
5409 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5411 /* BRW_NEW_GEOMETRY_PROGRAM */
5412 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5416 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5420 static const struct brw_tracked_state
genX(gs_samplers
) = {
5422 .mesa
= _NEW_TEXTURE
,
5423 .brw
= BRW_NEW_BATCH
|
5425 BRW_NEW_GEOMETRY_PROGRAM
,
5427 .emit
= genX(upload_gs_samplers
),
5433 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5435 /* BRW_NEW_TESS_PROGRAMS */
5436 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5440 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5443 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5445 .mesa
= _NEW_TEXTURE
,
5446 .brw
= BRW_NEW_BATCH
|
5448 BRW_NEW_TESS_PROGRAMS
,
5450 .emit
= genX(upload_tcs_samplers
),
5456 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5458 /* BRW_NEW_TESS_PROGRAMS */
5459 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5463 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5466 static const struct brw_tracked_state
genX(tes_samplers
) = {
5468 .mesa
= _NEW_TEXTURE
,
5469 .brw
= BRW_NEW_BATCH
|
5471 BRW_NEW_TESS_PROGRAMS
,
5473 .emit
= genX(upload_tes_samplers
),
5479 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5481 /* BRW_NEW_COMPUTE_PROGRAM */
5482 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5486 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5489 const struct brw_tracked_state
genX(cs_samplers
) = {
5491 .mesa
= _NEW_TEXTURE
,
5492 .brw
= BRW_NEW_BATCH
|
5494 BRW_NEW_COMPUTE_PROGRAM
,
5496 .emit
= genX(upload_cs_samplers
),
5500 /* ---------------------------------------------------------------------- */
5504 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5506 struct gl_context
*ctx
= &brw
->ctx
;
5508 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5509 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5510 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5511 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5512 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5516 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5519 .brw
= BRW_NEW_CONTEXT
|
5522 .emit
= genX(upload_blend_constant_color
)
5526 /* ---------------------------------------------------------------------- */
5529 genX(init_atoms
)(struct brw_context
*brw
)
5532 static const struct brw_tracked_state
*render_atoms
[] =
5534 /* Once all the programs are done, we know how large urb entry
5535 * sizes need to be and can decide if we need to change the urb
5539 &brw_recalculate_urb_fence
,
5542 &genX(color_calc_state
),
5544 /* Surface state setup. Must come before the VS/WM unit. The binding
5545 * table upload must be last.
5547 &brw_vs_pull_constants
,
5548 &brw_wm_pull_constants
,
5549 &brw_renderbuffer_surfaces
,
5550 &brw_renderbuffer_read_surfaces
,
5551 &brw_texture_surfaces
,
5552 &brw_vs_binding_table
,
5553 &brw_wm_binding_table
,
5558 /* These set up state for brw_psp_urb_cbs */
5560 &genX(sf_clip_viewport
),
5562 &genX(vs_state
), /* always required, enabled or not */
5568 &brw_binding_table_pointers
,
5569 &genX(blend_constant_color
),
5573 &genX(polygon_stipple
),
5574 &genX(polygon_stipple_offset
),
5576 &genX(line_stipple
),
5580 &genX(drawing_rect
),
5581 &brw_indices
, /* must come before brw_vertices */
5582 &genX(index_buffer
),
5585 &brw_constant_buffer
5588 static const struct brw_tracked_state
*render_atoms
[] =
5590 &genX(sf_clip_viewport
),
5592 /* Command packets: */
5597 &genX(blend_state
), /* must do before cc unit */
5598 &genX(color_calc_state
), /* must do before cc unit */
5599 &genX(depth_stencil_state
), /* must do before cc unit */
5601 &genX(vs_push_constants
), /* Before vs_state */
5602 &genX(gs_push_constants
), /* Before gs_state */
5603 &genX(wm_push_constants
), /* Before wm_state */
5605 /* Surface state setup. Must come before the VS/WM unit. The binding
5606 * table upload must be last.
5608 &brw_vs_pull_constants
,
5609 &brw_vs_ubo_surfaces
,
5610 &brw_gs_pull_constants
,
5611 &brw_gs_ubo_surfaces
,
5612 &brw_wm_pull_constants
,
5613 &brw_wm_ubo_surfaces
,
5614 &gen6_renderbuffer_surfaces
,
5615 &brw_renderbuffer_read_surfaces
,
5616 &brw_texture_surfaces
,
5618 &brw_vs_binding_table
,
5619 &gen6_gs_binding_table
,
5620 &brw_wm_binding_table
,
5625 &gen6_sampler_state
,
5626 &genX(multisample_state
),
5634 &genX(scissor_state
),
5636 &gen6_binding_table_pointers
,
5640 &genX(polygon_stipple
),
5641 &genX(polygon_stipple_offset
),
5643 &genX(line_stipple
),
5645 &genX(drawing_rect
),
5647 &brw_indices
, /* must come before brw_vertices */
5648 &genX(index_buffer
),
5652 static const struct brw_tracked_state
*render_atoms
[] =
5654 /* Command packets: */
5657 &genX(sf_clip_viewport
),
5660 &gen7_push_constant_space
,
5662 &genX(blend_state
), /* must do before cc unit */
5663 &genX(color_calc_state
), /* must do before cc unit */
5664 &genX(depth_stencil_state
), /* must do before cc unit */
5666 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5667 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5668 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5669 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5670 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5672 &genX(vs_push_constants
), /* Before vs_state */
5673 &genX(tcs_push_constants
),
5674 &genX(tes_push_constants
),
5675 &genX(gs_push_constants
), /* Before gs_state */
5676 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5678 /* Surface state setup. Must come before the VS/WM unit. The binding
5679 * table upload must be last.
5681 &brw_vs_pull_constants
,
5682 &brw_vs_ubo_surfaces
,
5683 &brw_tcs_pull_constants
,
5684 &brw_tcs_ubo_surfaces
,
5685 &brw_tes_pull_constants
,
5686 &brw_tes_ubo_surfaces
,
5687 &brw_gs_pull_constants
,
5688 &brw_gs_ubo_surfaces
,
5689 &brw_wm_pull_constants
,
5690 &brw_wm_ubo_surfaces
,
5691 &gen6_renderbuffer_surfaces
,
5692 &brw_renderbuffer_read_surfaces
,
5693 &brw_texture_surfaces
,
5695 &genX(push_constant_packets
),
5697 &brw_vs_binding_table
,
5698 &brw_tcs_binding_table
,
5699 &brw_tes_binding_table
,
5700 &brw_gs_binding_table
,
5701 &brw_wm_binding_table
,
5705 &genX(tcs_samplers
),
5706 &genX(tes_samplers
),
5708 &genX(multisample_state
),
5722 &genX(scissor_state
),
5726 &genX(polygon_stipple
),
5727 &genX(polygon_stipple_offset
),
5729 &genX(line_stipple
),
5731 &genX(drawing_rect
),
5733 &brw_indices
, /* must come before brw_vertices */
5734 &genX(index_buffer
),
5742 static const struct brw_tracked_state
*render_atoms
[] =
5745 &genX(sf_clip_viewport
),
5748 &gen7_push_constant_space
,
5751 &genX(color_calc_state
),
5753 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5754 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5755 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5756 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5757 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5759 &genX(vs_push_constants
), /* Before vs_state */
5760 &genX(tcs_push_constants
),
5761 &genX(tes_push_constants
),
5762 &genX(gs_push_constants
), /* Before gs_state */
5763 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5765 /* Surface state setup. Must come before the VS/WM unit. The binding
5766 * table upload must be last.
5768 &brw_vs_pull_constants
,
5769 &brw_vs_ubo_surfaces
,
5770 &brw_tcs_pull_constants
,
5771 &brw_tcs_ubo_surfaces
,
5772 &brw_tes_pull_constants
,
5773 &brw_tes_ubo_surfaces
,
5774 &brw_gs_pull_constants
,
5775 &brw_gs_ubo_surfaces
,
5776 &brw_wm_pull_constants
,
5777 &brw_wm_ubo_surfaces
,
5778 &gen6_renderbuffer_surfaces
,
5779 &brw_renderbuffer_read_surfaces
,
5780 &brw_texture_surfaces
,
5782 &genX(push_constant_packets
),
5784 &brw_vs_binding_table
,
5785 &brw_tcs_binding_table
,
5786 &brw_tes_binding_table
,
5787 &brw_gs_binding_table
,
5788 &brw_wm_binding_table
,
5792 &genX(tcs_samplers
),
5793 &genX(tes_samplers
),
5795 &genX(multisample_state
),
5804 &genX(raster_state
),
5810 &genX(depth_stencil_state
),
5813 &genX(scissor_state
),
5817 &genX(polygon_stipple
),
5818 &genX(polygon_stipple_offset
),
5820 &genX(line_stipple
),
5822 &genX(drawing_rect
),
5827 &genX(index_buffer
),
5835 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5836 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5837 render_atoms
, ARRAY_SIZE(render_atoms
));
5840 static const struct brw_tracked_state
*compute_atoms
[] =
5843 &brw_cs_image_surfaces
,
5844 &genX(cs_push_constants
),
5845 &genX(cs_pull_constants
),
5846 &brw_cs_ubo_surfaces
,
5847 &brw_cs_texture_surfaces
,
5848 &brw_cs_work_groups_surface
,
5853 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5854 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5855 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5857 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);