2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 UNUSED
static struct brw_address
124 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
134 static struct brw_address
135 KSP(struct brw_context
*brw
, uint32_t offset
)
137 return ro_bo(brw
->cache
.bo
, offset
);
141 KSP(struct brw_context
*brw
, uint32_t offset
)
147 #include "genxml/genX_pack.h"
149 #define _brw_cmd_length(cmd) cmd ## _length
150 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
151 #define _brw_cmd_header(cmd) cmd ## _header
152 #define _brw_cmd_pack(cmd) cmd ## _pack
154 #define brw_batch_emit(brw, cmd, name) \
155 for (struct cmd name = { _brw_cmd_header(cmd) }, \
156 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
157 __builtin_expect(_dst != NULL, 1); \
158 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
161 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
162 uint32_t *_dw = emit_dwords(brw, n); \
163 struct cmd template = { \
164 _brw_cmd_header(cmd), \
165 .DWordLength = n - _brw_cmd_length_bias(cmd), \
168 _brw_cmd_pack(cmd)(brw, _dw, &template); \
169 _dw + 1; /* Array starts at dw[1] */ \
172 #define brw_state_emit(brw, cmd, align, offset, name) \
173 for (struct cmd name = {}, \
174 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
176 __builtin_expect(_dst != NULL, 1); \
177 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 * Polygon stipple packet
184 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
186 struct gl_context
*ctx
= &brw
->ctx
;
189 if (!ctx
->Polygon
.StippleFlag
)
192 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
193 /* Polygon stipple is provided in OpenGL order, i.e. bottom
194 * row first. If we're rendering to a window (i.e. the
195 * default frame buffer object, 0), then we need to invert
196 * it to match our pixel layout. But if we're rendering
197 * to a FBO (i.e. any named frame buffer object), we *don't*
198 * need to invert - we already match the layout.
200 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
201 for (unsigned i
= 0; i
< 32; i
++)
202 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
204 for (unsigned i
= 0; i
< 32; i
++)
205 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
210 static const struct brw_tracked_state
genX(polygon_stipple
) = {
212 .mesa
= _NEW_POLYGON
|
214 .brw
= BRW_NEW_CONTEXT
,
216 .emit
= genX(upload_polygon_stipple
),
220 * Polygon stipple offset packet
223 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
225 struct gl_context
*ctx
= &brw
->ctx
;
228 if (!ctx
->Polygon
.StippleFlag
)
231 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
234 * If we're drawing to a system window we have to invert the Y axis
235 * in order to match the OpenGL pixel coordinate system, and our
236 * offset must be matched to the window position. If we're drawing
237 * to a user-created FBO then our native pixel coordinate system
238 * works just fine, and there's no window system to worry about.
240 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
241 poly
.PolygonStippleYOffset
=
242 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
247 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
249 .mesa
= _NEW_BUFFERS
|
251 .brw
= BRW_NEW_CONTEXT
,
253 .emit
= genX(upload_polygon_stipple_offset
),
257 * Line stipple packet
260 genX(upload_line_stipple
)(struct brw_context
*brw
)
262 struct gl_context
*ctx
= &brw
->ctx
;
264 if (!ctx
->Line
.StippleFlag
)
267 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
268 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
270 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
271 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
275 static const struct brw_tracked_state
genX(line_stipple
) = {
278 .brw
= BRW_NEW_CONTEXT
,
280 .emit
= genX(upload_line_stipple
),
283 /* Constant single cliprect for framebuffer object or DRI2 drawing */
285 genX(upload_drawing_rect
)(struct brw_context
*brw
)
287 struct gl_context
*ctx
= &brw
->ctx
;
288 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
289 const unsigned int fb_width
= _mesa_geometric_width(fb
);
290 const unsigned int fb_height
= _mesa_geometric_height(fb
);
292 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
293 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
294 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
298 static const struct brw_tracked_state
genX(drawing_rect
) = {
300 .mesa
= _NEW_BUFFERS
,
301 .brw
= BRW_NEW_BLORP
|
304 .emit
= genX(upload_drawing_rect
),
308 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
312 unsigned start_offset
,
317 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
318 .VertexBufferIndex
= buffer_nr
,
319 .BufferPitch
= stride
,
320 .BufferStartingAddress
= ro_bo(bo
, start_offset
),
322 .BufferSize
= end_offset
- start_offset
,
326 .AddressModifyEnable
= true,
330 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
331 .InstanceDataStepRate
= step_rate
,
333 .EndAddress
= ro_bo(bo
, end_offset
- 1),
338 .VertexBufferMOCS
= CNL_MOCS_WB
,
340 .VertexBufferMOCS
= SKL_MOCS_WB
,
342 .VertexBufferMOCS
= BDW_MOCS_WB
,
344 .VertexBufferMOCS
= GEN7_MOCS_L3
,
348 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
349 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
353 is_passthru_format(uint32_t format
)
356 case ISL_FORMAT_R64_PASSTHRU
:
357 case ISL_FORMAT_R64G64_PASSTHRU
:
358 case ISL_FORMAT_R64G64B64_PASSTHRU
:
359 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
367 uploads_needed(uint32_t format
,
370 if (!is_passthru_format(format
))
377 case ISL_FORMAT_R64_PASSTHRU
:
378 case ISL_FORMAT_R64G64_PASSTHRU
:
380 case ISL_FORMAT_R64G64B64_PASSTHRU
:
381 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
384 unreachable("not reached");
389 * Returns the format that we are finally going to use when upload a vertex
390 * element. It will only change if we are using *64*PASSTHRU formats, as for
391 * gen < 8 they need to be splitted on two *32*FLOAT formats.
393 * @upload points in which upload we are. Valid values are [0,1]
396 downsize_format_if_needed(uint32_t format
,
399 assert(upload
== 0 || upload
== 1);
401 if (!is_passthru_format(format
))
404 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
405 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
406 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
407 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
408 * flagging that we want to fill with zeroes this second forced upload.
411 case ISL_FORMAT_R64_PASSTHRU
:
412 return !upload
? ISL_FORMAT_R32G32_FLOAT
413 : ISL_FORMAT_R32_FLOAT
;
414 case ISL_FORMAT_R64G64_PASSTHRU
:
415 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
416 : ISL_FORMAT_R32_FLOAT
;
417 case ISL_FORMAT_R64G64B64_PASSTHRU
:
418 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
419 : ISL_FORMAT_R32G32_FLOAT
;
420 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
421 return ISL_FORMAT_R32G32B32A32_FLOAT
;
423 unreachable("not reached");
428 * Returns the number of componentes associated with a format that is used on
429 * a 64 to 32 format split. See downsize_format()
432 upload_format_size(uint32_t upload_format
)
434 switch (upload_format
) {
435 case ISL_FORMAT_R32_FLOAT
:
437 /* downsized_format has returned this one in order to flag that we are
438 * performing a second upload which we want to have filled with
439 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
440 * vertex shader input variables.
444 case ISL_FORMAT_R32G32_FLOAT
:
446 case ISL_FORMAT_R32G32B32A32_FLOAT
:
449 unreachable("not reached");
454 genX(emit_vertices
)(struct brw_context
*brw
)
456 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
459 brw_prepare_vertices(brw
);
460 brw_prepare_shader_draw_parameters(brw
);
463 brw_emit_query_begin(brw
);
466 const struct brw_vs_prog_data
*vs_prog_data
=
467 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
470 struct gl_context
*ctx
= &brw
->ctx
;
471 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
472 ctx
->Polygon
.BackMode
!= GL_FILL
);
474 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
475 unsigned vue
= brw
->vb
.nr_enabled
;
477 /* The element for the edge flags must always be last, so we have to
478 * insert the SGVS before it in that case.
480 if (uses_edge_flag
) {
486 "Trying to insert VID/IID past 33rd vertex element, "
487 "need to reorder the vertex attrbutes.");
489 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
490 if (vs_prog_data
->uses_vertexid
) {
491 vfs
.VertexIDEnable
= true;
492 vfs
.VertexIDComponentNumber
= 2;
493 vfs
.VertexIDElementOffset
= vue
;
496 if (vs_prog_data
->uses_instanceid
) {
497 vfs
.InstanceIDEnable
= true;
498 vfs
.InstanceIDComponentNumber
= 3;
499 vfs
.InstanceIDElementOffset
= vue
;
503 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
504 vfi
.InstancingEnable
= true;
505 vfi
.VertexElementIndex
= vue
;
508 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
511 /* Normally we don't need an element for the SGVS attribute because the
512 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
513 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
514 * we're using draw parameters then we need an element for the those
515 * values. Additionally if there is an edge flag element then the SGVS
516 * can't be inserted past that so we need a dummy element to ensure that
517 * the edge flag is the last one.
519 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
520 vs_prog_data
->uses_baseinstance
||
521 ((vs_prog_data
->uses_instanceid
||
522 vs_prog_data
->uses_vertexid
)
525 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
526 vs_prog_data
->uses_baseinstance
||
527 vs_prog_data
->uses_instanceid
||
528 vs_prog_data
->uses_vertexid
);
530 unsigned nr_elements
=
531 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
534 /* If any of the formats of vb.enabled needs more that one upload, we need
535 * to add it to nr_elements
537 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
538 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
539 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
541 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
546 /* If the VS doesn't read any inputs (calculating vertex position from
547 * a state variable for some reason, for example), emit a single pad
548 * VERTEX_ELEMENT struct and bail.
550 * The stale VB state stays in place, but they don't do anything unless
551 * a VE loads from them.
553 if (nr_elements
== 0) {
554 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
555 1 + GENX(VERTEX_ELEMENT_STATE_length
));
556 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
558 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
559 .Component0Control
= VFCOMP_STORE_0
,
560 .Component1Control
= VFCOMP_STORE_0
,
561 .Component2Control
= VFCOMP_STORE_0
,
562 .Component3Control
= VFCOMP_STORE_1_FP
,
564 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
568 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
569 const bool uses_draw_params
=
570 vs_prog_data
->uses_basevertex
||
571 vs_prog_data
->uses_baseinstance
;
572 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
573 uses_draw_params
+ vs_prog_data
->uses_drawid
;
576 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
578 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
579 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
581 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
582 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
583 /* Prior to Haswell and Bay Trail we have to use 4-component formats
584 * to fake 3-component ones. In particular, we do this for
585 * half-float and 8 and 16-bit integer formats. This means that the
586 * vertex element may poke over the end of the buffer by 2 bytes.
588 const unsigned padding
=
589 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
590 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
591 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
598 if (uses_draw_params
) {
599 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
600 brw
->draw
.draw_params_bo
,
601 brw
->draw
.draw_params_offset
,
602 brw
->draw
.draw_params_bo
->size
,
607 if (vs_prog_data
->uses_drawid
) {
608 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
609 brw
->draw
.draw_id_bo
,
610 brw
->draw
.draw_id_offset
,
611 brw
->draw
.draw_id_bo
->size
,
617 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
618 * presumably for VertexID/InstanceID.
621 assert(nr_elements
<= 34);
622 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
624 assert(nr_elements
<= 18);
627 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
628 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
630 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
631 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
632 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
633 uint32_t comp0
= VFCOMP_STORE_SRC
;
634 uint32_t comp1
= VFCOMP_STORE_SRC
;
635 uint32_t comp2
= VFCOMP_STORE_SRC
;
636 uint32_t comp3
= VFCOMP_STORE_SRC
;
637 const unsigned num_uploads
= GEN_GEN
< 8 ?
638 uploads_needed(format
, input
->is_dual_slot
) : 1;
641 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
642 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
643 * element which has edge flag enabled."
645 assert(!(is_passthru_format(format
) && uses_edge_flag
));
648 /* The gen4 driver expects edgeflag to come in as a float, and passes
649 * that float on to the tests in the clipper. Mesa's current vertex
650 * attribute value for EdgeFlag is stored as a float, which works out.
651 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
652 * integer ubyte. Just rewrite that to convert to a float.
654 * Gen6+ passes edgeflag as sideband along with the vertex, instead
655 * of in the VUE. We have to upload it sideband as the last vertex
656 * element according to the B-Spec.
659 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
660 gen6_edgeflag_input
= input
;
665 for (unsigned c
= 0; c
< num_uploads
; c
++) {
666 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
667 downsize_format_if_needed(format
, c
);
668 /* If we need more that one upload, the offset stride would be 128
669 * bits (16 bytes), as for previous uploads we are using the full
671 const unsigned offset
= input
->offset
+ c
* 16;
673 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
674 upload_format_size(upload_format
) : input
->glarray
->Size
;
677 case 0: comp0
= VFCOMP_STORE_0
;
678 case 1: comp1
= VFCOMP_STORE_0
;
679 case 2: comp2
= VFCOMP_STORE_0
;
681 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
682 comp3
= VFCOMP_STORE_0
;
683 } else if (input
->glarray
->Integer
) {
684 comp3
= VFCOMP_STORE_1_INT
;
686 comp3
= VFCOMP_STORE_1_FP
;
693 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
695 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
696 * formats, 64-bit components are stored in the URB without any
697 * conversion. In this case, vertex elements must be written as 128
698 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
699 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
700 * component into the URB, Component 1 must be specified as
701 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
702 * order to output a 128-bit vertex element, or Components 1-3 must
703 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
704 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
705 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
708 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
709 /* Store vertex elements which correspond to double and dvec2 vertex
710 * shader inputs as 128-bit vertex elements, instead of 256-bits.
712 comp2
= VFCOMP_NOSTORE
;
713 comp3
= VFCOMP_NOSTORE
;
717 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
718 .VertexBufferIndex
= input
->buffer
,
720 .SourceElementFormat
= upload_format
,
721 .SourceElementOffset
= offset
,
722 .Component0Control
= comp0
,
723 .Component1Control
= comp1
,
724 .Component2Control
= comp2
,
725 .Component3Control
= comp3
,
727 .DestinationElementOffset
= i
* 4,
731 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
732 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
736 if (needs_sgvs_element
) {
737 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
739 .Component0Control
= VFCOMP_STORE_0
,
740 .Component1Control
= VFCOMP_STORE_0
,
741 .Component2Control
= VFCOMP_STORE_0
,
742 .Component3Control
= VFCOMP_STORE_0
,
744 .DestinationElementOffset
= i
* 4,
749 if (vs_prog_data
->uses_basevertex
||
750 vs_prog_data
->uses_baseinstance
) {
751 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
752 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
753 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
754 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
757 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
758 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
759 if (vs_prog_data
->uses_basevertex
)
760 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
762 if (vs_prog_data
->uses_baseinstance
)
763 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
765 if (vs_prog_data
->uses_vertexid
)
766 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
768 if (vs_prog_data
->uses_instanceid
)
769 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
772 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
773 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
776 if (vs_prog_data
->uses_drawid
) {
777 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
779 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
780 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32_UINT
,
781 .Component0Control
= VFCOMP_STORE_SRC
,
782 .Component1Control
= VFCOMP_STORE_0
,
783 .Component2Control
= VFCOMP_STORE_0
,
784 .Component3Control
= VFCOMP_STORE_0
,
786 .DestinationElementOffset
= i
* 4,
790 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
791 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
795 if (gen6_edgeflag_input
) {
796 const uint32_t format
=
797 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
799 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
801 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
802 .EdgeFlagEnable
= true,
803 .SourceElementFormat
= format
,
804 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
805 .Component0Control
= VFCOMP_STORE_SRC
,
806 .Component1Control
= VFCOMP_STORE_0
,
807 .Component2Control
= VFCOMP_STORE_0
,
808 .Component3Control
= VFCOMP_STORE_0
,
811 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
812 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
817 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
818 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
819 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
820 unsigned element_index
;
822 /* The edge flag element is reordered to be the last one in the code
823 * above so we need to compensate for that in the element indices used
826 if (input
== gen6_edgeflag_input
)
827 element_index
= nr_elements
- 1;
831 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
832 vfi
.VertexElementIndex
= element_index
;
833 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
834 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
838 if (vs_prog_data
->uses_drawid
) {
839 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
841 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
842 vfi
.VertexElementIndex
= element
;
848 static const struct brw_tracked_state
genX(vertices
) = {
850 .mesa
= _NEW_POLYGON
,
851 .brw
= BRW_NEW_BATCH
|
854 BRW_NEW_VS_PROG_DATA
,
856 .emit
= genX(emit_vertices
),
860 genX(emit_index_buffer
)(struct brw_context
*brw
)
862 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
864 if (index_buffer
== NULL
)
867 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
868 #if GEN_GEN < 8 && !GEN_IS_HASWELL
869 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
871 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
872 ib
.BufferStartingAddress
= ro_bo(brw
->ib
.bo
, 0);
874 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
875 ib
.BufferSize
= brw
->ib
.size
;
877 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
882 static const struct brw_tracked_state
genX(index_buffer
) = {
885 .brw
= BRW_NEW_BATCH
|
887 BRW_NEW_INDEX_BUFFER
,
889 .emit
= genX(emit_index_buffer
),
892 #if GEN_IS_HASWELL || GEN_GEN >= 8
894 genX(upload_cut_index
)(struct brw_context
*brw
)
896 const struct gl_context
*ctx
= &brw
->ctx
;
898 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
899 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
900 vf
.IndexedDrawCutIndexEnable
= true;
901 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
906 const struct brw_tracked_state
genX(cut_index
) = {
908 .mesa
= _NEW_TRANSFORM
,
909 .brw
= BRW_NEW_INDEX_BUFFER
,
911 .emit
= genX(upload_cut_index
),
917 * Determine the appropriate attribute override value to store into the
918 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
919 * override value contains two pieces of information: the location of the
920 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
921 * flag indicating whether to "swizzle" the attribute based on the direction
922 * the triangle is facing.
924 * If an attribute is "swizzled", then the given VUE location is used for
925 * front-facing triangles, and the VUE location that immediately follows is
926 * used for back-facing triangles. We use this to implement the mapping from
927 * gl_FrontColor/gl_BackColor to gl_Color.
929 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
930 * being instructed to begin reading attribute data. It can be set to a
931 * nonzero value to prevent the SF unit from wasting time reading elements of
932 * the VUE that are not needed by the fragment shader. It is measured in
933 * 256-bit increments.
936 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
937 const struct brw_vue_map
*vue_map
,
938 int urb_entry_read_offset
, int fs_attr
,
939 bool two_side_color
, uint32_t *max_source_attr
)
941 /* Find the VUE slot for this attribute. */
942 int slot
= vue_map
->varying_to_slot
[fs_attr
];
944 /* Viewport and Layer are stored in the VUE header. We need to override
945 * them to zero if earlier stages didn't write them, as GL requires that
946 * they read back as zero when not explicitly set.
948 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
949 attr
->ComponentOverrideX
= true;
950 attr
->ComponentOverrideW
= true;
951 attr
->ConstantSource
= CONST_0000
;
953 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
954 attr
->ComponentOverrideY
= true;
955 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
956 attr
->ComponentOverrideZ
= true;
961 /* If there was only a back color written but not front, use back
962 * as the color instead of undefined
964 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
965 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
966 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
967 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
970 /* This attribute does not exist in the VUE--that means that the vertex
971 * shader did not write to it. This means that either:
973 * (a) This attribute is a texture coordinate, and it is going to be
974 * replaced with point coordinates (as a consequence of a call to
975 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
976 * hardware will ignore whatever attribute override we supply.
978 * (b) This attribute is read by the fragment shader but not written by
979 * the vertex shader, so its value is undefined. Therefore the
980 * attribute override we supply doesn't matter.
982 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
983 * previous shader stage.
985 * Note that we don't have to worry about the cases where the attribute
986 * is gl_PointCoord or is undergoing point sprite coordinate
987 * replacement, because in those cases, this function isn't called.
989 * In case (c), we need to program the attribute overrides so that the
990 * primitive ID will be stored in this slot. In every other case, the
991 * attribute override we supply doesn't matter. So just go ahead and
992 * program primitive ID in every case.
994 attr
->ComponentOverrideW
= true;
995 attr
->ComponentOverrideX
= true;
996 attr
->ComponentOverrideY
= true;
997 attr
->ComponentOverrideZ
= true;
998 attr
->ConstantSource
= PRIM_ID
;
1002 /* Compute the location of the attribute relative to urb_entry_read_offset.
1003 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1004 * it counts for two 128-bit VUE slots.
1006 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1007 assert(source_attr
>= 0 && source_attr
< 32);
1009 /* If we are doing two-sided color, and the VUE slot following this one
1010 * represents a back-facing color, then we need to instruct the SF unit to
1011 * do back-facing swizzling.
1013 bool swizzling
= two_side_color
&&
1014 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1015 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1016 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1017 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1019 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1020 if (*max_source_attr
< source_attr
+ swizzling
)
1021 *max_source_attr
= source_attr
+ swizzling
;
1023 attr
->SourceAttribute
= source_attr
;
1025 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1030 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1031 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1032 uint32_t *point_sprite_enables
,
1033 uint32_t *urb_entry_read_length
,
1034 uint32_t *urb_entry_read_offset
)
1036 const struct gl_context
*ctx
= &brw
->ctx
;
1039 const struct gl_point_attrib
*point
= &ctx
->Point
;
1041 /* BRW_NEW_FRAGMENT_PROGRAM */
1042 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1044 /* BRW_NEW_FS_PROG_DATA */
1045 const struct brw_wm_prog_data
*wm_prog_data
=
1046 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1047 uint32_t max_source_attr
= 0;
1049 *point_sprite_enables
= 0;
1052 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1053 &brw
->vue_map_geom_out
);
1055 /* Each URB offset packs two varying slots */
1056 assert(first_slot
% 2 == 0);
1057 *urb_entry_read_offset
= first_slot
/ 2;
1059 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1060 * description of dw10 Point Sprite Texture Coordinate Enable:
1062 * "This field must be programmed to zero when non-point primitives
1065 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1066 * must be programmed to zero when rendering non-point primitives, but
1067 * the IvyBridge PRM does, and if we don't, we get garbage.
1069 * This is not required on Haswell, as the hardware ignores this state
1070 * when drawing non-points -- although we do still need to be careful to
1071 * correctly set the attr overrides.
1074 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1076 bool drawing_points
= brw_is_drawing_points(brw
);
1078 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1079 int input_index
= wm_prog_data
->urb_setup
[attr
];
1081 if (input_index
< 0)
1085 bool point_sprite
= false;
1086 if (drawing_points
) {
1087 if (point
->PointSprite
&&
1088 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1089 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1090 point_sprite
= true;
1093 if (attr
== VARYING_SLOT_PNTC
)
1094 point_sprite
= true;
1097 *point_sprite_enables
|= (1 << input_index
);
1100 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1101 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1103 if (!point_sprite
) {
1104 genX(get_attr_override
)(&attribute
,
1105 &brw
->vue_map_geom_out
,
1106 *urb_entry_read_offset
, attr
,
1107 _mesa_vertex_program_two_side_enabled(ctx
),
1111 /* The hardware can only do the overrides on 16 overrides at a
1112 * time, and the other up to 16 have to be lined up so that the
1113 * input index = the output index. We'll need to do some
1114 * tweaking to make sure that's the case.
1116 if (input_index
< 16)
1117 attr_overrides
[input_index
] = attribute
;
1119 assert(attribute
.SourceAttribute
== input_index
);
1122 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1123 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1125 * "This field should be set to the minimum length required to read the
1126 * maximum source attribute. The maximum source attribute is indicated
1127 * by the maximum value of the enabled Attribute # Source Attribute if
1128 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1129 * enable is not set.
1130 * read_length = ceiling((max_source_attr + 1) / 2)
1132 * [errata] Corruption/Hang possible if length programmed larger than
1135 * Similar text exists for Ivy Bridge.
1137 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1141 /* ---------------------------------------------------------------------- */
1144 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1146 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1148 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1152 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1154 struct gl_context
*ctx
= &brw
->ctx
;
1157 struct intel_renderbuffer
*depth_irb
=
1158 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1161 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1164 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1165 const int b
= stencil
->_BackFace
;
1167 if (depth
->Test
&& depth_irb
) {
1168 ds
->DepthTestEnable
= true;
1169 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1170 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1173 if (brw
->stencil_enabled
) {
1174 ds
->StencilTestEnable
= true;
1175 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1176 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1178 ds
->StencilTestFunction
=
1179 intel_translate_compare_func(stencil
->Function
[0]);
1181 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1182 ds
->StencilPassDepthPassOp
=
1183 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1184 ds
->StencilPassDepthFailOp
=
1185 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1187 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1189 if (brw
->stencil_two_sided
) {
1190 ds
->DoubleSidedStencilEnable
= true;
1191 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1192 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1194 ds
->BackfaceStencilTestFunction
=
1195 intel_translate_compare_func(stencil
->Function
[b
]);
1196 ds
->BackfaceStencilFailOp
=
1197 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1198 ds
->BackfaceStencilPassDepthPassOp
=
1199 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1200 ds
->BackfaceStencilPassDepthFailOp
=
1201 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1204 #if GEN_GEN <= 5 || GEN_GEN >= 9
1205 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1206 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1213 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1216 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1217 set_depth_stencil_bits(brw
, &wmds
);
1221 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1222 set_depth_stencil_bits(brw
, &ds
);
1225 /* Now upload a pointer to the indirect state */
1227 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1228 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1229 ptr
.DEPTH_STENCIL_STATEChange
= true;
1232 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1233 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1239 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1241 .mesa
= _NEW_BUFFERS
|
1244 .brw
= BRW_NEW_BLORP
|
1245 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1247 BRW_NEW_STATE_BASE_ADDRESS
),
1249 .emit
= genX(upload_depth_stencil_state
),
1253 /* ---------------------------------------------------------------------- */
1258 genX(upload_clip_state
)(struct brw_context
*brw
)
1260 struct gl_context
*ctx
= &brw
->ctx
;
1262 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1263 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1264 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1265 clip
.GRFRegisterCount
=
1266 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1267 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1268 clip
.SingleProgramFlow
= true;
1269 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1270 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1272 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1273 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1274 clip
.DispatchGRFStartRegisterForURBData
= 1;
1275 clip
.VertexURBEntryReadOffset
= 0;
1277 /* BRW_NEW_URB_FENCE */
1278 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1279 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1281 if (brw
->urb
.nr_clip_entries
>= 10) {
1282 /* Half of the URB entries go to each thread, and it has to be an
1285 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1287 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1288 * only 2 threads can output VUEs at a time.
1290 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1292 assert(brw
->urb
.nr_clip_entries
>= 5);
1293 clip
.MaximumNumberofThreads
= 1 - 1;
1296 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1297 clip
.UserClipFlagsMustClipEnable
= true;
1298 clip
.GuardbandClipTestEnable
= true;
1300 clip
.ClipperViewportStatePointer
=
1301 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1303 clip
.ScreenSpaceViewportXMin
= -1;
1304 clip
.ScreenSpaceViewportXMax
= 1;
1305 clip
.ScreenSpaceViewportYMin
= -1;
1306 clip
.ScreenSpaceViewportYMax
= 1;
1308 clip
.ViewportXYClipTestEnable
= true;
1309 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1311 /* _NEW_TRANSFORM */
1312 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1313 clip
.UserClipDistanceClipTestEnableBitmask
=
1314 ctx
->Transform
.ClipPlanesEnabled
;
1316 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1319 clip
.UserClipDistanceClipTestEnableBitmask
=
1320 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1323 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1324 clip
.APIMode
= APIMODE_D3D
;
1326 clip
.APIMode
= APIMODE_OGL
;
1328 clip
.GuardbandClipTestEnable
= true;
1330 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1333 clip
.NegativeWClipTestEnable
= true;
1338 const struct brw_tracked_state
genX(clip_state
) = {
1340 .mesa
= _NEW_TRANSFORM
|
1342 .brw
= BRW_NEW_BATCH
|
1344 BRW_NEW_CLIP_PROG_DATA
|
1345 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1346 BRW_NEW_PROGRAM_CACHE
|
1349 .emit
= genX(upload_clip_state
),
1355 genX(upload_clip_state
)(struct brw_context
*brw
)
1357 struct gl_context
*ctx
= &brw
->ctx
;
1360 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1362 /* BRW_NEW_FS_PROG_DATA */
1363 struct brw_wm_prog_data
*wm_prog_data
=
1364 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1366 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1367 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1369 if (wm_prog_data
->barycentric_interp_modes
&
1370 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1371 clip
.NonPerspectiveBarycentricEnable
= true;
1374 clip
.EarlyCullEnable
= true;
1378 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1380 if (ctx
->Polygon
.CullFlag
) {
1381 switch (ctx
->Polygon
.CullFaceMode
) {
1383 clip
.CullMode
= CULLMODE_FRONT
;
1386 clip
.CullMode
= CULLMODE_BACK
;
1388 case GL_FRONT_AND_BACK
:
1389 clip
.CullMode
= CULLMODE_BOTH
;
1392 unreachable("Should not get here: invalid CullFlag");
1395 clip
.CullMode
= CULLMODE_NONE
;
1400 clip
.UserClipDistanceCullTestEnableBitmask
=
1401 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1403 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1407 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1408 clip
.TriangleStripListProvokingVertexSelect
= 0;
1409 clip
.TriangleFanProvokingVertexSelect
= 1;
1410 clip
.LineStripListProvokingVertexSelect
= 0;
1412 clip
.TriangleStripListProvokingVertexSelect
= 2;
1413 clip
.TriangleFanProvokingVertexSelect
= 2;
1414 clip
.LineStripListProvokingVertexSelect
= 1;
1417 /* _NEW_TRANSFORM */
1418 clip
.UserClipDistanceClipTestEnableBitmask
=
1419 ctx
->Transform
.ClipPlanesEnabled
;
1422 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1425 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1426 clip
.APIMode
= APIMODE_D3D
;
1428 clip
.APIMode
= APIMODE_OGL
;
1430 clip
.GuardbandClipTestEnable
= true;
1432 /* BRW_NEW_VIEWPORT_COUNT */
1433 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1435 if (ctx
->RasterDiscard
) {
1436 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1438 perf_debug("Rasterizer discard is currently implemented via the "
1439 "clipper; having the GS not write primitives would "
1440 "likely be faster.\n");
1443 clip
.ClipMode
= CLIPMODE_NORMAL
;
1446 clip
.ClipEnable
= true;
1449 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1451 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1452 clip
.ViewportXYClipTestEnable
= true;
1454 clip
.MinimumPointWidth
= 0.125;
1455 clip
.MaximumPointWidth
= 255.875;
1456 clip
.MaximumVPIndex
= viewport_count
- 1;
1457 if (_mesa_geometric_layers(fb
) == 0)
1458 clip
.ForceZeroRTAIndexEnable
= true;
1462 static const struct brw_tracked_state
genX(clip_state
) = {
1464 .mesa
= _NEW_BUFFERS
|
1468 .brw
= BRW_NEW_BLORP
|
1470 BRW_NEW_FS_PROG_DATA
|
1471 BRW_NEW_GS_PROG_DATA
|
1472 BRW_NEW_VS_PROG_DATA
|
1473 BRW_NEW_META_IN_PROGRESS
|
1475 BRW_NEW_RASTERIZER_DISCARD
|
1476 BRW_NEW_TES_PROG_DATA
|
1477 BRW_NEW_VIEWPORT_COUNT
,
1479 .emit
= genX(upload_clip_state
),
1483 /* ---------------------------------------------------------------------- */
1486 genX(upload_sf
)(struct brw_context
*brw
)
1488 struct gl_context
*ctx
= &brw
->ctx
;
1493 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1494 UNUSED
const bool multisampled_fbo
=
1495 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1499 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1501 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1503 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1504 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1505 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1506 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1507 sf
.DispatchGRFStartRegisterForURBData
= 3;
1508 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1509 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1510 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1511 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1513 /* STATE_PREFETCH command description describes this state as being
1514 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1517 sf
.SetupViewportStateOffset
=
1518 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1520 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1522 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1523 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1525 sf
.MaximumNumberofThreads
=
1526 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1528 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1530 sf
.DestinationOriginHorizontalBias
= 0.5;
1531 sf
.DestinationOriginVerticalBias
= 0.5;
1533 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1534 sf
.StatisticsEnable
= true;
1536 sf
.ViewportTransformEnable
= true;
1540 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1545 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1547 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1548 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1549 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1551 switch (ctx
->Polygon
.FrontMode
) {
1553 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1556 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1559 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1562 unreachable("not reached");
1565 switch (ctx
->Polygon
.BackMode
) {
1567 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1570 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1573 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1576 unreachable("not reached");
1579 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1580 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1582 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1583 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1584 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1587 sf
.ScissorRectangleEnable
= true;
1589 if (ctx
->Polygon
.CullFlag
) {
1590 switch (ctx
->Polygon
.CullFaceMode
) {
1592 sf
.CullMode
= CULLMODE_FRONT
;
1595 sf
.CullMode
= CULLMODE_BACK
;
1597 case GL_FRONT_AND_BACK
:
1598 sf
.CullMode
= CULLMODE_BOTH
;
1601 unreachable("not reached");
1604 sf
.CullMode
= CULLMODE_NONE
;
1608 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1615 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1617 if (devinfo
->is_cherryview
)
1618 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1620 sf
.LineWidth
= brw_get_line_width(brw
);
1622 sf
.LineWidth
= brw_get_line_width(brw
);
1625 if (ctx
->Line
.SmoothFlag
) {
1626 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1628 sf
.AntiAliasingEnable
= true;
1632 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1633 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1634 /* Clamp to the hardware limits */
1635 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1637 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1638 if (use_state_point_size(brw
))
1639 sf
.PointWidthSource
= State
;
1642 /* _NEW_POINT | _NEW_MULTISAMPLE */
1643 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1644 !ctx
->Point
.PointSprite
)
1645 sf
.SmoothPointEnable
= true;
1650 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1652 const bool multisampled_fbo
=
1653 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1654 if (multisampled_fbo
)
1655 sf
.SmoothPointEnable
= false;
1658 #if GEN_IS_G4X || GEN_GEN >= 5
1659 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1663 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1664 sf
.TriangleStripListProvokingVertexSelect
= 2;
1665 sf
.TriangleFanProvokingVertexSelect
= 2;
1666 sf
.LineStripListProvokingVertexSelect
= 1;
1668 sf
.TriangleFanProvokingVertexSelect
= 1;
1672 /* BRW_NEW_FS_PROG_DATA */
1673 const struct brw_wm_prog_data
*wm_prog_data
=
1674 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1676 sf
.AttributeSwizzleEnable
= true;
1677 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1680 * Window coordinates in an FBO are inverted, which means point
1681 * sprite origin must be inverted, too.
1683 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1684 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1686 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1689 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1690 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1692 uint32_t urb_entry_read_length
;
1693 uint32_t urb_entry_read_offset
;
1694 uint32_t point_sprite_enables
;
1695 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1696 &urb_entry_read_length
,
1697 &urb_entry_read_offset
);
1698 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1699 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1700 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1701 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1706 static const struct brw_tracked_state
genX(sf_state
) = {
1708 .mesa
= _NEW_LIGHT
|
1712 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1713 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1714 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1715 .brw
= BRW_NEW_BLORP
|
1716 BRW_NEW_VUE_MAP_GEOM_OUT
|
1717 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1718 BRW_NEW_PROGRAM_CACHE
|
1719 BRW_NEW_SF_PROG_DATA
|
1723 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1724 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1725 BRW_NEW_GS_PROG_DATA
|
1727 BRW_NEW_TES_PROG_DATA
1729 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1730 BRW_NEW_FRAGMENT_PROGRAM
1733 .emit
= genX(upload_sf
),
1736 /* ---------------------------------------------------------------------- */
1739 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1741 struct gl_context
*ctx
= &brw
->ctx
;
1742 /* BRW_NEW_FRAGMENT_PROGRAM */
1743 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1747 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1748 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1749 uint64_t outputs_written
= fp
->info
.outputs_written
;
1752 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1753 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1754 (ctx
->Color
.ColorMask
[i
][0] ||
1755 ctx
->Color
.ColorMask
[i
][1] ||
1756 ctx
->Color
.ColorMask
[i
][2] ||
1757 ctx
->Color
.ColorMask
[i
][3])) {
1766 genX(upload_wm
)(struct brw_context
*brw
)
1768 struct gl_context
*ctx
= &brw
->ctx
;
1770 /* BRW_NEW_FS_PROG_DATA */
1771 const struct brw_wm_prog_data
*wm_prog_data
=
1772 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1774 UNUSED
bool writes_depth
=
1775 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1776 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1777 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1780 /* We can't fold this into gen6_upload_wm_push_constants(), because
1781 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1782 * (3DSTATE_CONSTANT_PS [DevSNB]):
1784 * "[DevSNB]: This packet must be followed by WM_STATE."
1786 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1787 if (wm_prog_data
->base
.nr_params
!= 0) {
1788 wmcp
.Buffer0Valid
= true;
1789 /* Pointer to the WM constant buffer. Covered by the set of
1790 * state flags from gen6_upload_wm_push_constants.
1792 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1793 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1799 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1800 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1801 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1803 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1804 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1806 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1807 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1808 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1809 /* These two fields should be the same pre-gen6, which is why we
1810 * only have one hardware field to program for both dispatch
1813 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1814 wm_prog_data
->dispatch_grf_start_reg_2
);
1817 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1818 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1820 if (stage_state
->sampler_count
)
1821 wm
.SamplerStatePointer
=
1822 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1824 if (wm_prog_data
->prog_offset_2
)
1825 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1828 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1829 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1830 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1831 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1832 wm
.EarlyDepthTestEnable
= true;
1833 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1834 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1837 if (ctx
->Polygon
.OffsetFill
) {
1838 wm
.GlobalDepthOffsetEnable
= true;
1839 /* Something weird going on with legacy_global_depth_bias,
1840 * offset_constant, scaling and MRD. This value passes glean
1841 * but gives some odd results elsewere (eg. the
1842 * quad-offset-units test).
1844 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1846 /* This is the only value that passes glean:
1848 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1851 wm
.DepthCoefficientURBReadOffset
= 1;
1854 /* BRW_NEW_STATS_WM */
1855 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1858 if (wm_prog_data
->base
.use_alt_mode
)
1859 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1861 wm
.SamplerCount
= GEN_GEN
== 5 ?
1862 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1864 wm
.BindingTableEntryCount
=
1865 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1866 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1867 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1868 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1869 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1870 wm_prog_data
->base
.dispatch_grf_start_reg
;
1872 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1873 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1877 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1878 wm
.KernelStartPointer2
=
1879 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1884 wm
.DualSourceBlendEnable
=
1885 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1886 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1887 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1888 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1890 /* From the SNB PRM, volume 2 part 1, page 281:
1891 * "If the PS kernel does not need the Position XY Offsets
1892 * to compute a Position XY value, then this field should be
1893 * programmed to POSOFFSET_NONE."
1895 * "SW Recommendation: If the PS kernel needs the Position Offsets
1896 * to compute a Position XY value, this field should match Position
1897 * ZW Interpolation Mode to ensure a consistent position.xyzw
1899 * We only require XY sample offsets. So, this recommendation doesn't
1900 * look useful at the moment. We might need this in future.
1902 if (wm_prog_data
->uses_pos_offset
)
1903 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1905 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1907 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1908 wm_prog_data
->dispatch_grf_start_reg_2
;
1911 if (wm_prog_data
->base
.total_scratch
) {
1912 wm
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
1913 wm
.PerThreadScratchSpace
=
1914 ffs(stage_state
->per_thread_scratch
) - 11;
1917 wm
.PixelShaderComputedDepth
= writes_depth
;
1921 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1924 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1929 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1932 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1934 if (multisampled_fbo
) {
1935 /* _NEW_MULTISAMPLE */
1936 if (ctx
->Multisample
.Enabled
)
1937 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1939 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1941 if (wm_prog_data
->persample_dispatch
)
1942 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1944 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1946 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1947 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1950 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1951 if (wm_prog_data
->uses_kill
||
1952 _mesa_is_alpha_test_enabled(ctx
) ||
1953 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1954 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1955 wm
.PixelShaderKillsPixel
= true;
1958 /* _NEW_BUFFERS | _NEW_COLOR */
1959 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1960 wm
.PixelShaderKillsPixel
||
1961 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1962 wm
.ThreadDispatchEnable
= true;
1966 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1967 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1970 /* The "UAV access enable" bits are unnecessary on HSW because they only
1971 * seem to have an effect on the HW-assisted coherency mechanism which we
1972 * don't need, and the rasterization-related UAV_ONLY flag and the
1973 * DISPATCH_ENABLE bit can be set independently from it.
1974 * C.f. gen8_upload_ps_extra().
1976 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1980 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1981 wm_prog_data
->has_side_effects
)
1987 /* BRW_NEW_FS_PROG_DATA */
1988 if (wm_prog_data
->early_fragment_tests
)
1989 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1990 else if (wm_prog_data
->has_side_effects
)
1991 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1996 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
1997 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
1998 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
2001 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
2006 static const struct brw_tracked_state
genX(wm_state
) = {
2010 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
2013 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2014 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2015 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2016 .brw
= BRW_NEW_BLORP
|
2017 BRW_NEW_FS_PROG_DATA
|
2018 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2019 BRW_NEW_FRAGMENT_PROGRAM
|
2020 BRW_NEW_PROGRAM_CACHE
|
2021 BRW_NEW_SAMPLER_STATE_TABLE
|
2024 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2026 .emit
= genX(upload_wm
),
2029 /* ---------------------------------------------------------------------- */
2031 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2032 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2033 pkt.SamplerCount = \
2034 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2035 pkt.BindingTableEntryCount = \
2036 stage_prog_data->binding_table.size_bytes / 4; \
2037 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2039 if (stage_prog_data->total_scratch) { \
2040 pkt.ScratchSpaceBasePointer = rw_bo(stage_state->scratch_bo, 0); \
2041 pkt.PerThreadScratchSpace = \
2042 ffs(stage_state->per_thread_scratch) - 11; \
2045 pkt.DispatchGRFStartRegisterForURBData = \
2046 stage_prog_data->dispatch_grf_start_reg; \
2047 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2048 pkt.prefix##URBEntryReadOffset = 0; \
2050 pkt.StatisticsEnable = true; \
2054 genX(upload_vs_state
)(struct brw_context
*brw
)
2056 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2057 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2058 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2060 /* BRW_NEW_VS_PROG_DATA */
2061 const struct brw_vue_prog_data
*vue_prog_data
=
2062 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2063 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2065 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2066 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2069 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2070 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2072 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2073 * command that causes the VS Function Enable to toggle. Pipeline
2074 * flush can be executed by sending a PIPE_CONTROL command with CS
2075 * stall bit set and a post sync operation.
2077 * We've already done such a flush at the start of state upload, so we
2078 * don't need to do another one here.
2080 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2081 if (stage_state
->push_const_size
!= 0) {
2082 cvs
.Buffer0Valid
= true;
2083 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2084 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2089 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2090 gen7_emit_vs_workaround_flush(brw
);
2093 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2095 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2096 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2098 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2100 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2103 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2104 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2105 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2107 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2108 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2110 vs
.MaximumNumberofThreads
=
2111 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2113 vs
.StatisticsEnable
= false;
2114 vs
.SamplerStatePointer
=
2115 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2119 /* Force single program flow on Ironlake. We cannot reliably get
2120 * all applications working without it. See:
2121 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2123 * The most notable and reliably failing application is the Humus
2126 vs
.SingleProgramFlow
= true;
2127 vs
.SamplerCount
= 0; /* hardware requirement */
2131 vs
.SIMD8DispatchEnable
=
2132 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2134 vs
.UserClipDistanceCullTestEnableBitmask
=
2135 vue_prog_data
->cull_distance_mask
;
2140 /* Based on my reading of the simulator, the VS constants don't get
2141 * pulled into the VS FF unit until an appropriate pipeline flush
2142 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2143 * references to them into a little FIFO. The flushes are common,
2144 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2145 * the primitive to use the wrong constants. Then the FIFO
2146 * containing the constant setup gets added to again on the next
2147 * constants change, and eventually when a flush does happen the
2148 * unit is overwhelmed by constant changes and dies.
2150 * To avoid this, send a PIPE_CONTROL down the line that will
2151 * update the unit immediately loading the constants. The flush
2152 * type bits here were those set by the STATE_BASE_ADDRESS whose
2153 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2154 * bug reports that led to this workaround, and may be more than
2155 * what is strictly required to avoid the issue.
2157 brw_emit_pipe_control_flush(brw
,
2158 PIPE_CONTROL_DEPTH_STALL
|
2159 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2160 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2164 static const struct brw_tracked_state
genX(vs_state
) = {
2166 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2167 .brw
= BRW_NEW_BATCH
|
2170 BRW_NEW_VS_PROG_DATA
|
2171 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2172 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2173 BRW_NEW_PROGRAM_CACHE
|
2174 BRW_NEW_SAMPLER_STATE_TABLE
|
2178 .emit
= genX(upload_vs_state
),
2181 /* ---------------------------------------------------------------------- */
2184 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2186 struct gl_context
*ctx
= &brw
->ctx
;
2188 /* BRW_NEW_VIEWPORT_COUNT */
2189 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2191 struct GENX(CC_VIEWPORT
) ccv
;
2192 uint32_t cc_vp_offset
;
2194 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2197 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2198 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2199 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2200 if (ctx
->Transform
.DepthClamp
) {
2201 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2202 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2204 ccv
.MinimumDepth
= 0.0;
2205 ccv
.MaximumDepth
= 1.0;
2207 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2208 cc_map
+= GENX(CC_VIEWPORT_length
);
2212 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2213 ptr
.CCViewportPointer
= cc_vp_offset
;
2216 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2217 vp
.CCViewportStateChange
= 1;
2218 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2221 brw
->cc
.vp_offset
= cc_vp_offset
;
2222 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2226 const struct brw_tracked_state
genX(cc_vp
) = {
2228 .mesa
= _NEW_TRANSFORM
|
2230 .brw
= BRW_NEW_BATCH
|
2232 BRW_NEW_VIEWPORT_COUNT
,
2234 .emit
= genX(upload_cc_viewport
)
2237 /* ---------------------------------------------------------------------- */
2240 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2241 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2242 struct GENX(SCISSOR_RECT
) *sc
)
2246 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2247 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2248 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2249 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2250 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2252 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2253 /* If the scissor was out of bounds and got clamped to 0 width/height
2254 * at the bounds, the subtraction of 1 from maximums could produce a
2255 * negative number and thus not clip anything. Instead, just provide
2256 * a min > max scissor inside the bounds, which produces the expected
2259 sc
->ScissorRectangleXMin
= 1;
2260 sc
->ScissorRectangleXMax
= 0;
2261 sc
->ScissorRectangleYMin
= 1;
2262 sc
->ScissorRectangleYMax
= 0;
2263 } else if (render_to_fbo
) {
2264 /* texmemory: Y=0=bottom */
2265 sc
->ScissorRectangleXMin
= bbox
[0];
2266 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2267 sc
->ScissorRectangleYMin
= bbox
[2];
2268 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2270 /* memory: Y=0=top */
2271 sc
->ScissorRectangleXMin
= bbox
[0];
2272 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2273 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2274 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2280 genX(upload_scissor_state
)(struct brw_context
*brw
)
2282 struct gl_context
*ctx
= &brw
->ctx
;
2283 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2284 struct GENX(SCISSOR_RECT
) scissor
;
2285 uint32_t scissor_state_offset
;
2286 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2287 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2288 uint32_t *scissor_map
;
2290 /* BRW_NEW_VIEWPORT_COUNT */
2291 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2293 scissor_map
= brw_state_batch(
2294 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2295 32, &scissor_state_offset
);
2297 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2299 /* The scissor only needs to handle the intersection of drawable and
2300 * scissor rect. Clipping to the boundaries of static shared buffers
2301 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2303 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2304 * inclusive but max is exclusive.
2306 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2307 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2308 GENX(SCISSOR_RECT_pack
)(
2309 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2312 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2313 ptr
.ScissorRectPointer
= scissor_state_offset
;
2317 static const struct brw_tracked_state
genX(scissor_state
) = {
2319 .mesa
= _NEW_BUFFERS
|
2322 .brw
= BRW_NEW_BATCH
|
2324 BRW_NEW_VIEWPORT_COUNT
,
2326 .emit
= genX(upload_scissor_state
),
2330 /* ---------------------------------------------------------------------- */
2333 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2334 float m00
, float m11
, float m30
, float m31
,
2335 float *xmin
, float *xmax
,
2336 float *ymin
, float *ymax
)
2338 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2339 * Strips and Fans documentation:
2341 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2342 * fixed-point "guardband" range supported by the rasterization hardware"
2346 * "In almost all circumstances, if an object’s vertices are actually
2347 * modified by this clamping (i.e., had X or Y coordinates outside of
2348 * the guardband extent the rendered object will not match the intended
2349 * result. Therefore software should take steps to ensure that this does
2350 * not happen - e.g., by clipping objects such that they do not exceed
2351 * these limits after the Drawing Rectangle is applied."
2353 * I believe the fundamental restriction is that the rasterizer (in
2354 * the SF/WM stages) have a limit on the number of pixels that can be
2355 * rasterized. We need to ensure any coordinates beyond the rasterizer
2356 * limit are handled by the clipper. So effectively that limit becomes
2357 * the clipper's guardband size.
2359 * It goes on to say:
2361 * "In addition, in order to be correctly rendered, objects must have a
2362 * screenspace bounding box not exceeding 8K in the X or Y direction.
2363 * This additional restriction must also be comprehended by software,
2364 * i.e., enforced by use of clipping."
2366 * This makes no sense. Gen7+ hardware supports 16K render targets,
2367 * and you definitely need to be able to draw polygons that fill the
2368 * surface. Our assumption is that the rasterizer was limited to 8K
2369 * on Sandybridge, which only supports 8K surfaces, and it was actually
2370 * increased to 16K on Ivybridge and later.
2372 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2374 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2376 if (m00
!= 0 && m11
!= 0) {
2377 /* First, we compute the screen-space render area */
2378 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2379 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2380 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2381 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2383 /* We want the guardband to be centered on that */
2384 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2385 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2386 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2387 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2389 /* Now we need it in native device coordinates */
2390 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2391 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2392 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2393 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2395 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2396 * flipped upside-down. X should be fine though.
2398 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2399 *xmin
= ndc_gb_xmin
;
2400 *xmax
= ndc_gb_xmax
;
2401 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2402 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2404 /* The viewport scales to 0, so nothing will be rendered. */
2413 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2415 struct gl_context
*ctx
= &brw
->ctx
;
2416 float y_scale
, y_bias
;
2418 /* BRW_NEW_VIEWPORT_COUNT */
2419 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2422 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2423 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2424 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2428 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2429 uint32_t sf_clip_vp_offset
;
2430 uint32_t *sf_clip_map
=
2431 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2432 64, &sf_clip_vp_offset
);
2434 struct GENX(SF_VIEWPORT
) sfv
;
2435 struct GENX(CLIP_VIEWPORT
) clv
;
2436 uint32_t sf_vp_offset
, clip_vp_offset
;
2438 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2440 uint32_t *clip_map
=
2441 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2442 32, &clip_vp_offset
);
2446 if (render_to_fbo
) {
2451 y_bias
= (float)fb_height
;
2454 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2455 /* _NEW_VIEWPORT: Guardband Clipping */
2456 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2457 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2459 sfv
.ViewportMatrixElementm00
= scale
[0];
2460 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2461 sfv
.ViewportMatrixElementm22
= scale
[2],
2462 sfv
.ViewportMatrixElementm30
= translate
[0],
2463 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2464 sfv
.ViewportMatrixElementm32
= translate
[2],
2465 brw_calculate_guardband_size(fb_width
, fb_height
,
2466 sfv
.ViewportMatrixElementm00
,
2467 sfv
.ViewportMatrixElementm11
,
2468 sfv
.ViewportMatrixElementm30
,
2469 sfv
.ViewportMatrixElementm31
,
2470 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2473 clv
.XMinClipGuardband
= gb_xmin
;
2474 clv
.XMaxClipGuardband
= gb_xmax
;
2475 clv
.YMinClipGuardband
= gb_ymin
;
2476 clv
.YMaxClipGuardband
= gb_ymax
;
2479 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2480 &sfv
.ScissorRectangle
);
2482 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2483 * The hardware will take the intersection of the drawing rectangle,
2484 * scissor rectangle, and the viewport extents. We don't need to be
2485 * smart, and can therefore just program the viewport extents.
2487 const float viewport_Xmax
=
2488 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2489 const float viewport_Ymax
=
2490 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2492 if (render_to_fbo
) {
2493 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2494 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2495 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2496 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2498 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2499 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2500 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2501 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2506 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2507 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2509 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2510 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2511 sf_map
+= GENX(SF_VIEWPORT_length
);
2512 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2517 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2518 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2521 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2522 vp
.SFViewportStateChange
= 1;
2523 vp
.CLIPViewportStateChange
= 1;
2524 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2525 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2528 brw
->sf
.vp_offset
= sf_vp_offset
;
2529 brw
->clip
.vp_offset
= clip_vp_offset
;
2530 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2534 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2536 .mesa
= _NEW_BUFFERS
|
2538 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2539 .brw
= BRW_NEW_BATCH
|
2541 BRW_NEW_VIEWPORT_COUNT
,
2543 .emit
= genX(upload_sf_clip_viewport
),
2546 /* ---------------------------------------------------------------------- */
2549 genX(upload_gs_state
)(struct brw_context
*brw
)
2551 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2552 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2553 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2554 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2555 /* BRW_NEW_GEOMETRY_PROGRAM */
2556 bool active
= GEN_GEN
>= 6 && gs_prog
;
2558 /* BRW_NEW_GS_PROG_DATA */
2559 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2560 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2561 brw_vue_prog_data(stage_prog_data
);
2563 const struct brw_gs_prog_data
*gs_prog_data
=
2564 brw_gs_prog_data(stage_prog_data
);
2568 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2569 if (active
&& stage_state
->push_const_size
!= 0) {
2570 cgs
.Buffer0Valid
= true;
2571 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2572 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2577 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2579 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2580 * Geometry > Geometry Shader > State:
2582 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2583 * whole fixed function pipeline when the GS enable changes value in
2586 * The hardware architects have clarified that in this context "flush the
2587 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2590 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2591 gen7_emit_cs_stall_flush(brw
);
2595 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2597 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2598 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2603 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2606 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2607 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2608 gs
.ControlDataHeaderSize
=
2609 gs_prog_data
->control_data_header_size_hwords
;
2611 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2612 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2614 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2616 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2619 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2620 * Ivy Bridge and Haswell.
2622 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2623 * strip to be delivered to the geometry shader in an order that does
2624 * not strictly follow the OpenGL spec, but preserves triangle
2625 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2626 * the geometry shader sees triangles:
2628 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2630 * (Clearing the bit is even worse, because it fails to preserve
2633 * Triangle strips with adjacency always ordered in a way that preserves
2634 * triangle orientation but does not strictly follow the OpenGL spec,
2635 * regardless of the setting of this bit.
2637 * On Haswell, both triangle strips and triangle strips with adjacency
2638 * are always ordered in a way that preserves triangle orientation.
2639 * Setting this bit causes the ordering to strictly follow the OpenGL
2642 * So in either case we want to set the bit. Unfortunately on Ivy
2643 * Bridge this will get the order close to correct but not perfect.
2645 gs
.ReorderMode
= TRAILING
;
2646 gs
.MaximumNumberofThreads
=
2647 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2648 : (devinfo
->max_gs_threads
- 1);
2651 gs
.SOStatisticsEnable
= true;
2652 if (gs_prog
->info
.has_transform_feedback_varyings
)
2653 gs
.SVBIPayloadEnable
= true;
2655 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2656 * was previously done for gen6.
2658 * TODO: test with both disabled to see if the HW is behaving
2659 * as expected, like in gen7.
2661 gs
.SingleProgramFlow
= true;
2662 gs
.VectorMaskEnable
= true;
2666 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2668 if (gs_prog_data
->static_vertex_count
!= -1) {
2669 gs
.StaticOutput
= true;
2670 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2672 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2674 gs
.UserClipDistanceCullTestEnableBitmask
=
2675 vue_prog_data
->cull_distance_mask
;
2677 const int urb_entry_write_offset
= 1;
2678 const uint32_t urb_entry_output_length
=
2679 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2680 urb_entry_write_offset
;
2682 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2683 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2689 if (!active
&& brw
->ff_gs
.prog_active
) {
2690 /* In gen6, transform feedback for the VS stage is done with an
2691 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2694 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2695 gs
.SingleProgramFlow
= true;
2696 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2697 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2700 gs
.GRFRegisterCount
=
2701 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2702 /* BRW_NEW_URB_FENCE */
2703 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2704 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2705 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2706 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2709 gs
.VectorMaskEnable
= true;
2710 gs
.SVBIPayloadEnable
= true;
2711 gs
.SVBIPostIncrementEnable
= true;
2712 gs
.SVBIPostIncrementValue
=
2713 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2714 gs
.SOStatisticsEnable
= true;
2715 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2719 if (!active
&& !brw
->ff_gs
.prog_active
) {
2721 gs
.DispatchGRFStartRegisterForURBData
= 1;
2723 gs
.IncludeVertexHandles
= true;
2729 gs
.StatisticsEnable
= true;
2731 #if GEN_GEN == 5 || GEN_GEN == 6
2732 gs
.RenderingEnabled
= true;
2735 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2740 brw
->gs
.enabled
= active
;
2744 static const struct brw_tracked_state
genX(gs_state
) = {
2746 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2747 .brw
= BRW_NEW_BATCH
|
2749 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2750 BRW_NEW_PROGRAM_CACHE
|
2752 BRW_NEW_VIEWPORT_COUNT
2754 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2755 BRW_NEW_GEOMETRY_PROGRAM
|
2756 BRW_NEW_GS_PROG_DATA
2758 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2760 .emit
= genX(upload_gs_state
),
2763 /* ---------------------------------------------------------------------- */
2765 UNUSED
static GLenum
2766 fix_dual_blend_alpha_to_one(GLenum function
)
2772 case GL_ONE_MINUS_SRC1_ALPHA
:
2779 #define blend_factor(x) brw_translate_blend_factor(x)
2780 #define blend_eqn(x) brw_translate_blend_equation(x)
2783 * Modify blend function to force destination alpha to 1.0
2785 * If \c function specifies a blend function that uses destination alpha,
2786 * replace it with a function that hard-wires destination alpha to 1.0. This
2787 * is used when rendering to xRGB targets.
2790 brw_fix_xRGB_alpha(GLenum function
)
2796 case GL_ONE_MINUS_DST_ALPHA
:
2797 case GL_SRC_ALPHA_SATURATE
:
2805 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2807 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2811 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2814 struct gl_context
*ctx
= &brw
->ctx
;
2817 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2819 bool independent_alpha_blend
= false;
2821 /* Used for implementing the following bit of GL_EXT_texture_integer:
2822 * "Per-fragment operations that require floating-point color
2823 * components, including multisample alpha operations, alpha test,
2824 * blending, and dithering, have no effect when the corresponding
2825 * colors are written to an integer color buffer."
2827 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2829 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2830 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2833 if (ctx
->Color
.ColorLogicOpEnabled
) {
2834 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2835 : GL_UNSIGNED_NORMALIZED
;
2836 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2837 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2838 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2840 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2841 _mesa_enum_to_string(rb_type
));
2842 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2843 entry
->LogicOpEnable
= true;
2844 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2846 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2847 && (GEN_GEN
<= 5 || !integer
)) {
2848 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2849 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2850 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2851 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2852 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2853 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2855 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2856 srcRGB
= dstRGB
= GL_ONE
;
2858 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2859 srcA
= dstA
= GL_ONE
;
2861 /* Due to hardware limitations, the destination may have information
2862 * in an alpha channel even when the format specifies no alpha
2863 * channel. In order to avoid getting any incorrect blending due to
2864 * that alpha channel, coerce the blend factors to values that will
2865 * not read the alpha channel, but will instead use the correct
2866 * implicit value for alpha.
2868 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2869 GL_TEXTURE_ALPHA_TYPE
)) {
2870 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2871 srcA
= brw_fix_xRGB_alpha(srcA
);
2872 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2873 dstA
= brw_fix_xRGB_alpha(dstA
);
2876 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2877 * "If Dual Source Blending is enabled, this bit must be disabled."
2879 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2880 * and leave it enabled anyway.
2882 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2883 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2884 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2885 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2886 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2889 entry
->ColorBufferBlendEnable
= true;
2890 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2891 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2892 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2893 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2894 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2895 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2897 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2898 independent_alpha_blend
= true;
2901 return independent_alpha_blend
;
2906 genX(upload_blend_state
)(struct brw_context
*brw
)
2908 struct gl_context
*ctx
= &brw
->ctx
;
2911 /* We need at least one BLEND_STATE written, because we might do
2912 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2913 * for computed depth or alpha test), which will do an FB write
2914 * with render target 0, which will reference BLEND_STATE[0] for
2915 * alpha test enable.
2917 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2918 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2919 nr_draw_buffers
= 1;
2921 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2923 size
+= GENX(BLEND_STATE_length
) * 4;
2926 uint32_t *blend_map
;
2927 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2930 struct GENX(BLEND_STATE
) blend
= { 0 };
2933 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2934 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2937 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2938 * "If drawbuffer zero is not NONE and the buffer it references has an
2939 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2940 * operations are skipped."
2942 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2943 /* _NEW_MULTISAMPLE */
2944 if (_mesa_is_multisample_enabled(ctx
)) {
2945 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2946 blend
.AlphaToCoverageEnable
= true;
2947 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2949 if (ctx
->Multisample
.SampleAlphaToOne
)
2950 blend
.AlphaToOneEnable
= true;
2954 if (ctx
->Color
.AlphaEnabled
) {
2955 blend
.AlphaTestEnable
= true;
2956 blend
.AlphaTestFunction
=
2957 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2960 if (ctx
->Color
.DitherFlag
) {
2961 blend
.ColorDitherEnable
= true;
2966 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2967 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2971 blend
.IndependentAlphaBlendEnable
=
2972 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
2973 blend
.IndependentAlphaBlendEnable
;
2975 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2976 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2978 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2979 * clamping in the fragment shader. For its clamping of
2980 * blending, the spec says:
2982 * "RESOLVED: For fixed-point color buffers, the inputs and
2983 * the result of the blending equation are clamped. For
2984 * floating-point color buffers, no clamping occurs."
2986 * So, generally, we want clamping to the render target's range.
2987 * And, good news, the hardware tables for both pre- and
2988 * post-blend color clamping are either ignored, or any are
2989 * allowed, or clamping is required but RT range clamping is a
2992 entry
.PreBlendColorClampEnable
= true;
2993 entry
.PostBlendColorClampEnable
= true;
2994 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2996 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2997 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2998 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2999 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
3002 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
3004 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3010 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3014 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3015 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3016 ptr
.BLEND_STATEChange
= true;
3019 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3020 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3022 ptr
.BlendStatePointerValid
= true;
3028 static const struct brw_tracked_state
genX(blend_state
) = {
3030 .mesa
= _NEW_BUFFERS
|
3033 .brw
= BRW_NEW_BATCH
|
3035 BRW_NEW_STATE_BASE_ADDRESS
,
3037 .emit
= genX(upload_blend_state
),
3041 /* ---------------------------------------------------------------------- */
3044 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3045 [MESA_SHADER_VERTEX
] = 21,
3046 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3047 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3048 [MESA_SHADER_GEOMETRY
] = 22,
3049 [MESA_SHADER_FRAGMENT
] = 23,
3050 [MESA_SHADER_COMPUTE
] = 0,
3054 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3056 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3057 struct gl_context
*ctx
= &brw
->ctx
;
3059 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3061 struct brw_stage_state
*stage_states
[] = {
3069 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3070 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3071 gen7_emit_vs_workaround_flush(brw
);
3073 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3074 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3075 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3077 if (!stage_state
->push_constants_dirty
)
3080 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3081 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3082 if (stage_state
->prog_data
) {
3083 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3084 /* The Skylake PRM contains the following restriction:
3086 * "The driver must ensure The following case does not occur
3087 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3088 * buffer 3 read length equal to zero committed followed by a
3089 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3092 * To avoid this, we program the buffers in the highest slots.
3093 * This way, slot 0 is only used if slot 3 is also used.
3097 for (int i
= 3; i
>= 0; i
--) {
3098 const struct brw_ubo_range
*range
=
3099 &stage_state
->prog_data
->ubo_ranges
[i
];
3101 if (range
->length
== 0)
3104 const struct gl_uniform_block
*block
=
3105 prog
->sh
.UniformBlocks
[range
->block
];
3106 const struct gl_buffer_binding
*binding
=
3107 &ctx
->UniformBufferBindings
[block
->Binding
];
3109 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3110 static unsigned msg_id
= 0;
3111 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3112 MESA_DEBUG_TYPE_UNDEFINED
,
3113 MESA_DEBUG_SEVERITY_HIGH
,
3114 "UBO %d unbound, %s shader uniform data "
3115 "will be undefined.",
3117 _mesa_shader_stage_to_string(stage
));
3121 assert(binding
->Offset
% 32 == 0);
3123 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3124 intel_buffer_object(binding
->BufferObject
),
3125 binding
->Offset
, range
->length
* 32, false);
3127 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3128 pkt
.ConstantBody
.Buffer
[n
] =
3129 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3133 if (stage_state
->push_const_size
> 0) {
3135 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3136 pkt
.ConstantBody
.Buffer
[n
] =
3137 ro_bo(stage_state
->push_const_bo
,
3138 stage_state
->push_const_offset
);
3141 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3142 pkt
.ConstantBody
.Buffer
[0].offset
=
3143 stage_state
->push_const_offset
| mocs
;
3148 stage_state
->push_constants_dirty
= false;
3149 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3153 const struct brw_tracked_state
genX(push_constant_packets
) = {
3156 .brw
= BRW_NEW_DRAW_CALL
,
3158 .emit
= genX(upload_push_constant_packets
),
3164 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3166 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3168 /* BRW_NEW_VERTEX_PROGRAM */
3169 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3170 /* BRW_NEW_VS_PROG_DATA */
3171 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3173 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3176 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3178 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3180 .brw
= BRW_NEW_BATCH
|
3182 BRW_NEW_VERTEX_PROGRAM
|
3183 BRW_NEW_VS_PROG_DATA
,
3185 .emit
= genX(upload_vs_push_constants
),
3189 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3191 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3193 /* BRW_NEW_GEOMETRY_PROGRAM */
3194 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3196 /* BRW_NEW_GS_PROG_DATA */
3197 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3199 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3202 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3204 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3206 .brw
= BRW_NEW_BATCH
|
3208 BRW_NEW_GEOMETRY_PROGRAM
|
3209 BRW_NEW_GS_PROG_DATA
,
3211 .emit
= genX(upload_gs_push_constants
),
3215 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3217 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3218 /* BRW_NEW_FRAGMENT_PROGRAM */
3219 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3220 /* BRW_NEW_FS_PROG_DATA */
3221 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3223 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3226 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3228 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3229 .brw
= BRW_NEW_BATCH
|
3231 BRW_NEW_FRAGMENT_PROGRAM
|
3232 BRW_NEW_FS_PROG_DATA
,
3234 .emit
= genX(upload_wm_push_constants
),
3238 /* ---------------------------------------------------------------------- */
3242 genX(determine_sample_mask
)(struct brw_context
*brw
)
3244 struct gl_context
*ctx
= &brw
->ctx
;
3245 float coverage
= 1.0f
;
3246 float coverage_invert
= false;
3247 unsigned sample_mask
= ~0u;
3249 /* BRW_NEW_NUM_SAMPLES */
3250 unsigned num_samples
= brw
->num_samples
;
3252 if (_mesa_is_multisample_enabled(ctx
)) {
3253 if (ctx
->Multisample
.SampleCoverage
) {
3254 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3255 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3257 if (ctx
->Multisample
.SampleMask
) {
3258 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3262 if (num_samples
> 1) {
3263 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3264 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3265 if (coverage_invert
)
3266 coverage_bits
^= (1 << num_samples
) - 1;
3267 return coverage_bits
& sample_mask
;
3274 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3275 unsigned num_samples
)
3277 unsigned log2_samples
= ffs(num_samples
) - 1;
3279 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3280 multi
.PixelLocation
= CENTER
;
3281 multi
.NumberofMultisamples
= log2_samples
;
3283 GEN_SAMPLE_POS_4X(multi
.Sample
);
3285 switch (num_samples
) {
3287 GEN_SAMPLE_POS_1X(multi
.Sample
);
3290 GEN_SAMPLE_POS_2X(multi
.Sample
);
3293 GEN_SAMPLE_POS_4X(multi
.Sample
);
3296 GEN_SAMPLE_POS_8X(multi
.Sample
);
3306 genX(upload_multisample_state
)(struct brw_context
*brw
)
3308 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3310 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3312 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3313 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3317 static const struct brw_tracked_state
genX(multisample_state
) = {
3319 .mesa
= _NEW_MULTISAMPLE
|
3320 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3321 .brw
= BRW_NEW_BLORP
|
3323 BRW_NEW_NUM_SAMPLES
,
3325 .emit
= genX(upload_multisample_state
)
3329 /* ---------------------------------------------------------------------- */
3332 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3334 struct gl_context
*ctx
= &brw
->ctx
;
3336 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3338 cc
.IndependentAlphaBlendEnable
=
3339 set_blend_entry_bits(brw
, &cc
, 0, false);
3340 set_depth_stencil_bits(brw
, &cc
);
3342 if (ctx
->Color
.AlphaEnabled
&&
3343 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3344 cc
.AlphaTestEnable
= true;
3345 cc
.AlphaTestFunction
=
3346 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3349 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3351 cc
.StatisticsEnable
= brw
->stats_wm
;
3353 cc
.CCViewportStatePointer
=
3354 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3357 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3358 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3359 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3360 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3364 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3365 cc
.BackfaceStencilReferenceValue
=
3366 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3372 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3373 ctx
->Color
.AlphaRef
);
3377 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3378 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3380 ptr
.ColorCalcStatePointerValid
= true;
3384 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3388 static const struct brw_tracked_state
genX(color_calc_state
) = {
3390 .mesa
= _NEW_COLOR
|
3392 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3395 .brw
= BRW_NEW_BATCH
|
3397 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3399 : BRW_NEW_CC_STATE
|
3400 BRW_NEW_STATE_BASE_ADDRESS
),
3402 .emit
= genX(upload_color_calc_state
),
3406 /* ---------------------------------------------------------------------- */
3410 genX(upload_sbe
)(struct brw_context
*brw
)
3412 struct gl_context
*ctx
= &brw
->ctx
;
3413 /* BRW_NEW_FRAGMENT_PROGRAM */
3414 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3415 /* BRW_NEW_FS_PROG_DATA */
3416 const struct brw_wm_prog_data
*wm_prog_data
=
3417 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3419 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3421 #define attr_overrides sbe.Attribute
3423 uint32_t urb_entry_read_length
;
3424 uint32_t urb_entry_read_offset
;
3425 uint32_t point_sprite_enables
;
3427 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3428 sbe
.AttributeSwizzleEnable
= true;
3429 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3432 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3436 * Window coordinates in an FBO are inverted, which means point
3437 * sprite origin must be inverted.
3439 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3440 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3442 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3444 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3445 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3446 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3447 * BRW_NEW_VUE_MAP_GEOM_OUT
3449 genX(calculate_attr_overrides
)(brw
,
3451 &point_sprite_enables
,
3452 &urb_entry_read_length
,
3453 &urb_entry_read_offset
);
3455 /* Typically, the URB entry read length and offset should be programmed
3456 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3457 * stage which produces geometry. However, we don't know the proper
3458 * value until we call calculate_attr_overrides().
3460 * To fit with our existing code, we override the inherited values and
3461 * specify it here directly, as we did on previous generations.
3463 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3464 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3465 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3466 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3469 sbe
.ForceVertexURBEntryReadLength
= true;
3470 sbe
.ForceVertexURBEntryReadOffset
= true;
3474 /* prepare the active component dwords */
3475 const int num_inputs
= urb_entry_read_length
* 2;
3476 for (int input_index
= 0; input_index
< num_inputs
; input_index
++) {
3477 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3483 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3484 for (int i
= 0; i
< 16; i
++)
3485 sbes
.Attribute
[i
] = attr_overrides
[i
];
3489 #undef attr_overrides
3492 static const struct brw_tracked_state
genX(sbe_state
) = {
3494 .mesa
= _NEW_BUFFERS
|
3499 .brw
= BRW_NEW_BLORP
|
3501 BRW_NEW_FRAGMENT_PROGRAM
|
3502 BRW_NEW_FS_PROG_DATA
|
3503 BRW_NEW_GS_PROG_DATA
|
3504 BRW_NEW_TES_PROG_DATA
|
3505 BRW_NEW_VUE_MAP_GEOM_OUT
|
3506 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3509 .emit
= genX(upload_sbe
),
3513 /* ---------------------------------------------------------------------- */
3517 * Outputs the 3DSTATE_SO_DECL_LIST command.
3519 * The data output is a series of 64-bit entries containing a SO_DECL per
3520 * stream. We only have one stream of rendering coming out of the GS unit, so
3521 * we only emit stream 0 (low 16 bits) SO_DECLs.
3524 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3525 const struct brw_vue_map
*vue_map
)
3527 struct gl_context
*ctx
= &brw
->ctx
;
3528 /* BRW_NEW_TRANSFORM_FEEDBACK */
3529 struct gl_transform_feedback_object
*xfb_obj
=
3530 ctx
->TransformFeedback
.CurrentObject
;
3531 const struct gl_transform_feedback_info
*linked_xfb_info
=
3532 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3533 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3534 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3535 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3536 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3538 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3540 memset(so_decl
, 0, sizeof(so_decl
));
3542 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3543 * command feels strange -- each dword pair contains a SO_DECL per stream.
3545 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3546 const struct gl_transform_feedback_output
*output
=
3547 &linked_xfb_info
->Outputs
[i
];
3548 const int buffer
= output
->OutputBuffer
;
3549 const int varying
= output
->OutputRegister
;
3550 const unsigned stream_id
= output
->StreamId
;
3551 assert(stream_id
< MAX_VERTEX_STREAMS
);
3553 buffer_mask
[stream_id
] |= 1 << buffer
;
3555 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3557 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3558 * array. Instead, it simply increments DstOffset for the following
3559 * input by the number of components that should be skipped.
3561 * Our hardware is unusual in that it requires us to program SO_DECLs
3562 * for fake "hole" components, rather than simply taking the offset
3563 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3564 * program as many size = 4 holes as we can, then a final hole to
3565 * accommodate the final 1, 2, or 3 remaining.
3567 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3569 while (skip_components
> 0) {
3570 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3572 .OutputBufferSlot
= output
->OutputBuffer
,
3573 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3575 skip_components
-= 4;
3578 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3580 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3581 .OutputBufferSlot
= output
->OutputBuffer
,
3582 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3584 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3587 if (decls
[stream_id
] > max_decls
)
3588 max_decls
= decls
[stream_id
];
3592 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3593 .StreamtoBufferSelects0
= buffer_mask
[0],
3594 .StreamtoBufferSelects1
= buffer_mask
[1],
3595 .StreamtoBufferSelects2
= buffer_mask
[2],
3596 .StreamtoBufferSelects3
= buffer_mask
[3],
3597 .NumEntries0
= decls
[0],
3598 .NumEntries1
= decls
[1],
3599 .NumEntries2
= decls
[2],
3600 .NumEntries3
= decls
[3]);
3602 for (int i
= 0; i
< max_decls
; i
++) {
3603 GENX(SO_DECL_ENTRY_pack
)(
3604 brw
, dw
+ 2 + i
* 2,
3605 &(struct GENX(SO_DECL_ENTRY
)) {
3606 .Stream0Decl
= so_decl
[0][i
],
3607 .Stream1Decl
= so_decl
[1][i
],
3608 .Stream2Decl
= so_decl
[2][i
],
3609 .Stream3Decl
= so_decl
[3][i
],
3615 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3617 struct gl_context
*ctx
= &brw
->ctx
;
3618 /* BRW_NEW_TRANSFORM_FEEDBACK */
3619 struct gl_transform_feedback_object
*xfb_obj
=
3620 ctx
->TransformFeedback
.CurrentObject
;
3622 const struct gl_transform_feedback_info
*linked_xfb_info
=
3623 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3625 struct brw_transform_feedback_object
*brw_obj
=
3626 (struct brw_transform_feedback_object
*) xfb_obj
;
3627 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3630 /* Set up the up to 4 output buffers. These are the ranges defined in the
3631 * gl_transform_feedback_object.
3633 for (int i
= 0; i
< 4; i
++) {
3634 struct intel_buffer_object
*bufferobj
=
3635 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3638 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3639 sob
.SOBufferIndex
= i
;
3644 uint32_t start
= xfb_obj
->Offset
[i
];
3645 assert(start
% 4 == 0);
3646 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3648 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3649 assert(end
<= bo
->size
);
3651 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3652 sob
.SOBufferIndex
= i
;
3654 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3656 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3657 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3659 sob
.SOBufferEnable
= true;
3660 sob
.StreamOffsetWriteEnable
= true;
3661 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3662 sob
.SOBufferMOCS
= mocs_wb
;
3664 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3665 sob
.StreamOutputBufferOffsetAddress
=
3666 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3668 if (brw_obj
->zero_offsets
) {
3669 /* Zero out the offset and write that to offset_bo */
3670 sob
.StreamOffset
= 0;
3672 /* Use offset_bo as the "Stream Offset." */
3673 sob
.StreamOffset
= 0xFFFFFFFF;
3680 brw_obj
->zero_offsets
= false;
3685 query_active(struct gl_query_object
*q
)
3687 return q
&& q
->Active
;
3691 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3692 const struct brw_vue_map
*vue_map
)
3694 struct gl_context
*ctx
= &brw
->ctx
;
3695 /* BRW_NEW_TRANSFORM_FEEDBACK */
3696 struct gl_transform_feedback_object
*xfb_obj
=
3697 ctx
->TransformFeedback
.CurrentObject
;
3699 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3701 int urb_entry_read_offset
= 0;
3702 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3703 urb_entry_read_offset
;
3705 sos
.SOFunctionEnable
= true;
3706 sos
.SOStatisticsEnable
= true;
3708 /* BRW_NEW_RASTERIZER_DISCARD */
3709 if (ctx
->RasterDiscard
) {
3710 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3711 sos
.RenderingDisable
= true;
3713 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3714 "query active relies on the clipper.\n");
3719 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3720 sos
.ReorderMode
= TRAILING
;
3723 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3724 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3725 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3726 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3728 const struct gl_transform_feedback_info
*linked_xfb_info
=
3729 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3730 /* Set buffer pitches; 0 means unbound. */
3731 if (xfb_obj
->Buffers
[0])
3732 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3733 if (xfb_obj
->Buffers
[1])
3734 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3735 if (xfb_obj
->Buffers
[2])
3736 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3737 if (xfb_obj
->Buffers
[3])
3738 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3741 /* We always read the whole vertex. This could be reduced at some
3742 * point by reading less and offsetting the register index in the
3745 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3746 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3747 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3748 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3749 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3750 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3751 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3752 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3758 genX(upload_sol
)(struct brw_context
*brw
)
3760 struct gl_context
*ctx
= &brw
->ctx
;
3761 /* BRW_NEW_TRANSFORM_FEEDBACK */
3762 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3765 genX(upload_3dstate_so_buffers
)(brw
);
3767 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3768 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3771 /* Finally, set up the SOL stage. This command must always follow updates to
3772 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3773 * MMIO register updates (current performed by the kernel at each batch
3776 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3779 static const struct brw_tracked_state
genX(sol_state
) = {
3782 .brw
= BRW_NEW_BATCH
|
3784 BRW_NEW_RASTERIZER_DISCARD
|
3785 BRW_NEW_VUE_MAP_GEOM_OUT
|
3786 BRW_NEW_TRANSFORM_FEEDBACK
,
3788 .emit
= genX(upload_sol
),
3792 /* ---------------------------------------------------------------------- */
3796 genX(upload_ps
)(struct brw_context
*brw
)
3798 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3799 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3801 /* BRW_NEW_FS_PROG_DATA */
3802 const struct brw_wm_prog_data
*prog_data
=
3803 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3804 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3809 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3810 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3811 * incorrect for subspans where some of the pixels are unlit. We believe
3812 * the bit just didn't take effect in previous generations.
3814 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3817 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3819 /* BRW_NEW_FS_PROG_DATA */
3820 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3822 if (prog_data
->base
.use_alt_mode
)
3823 ps
.FloatingPointMode
= Alternate
;
3825 /* Haswell requires the sample mask to be set in this packet as well as
3826 * in 3DSTATE_SAMPLE_MASK; the values should match.
3829 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3831 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3834 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3835 * it implicitly scales for different GT levels (which have some # of
3838 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3841 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3843 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3845 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3848 if (prog_data
->base
.nr_params
> 0 ||
3849 prog_data
->base
.ubo_ranges
[0].length
> 0)
3850 ps
.PushConstantEnable
= true;
3853 /* From the IVB PRM, volume 2 part 1, page 287:
3854 * "This bit is inserted in the PS payload header and made available to
3855 * the DataPort (either via the message header or via header bypass) to
3856 * indicate that oMask data (one or two phases) is included in Render
3857 * Target Write messages. If present, the oMask data is used to mask off
3860 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3862 /* The hardware wedges if you have this bit set but don't turn on any
3863 * dual source blend factors.
3865 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3867 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3868 (ctx
->Color
.BlendEnabled
& 1) &&
3869 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3871 /* BRW_NEW_FS_PROG_DATA */
3872 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3875 /* From the documentation for this packet:
3876 * "If the PS kernel does not need the Position XY Offsets to
3877 * compute a Position Value, then this field should be programmed
3878 * to POSOFFSET_NONE."
3880 * "SW Recommendation: If the PS kernel needs the Position Offsets
3881 * to compute a Position XY value, this field should match Position
3882 * ZW Interpolation Mode to ensure a consistent position.xyzw
3885 * We only require XY sample offsets. So, this recommendation doesn't
3886 * look useful at the moment. We might need this in future.
3888 if (prog_data
->uses_pos_offset
)
3889 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3891 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3893 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3894 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3895 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3896 prog_data
->base
.dispatch_grf_start_reg
;
3897 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3898 prog_data
->dispatch_grf_start_reg_2
;
3900 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3901 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3902 prog_data
->prog_offset_2
;
3904 if (prog_data
->base
.total_scratch
) {
3905 ps
.ScratchSpaceBasePointer
=
3906 rw_bo(stage_state
->scratch_bo
,
3907 ffs(stage_state
->per_thread_scratch
) - 11);
3912 static const struct brw_tracked_state
genX(ps_state
) = {
3914 .mesa
= _NEW_MULTISAMPLE
|
3915 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3918 .brw
= BRW_NEW_BATCH
|
3920 BRW_NEW_FS_PROG_DATA
,
3922 .emit
= genX(upload_ps
),
3926 /* ---------------------------------------------------------------------- */
3930 genX(upload_hs_state
)(struct brw_context
*brw
)
3932 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3933 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3934 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3935 const struct brw_vue_prog_data
*vue_prog_data
=
3936 brw_vue_prog_data(stage_prog_data
);
3938 /* BRW_NEW_TES_PROG_DATA */
3939 struct brw_tcs_prog_data
*tcs_prog_data
=
3940 brw_tcs_prog_data(stage_prog_data
);
3942 if (!tcs_prog_data
) {
3943 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3945 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3946 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3948 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3949 hs
.IncludeVertexHandles
= true;
3951 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3956 static const struct brw_tracked_state
genX(hs_state
) = {
3959 .brw
= BRW_NEW_BATCH
|
3961 BRW_NEW_TCS_PROG_DATA
|
3962 BRW_NEW_TESS_PROGRAMS
,
3964 .emit
= genX(upload_hs_state
),
3968 genX(upload_ds_state
)(struct brw_context
*brw
)
3970 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3971 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3972 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3974 /* BRW_NEW_TES_PROG_DATA */
3975 const struct brw_tes_prog_data
*tes_prog_data
=
3976 brw_tes_prog_data(stage_prog_data
);
3977 const struct brw_vue_prog_data
*vue_prog_data
=
3978 brw_vue_prog_data(stage_prog_data
);
3980 if (!tes_prog_data
) {
3981 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3983 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3984 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3986 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3987 ds
.ComputeWCoordinateEnable
=
3988 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3991 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3992 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3993 ds
.UserClipDistanceCullTestEnableBitmask
=
3994 vue_prog_data
->cull_distance_mask
;
4000 static const struct brw_tracked_state
genX(ds_state
) = {
4003 .brw
= BRW_NEW_BATCH
|
4005 BRW_NEW_TESS_PROGRAMS
|
4006 BRW_NEW_TES_PROG_DATA
,
4008 .emit
= genX(upload_ds_state
),
4011 /* ---------------------------------------------------------------------- */
4014 upload_te_state(struct brw_context
*brw
)
4016 /* BRW_NEW_TESS_PROGRAMS */
4017 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4019 /* BRW_NEW_TES_PROG_DATA */
4020 const struct brw_tes_prog_data
*tes_prog_data
=
4021 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4024 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4025 te
.Partitioning
= tes_prog_data
->partitioning
;
4026 te
.OutputTopology
= tes_prog_data
->output_topology
;
4027 te
.TEDomain
= tes_prog_data
->domain
;
4029 te
.MaximumTessellationFactorOdd
= 63.0;
4030 te
.MaximumTessellationFactorNotOdd
= 64.0;
4033 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4037 static const struct brw_tracked_state
genX(te_state
) = {
4040 .brw
= BRW_NEW_BLORP
|
4042 BRW_NEW_TES_PROG_DATA
|
4043 BRW_NEW_TESS_PROGRAMS
,
4045 .emit
= upload_te_state
,
4048 /* ---------------------------------------------------------------------- */
4051 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4053 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4054 /* BRW_NEW_TESS_PROGRAMS */
4055 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4057 /* BRW_NEW_TES_PROG_DATA */
4058 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4059 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4062 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4064 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4065 .brw
= BRW_NEW_BATCH
|
4067 BRW_NEW_TESS_PROGRAMS
|
4068 BRW_NEW_TES_PROG_DATA
,
4070 .emit
= genX(upload_tes_push_constants
),
4074 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4076 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4077 /* BRW_NEW_TESS_PROGRAMS */
4078 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4080 /* BRW_NEW_TCS_PROG_DATA */
4081 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4083 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4086 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4088 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4089 .brw
= BRW_NEW_BATCH
|
4091 BRW_NEW_DEFAULT_TESS_LEVELS
|
4092 BRW_NEW_TESS_PROGRAMS
|
4093 BRW_NEW_TCS_PROG_DATA
,
4095 .emit
= genX(upload_tcs_push_constants
),
4100 /* ---------------------------------------------------------------------- */
4104 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4106 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4108 /* BRW_NEW_COMPUTE_PROGRAM */
4109 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4112 /* BRW_NEW_CS_PROG_DATA */
4113 struct brw_cs_prog_data
*cs_prog_data
=
4114 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4116 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4117 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4121 const struct brw_tracked_state
genX(cs_push_constants
) = {
4123 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4124 .brw
= BRW_NEW_BATCH
|
4126 BRW_NEW_COMPUTE_PROGRAM
|
4127 BRW_NEW_CS_PROG_DATA
,
4129 .emit
= genX(upload_cs_push_constants
),
4133 * Creates a new CS constant buffer reflecting the current CS program's
4134 * constants, if needed by the CS program.
4137 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4139 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4141 /* BRW_NEW_COMPUTE_PROGRAM */
4142 struct brw_program
*cp
=
4143 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4145 /* BRW_NEW_CS_PROG_DATA */
4146 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4148 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4149 /* _NEW_PROGRAM_CONSTANTS */
4150 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4151 stage_state
, prog_data
);
4154 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4156 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4157 .brw
= BRW_NEW_BATCH
|
4159 BRW_NEW_COMPUTE_PROGRAM
|
4160 BRW_NEW_CS_PROG_DATA
,
4162 .emit
= genX(upload_cs_pull_constants
),
4166 genX(upload_cs_state
)(struct brw_context
*brw
)
4168 if (!brw
->cs
.base
.prog_data
)
4172 uint32_t *desc
= (uint32_t*) brw_state_batch(
4173 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4176 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4177 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4178 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4179 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4181 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4182 brw_emit_buffer_surface_state(
4183 brw
, &stage_state
->surf_offset
[
4184 prog_data
->binding_table
.shader_time_start
],
4185 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4186 brw
->shader_time
.bo
->size
, 1,
4190 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4191 32, &stage_state
->bind_bo_offset
);
4193 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4195 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4196 * the only bits that are changed are scoreboard related: Scoreboard
4197 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4198 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4200 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4201 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4203 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4205 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4206 if (prog_data
->total_scratch
) {
4207 uint32_t per_thread_scratch_value
;
4210 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4211 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4213 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4214 } else if (GEN_IS_HASWELL
) {
4215 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4216 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4218 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4220 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4221 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4223 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4225 vfe
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
4226 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4229 /* If brw->screen->subslice_total is greater than one, then
4230 * devinfo->max_cs_threads stores number of threads per sub-slice;
4231 * thus we need to multiply by that number by subslices to get
4232 * the actual maximum number of threads; the -1 is because the HW
4233 * has a bias of 1 (would not make sense to say the maximum number
4236 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4237 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4238 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4239 vfe
.ResetGatewayTimer
=
4240 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4242 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4248 /* We are uploading duplicated copies of push constant uniforms for each
4249 * thread. Although the local id data needs to vary per thread, it won't
4250 * change for other uniform data. Unfortunately this duplication is
4251 * required for gen7. As of Haswell, this duplication can be avoided,
4252 * but this older mechanism with duplicated data continues to work.
4254 * FINISHME: As of Haswell, we could make use of the
4255 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4256 * field to only store one copy of uniform data.
4258 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4259 * which is described in the GPGPU_WALKER command and in the Broadwell
4260 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4261 * Operations => GPGPU Mode => Indirect Payload Storage.
4263 * Note: The constant data is built in brw_upload_cs_push_constants
4266 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4268 const uint32_t vfe_curbe_allocation
=
4269 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4270 cs_prog_data
->push
.cross_thread
.regs
, 2);
4271 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4274 if (cs_prog_data
->push
.total
.size
> 0) {
4275 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4276 curbe
.CURBETotalDataLength
=
4277 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4278 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4282 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4283 memcpy(bind
, stage_state
->surf_offset
,
4284 prog_data
->binding_table
.size_bytes
);
4285 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4286 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4287 .SamplerStatePointer
= stage_state
->sampler_offset
,
4288 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4289 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4290 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4291 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4292 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4293 prog_data
->total_shared
),
4294 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4295 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4296 .CrossThreadConstantDataReadLength
=
4297 cs_prog_data
->push
.cross_thread
.regs
,
4301 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4303 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4304 load
.InterfaceDescriptorTotalLength
=
4305 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4306 load
.InterfaceDescriptorDataStartAddress
= offset
;
4310 static const struct brw_tracked_state
genX(cs_state
) = {
4312 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4313 .brw
= BRW_NEW_BATCH
|
4315 BRW_NEW_CS_PROG_DATA
|
4316 BRW_NEW_SAMPLER_STATE_TABLE
|
4319 .emit
= genX(upload_cs_state
)
4324 /* ---------------------------------------------------------------------- */
4328 genX(upload_raster
)(struct brw_context
*brw
)
4330 const struct gl_context
*ctx
= &brw
->ctx
;
4333 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4336 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4339 const struct gl_point_attrib
*point
= &ctx
->Point
;
4341 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4342 if (brw
->polygon_front_bit
== render_to_fbo
)
4343 raster
.FrontWinding
= CounterClockwise
;
4345 if (polygon
->CullFlag
) {
4346 switch (polygon
->CullFaceMode
) {
4348 raster
.CullMode
= CULLMODE_FRONT
;
4351 raster
.CullMode
= CULLMODE_BACK
;
4353 case GL_FRONT_AND_BACK
:
4354 raster
.CullMode
= CULLMODE_BOTH
;
4357 unreachable("not reached");
4360 raster
.CullMode
= CULLMODE_NONE
;
4363 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4365 raster
.DXMultisampleRasterizationEnable
=
4366 _mesa_is_multisample_enabled(ctx
);
4368 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4369 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4370 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4372 switch (polygon
->FrontMode
) {
4374 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4377 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4380 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4383 unreachable("not reached");
4386 switch (polygon
->BackMode
) {
4388 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4391 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4394 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4397 unreachable("not reached");
4401 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4405 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4407 const bool multisampled_fbo
=
4408 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4409 if (multisampled_fbo
)
4410 raster
.AntialiasingEnable
= false;
4414 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4416 /* _NEW_TRANSFORM */
4417 if (!ctx
->Transform
.DepthClamp
) {
4419 raster
.ViewportZFarClipTestEnable
= true;
4420 raster
.ViewportZNearClipTestEnable
= true;
4422 raster
.ViewportZClipTestEnable
= true;
4426 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4428 raster
.ConservativeRasterizationEnable
=
4429 ctx
->IntelConservativeRasterization
;
4432 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4433 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4435 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4439 static const struct brw_tracked_state
genX(raster_state
) = {
4441 .mesa
= _NEW_BUFFERS
|
4448 .brw
= BRW_NEW_BLORP
|
4450 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4452 .emit
= genX(upload_raster
),
4456 /* ---------------------------------------------------------------------- */
4460 genX(upload_ps_extra
)(struct brw_context
*brw
)
4462 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4464 const struct brw_wm_prog_data
*prog_data
=
4465 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4467 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4468 psx
.PixelShaderValid
= true;
4469 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4470 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4471 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4472 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4473 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4474 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4476 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4477 if (prog_data
->uses_sample_mask
) {
4479 if (prog_data
->post_depth_coverage
)
4480 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4481 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4482 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4484 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4486 psx
.PixelShaderUsesInputCoverageMask
= true;
4490 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4492 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4493 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4496 /* The stricter cross-primitive coherency guarantees that the hardware
4497 * gives us with the "Accesses UAV" bit set for at least one shader stage
4498 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4499 * are redundant within the current image, atomic counter and SSBO GL
4500 * APIs, which all have very loose ordering and coherency requirements
4501 * and generally rely on the application to insert explicit barriers when
4502 * a shader invocation is expected to see the memory writes performed by
4503 * the invocations of some previous primitive. Regardless of the value
4504 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4505 * cause an in most cases useless DC flush when the lowermost stage with
4506 * the bit set finishes execution.
4508 * It would be nice to disable it, but in some cases we can't because on
4509 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4510 * signal (which could be set independently from the coherency mechanism
4511 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4512 * determine whether the hardware skips execution of the fragment shader
4513 * or not via the ThreadDispatchEnable signal. However if we know that
4514 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4515 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4516 * difference so we may just disable it here.
4518 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4519 * take into account KillPixels when no depth or stencil writes are
4520 * enabled. In order for occlusion queries to work correctly with no
4521 * attachments, we need to force-enable here.
4523 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4526 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4527 !brw_color_buffer_write_enabled(brw
))
4528 psx
.PixelShaderHasUAV
= true;
4532 const struct brw_tracked_state
genX(ps_extra
) = {
4534 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4535 .brw
= BRW_NEW_BLORP
|
4537 BRW_NEW_FRAGMENT_PROGRAM
|
4538 BRW_NEW_FS_PROG_DATA
|
4539 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4541 .emit
= genX(upload_ps_extra
),
4545 /* ---------------------------------------------------------------------- */
4549 genX(upload_ps_blend
)(struct brw_context
*brw
)
4551 struct gl_context
*ctx
= &brw
->ctx
;
4554 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4555 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4558 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4560 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4561 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4562 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4564 bool alpha_to_one
= false;
4566 if (!buffer0_is_integer
) {
4567 /* _NEW_MULTISAMPLE */
4569 if (_mesa_is_multisample_enabled(ctx
)) {
4570 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4571 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4574 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4577 /* Used for implementing the following bit of GL_EXT_texture_integer:
4578 * "Per-fragment operations that require floating-point color
4579 * components, including multisample alpha operations, alpha test,
4580 * blending, and dithering, have no effect when the corresponding
4581 * colors are written to an integer color buffer."
4583 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4584 * "If drawbuffer zero is not NONE and the buffer it references has an
4585 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4586 * operations are skipped."
4588 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4589 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4590 GLenum eqA
= color
->Blend
[0].EquationA
;
4591 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4592 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4593 GLenum srcA
= color
->Blend
[0].SrcA
;
4594 GLenum dstA
= color
->Blend
[0].DstA
;
4596 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4597 srcRGB
= dstRGB
= GL_ONE
;
4599 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4600 srcA
= dstA
= GL_ONE
;
4602 /* Due to hardware limitations, the destination may have information
4603 * in an alpha channel even when the format specifies no alpha
4604 * channel. In order to avoid getting any incorrect blending due to
4605 * that alpha channel, coerce the blend factors to values that will
4606 * not read the alpha channel, but will instead use the correct
4607 * implicit value for alpha.
4609 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4610 GL_TEXTURE_ALPHA_TYPE
)) {
4611 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4612 srcA
= brw_fix_xRGB_alpha(srcA
);
4613 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4614 dstA
= brw_fix_xRGB_alpha(dstA
);
4617 /* Alpha to One doesn't work with Dual Color Blending. Override
4618 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4620 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4621 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4622 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4623 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4624 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4627 pb
.ColorBufferBlendEnable
= true;
4628 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4629 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4630 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4631 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4633 pb
.IndependentAlphaBlendEnable
=
4634 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4639 static const struct brw_tracked_state
genX(ps_blend
) = {
4641 .mesa
= _NEW_BUFFERS
|
4644 .brw
= BRW_NEW_BLORP
|
4646 BRW_NEW_FRAGMENT_PROGRAM
,
4648 .emit
= genX(upload_ps_blend
)
4652 /* ---------------------------------------------------------------------- */
4656 genX(emit_vf_topology
)(struct brw_context
*brw
)
4658 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4659 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4663 static const struct brw_tracked_state
genX(vf_topology
) = {
4666 .brw
= BRW_NEW_BLORP
|
4669 .emit
= genX(emit_vf_topology
),
4673 /* ---------------------------------------------------------------------- */
4677 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4679 uint32_t offset_in_bytes
,
4682 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4683 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4684 mi_rpc
.ReportID
= report_id
;
4689 /* ---------------------------------------------------------------------- */
4692 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4695 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4696 struct brw_stage_state
*stage_state
)
4699 static const uint16_t packet_headers
[] = {
4700 [MESA_SHADER_VERTEX
] = 43,
4701 [MESA_SHADER_TESS_CTRL
] = 44,
4702 [MESA_SHADER_TESS_EVAL
] = 45,
4703 [MESA_SHADER_GEOMETRY
] = 46,
4704 [MESA_SHADER_FRAGMENT
] = 47,
4707 /* Ivybridge requires a workaround flush before VS packets. */
4708 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4709 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4710 gen7_emit_vs_workaround_flush(brw
);
4713 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4714 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4715 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4721 has_component(mesa_format format
, int i
)
4723 if (_mesa_is_format_color_format(format
))
4724 return _mesa_format_has_color_component(format
, i
);
4726 /* depth and stencil have only one component */
4731 * Upload SAMPLER_BORDER_COLOR_STATE.
4734 genX(upload_default_color
)(struct brw_context
*brw
,
4735 const struct gl_sampler_object
*sampler
,
4736 mesa_format format
, GLenum base_format
,
4737 bool is_integer_format
, bool is_stencil_sampling
,
4738 uint32_t *sdc_offset
)
4740 union gl_color_union color
;
4742 switch (base_format
) {
4743 case GL_DEPTH_COMPONENT
:
4744 /* GL specs that border color for depth textures is taken from the
4745 * R channel, while the hardware uses A. Spam R into all the
4746 * channels for safety.
4748 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4749 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4750 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4751 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4757 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4760 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4761 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4762 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4763 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4766 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4767 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4768 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4769 color
.ui
[3] = float_as_int(1.0);
4771 case GL_LUMINANCE_ALPHA
:
4772 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4773 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4774 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4775 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4778 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4779 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4780 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4781 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4785 /* In some cases we use an RGBA surface format for GL RGB textures,
4786 * where we've initialized the A channel to 1.0. We also have to set
4787 * the border color alpha to 1.0 in that case.
4789 if (base_format
== GL_RGB
)
4790 color
.ui
[3] = float_as_int(1.0);
4795 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4799 uint32_t *sdc
= brw_state_batch(
4800 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4801 alignment
, sdc_offset
);
4803 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4805 #define ASSIGN(dst, src) \
4810 #define ASSIGNu16(dst, src) \
4812 dst = (uint16_t)src; \
4815 #define ASSIGNu8(dst, src) \
4817 dst = (uint8_t)src; \
4820 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4821 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4822 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4823 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4824 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4827 /* On Broadwell, the border color is represented as four 32-bit floats,
4828 * integers, or unsigned values, interpreted according to the surface
4829 * format. This matches the sampler->BorderColor union exactly; just
4830 * memcpy the values.
4832 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4833 #elif GEN_IS_HASWELL
4834 if (is_integer_format
|| is_stencil_sampling
) {
4835 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4836 const int bits_per_channel
=
4837 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4839 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4840 * "If any color channel is missing from the surface format,
4841 * corresponding border color should be programmed as zero and if
4842 * alpha channel is missing, corresponding Alpha border color should
4843 * be programmed as 1."
4845 unsigned c
[4] = { 0, 0, 0, 1 };
4846 for (int i
= 0; i
< 4; i
++) {
4847 if (has_component(format
, i
))
4851 switch (bits_per_channel
) {
4853 /* Copy RGBA in order. */
4854 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4857 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4859 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4862 if (base_format
== GL_RG
) {
4863 /* Careful inspection of the tables reveals that for RG32 formats,
4864 * the green channel needs to go where blue normally belongs.
4866 state
.BorderColor32bitRed
= c
[0];
4867 state
.BorderColor32bitBlue
= c
[1];
4868 state
.BorderColor32bitAlpha
= 1;
4870 /* Copy RGBA in order. */
4871 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4875 assert(!"Invalid number of bits per channel in integer format.");
4879 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4881 #elif GEN_GEN == 5 || GEN_GEN == 6
4882 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4883 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4884 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4886 #define MESA_FLOAT_TO_HALF(dst, src) \
4887 dst = _mesa_float_to_half(src);
4889 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4891 #undef MESA_FLOAT_TO_HALF
4893 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4894 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4895 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4896 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4898 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4900 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4902 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4906 #undef BORDER_COLOR_ATTR
4908 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4912 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4919 /* GL_CLAMP is the weird mode where coordinates are clamped to
4920 * [0.0, 1.0], so linear filtering of coordinates outside of
4921 * [0.0, 1.0] give you half edge texel value and half border
4924 * Gen8+ supports this natively.
4926 return TCM_HALF_BORDER
;
4928 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4929 * and set clamp_border here, which gets the result desired.
4930 * We just use clamp(_to_edge) for nearest, because for nearest
4931 * clamping to 1.0 gives border color instead of the desired
4937 return TCM_CLAMP_BORDER
;
4939 case GL_CLAMP_TO_EDGE
:
4941 case GL_CLAMP_TO_BORDER
:
4942 return TCM_CLAMP_BORDER
;
4943 case GL_MIRRORED_REPEAT
:
4945 case GL_MIRROR_CLAMP_TO_EDGE
:
4946 return TCM_MIRROR_ONCE
;
4953 * Return true if the given wrap mode requires the border color to exist.
4956 wrap_mode_needs_border_color(unsigned wrap_mode
)
4959 return wrap_mode
== TCM_CLAMP_BORDER
||
4960 wrap_mode
== TCM_HALF_BORDER
;
4962 return wrap_mode
== TCM_CLAMP_BORDER
;
4967 * Sets the sampler state for a single unit based off of the sampler key
4971 genX(update_sampler_state
)(struct brw_context
*brw
,
4972 GLenum target
, bool tex_cube_map_seamless
,
4973 GLfloat tex_unit_lod_bias
,
4974 mesa_format format
, GLenum base_format
,
4975 const struct gl_texture_object
*texObj
,
4976 const struct gl_sampler_object
*sampler
,
4977 uint32_t *sampler_state
,
4978 uint32_t batch_offset_for_sampler_state
)
4980 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
4982 /* Select min and mip filters. */
4983 switch (sampler
->MinFilter
) {
4985 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4986 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4989 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4990 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4992 case GL_NEAREST_MIPMAP_NEAREST
:
4993 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4994 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4996 case GL_LINEAR_MIPMAP_NEAREST
:
4997 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4998 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5000 case GL_NEAREST_MIPMAP_LINEAR
:
5001 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5002 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5004 case GL_LINEAR_MIPMAP_LINEAR
:
5005 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5006 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5009 unreachable("not reached");
5012 /* Select mag filter. */
5013 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5014 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5016 /* Enable anisotropic filtering if desired. */
5017 samp_st
.MaximumAnisotropy
= RATIO21
;
5019 if (sampler
->MaxAnisotropy
> 1.0f
) {
5020 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5021 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5022 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5023 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5025 if (sampler
->MaxAnisotropy
> 2.0f
) {
5026 samp_st
.MaximumAnisotropy
=
5027 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5031 /* Set address rounding bits if not using nearest filtering. */
5032 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5033 samp_st
.UAddressMinFilterRoundingEnable
= true;
5034 samp_st
.VAddressMinFilterRoundingEnable
= true;
5035 samp_st
.RAddressMinFilterRoundingEnable
= true;
5038 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5039 samp_st
.UAddressMagFilterRoundingEnable
= true;
5040 samp_st
.VAddressMagFilterRoundingEnable
= true;
5041 samp_st
.RAddressMagFilterRoundingEnable
= true;
5044 bool either_nearest
=
5045 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5046 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
5047 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
5048 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
5050 if (target
== GL_TEXTURE_CUBE_MAP
||
5051 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5052 /* Cube maps must use the same wrap mode for all three coordinate
5053 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5055 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5056 * integer formats. Fall back to CLAMP for now.
5058 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5059 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5068 } else if (target
== GL_TEXTURE_1D
) {
5069 /* There's a bug in 1D texture sampling - it actually pays
5070 * attention to the wrap_t value, though it should not.
5071 * Override the wrap_t value here to GL_REPEAT to keep
5072 * any nonexistent border pixels from floating in.
5077 samp_st
.TCXAddressControlMode
= wrap_s
;
5078 samp_st
.TCYAddressControlMode
= wrap_t
;
5079 samp_st
.TCZAddressControlMode
= wrap_r
;
5081 samp_st
.ShadowFunction
=
5082 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5083 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5086 /* Set shadow function. */
5087 samp_st
.AnisotropicAlgorithm
=
5088 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5089 EWAApproximation
: LEGACY
;
5093 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5096 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5097 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5098 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5099 samp_st
.TextureLODBias
=
5100 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5103 samp_st
.BaseMipLevel
=
5104 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5105 samp_st
.MinandMagStateNotEqual
=
5106 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5109 /* Upload the border color if necessary. If not, just point it at
5110 * offset 0 (the start of the batch) - the color should be ignored,
5111 * but that address won't fault in case something reads it anyway.
5113 uint32_t border_color_offset
= 0;
5114 if (wrap_mode_needs_border_color(wrap_s
) ||
5115 wrap_mode_needs_border_color(wrap_t
) ||
5116 wrap_mode_needs_border_color(wrap_r
)) {
5117 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5118 texObj
->_IsIntegerFormat
,
5119 texObj
->StencilSampling
,
5120 &border_color_offset
);
5123 samp_st
.BorderColorPointer
=
5124 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5126 samp_st
.BorderColorPointer
= border_color_offset
;
5130 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5132 samp_st
.LODPreClampEnable
= true;
5135 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5139 update_sampler_state(struct brw_context
*brw
,
5141 uint32_t *sampler_state
,
5142 uint32_t batch_offset_for_sampler_state
)
5144 struct gl_context
*ctx
= &brw
->ctx
;
5145 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5146 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5147 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5149 /* These don't use samplers at all. */
5150 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5153 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5154 genX(update_sampler_state
)(brw
, texObj
->Target
,
5155 ctx
->Texture
.CubeMapSeamless
,
5157 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5159 sampler_state
, batch_offset_for_sampler_state
);
5163 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5164 struct gl_program
*prog
,
5165 struct brw_stage_state
*stage_state
)
5167 struct gl_context
*ctx
= &brw
->ctx
;
5168 uint32_t sampler_count
= stage_state
->sampler_count
;
5170 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5172 if (sampler_count
== 0)
5175 /* SAMPLER_STATE is 4 DWords on all platforms. */
5176 const int dwords
= GENX(SAMPLER_STATE_length
);
5177 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5179 uint32_t *sampler_state
= brw_state_batch(brw
,
5180 sampler_count
* size_in_bytes
,
5181 32, &stage_state
->sampler_offset
);
5182 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5184 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
5186 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5187 if (SamplersUsed
& (1 << s
)) {
5188 const unsigned unit
= prog
->SamplerUnits
[s
];
5189 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5190 update_sampler_state(brw
, unit
, sampler_state
,
5191 batch_offset_for_sampler_state
);
5195 sampler_state
+= dwords
;
5196 batch_offset_for_sampler_state
+= size_in_bytes
;
5199 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5200 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5201 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5203 /* Flag that the sampler state table pointer has changed; later atoms
5206 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5211 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5213 /* BRW_NEW_FRAGMENT_PROGRAM */
5214 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5215 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5218 static const struct brw_tracked_state
genX(fs_samplers
) = {
5220 .mesa
= _NEW_TEXTURE
,
5221 .brw
= BRW_NEW_BATCH
|
5223 BRW_NEW_FRAGMENT_PROGRAM
,
5225 .emit
= genX(upload_fs_samplers
),
5229 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5231 /* BRW_NEW_VERTEX_PROGRAM */
5232 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5233 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5236 static const struct brw_tracked_state
genX(vs_samplers
) = {
5238 .mesa
= _NEW_TEXTURE
,
5239 .brw
= BRW_NEW_BATCH
|
5241 BRW_NEW_VERTEX_PROGRAM
,
5243 .emit
= genX(upload_vs_samplers
),
5248 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5250 /* BRW_NEW_GEOMETRY_PROGRAM */
5251 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5255 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5259 static const struct brw_tracked_state
genX(gs_samplers
) = {
5261 .mesa
= _NEW_TEXTURE
,
5262 .brw
= BRW_NEW_BATCH
|
5264 BRW_NEW_GEOMETRY_PROGRAM
,
5266 .emit
= genX(upload_gs_samplers
),
5272 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5274 /* BRW_NEW_TESS_PROGRAMS */
5275 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5279 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5282 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5284 .mesa
= _NEW_TEXTURE
,
5285 .brw
= BRW_NEW_BATCH
|
5287 BRW_NEW_TESS_PROGRAMS
,
5289 .emit
= genX(upload_tcs_samplers
),
5295 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5297 /* BRW_NEW_TESS_PROGRAMS */
5298 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5302 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5305 static const struct brw_tracked_state
genX(tes_samplers
) = {
5307 .mesa
= _NEW_TEXTURE
,
5308 .brw
= BRW_NEW_BATCH
|
5310 BRW_NEW_TESS_PROGRAMS
,
5312 .emit
= genX(upload_tes_samplers
),
5318 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5320 /* BRW_NEW_COMPUTE_PROGRAM */
5321 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5325 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5328 const struct brw_tracked_state
genX(cs_samplers
) = {
5330 .mesa
= _NEW_TEXTURE
,
5331 .brw
= BRW_NEW_BATCH
|
5333 BRW_NEW_COMPUTE_PROGRAM
,
5335 .emit
= genX(upload_cs_samplers
),
5339 /* ---------------------------------------------------------------------- */
5343 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5345 struct gl_context
*ctx
= &brw
->ctx
;
5347 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5348 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5349 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5350 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5351 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5355 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5358 .brw
= BRW_NEW_CONTEXT
|
5361 .emit
= genX(upload_blend_constant_color
)
5365 /* ---------------------------------------------------------------------- */
5368 genX(init_atoms
)(struct brw_context
*brw
)
5371 static const struct brw_tracked_state
*render_atoms
[] =
5373 /* Once all the programs are done, we know how large urb entry
5374 * sizes need to be and can decide if we need to change the urb
5378 &brw_recalculate_urb_fence
,
5381 &genX(color_calc_state
),
5383 /* Surface state setup. Must come before the VS/WM unit. The binding
5384 * table upload must be last.
5386 &brw_vs_pull_constants
,
5387 &brw_wm_pull_constants
,
5388 &brw_renderbuffer_surfaces
,
5389 &brw_renderbuffer_read_surfaces
,
5390 &brw_texture_surfaces
,
5391 &brw_vs_binding_table
,
5392 &brw_wm_binding_table
,
5397 /* These set up state for brw_psp_urb_cbs */
5399 &genX(sf_clip_viewport
),
5401 &genX(vs_state
), /* always required, enabled or not */
5407 &brw_binding_table_pointers
,
5408 &genX(blend_constant_color
),
5412 &genX(polygon_stipple
),
5413 &genX(polygon_stipple_offset
),
5415 &genX(line_stipple
),
5419 &genX(drawing_rect
),
5420 &brw_indices
, /* must come before brw_vertices */
5421 &genX(index_buffer
),
5424 &brw_constant_buffer
5427 static const struct brw_tracked_state
*render_atoms
[] =
5429 &genX(sf_clip_viewport
),
5431 /* Command packets: */
5436 &genX(blend_state
), /* must do before cc unit */
5437 &genX(color_calc_state
), /* must do before cc unit */
5438 &genX(depth_stencil_state
), /* must do before cc unit */
5440 &genX(vs_push_constants
), /* Before vs_state */
5441 &genX(gs_push_constants
), /* Before gs_state */
5442 &genX(wm_push_constants
), /* Before wm_state */
5444 /* Surface state setup. Must come before the VS/WM unit. The binding
5445 * table upload must be last.
5447 &brw_vs_pull_constants
,
5448 &brw_vs_ubo_surfaces
,
5449 &brw_gs_pull_constants
,
5450 &brw_gs_ubo_surfaces
,
5451 &brw_wm_pull_constants
,
5452 &brw_wm_ubo_surfaces
,
5453 &gen6_renderbuffer_surfaces
,
5454 &brw_renderbuffer_read_surfaces
,
5455 &brw_texture_surfaces
,
5457 &brw_vs_binding_table
,
5458 &gen6_gs_binding_table
,
5459 &brw_wm_binding_table
,
5464 &gen6_sampler_state
,
5465 &genX(multisample_state
),
5473 &genX(scissor_state
),
5475 &gen6_binding_table_pointers
,
5479 &genX(polygon_stipple
),
5480 &genX(polygon_stipple_offset
),
5482 &genX(line_stipple
),
5484 &genX(drawing_rect
),
5486 &brw_indices
, /* must come before brw_vertices */
5487 &genX(index_buffer
),
5491 static const struct brw_tracked_state
*render_atoms
[] =
5493 /* Command packets: */
5496 &genX(sf_clip_viewport
),
5499 &gen7_push_constant_space
,
5501 &genX(blend_state
), /* must do before cc unit */
5502 &genX(color_calc_state
), /* must do before cc unit */
5503 &genX(depth_stencil_state
), /* must do before cc unit */
5505 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5506 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5507 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5508 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5509 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5511 &genX(vs_push_constants
), /* Before vs_state */
5512 &genX(tcs_push_constants
),
5513 &genX(tes_push_constants
),
5514 &genX(gs_push_constants
), /* Before gs_state */
5515 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5517 /* Surface state setup. Must come before the VS/WM unit. The binding
5518 * table upload must be last.
5520 &brw_vs_pull_constants
,
5521 &brw_vs_ubo_surfaces
,
5522 &brw_tcs_pull_constants
,
5523 &brw_tcs_ubo_surfaces
,
5524 &brw_tes_pull_constants
,
5525 &brw_tes_ubo_surfaces
,
5526 &brw_gs_pull_constants
,
5527 &brw_gs_ubo_surfaces
,
5528 &brw_wm_pull_constants
,
5529 &brw_wm_ubo_surfaces
,
5530 &gen6_renderbuffer_surfaces
,
5531 &brw_renderbuffer_read_surfaces
,
5532 &brw_texture_surfaces
,
5534 &genX(push_constant_packets
),
5536 &brw_vs_binding_table
,
5537 &brw_tcs_binding_table
,
5538 &brw_tes_binding_table
,
5539 &brw_gs_binding_table
,
5540 &brw_wm_binding_table
,
5544 &genX(tcs_samplers
),
5545 &genX(tes_samplers
),
5547 &genX(multisample_state
),
5561 &genX(scissor_state
),
5565 &genX(polygon_stipple
),
5566 &genX(polygon_stipple_offset
),
5568 &genX(line_stipple
),
5570 &genX(drawing_rect
),
5572 &brw_indices
, /* must come before brw_vertices */
5573 &genX(index_buffer
),
5581 static const struct brw_tracked_state
*render_atoms
[] =
5584 &genX(sf_clip_viewport
),
5587 &gen7_push_constant_space
,
5590 &genX(color_calc_state
),
5592 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5593 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5594 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5595 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5596 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5598 &genX(vs_push_constants
), /* Before vs_state */
5599 &genX(tcs_push_constants
),
5600 &genX(tes_push_constants
),
5601 &genX(gs_push_constants
), /* Before gs_state */
5602 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5604 /* Surface state setup. Must come before the VS/WM unit. The binding
5605 * table upload must be last.
5607 &brw_vs_pull_constants
,
5608 &brw_vs_ubo_surfaces
,
5609 &brw_tcs_pull_constants
,
5610 &brw_tcs_ubo_surfaces
,
5611 &brw_tes_pull_constants
,
5612 &brw_tes_ubo_surfaces
,
5613 &brw_gs_pull_constants
,
5614 &brw_gs_ubo_surfaces
,
5615 &brw_wm_pull_constants
,
5616 &brw_wm_ubo_surfaces
,
5617 &gen6_renderbuffer_surfaces
,
5618 &brw_renderbuffer_read_surfaces
,
5619 &brw_texture_surfaces
,
5621 &genX(push_constant_packets
),
5623 &brw_vs_binding_table
,
5624 &brw_tcs_binding_table
,
5625 &brw_tes_binding_table
,
5626 &brw_gs_binding_table
,
5627 &brw_wm_binding_table
,
5631 &genX(tcs_samplers
),
5632 &genX(tes_samplers
),
5634 &genX(multisample_state
),
5643 &genX(raster_state
),
5649 &genX(depth_stencil_state
),
5652 &genX(scissor_state
),
5656 &genX(polygon_stipple
),
5657 &genX(polygon_stipple_offset
),
5659 &genX(line_stipple
),
5661 &genX(drawing_rect
),
5666 &genX(index_buffer
),
5674 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5675 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5676 render_atoms
, ARRAY_SIZE(render_atoms
));
5679 static const struct brw_tracked_state
*compute_atoms
[] =
5682 &brw_cs_image_surfaces
,
5683 &genX(cs_push_constants
),
5684 &genX(cs_pull_constants
),
5685 &brw_cs_ubo_surfaces
,
5686 &brw_cs_texture_surfaces
,
5687 &brw_cs_work_groups_surface
,
5692 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5693 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5694 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5696 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);