2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
35 #include "brw_context.h"
37 #include "brw_defines.h"
40 #include "brw_multisample_state.h"
41 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
46 #include "intel_buffer_objects.h"
47 #include "intel_fbo.h"
49 #include "main/enums.h"
50 #include "main/fbobject.h"
51 #include "main/framebuffer.h"
52 #include "main/glformats.h"
53 #include "main/shaderapi.h"
54 #include "main/stencil.h"
55 #include "main/transformfeedback.h"
56 #include "main/varray.h"
57 #include "main/viewport.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
71 uint32_t read_domains
;
72 uint32_t write_domain
;
77 emit_reloc(struct brw_context
*brw
,
78 void *location
, struct brw_address address
, uint32_t delta
)
80 uint32_t offset
= (char *) location
- (char *) brw
->batch
.map
;
82 return brw_emit_reloc(&brw
->batch
, offset
, address
.bo
,
83 address
.offset
+ delta
,
85 address
.write_domain
);
88 #define __gen_address_type struct brw_address
89 #define __gen_user_data struct brw_context
92 __gen_combine_address(struct brw_context
*brw
, void *location
,
93 struct brw_address address
, uint32_t delta
)
95 if (address
.bo
== NULL
) {
96 return address
.offset
+ delta
;
98 return emit_reloc(brw
, location
, address
, delta
);
102 static inline struct brw_address
103 render_bo(struct brw_bo
*bo
, uint32_t offset
)
105 return (struct brw_address
) {
108 .read_domains
= I915_GEM_DOMAIN_RENDER
,
109 .write_domain
= I915_GEM_DOMAIN_RENDER
,
113 static inline struct brw_address
114 render_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
116 return (struct brw_address
) {
119 .read_domains
= I915_GEM_DOMAIN_RENDER
,
124 static inline struct brw_address
125 instruction_bo(struct brw_bo
*bo
, uint32_t offset
)
127 return (struct brw_address
) {
130 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
131 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
135 static inline struct brw_address
136 instruction_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
138 return (struct brw_address
) {
141 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
146 static inline struct brw_address
147 vertex_bo(struct brw_bo
*bo
, uint32_t offset
)
149 return (struct brw_address
) {
152 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
157 #include "genxml/genX_pack.h"
159 #define _brw_cmd_length(cmd) cmd ## _length
160 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
161 #define _brw_cmd_header(cmd) cmd ## _header
162 #define _brw_cmd_pack(cmd) cmd ## _pack
164 #define brw_batch_emit(brw, cmd, name) \
165 for (struct cmd name = { _brw_cmd_header(cmd) }, \
166 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
167 __builtin_expect(_dst != NULL, 1); \
168 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
171 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
172 uint32_t *_dw = emit_dwords(brw, n); \
173 struct cmd template = { \
174 _brw_cmd_header(cmd), \
175 .DWordLength = n - _brw_cmd_length_bias(cmd), \
178 _brw_cmd_pack(cmd)(brw, _dw, &template); \
179 _dw + 1; /* Array starts at dw[1] */ \
182 #define brw_state_emit(brw, cmd, align, offset, name) \
183 for (struct cmd name = { 0, }, \
184 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
186 __builtin_expect(_dst != NULL, 1); \
187 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
191 * Polygon stipple packet
194 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
196 struct gl_context
*ctx
= &brw
->ctx
;
199 if (!ctx
->Polygon
.StippleFlag
)
202 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
203 /* Polygon stipple is provided in OpenGL order, i.e. bottom
204 * row first. If we're rendering to a window (i.e. the
205 * default frame buffer object, 0), then we need to invert
206 * it to match our pixel layout. But if we're rendering
207 * to a FBO (i.e. any named frame buffer object), we *don't*
208 * need to invert - we already match the layout.
210 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
211 for (unsigned i
= 0; i
< 32; i
++)
212 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
214 for (unsigned i
= 0; i
< 32; i
++)
215 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
220 static const struct brw_tracked_state
genX(polygon_stipple
) = {
222 .mesa
= _NEW_POLYGON
|
224 .brw
= BRW_NEW_CONTEXT
,
226 .emit
= genX(upload_polygon_stipple
),
230 * Polygon stipple offset packet
233 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
235 struct gl_context
*ctx
= &brw
->ctx
;
238 if (!ctx
->Polygon
.StippleFlag
)
241 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
244 * If we're drawing to a system window we have to invert the Y axis
245 * in order to match the OpenGL pixel coordinate system, and our
246 * offset must be matched to the window position. If we're drawing
247 * to a user-created FBO then our native pixel coordinate system
248 * works just fine, and there's no window system to worry about.
250 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
251 poly
.PolygonStippleYOffset
=
252 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
257 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
259 .mesa
= _NEW_BUFFERS
|
261 .brw
= BRW_NEW_CONTEXT
,
263 .emit
= genX(upload_polygon_stipple_offset
),
267 * Line stipple packet
270 genX(upload_line_stipple
)(struct brw_context
*brw
)
272 struct gl_context
*ctx
= &brw
->ctx
;
274 if (!ctx
->Line
.StippleFlag
)
277 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
278 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
280 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
281 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
285 static const struct brw_tracked_state
genX(line_stipple
) = {
288 .brw
= BRW_NEW_CONTEXT
,
290 .emit
= genX(upload_line_stipple
),
293 /* Constant single cliprect for framebuffer object or DRI2 drawing */
295 genX(upload_drawing_rect
)(struct brw_context
*brw
)
297 struct gl_context
*ctx
= &brw
->ctx
;
298 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
299 const unsigned int fb_width
= _mesa_geometric_width(fb
);
300 const unsigned int fb_height
= _mesa_geometric_height(fb
);
302 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
303 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
304 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
308 static const struct brw_tracked_state
genX(drawing_rect
) = {
310 .mesa
= _NEW_BUFFERS
,
311 .brw
= BRW_NEW_BLORP
|
314 .emit
= genX(upload_drawing_rect
),
318 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
322 unsigned start_offset
,
327 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
328 .VertexBufferIndex
= buffer_nr
,
329 .BufferPitch
= stride
,
330 .BufferStartingAddress
= vertex_bo(bo
, start_offset
),
332 .BufferSize
= end_offset
- start_offset
,
336 .AddressModifyEnable
= true,
340 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
341 .InstanceDataStepRate
= step_rate
,
343 .EndAddress
= vertex_bo(bo
, end_offset
- 1),
348 .VertexBufferMOCS
= SKL_MOCS_WB
,
350 .VertexBufferMOCS
= BDW_MOCS_WB
,
352 .VertexBufferMOCS
= GEN7_MOCS_L3
,
356 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
357 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
361 is_passthru_format(uint32_t format
)
364 case ISL_FORMAT_R64_PASSTHRU
:
365 case ISL_FORMAT_R64G64_PASSTHRU
:
366 case ISL_FORMAT_R64G64B64_PASSTHRU
:
367 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
375 uploads_needed(uint32_t format
)
377 if (!is_passthru_format(format
))
381 case ISL_FORMAT_R64_PASSTHRU
:
382 case ISL_FORMAT_R64G64_PASSTHRU
:
384 case ISL_FORMAT_R64G64B64_PASSTHRU
:
385 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
388 unreachable("not reached");
393 * Returns the format that we are finally going to use when upload a vertex
394 * element. It will only change if we are using *64*PASSTHRU formats, as for
395 * gen < 8 they need to be splitted on two *32*FLOAT formats.
397 * @upload points in which upload we are. Valid values are [0,1]
400 downsize_format_if_needed(uint32_t format
,
403 assert(upload
== 0 || upload
== 1);
405 if (!is_passthru_format(format
))
409 case ISL_FORMAT_R64_PASSTHRU
:
410 return ISL_FORMAT_R32G32_FLOAT
;
411 case ISL_FORMAT_R64G64_PASSTHRU
:
412 return ISL_FORMAT_R32G32B32A32_FLOAT
;
413 case ISL_FORMAT_R64G64B64_PASSTHRU
:
414 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
415 : ISL_FORMAT_R32G32_FLOAT
;
416 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
417 return ISL_FORMAT_R32G32B32A32_FLOAT
;
419 unreachable("not reached");
424 * Returns the number of componentes associated with a format that is used on
425 * a 64 to 32 format split. See downsize_format()
428 upload_format_size(uint32_t upload_format
)
430 switch (upload_format
) {
431 case ISL_FORMAT_R32G32_FLOAT
:
433 case ISL_FORMAT_R32G32B32A32_FLOAT
:
436 unreachable("not reached");
441 genX(emit_vertices
)(struct brw_context
*brw
)
445 brw_prepare_vertices(brw
);
446 brw_prepare_shader_draw_parameters(brw
);
449 brw_emit_query_begin(brw
);
452 const struct brw_vs_prog_data
*vs_prog_data
=
453 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
456 struct gl_context
*ctx
= &brw
->ctx
;
457 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
458 ctx
->Polygon
.BackMode
!= GL_FILL
);
460 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
461 unsigned vue
= brw
->vb
.nr_enabled
;
463 /* The element for the edge flags must always be last, so we have to
464 * insert the SGVS before it in that case.
466 if (uses_edge_flag
) {
472 "Trying to insert VID/IID past 33rd vertex element, "
473 "need to reorder the vertex attrbutes.");
475 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
476 if (vs_prog_data
->uses_vertexid
) {
477 vfs
.VertexIDEnable
= true;
478 vfs
.VertexIDComponentNumber
= 2;
479 vfs
.VertexIDElementOffset
= vue
;
482 if (vs_prog_data
->uses_instanceid
) {
483 vfs
.InstanceIDEnable
= true;
484 vfs
.InstanceIDComponentNumber
= 3;
485 vfs
.InstanceIDElementOffset
= vue
;
489 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
490 vfi
.InstancingEnable
= true;
491 vfi
.VertexElementIndex
= vue
;
494 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
497 /* Normally we don't need an element for the SGVS attribute because the
498 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
499 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
500 * we're using draw parameters then we need an element for the those
501 * values. Additionally if there is an edge flag element then the SGVS
502 * can't be inserted past that so we need a dummy element to ensure that
503 * the edge flag is the last one.
505 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
506 vs_prog_data
->uses_baseinstance
||
507 ((vs_prog_data
->uses_instanceid
||
508 vs_prog_data
->uses_vertexid
)
511 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
512 vs_prog_data
->uses_baseinstance
||
513 vs_prog_data
->uses_instanceid
||
514 vs_prog_data
->uses_vertexid
);
516 unsigned nr_elements
=
517 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
520 /* If any of the formats of vb.enabled needs more that one upload, we need
521 * to add it to nr_elements
523 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
524 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
525 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
527 if (uploads_needed(format
) > 1)
532 /* If the VS doesn't read any inputs (calculating vertex position from
533 * a state variable for some reason, for example), emit a single pad
534 * VERTEX_ELEMENT struct and bail.
536 * The stale VB state stays in place, but they don't do anything unless
537 * a VE loads from them.
539 if (nr_elements
== 0) {
540 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
541 1 + GENX(VERTEX_ELEMENT_STATE_length
));
542 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
544 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
545 .Component0Control
= VFCOMP_STORE_0
,
546 .Component1Control
= VFCOMP_STORE_0
,
547 .Component2Control
= VFCOMP_STORE_0
,
548 .Component3Control
= VFCOMP_STORE_1_FP
,
550 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
554 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
555 const bool uses_draw_params
=
556 vs_prog_data
->uses_basevertex
||
557 vs_prog_data
->uses_baseinstance
;
558 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
559 uses_draw_params
+ vs_prog_data
->uses_drawid
;
562 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
564 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
565 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
567 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
568 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
569 /* Prior to Haswell and Bay Trail we have to use 4-component formats
570 * to fake 3-component ones. In particular, we do this for
571 * half-float and 8 and 16-bit integer formats. This means that the
572 * vertex element may poke over the end of the buffer by 2 bytes.
574 const unsigned padding
=
575 (GEN_GEN
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
576 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
577 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
584 if (uses_draw_params
) {
585 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
586 brw
->draw
.draw_params_bo
,
587 brw
->draw
.draw_params_offset
,
588 brw
->draw
.draw_params_bo
->size
,
593 if (vs_prog_data
->uses_drawid
) {
594 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
595 brw
->draw
.draw_id_bo
,
596 brw
->draw
.draw_id_offset
,
597 brw
->draw
.draw_id_bo
->size
,
603 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
604 * presumably for VertexID/InstanceID.
607 assert(nr_elements
<= 34);
608 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
610 assert(nr_elements
<= 18);
613 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
614 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
616 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
617 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
618 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
619 uint32_t comp0
= VFCOMP_STORE_SRC
;
620 uint32_t comp1
= VFCOMP_STORE_SRC
;
621 uint32_t comp2
= VFCOMP_STORE_SRC
;
622 uint32_t comp3
= VFCOMP_STORE_SRC
;
623 const unsigned num_uploads
= GEN_GEN
< 8 ? uploads_needed(format
) : 1;
626 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
627 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
628 * element which has edge flag enabled."
630 assert(!(is_passthru_format(format
) && uses_edge_flag
));
633 /* The gen4 driver expects edgeflag to come in as a float, and passes
634 * that float on to the tests in the clipper. Mesa's current vertex
635 * attribute value for EdgeFlag is stored as a float, which works out.
636 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
637 * integer ubyte. Just rewrite that to convert to a float.
639 * Gen6+ passes edgeflag as sideband along with the vertex, instead
640 * of in the VUE. We have to upload it sideband as the last vertex
641 * element according to the B-Spec.
644 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
645 gen6_edgeflag_input
= input
;
650 for (unsigned c
= 0; c
< num_uploads
; c
++) {
651 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
652 downsize_format_if_needed(format
, c
);
653 /* If we need more that one upload, the offset stride would be 128
654 * bits (16 bytes), as for previous uploads we are using the full
656 const unsigned offset
= input
->offset
+ c
* 16;
658 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
659 upload_format_size(upload_format
) : input
->glarray
->Size
;
662 case 0: comp0
= VFCOMP_STORE_0
;
663 case 1: comp1
= VFCOMP_STORE_0
;
664 case 2: comp2
= VFCOMP_STORE_0
;
666 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
667 comp3
= VFCOMP_STORE_0
;
668 } else if (input
->glarray
->Integer
) {
669 comp3
= VFCOMP_STORE_1_INT
;
671 comp3
= VFCOMP_STORE_1_FP
;
678 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
680 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
681 * formats, 64-bit components are stored in the URB without any
682 * conversion. In this case, vertex elements must be written as 128
683 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
684 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
685 * component into the URB, Component 1 must be specified as
686 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
687 * order to output a 128-bit vertex element, or Components 1-3 must
688 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
689 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
690 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
693 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
694 /* Store vertex elements which correspond to double and dvec2 vertex
695 * shader inputs as 128-bit vertex elements, instead of 256-bits.
697 comp2
= VFCOMP_NOSTORE
;
698 comp3
= VFCOMP_NOSTORE
;
702 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
703 .VertexBufferIndex
= input
->buffer
,
705 .SourceElementFormat
= upload_format
,
706 .SourceElementOffset
= offset
,
707 .Component0Control
= comp0
,
708 .Component1Control
= comp1
,
709 .Component2Control
= comp2
,
710 .Component3Control
= comp3
,
712 .DestinationElementOffset
= i
* 4,
716 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
717 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
721 if (needs_sgvs_element
) {
722 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
724 .Component0Control
= VFCOMP_STORE_0
,
725 .Component1Control
= VFCOMP_STORE_0
,
726 .Component2Control
= VFCOMP_STORE_0
,
727 .Component3Control
= VFCOMP_STORE_0
,
729 .DestinationElementOffset
= i
* 4,
734 if (vs_prog_data
->uses_basevertex
||
735 vs_prog_data
->uses_baseinstance
) {
736 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
737 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
738 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
739 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
742 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
743 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
744 if (vs_prog_data
->uses_basevertex
)
745 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
747 if (vs_prog_data
->uses_baseinstance
)
748 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
750 if (vs_prog_data
->uses_vertexid
)
751 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
753 if (vs_prog_data
->uses_instanceid
)
754 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
757 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
758 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
761 if (vs_prog_data
->uses_drawid
) {
762 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
764 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
765 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
766 .Component0Control
= VFCOMP_STORE_SRC
,
767 .Component1Control
= VFCOMP_STORE_0
,
768 .Component2Control
= VFCOMP_STORE_0
,
769 .Component3Control
= VFCOMP_STORE_0
,
771 .DestinationElementOffset
= i
* 4,
775 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
776 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
780 if (gen6_edgeflag_input
) {
781 const uint32_t format
=
782 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
784 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
786 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
787 .EdgeFlagEnable
= true,
788 .SourceElementFormat
= format
,
789 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
790 .Component0Control
= VFCOMP_STORE_SRC
,
791 .Component1Control
= VFCOMP_STORE_0
,
792 .Component2Control
= VFCOMP_STORE_0
,
793 .Component3Control
= VFCOMP_STORE_0
,
796 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
797 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
802 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
803 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
804 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
805 unsigned element_index
;
807 /* The edge flag element is reordered to be the last one in the code
808 * above so we need to compensate for that in the element indices used
811 if (input
== gen6_edgeflag_input
)
812 element_index
= nr_elements
- 1;
816 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
817 vfi
.VertexElementIndex
= element_index
;
818 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
819 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
823 if (vs_prog_data
->uses_drawid
) {
824 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
826 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
827 vfi
.VertexElementIndex
= element
;
833 static const struct brw_tracked_state
genX(vertices
) = {
835 .mesa
= _NEW_POLYGON
,
836 .brw
= BRW_NEW_BATCH
|
839 BRW_NEW_VS_PROG_DATA
,
841 .emit
= genX(emit_vertices
),
845 genX(emit_index_buffer
)(struct brw_context
*brw
)
847 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
849 if (index_buffer
== NULL
)
852 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
853 #if GEN_GEN < 8 && !GEN_IS_HASWELL
854 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
856 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
857 ib
.BufferStartingAddress
= vertex_bo(brw
->ib
.bo
, 0);
859 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
860 ib
.BufferSize
= brw
->ib
.size
;
862 ib
.BufferEndingAddress
= vertex_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
867 static const struct brw_tracked_state
genX(index_buffer
) = {
870 .brw
= BRW_NEW_BATCH
|
872 BRW_NEW_INDEX_BUFFER
,
874 .emit
= genX(emit_index_buffer
),
877 #if GEN_IS_HASWELL || GEN_GEN >= 8
879 genX(upload_cut_index
)(struct brw_context
*brw
)
881 const struct gl_context
*ctx
= &brw
->ctx
;
883 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
884 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
885 vf
.IndexedDrawCutIndexEnable
= true;
886 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
891 const struct brw_tracked_state
genX(cut_index
) = {
893 .mesa
= _NEW_TRANSFORM
,
894 .brw
= BRW_NEW_INDEX_BUFFER
,
896 .emit
= genX(upload_cut_index
),
902 * Determine the appropriate attribute override value to store into the
903 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
904 * override value contains two pieces of information: the location of the
905 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
906 * flag indicating whether to "swizzle" the attribute based on the direction
907 * the triangle is facing.
909 * If an attribute is "swizzled", then the given VUE location is used for
910 * front-facing triangles, and the VUE location that immediately follows is
911 * used for back-facing triangles. We use this to implement the mapping from
912 * gl_FrontColor/gl_BackColor to gl_Color.
914 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
915 * being instructed to begin reading attribute data. It can be set to a
916 * nonzero value to prevent the SF unit from wasting time reading elements of
917 * the VUE that are not needed by the fragment shader. It is measured in
918 * 256-bit increments.
921 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
922 const struct brw_vue_map
*vue_map
,
923 int urb_entry_read_offset
, int fs_attr
,
924 bool two_side_color
, uint32_t *max_source_attr
)
926 /* Find the VUE slot for this attribute. */
927 int slot
= vue_map
->varying_to_slot
[fs_attr
];
929 /* Viewport and Layer are stored in the VUE header. We need to override
930 * them to zero if earlier stages didn't write them, as GL requires that
931 * they read back as zero when not explicitly set.
933 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
934 attr
->ComponentOverrideX
= true;
935 attr
->ComponentOverrideW
= true;
936 attr
->ConstantSource
= CONST_0000
;
938 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
939 attr
->ComponentOverrideY
= true;
940 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
941 attr
->ComponentOverrideZ
= true;
946 /* If there was only a back color written but not front, use back
947 * as the color instead of undefined
949 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
950 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
951 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
952 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
955 /* This attribute does not exist in the VUE--that means that the vertex
956 * shader did not write to it. This means that either:
958 * (a) This attribute is a texture coordinate, and it is going to be
959 * replaced with point coordinates (as a consequence of a call to
960 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
961 * hardware will ignore whatever attribute override we supply.
963 * (b) This attribute is read by the fragment shader but not written by
964 * the vertex shader, so its value is undefined. Therefore the
965 * attribute override we supply doesn't matter.
967 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
968 * previous shader stage.
970 * Note that we don't have to worry about the cases where the attribute
971 * is gl_PointCoord or is undergoing point sprite coordinate
972 * replacement, because in those cases, this function isn't called.
974 * In case (c), we need to program the attribute overrides so that the
975 * primitive ID will be stored in this slot. In every other case, the
976 * attribute override we supply doesn't matter. So just go ahead and
977 * program primitive ID in every case.
979 attr
->ComponentOverrideW
= true;
980 attr
->ComponentOverrideX
= true;
981 attr
->ComponentOverrideY
= true;
982 attr
->ComponentOverrideZ
= true;
983 attr
->ConstantSource
= PRIM_ID
;
987 /* Compute the location of the attribute relative to urb_entry_read_offset.
988 * Each increment of urb_entry_read_offset represents a 256-bit value, so
989 * it counts for two 128-bit VUE slots.
991 int source_attr
= slot
- 2 * urb_entry_read_offset
;
992 assert(source_attr
>= 0 && source_attr
< 32);
994 /* If we are doing two-sided color, and the VUE slot following this one
995 * represents a back-facing color, then we need to instruct the SF unit to
996 * do back-facing swizzling.
998 bool swizzling
= two_side_color
&&
999 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1000 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1001 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1002 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1004 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1005 if (*max_source_attr
< source_attr
+ swizzling
)
1006 *max_source_attr
= source_attr
+ swizzling
;
1008 attr
->SourceAttribute
= source_attr
;
1010 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1015 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1016 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1017 uint32_t *point_sprite_enables
,
1018 uint32_t *urb_entry_read_length
,
1019 uint32_t *urb_entry_read_offset
)
1021 const struct gl_context
*ctx
= &brw
->ctx
;
1024 const struct gl_point_attrib
*point
= &ctx
->Point
;
1026 /* BRW_NEW_FS_PROG_DATA */
1027 const struct brw_wm_prog_data
*wm_prog_data
=
1028 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1029 uint32_t max_source_attr
= 0;
1031 *point_sprite_enables
= 0;
1033 /* BRW_NEW_FRAGMENT_PROGRAM
1035 * If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
1036 * the full vertex header. Otherwise, we can program the SF to start
1037 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
1038 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1039 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
1042 bool fs_needs_vue_header
= brw
->fragment_program
->info
.inputs_read
&
1043 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1045 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
1047 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1048 * description of dw10 Point Sprite Texture Coordinate Enable:
1050 * "This field must be programmed to zero when non-point primitives
1053 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1054 * must be programmed to zero when rendering non-point primitives, but
1055 * the IvyBridge PRM does, and if we don't, we get garbage.
1057 * This is not required on Haswell, as the hardware ignores this state
1058 * when drawing non-points -- although we do still need to be careful to
1059 * correctly set the attr overrides.
1062 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1064 bool drawing_points
= brw_is_drawing_points(brw
);
1066 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1067 int input_index
= wm_prog_data
->urb_setup
[attr
];
1069 if (input_index
< 0)
1073 bool point_sprite
= false;
1074 if (drawing_points
) {
1075 if (point
->PointSprite
&&
1076 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1077 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1078 point_sprite
= true;
1081 if (attr
== VARYING_SLOT_PNTC
)
1082 point_sprite
= true;
1085 *point_sprite_enables
|= (1 << input_index
);
1088 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1089 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1091 if (!point_sprite
) {
1092 genX(get_attr_override
)(&attribute
,
1093 &brw
->vue_map_geom_out
,
1094 *urb_entry_read_offset
, attr
,
1095 brw
->ctx
.VertexProgram
._TwoSideEnabled
,
1099 /* The hardware can only do the overrides on 16 overrides at a
1100 * time, and the other up to 16 have to be lined up so that the
1101 * input index = the output index. We'll need to do some
1102 * tweaking to make sure that's the case.
1104 if (input_index
< 16)
1105 attr_overrides
[input_index
] = attribute
;
1107 assert(attribute
.SourceAttribute
== input_index
);
1110 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1111 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1113 * "This field should be set to the minimum length required to read the
1114 * maximum source attribute. The maximum source attribute is indicated
1115 * by the maximum value of the enabled Attribute # Source Attribute if
1116 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1117 * enable is not set.
1118 * read_length = ceiling((max_source_attr + 1) / 2)
1120 * [errata] Corruption/Hang possible if length programmed larger than
1123 * Similar text exists for Ivy Bridge.
1125 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1129 /* ---------------------------------------------------------------------- */
1133 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1135 struct gl_context
*ctx
= &brw
->ctx
;
1138 struct intel_renderbuffer
*depth_irb
=
1139 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1142 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1145 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1146 const int b
= stencil
->_BackFace
;
1149 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1152 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, wmds
) {
1154 if (depth
->Test
&& depth_irb
) {
1155 wmds
.DepthTestEnable
= true;
1156 wmds
.DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1157 wmds
.DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1160 if (stencil
->_Enabled
) {
1161 wmds
.StencilTestEnable
= true;
1162 wmds
.StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1163 wmds
.StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1165 wmds
.StencilTestFunction
=
1166 intel_translate_compare_func(stencil
->Function
[0]);
1167 wmds
.StencilFailOp
=
1168 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1169 wmds
.StencilPassDepthPassOp
=
1170 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1171 wmds
.StencilPassDepthFailOp
=
1172 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1174 wmds
.StencilBufferWriteEnable
= stencil
->_WriteEnabled
;
1176 if (stencil
->_TestTwoSide
) {
1177 wmds
.DoubleSidedStencilEnable
= true;
1178 wmds
.BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1179 wmds
.BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1181 wmds
.BackfaceStencilTestFunction
=
1182 intel_translate_compare_func(stencil
->Function
[b
]);
1183 wmds
.BackfaceStencilFailOp
=
1184 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1185 wmds
.BackfaceStencilPassDepthPassOp
=
1186 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1187 wmds
.BackfaceStencilPassDepthFailOp
=
1188 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1192 wmds
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1193 wmds
.BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1199 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1200 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1201 ptr
.DEPTH_STENCIL_STATEChange
= true;
1204 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1205 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1210 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1212 .mesa
= _NEW_BUFFERS
|
1215 .brw
= BRW_NEW_BLORP
|
1216 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1218 BRW_NEW_STATE_BASE_ADDRESS
),
1220 .emit
= genX(upload_depth_stencil_state
),
1224 /* ---------------------------------------------------------------------- */
1228 genX(upload_clip_state
)(struct brw_context
*brw
)
1230 struct gl_context
*ctx
= &brw
->ctx
;
1233 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1235 /* BRW_NEW_FS_PROG_DATA */
1236 struct brw_wm_prog_data
*wm_prog_data
=
1237 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1239 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1240 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1242 if (wm_prog_data
->barycentric_interp_modes
&
1243 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1244 clip
.NonPerspectiveBarycentricEnable
= true;
1247 clip
.EarlyCullEnable
= true;
1251 clip
.FrontWinding
= ctx
->Polygon
._FrontBit
== _mesa_is_user_fbo(fb
);
1253 if (ctx
->Polygon
.CullFlag
) {
1254 switch (ctx
->Polygon
.CullFaceMode
) {
1256 clip
.CullMode
= CULLMODE_FRONT
;
1259 clip
.CullMode
= CULLMODE_BACK
;
1261 case GL_FRONT_AND_BACK
:
1262 clip
.CullMode
= CULLMODE_BOTH
;
1265 unreachable("Should not get here: invalid CullFlag");
1268 clip
.CullMode
= CULLMODE_NONE
;
1273 clip
.UserClipDistanceCullTestEnableBitmask
=
1274 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1276 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1280 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1281 clip
.TriangleStripListProvokingVertexSelect
= 0;
1282 clip
.TriangleFanProvokingVertexSelect
= 1;
1283 clip
.LineStripListProvokingVertexSelect
= 0;
1285 clip
.TriangleStripListProvokingVertexSelect
= 2;
1286 clip
.TriangleFanProvokingVertexSelect
= 2;
1287 clip
.LineStripListProvokingVertexSelect
= 1;
1290 /* _NEW_TRANSFORM */
1291 clip
.UserClipDistanceClipTestEnableBitmask
=
1292 ctx
->Transform
.ClipPlanesEnabled
;
1295 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1298 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1299 clip
.APIMode
= APIMODE_D3D
;
1301 clip
.APIMode
= APIMODE_OGL
;
1303 clip
.GuardbandClipTestEnable
= true;
1305 /* BRW_NEW_VIEWPORT_COUNT */
1306 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1308 if (ctx
->RasterDiscard
) {
1309 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1311 perf_debug("Rasterizer discard is currently implemented via the "
1312 "clipper; having the GS not write primitives would "
1313 "likely be faster.\n");
1316 clip
.ClipMode
= CLIPMODE_NORMAL
;
1319 clip
.ClipEnable
= brw
->primitive
!= _3DPRIM_RECTLIST
;
1322 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1324 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1325 clip
.ViewportXYClipTestEnable
= true;
1327 clip
.MinimumPointWidth
= 0.125;
1328 clip
.MaximumPointWidth
= 255.875;
1329 clip
.MaximumVPIndex
= viewport_count
- 1;
1330 if (_mesa_geometric_layers(fb
) == 0)
1331 clip
.ForceZeroRTAIndexEnable
= true;
1335 static const struct brw_tracked_state
genX(clip_state
) = {
1337 .mesa
= _NEW_BUFFERS
|
1341 .brw
= BRW_NEW_BLORP
|
1343 BRW_NEW_FS_PROG_DATA
|
1344 BRW_NEW_GS_PROG_DATA
|
1345 BRW_NEW_VS_PROG_DATA
|
1346 BRW_NEW_META_IN_PROGRESS
|
1348 BRW_NEW_RASTERIZER_DISCARD
|
1349 BRW_NEW_TES_PROG_DATA
|
1350 BRW_NEW_VIEWPORT_COUNT
,
1352 .emit
= genX(upload_clip_state
),
1356 /* ---------------------------------------------------------------------- */
1360 genX(upload_sf
)(struct brw_context
*brw
)
1362 struct gl_context
*ctx
= &brw
->ctx
;
1367 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1368 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1371 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1372 sf
.StatisticsEnable
= true;
1373 sf
.ViewportTransformEnable
= true;
1377 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1382 sf
.FrontWinding
= ctx
->Polygon
._FrontBit
== render_to_fbo
;
1383 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1384 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1385 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1387 switch (ctx
->Polygon
.FrontMode
) {
1389 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1392 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1395 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1398 unreachable("not reached");
1401 switch (ctx
->Polygon
.BackMode
) {
1403 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1406 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1409 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1412 unreachable("not reached");
1415 sf
.ScissorRectangleEnable
= true;
1417 if (ctx
->Polygon
.CullFlag
) {
1418 switch (ctx
->Polygon
.CullFaceMode
) {
1420 sf
.CullMode
= CULLMODE_FRONT
;
1423 sf
.CullMode
= CULLMODE_BACK
;
1425 case GL_FRONT_AND_BACK
:
1426 sf
.CullMode
= CULLMODE_BOTH
;
1429 unreachable("not reached");
1432 sf
.CullMode
= CULLMODE_NONE
;
1436 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1439 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1440 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1442 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1443 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1444 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1449 if (brw
->is_cherryview
)
1450 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1452 sf
.LineWidth
= brw_get_line_width(brw
);
1454 sf
.LineWidth
= brw_get_line_width(brw
);
1457 if (ctx
->Line
.SmoothFlag
) {
1458 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1460 sf
.AntiAliasingEnable
= true;
1464 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1465 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1466 /* Clamp to the hardware limits */
1467 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1469 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1470 if (use_state_point_size(brw
))
1471 sf
.PointWidthSource
= State
;
1474 /* _NEW_POINT | _NEW_MULTISAMPLE */
1475 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1476 !ctx
->Point
.PointSprite
)
1477 sf
.SmoothPointEnable
= true;
1480 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1483 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1484 sf
.TriangleStripListProvokingVertexSelect
= 2;
1485 sf
.TriangleFanProvokingVertexSelect
= 2;
1486 sf
.LineStripListProvokingVertexSelect
= 1;
1488 sf
.TriangleFanProvokingVertexSelect
= 1;
1492 /* BRW_NEW_FS_PROG_DATA */
1493 const struct brw_wm_prog_data
*wm_prog_data
=
1494 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1496 sf
.AttributeSwizzleEnable
= true;
1497 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1500 * Window coordinates in an FBO are inverted, which means point
1501 * sprite origin must be inverted, too.
1503 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1504 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1506 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1509 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1510 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1512 uint32_t urb_entry_read_length
;
1513 uint32_t urb_entry_read_offset
;
1514 uint32_t point_sprite_enables
;
1515 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1516 &urb_entry_read_length
,
1517 &urb_entry_read_offset
);
1518 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1519 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1520 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1521 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1526 static const struct brw_tracked_state
genX(sf_state
) = {
1528 .mesa
= _NEW_LIGHT
|
1533 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1534 .brw
= BRW_NEW_BLORP
|
1536 BRW_NEW_VUE_MAP_GEOM_OUT
|
1537 (GEN_GEN
<= 7 ? BRW_NEW_GS_PROG_DATA
|
1539 BRW_NEW_TES_PROG_DATA
1541 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1542 BRW_NEW_FRAGMENT_PROGRAM
1545 .emit
= genX(upload_sf
),
1549 /* ---------------------------------------------------------------------- */
1553 genX(upload_wm
)(struct brw_context
*brw
)
1555 struct gl_context
*ctx
= &brw
->ctx
;
1557 /* BRW_NEW_FS_PROG_DATA */
1558 const struct brw_wm_prog_data
*wm_prog_data
=
1559 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1561 UNUSED
bool writes_depth
=
1562 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1565 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1566 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1568 /* We can't fold this into gen6_upload_wm_push_constants(), because
1569 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1570 * (3DSTATE_CONSTANT_PS [DevSNB]):
1572 * "[DevSNB]: This packet must be followed by WM_STATE."
1574 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1575 if (wm_prog_data
->base
.nr_params
!= 0) {
1576 wmcp
.Buffer0Valid
= true;
1577 /* Pointer to the WM constant buffer. Covered by the set of
1578 * state flags from gen6_upload_wm_push_constants.
1580 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1581 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1586 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1587 wm
.StatisticsEnable
= true;
1588 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1589 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1592 if (wm_prog_data
->base
.use_alt_mode
)
1593 wm
.FloatingPointMode
= Alternate
;
1595 wm
.SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1596 wm
.BindingTableEntryCount
= wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1597 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1598 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1599 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1600 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1601 wm_prog_data
->base
.dispatch_grf_start_reg
;
1602 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1603 wm_prog_data
->dispatch_grf_start_reg_2
;
1604 wm
.KernelStartPointer0
= stage_state
->prog_offset
;
1605 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1606 wm_prog_data
->prog_offset_2
;
1607 wm
.DualSourceBlendEnable
=
1608 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1609 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1610 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1611 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1613 /* From the SNB PRM, volume 2 part 1, page 281:
1614 * "If the PS kernel does not need the Position XY Offsets
1615 * to compute a Position XY value, then this field should be
1616 * programmed to POSOFFSET_NONE."
1618 * "SW Recommendation: If the PS kernel needs the Position Offsets
1619 * to compute a Position XY value, this field should match Position
1620 * ZW Interpolation Mode to ensure a consistent position.xyzw
1622 * We only require XY sample offsets. So, this recommendation doesn't
1623 * look useful at the moment. We might need this in future.
1625 if (wm_prog_data
->uses_pos_offset
)
1626 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1628 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1630 if (wm_prog_data
->base
.total_scratch
) {
1631 wm
.ScratchSpaceBasePointer
=
1632 render_bo(stage_state
->scratch_bo
,
1633 ffs(stage_state
->per_thread_scratch
) - 11);
1636 wm
.PixelShaderComputedDepth
= writes_depth
;
1639 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1642 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1645 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1646 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1650 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1652 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1653 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1654 if (wm_prog_data
->uses_kill
||
1655 _mesa_is_alpha_test_enabled(ctx
) ||
1656 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1657 wm_prog_data
->uses_omask
) {
1658 wm
.PixelShaderKillsPixel
= true;
1661 /* _NEW_BUFFERS | _NEW_COLOR */
1662 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1663 wm_prog_data
->has_side_effects
|| wm
.PixelShaderKillsPixel
) {
1664 wm
.ThreadDispatchEnable
= true;
1666 if (multisampled_fbo
) {
1667 /* _NEW_MULTISAMPLE */
1668 if (ctx
->Multisample
.Enabled
)
1669 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1671 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1673 if (wm_prog_data
->persample_dispatch
)
1674 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1676 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1678 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1679 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1683 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1684 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1687 /* The "UAV access enable" bits are unnecessary on HSW because they only
1688 * seem to have an effect on the HW-assisted coherency mechanism which we
1689 * don't need, and the rasterization-related UAV_ONLY flag and the
1690 * DISPATCH_ENABLE bit can be set independently from it.
1691 * C.f. gen8_upload_ps_extra().
1693 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1697 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1698 wm_prog_data
->has_side_effects
)
1704 /* BRW_NEW_FS_PROG_DATA */
1705 if (wm_prog_data
->early_fragment_tests
)
1706 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1707 else if (wm_prog_data
->has_side_effects
)
1708 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1713 static const struct brw_tracked_state
genX(wm_state
) = {
1717 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1721 (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
1722 .brw
= BRW_NEW_BLORP
|
1723 BRW_NEW_FS_PROG_DATA
|
1724 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
1726 .emit
= genX(upload_wm
),
1730 /* ---------------------------------------------------------------------- */
1733 static inline struct brw_address
1734 KSP(struct brw_context
*brw
, uint32_t offset
)
1736 return instruction_bo(brw
->cache
.bo
, offset
);
1739 static inline uint32_t
1740 KSP(struct brw_context
*brw
, uint32_t offset
)
1746 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1747 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
1748 pkt.SamplerCount = \
1749 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1750 pkt.BindingTableEntryCount = \
1751 stage_prog_data->binding_table.size_bytes / 4; \
1752 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
1754 if (stage_prog_data->total_scratch) { \
1755 pkt.ScratchSpaceBasePointer = \
1756 render_bo(stage_state->scratch_bo, 0); \
1757 pkt.PerThreadScratchSpace = \
1758 ffs(stage_state->per_thread_scratch) - 11; \
1761 pkt.DispatchGRFStartRegisterForURBData = \
1762 stage_prog_data->dispatch_grf_start_reg; \
1763 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1764 pkt.prefix##URBEntryReadOffset = 0; \
1766 pkt.StatisticsEnable = true; \
1770 genX(upload_vs_state
)(struct brw_context
*brw
)
1772 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
1773 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1774 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
1776 /* BRW_NEW_VS_PROG_DATA */
1777 const struct brw_vue_prog_data
*vue_prog_data
=
1778 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
1779 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
1781 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
1782 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
1785 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1786 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1788 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
1789 * command that causes the VS Function Enable to toggle. Pipeline
1790 * flush can be executed by sending a PIPE_CONTROL command with CS
1791 * stall bit set and a post sync operation.
1793 * We've already done such a flush at the start of state upload, so we
1794 * don't need to do another one here.
1796 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
1797 if (stage_state
->push_const_size
!= 0) {
1798 cvs
.Buffer0Valid
= true;
1799 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
1800 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1805 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
1806 gen7_emit_vs_workaround_flush(brw
);
1809 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
1811 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1812 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
1814 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1816 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1819 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
1820 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
1821 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
1823 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
1824 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1826 vs
.MaximumNumberofThreads
=
1827 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
1829 vs
.StatisticsEnable
= false;
1830 vs
.SamplerStatePointer
=
1831 instruction_ro_bo(brw
->batch
.bo
, stage_state
->sampler_offset
);
1835 /* Force single program flow on Ironlake. We cannot reliably get
1836 * all applications working without it. See:
1837 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
1839 * The most notable and reliably failing application is the Humus
1842 vs
.SingleProgramFlow
= true;
1843 vs
.SamplerCount
= 0; /* hardware requirement */
1847 vs
.SIMD8DispatchEnable
=
1848 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
1850 vs
.UserClipDistanceCullTestEnableBitmask
=
1851 vue_prog_data
->cull_distance_mask
;
1856 /* Based on my reading of the simulator, the VS constants don't get
1857 * pulled into the VS FF unit until an appropriate pipeline flush
1858 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
1859 * references to them into a little FIFO. The flushes are common,
1860 * but don't reliably happen between this and a 3DPRIMITIVE, causing
1861 * the primitive to use the wrong constants. Then the FIFO
1862 * containing the constant setup gets added to again on the next
1863 * constants change, and eventually when a flush does happen the
1864 * unit is overwhelmed by constant changes and dies.
1866 * To avoid this, send a PIPE_CONTROL down the line that will
1867 * update the unit immediately loading the constants. The flush
1868 * type bits here were those set by the STATE_BASE_ADDRESS whose
1869 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
1870 * bug reports that led to this workaround, and may be more than
1871 * what is strictly required to avoid the issue.
1873 brw_emit_pipe_control_flush(brw
,
1874 PIPE_CONTROL_DEPTH_STALL
|
1875 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1876 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
1880 static const struct brw_tracked_state
genX(vs_state
) = {
1882 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
1883 .brw
= BRW_NEW_BATCH
|
1886 BRW_NEW_VS_PROG_DATA
|
1887 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
1888 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1889 BRW_NEW_PROGRAM_CACHE
|
1890 BRW_NEW_SAMPLER_STATE_TABLE
|
1894 .emit
= genX(upload_vs_state
),
1897 /* ---------------------------------------------------------------------- */
1900 genX(upload_cc_viewport
)(struct brw_context
*brw
)
1902 struct gl_context
*ctx
= &brw
->ctx
;
1904 /* BRW_NEW_VIEWPORT_COUNT */
1905 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1907 struct GENX(CC_VIEWPORT
) ccv
;
1908 uint32_t cc_vp_offset
;
1910 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
1913 for (unsigned i
= 0; i
< viewport_count
; i
++) {
1914 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
1915 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
1916 if (ctx
->Transform
.DepthClamp
) {
1917 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
1918 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
1920 ccv
.MinimumDepth
= 0.0;
1921 ccv
.MaximumDepth
= 1.0;
1923 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
1924 cc_map
+= GENX(CC_VIEWPORT_length
);
1928 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1929 ptr
.CCViewportPointer
= cc_vp_offset
;
1932 brw
->cc
.vp_offset
= cc_vp_offset
;
1933 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
1937 const struct brw_tracked_state
genX(cc_vp
) = {
1939 .mesa
= _NEW_TRANSFORM
|
1941 .brw
= BRW_NEW_BATCH
|
1943 BRW_NEW_VIEWPORT_COUNT
,
1945 .emit
= genX(upload_cc_viewport
)
1948 /* ---------------------------------------------------------------------- */
1952 brw_calculate_guardband_size(const struct gen_device_info
*devinfo
,
1953 uint32_t fb_width
, uint32_t fb_height
,
1954 float m00
, float m11
, float m30
, float m31
,
1955 float *xmin
, float *xmax
,
1956 float *ymin
, float *ymax
)
1958 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1959 * Strips and Fans documentation:
1961 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1962 * fixed-point "guardband" range supported by the rasterization hardware"
1966 * "In almost all circumstances, if an object’s vertices are actually
1967 * modified by this clamping (i.e., had X or Y coordinates outside of
1968 * the guardband extent the rendered object will not match the intended
1969 * result. Therefore software should take steps to ensure that this does
1970 * not happen - e.g., by clipping objects such that they do not exceed
1971 * these limits after the Drawing Rectangle is applied."
1973 * I believe the fundamental restriction is that the rasterizer (in
1974 * the SF/WM stages) have a limit on the number of pixels that can be
1975 * rasterized. We need to ensure any coordinates beyond the rasterizer
1976 * limit are handled by the clipper. So effectively that limit becomes
1977 * the clipper's guardband size.
1979 * It goes on to say:
1981 * "In addition, in order to be correctly rendered, objects must have a
1982 * screenspace bounding box not exceeding 8K in the X or Y direction.
1983 * This additional restriction must also be comprehended by software,
1984 * i.e., enforced by use of clipping."
1986 * This makes no sense. Gen7+ hardware supports 16K render targets,
1987 * and you definitely need to be able to draw polygons that fill the
1988 * surface. Our assumption is that the rasterizer was limited to 8K
1989 * on Sandybridge, which only supports 8K surfaces, and it was actually
1990 * increased to 16K on Ivybridge and later.
1992 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1994 const float gb_size
= devinfo
->gen
>= 7 ? 16384.0f
: 8192.0f
;
1996 if (m00
!= 0 && m11
!= 0) {
1997 /* First, we compute the screen-space render area */
1998 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1999 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2000 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2001 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2003 /* We want the guardband to be centered on that */
2004 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2005 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2006 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2007 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2009 /* Now we need it in native device coordinates */
2010 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2011 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2012 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2013 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2015 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2016 * flipped upside-down. X should be fine though.
2018 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2019 *xmin
= ndc_gb_xmin
;
2020 *xmax
= ndc_gb_xmax
;
2021 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2022 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2024 /* The viewport scales to 0, so nothing will be rendered. */
2033 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2035 struct gl_context
*ctx
= &brw
->ctx
;
2036 float y_scale
, y_bias
;
2037 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2039 /* BRW_NEW_VIEWPORT_COUNT */
2040 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2043 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2044 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2045 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2049 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2050 uint32_t sf_clip_vp_offset
;
2051 uint32_t *sf_clip_map
= brw_state_batch(brw
, 16 * 4 * viewport_count
,
2052 64, &sf_clip_vp_offset
);
2054 struct GENX(SF_VIEWPORT
) sfv
;
2055 struct GENX(CLIP_VIEWPORT
) clv
;
2056 uint32_t *sf_map
= brw_state_batch(brw
, 8 * 4 * viewport_count
,
2057 32, &brw
->sf
.vp_offset
);
2058 uint32_t *clip_map
= brw_state_batch(brw
, 4 * 4 * viewport_count
,
2059 32, &brw
->clip
.vp_offset
);
2063 if (render_to_fbo
) {
2068 y_bias
= (float)fb_height
;
2071 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2072 /* _NEW_VIEWPORT: Guardband Clipping */
2073 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2074 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2076 sfv
.ViewportMatrixElementm00
= scale
[0];
2077 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2078 sfv
.ViewportMatrixElementm22
= scale
[2],
2079 sfv
.ViewportMatrixElementm30
= translate
[0],
2080 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2081 sfv
.ViewportMatrixElementm32
= translate
[2],
2082 brw_calculate_guardband_size(devinfo
, fb_width
, fb_height
,
2083 sfv
.ViewportMatrixElementm00
,
2084 sfv
.ViewportMatrixElementm11
,
2085 sfv
.ViewportMatrixElementm30
,
2086 sfv
.ViewportMatrixElementm31
,
2087 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2090 clv
.XMinClipGuardband
= gb_xmin
;
2091 clv
.XMaxClipGuardband
= gb_xmax
;
2092 clv
.YMinClipGuardband
= gb_ymin
;
2093 clv
.YMaxClipGuardband
= gb_ymax
;
2096 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2097 * The hardware will take the intersection of the drawing rectangle,
2098 * scissor rectangle, and the viewport extents. We don't need to be
2099 * smart, and can therefore just program the viewport extents.
2101 const float viewport_Xmax
=
2102 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2103 const float viewport_Ymax
=
2104 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2106 if (render_to_fbo
) {
2107 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2108 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2109 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2110 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2112 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2113 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2114 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2115 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2120 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2123 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2124 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2131 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2132 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2135 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2139 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2141 .mesa
= _NEW_BUFFERS
|
2143 .brw
= BRW_NEW_BATCH
|
2145 BRW_NEW_VIEWPORT_COUNT
,
2147 .emit
= genX(upload_sf_clip_viewport
),
2151 /* ---------------------------------------------------------------------- */
2155 genX(upload_gs_state
)(struct brw_context
*brw
)
2157 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2158 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2159 /* BRW_NEW_GEOMETRY_PROGRAM */
2160 bool active
= brw
->geometry_program
;
2162 /* BRW_NEW_GS_PROG_DATA */
2163 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2164 const struct brw_vue_prog_data
*vue_prog_data
=
2165 brw_vue_prog_data(stage_prog_data
);
2167 const struct brw_gs_prog_data
*gs_prog_data
=
2168 brw_gs_prog_data(stage_prog_data
);
2172 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2173 if (active
&& stage_state
->push_const_size
!= 0) {
2174 cgs
.Buffer0Valid
= true;
2175 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2176 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2181 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2183 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2184 * Geometry > Geometry Shader > State:
2186 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2187 * whole fixed function pipeline when the GS enable changes value in
2190 * The hardware architects have clarified that in this context "flush the
2191 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2194 if (brw
->gt
== 2 && brw
->gs
.enabled
!= active
)
2195 gen7_emit_cs_stall_flush(brw
);
2199 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2200 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2203 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2204 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2205 gs
.ControlDataHeaderSize
=
2206 gs_prog_data
->control_data_header_size_hwords
;
2208 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2209 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2211 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2213 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2216 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2217 * Ivy Bridge and Haswell.
2219 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2220 * strip to be delivered to the geometry shader in an order that does
2221 * not strictly follow the OpenGL spec, but preserves triangle
2222 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2223 * the geometry shader sees triangles:
2225 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2227 * (Clearing the bit is even worse, because it fails to preserve
2230 * Triangle strips with adjacency always ordered in a way that preserves
2231 * triangle orientation but does not strictly follow the OpenGL spec,
2232 * regardless of the setting of this bit.
2234 * On Haswell, both triangle strips and triangle strips with adjacency
2235 * are always ordered in a way that preserves triangle orientation.
2236 * Setting this bit causes the ordering to strictly follow the OpenGL
2239 * So in either case we want to set the bit. Unfortunately on Ivy
2240 * Bridge this will get the order close to correct but not perfect.
2242 gs
.ReorderMode
= TRAILING
;
2243 gs
.MaximumNumberofThreads
=
2244 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2245 : (devinfo
->max_gs_threads
- 1);
2248 gs
.SOStatisticsEnable
= true;
2249 gs
.RenderingEnabled
= 1;
2250 if (brw
->geometry_program
->info
.has_transform_feedback_varyings
)
2251 gs
.SVBIPayloadEnable
= true;
2253 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2254 * was previously done for gen6.
2256 * TODO: test with both disabled to see if the HW is behaving
2257 * as expected, like in gen7.
2259 gs
.SingleProgramFlow
= true;
2260 gs
.VectorMaskEnable
= true;
2264 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2266 if (gs_prog_data
->static_vertex_count
!= -1) {
2267 gs
.StaticOutput
= true;
2268 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2270 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2272 gs
.UserClipDistanceCullTestEnableBitmask
=
2273 vue_prog_data
->cull_distance_mask
;
2275 const int urb_entry_write_offset
= 1;
2276 const uint32_t urb_entry_output_length
=
2277 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2278 urb_entry_write_offset
;
2280 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2281 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2285 } else if (brw
->ff_gs
.prog_active
) {
2286 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
2287 * program. This function provides the needed 3DSTATE_GS for this.
2289 upload_gs_state_for_tf(brw
);
2292 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2293 gs
.StatisticsEnable
= true;
2295 gs
.RenderingEnabled
= true;
2299 gs
.DispatchGRFStartRegisterForURBData
= 1;
2301 gs
.IncludeVertexHandles
= true;
2307 brw
->gs
.enabled
= active
;
2311 static const struct brw_tracked_state
genX(gs_state
) = {
2313 .mesa
= (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
2314 .brw
= BRW_NEW_BATCH
|
2317 BRW_NEW_GEOMETRY_PROGRAM
|
2318 BRW_NEW_GS_PROG_DATA
|
2319 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2321 .emit
= genX(upload_gs_state
),
2325 /* ---------------------------------------------------------------------- */
2327 #define blend_factor(x) brw_translate_blend_factor(x)
2328 #define blend_eqn(x) brw_translate_blend_equation(x)
2332 genX(upload_blend_state
)(struct brw_context
*brw
)
2334 struct gl_context
*ctx
= &brw
->ctx
;
2337 /* We need at least one BLEND_STATE written, because we might do
2338 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2339 * for computed depth or alpha test), which will do an FB write
2340 * with render target 0, which will reference BLEND_STATE[0] for
2341 * alpha test enable.
2343 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2344 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2345 nr_draw_buffers
= 1;
2347 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2349 size
+= GENX(BLEND_STATE_length
) * 4;
2352 uint32_t *blend_map
;
2353 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2356 struct GENX(BLEND_STATE
) blend
= { 0 };
2359 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2360 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2363 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2364 * "If drawbuffer zero is not NONE and the buffer it references has an
2365 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2366 * operations are skipped."
2368 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2369 /* _NEW_MULTISAMPLE */
2370 if (_mesa_is_multisample_enabled(ctx
)) {
2371 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2372 blend
.AlphaToCoverageEnable
= true;
2373 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2375 if (ctx
->Multisample
.SampleAlphaToOne
)
2376 blend
.AlphaToOneEnable
= true;
2380 if (ctx
->Color
.AlphaEnabled
) {
2381 blend
.AlphaTestEnable
= true;
2382 blend
.AlphaTestFunction
=
2383 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2386 if (ctx
->Color
.DitherFlag
) {
2387 blend
.ColorDitherEnable
= true;
2392 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2393 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2399 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2401 /* Used for implementing the following bit of GL_EXT_texture_integer:
2402 * "Per-fragment operations that require floating-point color
2403 * components, including multisample alpha operations, alpha test,
2404 * blending, and dithering, have no effect when the corresponding
2405 * colors are written to an integer color buffer."
2407 bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2410 if (ctx
->Color
.ColorLogicOpEnabled
) {
2411 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2412 : GL_UNSIGNED_NORMALIZED
;
2413 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2414 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2415 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2417 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2418 _mesa_enum_to_string(rb_type
));
2419 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2420 entry
.LogicOpEnable
= true;
2421 entry
.LogicOpFunction
=
2422 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2424 } else if (ctx
->Color
.BlendEnabled
& (1 << i
) && !integer
&&
2425 !ctx
->Color
._AdvancedBlendMode
) {
2426 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2427 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2428 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2429 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2430 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2431 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2433 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2434 srcRGB
= dstRGB
= GL_ONE
;
2436 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2437 srcA
= dstA
= GL_ONE
;
2439 /* Due to hardware limitations, the destination may have information
2440 * in an alpha channel even when the format specifies no alpha
2441 * channel. In order to avoid getting any incorrect blending due to
2442 * that alpha channel, coerce the blend factors to values that will
2443 * not read the alpha channel, but will instead use the correct
2444 * implicit value for alpha.
2446 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2447 GL_TEXTURE_ALPHA_TYPE
)) {
2448 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2449 srcA
= brw_fix_xRGB_alpha(srcA
);
2450 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2451 dstA
= brw_fix_xRGB_alpha(dstA
);
2454 entry
.ColorBufferBlendEnable
= true;
2455 entry
.DestinationBlendFactor
= blend_factor(dstRGB
);
2456 entry
.SourceBlendFactor
= blend_factor(srcRGB
);
2457 entry
.DestinationAlphaBlendFactor
= blend_factor(dstA
);
2458 entry
.SourceAlphaBlendFactor
= blend_factor(srcA
);
2459 entry
.ColorBlendFunction
= blend_eqn(eqRGB
);
2460 entry
.AlphaBlendFunction
= blend_eqn(eqA
);
2462 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2463 blend
.IndependentAlphaBlendEnable
= true;
2466 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2467 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2469 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2470 * clamping in the fragment shader. For its clamping of
2471 * blending, the spec says:
2473 * "RESOLVED: For fixed-point color buffers, the inputs and
2474 * the result of the blending equation are clamped. For
2475 * floating-point color buffers, no clamping occurs."
2477 * So, generally, we want clamping to the render target's range.
2478 * And, good news, the hardware tables for both pre- and
2479 * post-blend color clamping are either ignored, or any are
2480 * allowed, or clamping is required but RT range clamping is a
2483 entry
.PreBlendColorClampEnable
= true;
2484 entry
.PostBlendColorClampEnable
= true;
2485 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2487 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2488 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2489 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2490 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2492 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2493 * "If Dual Source Blending is enabled, this bit must be disabled."
2495 WARN_ONCE(ctx
->Color
.Blend
[i
]._UsesDualSrc
&&
2496 _mesa_is_multisample_enabled(ctx
) &&
2497 ctx
->Multisample
.SampleAlphaToOne
,
2498 "HW workaround: disabling alpha to one with dual src "
2500 if (ctx
->Color
.Blend
[i
]._UsesDualSrc
)
2501 blend
.AlphaToOneEnable
= false;
2503 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2505 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2511 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2515 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2516 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2517 ptr
.BLEND_STATEChange
= true;
2520 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2521 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2523 ptr
.BlendStatePointerValid
= true;
2529 static const struct brw_tracked_state
genX(blend_state
) = {
2531 .mesa
= _NEW_BUFFERS
|
2534 .brw
= BRW_NEW_BATCH
|
2536 BRW_NEW_STATE_BASE_ADDRESS
,
2538 .emit
= genX(upload_blend_state
),
2542 /* ---------------------------------------------------------------------- */
2546 genX(upload_scissor_state
)(struct brw_context
*brw
)
2548 struct gl_context
*ctx
= &brw
->ctx
;
2549 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2550 struct GENX(SCISSOR_RECT
) scissor
;
2551 uint32_t scissor_state_offset
;
2552 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2553 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2554 uint32_t *scissor_map
;
2556 /* BRW_NEW_VIEWPORT_COUNT */
2557 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2559 scissor_map
= brw_state_batch(
2560 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2561 32, &scissor_state_offset
);
2563 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2565 /* The scissor only needs to handle the intersection of drawable and
2566 * scissor rect. Clipping to the boundaries of static shared buffers
2567 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2569 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2570 * inclusive but max is exclusive.
2572 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2575 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2576 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2577 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2578 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2579 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2581 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2582 /* If the scissor was out of bounds and got clamped to 0 width/height
2583 * at the bounds, the subtraction of 1 from maximums could produce a
2584 * negative number and thus not clip anything. Instead, just provide
2585 * a min > max scissor inside the bounds, which produces the expected
2588 scissor
.ScissorRectangleXMin
= 1;
2589 scissor
.ScissorRectangleXMax
= 0;
2590 scissor
.ScissorRectangleYMin
= 1;
2591 scissor
.ScissorRectangleYMax
= 0;
2592 } else if (render_to_fbo
) {
2593 /* texmemory: Y=0=bottom */
2594 scissor
.ScissorRectangleXMin
= bbox
[0];
2595 scissor
.ScissorRectangleXMax
= bbox
[1] - 1;
2596 scissor
.ScissorRectangleYMin
= bbox
[2];
2597 scissor
.ScissorRectangleYMax
= bbox
[3] - 1;
2599 /* memory: Y=0=top */
2600 scissor
.ScissorRectangleXMin
= bbox
[0];
2601 scissor
.ScissorRectangleXMax
= bbox
[1] - 1;
2602 scissor
.ScissorRectangleYMin
= fb_height
- bbox
[3];
2603 scissor
.ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2606 GENX(SCISSOR_RECT_pack
)(
2607 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2610 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2611 ptr
.ScissorRectPointer
= scissor_state_offset
;
2615 static const struct brw_tracked_state
genX(scissor_state
) = {
2617 .mesa
= _NEW_BUFFERS
|
2620 .brw
= BRW_NEW_BATCH
|
2622 BRW_NEW_VIEWPORT_COUNT
,
2624 .emit
= genX(upload_scissor_state
),
2628 /* ---------------------------------------------------------------------- */
2631 UNUSED
static const uint32_t push_constant_opcodes
[] = {
2632 [MESA_SHADER_VERTEX
] = 21,
2633 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2634 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2635 [MESA_SHADER_GEOMETRY
] = 22,
2636 [MESA_SHADER_FRAGMENT
] = 23,
2637 [MESA_SHADER_COMPUTE
] = 0,
2641 upload_constant_state(struct brw_context
*brw
,
2642 struct brw_stage_state
*stage_state
,
2643 bool active
, uint32_t stage
)
2645 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
2646 active
= active
&& stage_state
->push_const_size
!= 0;
2648 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2649 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2651 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2652 pkt
.ConstantBody
.ConstantBuffer2ReadLength
=
2653 stage_state
->push_const_size
;
2654 pkt
.ConstantBody
.PointerToConstantBuffer2
=
2655 render_ro_bo(brw
->curbe
.curbe_bo
, stage_state
->push_const_offset
);
2657 pkt
.ConstantBody
.ConstantBuffer0ReadLength
=
2658 stage_state
->push_const_size
;
2659 pkt
.ConstantBody
.PointerToConstantBuffer0
.offset
=
2660 stage_state
->push_const_offset
| mocs
;
2665 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
2671 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
2673 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2675 /* _BRW_NEW_VERTEX_PROGRAM */
2676 const struct brw_program
*vp
= brw_program_const(brw
->vertex_program
);
2677 /* BRW_NEW_VS_PROG_DATA */
2678 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
2680 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
2681 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
2684 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !brw
->is_baytrail
)
2685 gen7_emit_vs_workaround_flush(brw
);
2687 upload_constant_state(brw
, stage_state
, true /* active */,
2688 MESA_SHADER_VERTEX
);
2692 static const struct brw_tracked_state
genX(vs_push_constants
) = {
2694 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2696 .brw
= BRW_NEW_BATCH
|
2698 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2699 BRW_NEW_VERTEX_PROGRAM
|
2700 BRW_NEW_VS_PROG_DATA
,
2702 .emit
= genX(upload_vs_push_constants
),
2706 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
2708 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2710 /* BRW_NEW_GEOMETRY_PROGRAM */
2711 const struct brw_program
*gp
= brw_program_const(brw
->geometry_program
);
2714 /* BRW_NEW_GS_PROG_DATA */
2715 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
2717 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
2718 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
2722 upload_constant_state(brw
, stage_state
, gp
, MESA_SHADER_GEOMETRY
);
2726 static const struct brw_tracked_state
genX(gs_push_constants
) = {
2728 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2730 .brw
= BRW_NEW_BATCH
|
2732 BRW_NEW_GEOMETRY_PROGRAM
|
2733 BRW_NEW_GS_PROG_DATA
|
2734 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2736 .emit
= genX(upload_gs_push_constants
),
2740 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
2742 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
2743 /* BRW_NEW_FRAGMENT_PROGRAM */
2744 const struct brw_program
*fp
= brw_program_const(brw
->fragment_program
);
2745 /* BRW_NEW_FS_PROG_DATA */
2746 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
2748 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
2750 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
2753 upload_constant_state(brw
, stage_state
, true, MESA_SHADER_FRAGMENT
);
2757 static const struct brw_tracked_state
genX(wm_push_constants
) = {
2759 .mesa
= _NEW_PROGRAM_CONSTANTS
,
2760 .brw
= BRW_NEW_BATCH
|
2762 BRW_NEW_FRAGMENT_PROGRAM
|
2763 BRW_NEW_FS_PROG_DATA
|
2764 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2766 .emit
= genX(upload_wm_push_constants
),
2770 /* ---------------------------------------------------------------------- */
2774 genX(determine_sample_mask
)(struct brw_context
*brw
)
2776 struct gl_context
*ctx
= &brw
->ctx
;
2777 float coverage
= 1.0f
;
2778 float coverage_invert
= false;
2779 unsigned sample_mask
= ~0u;
2781 /* BRW_NEW_NUM_SAMPLES */
2782 unsigned num_samples
= brw
->num_samples
;
2784 if (_mesa_is_multisample_enabled(ctx
)) {
2785 if (ctx
->Multisample
.SampleCoverage
) {
2786 coverage
= ctx
->Multisample
.SampleCoverageValue
;
2787 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
2789 if (ctx
->Multisample
.SampleMask
) {
2790 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
2794 if (num_samples
> 1) {
2795 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
2796 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
2797 if (coverage_invert
)
2798 coverage_bits
^= (1 << num_samples
) - 1;
2799 return coverage_bits
& sample_mask
;
2806 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
2807 unsigned num_samples
)
2809 assert(brw
->num_samples
<= 16);
2811 unsigned log2_samples
= ffs(MAX2(num_samples
, 1)) - 1;
2813 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
2814 multi
.PixelLocation
= CENTER
;
2815 multi
.NumberofMultisamples
= log2_samples
;
2817 GEN_SAMPLE_POS_4X(multi
.Sample
);
2819 switch (num_samples
) {
2821 GEN_SAMPLE_POS_1X(multi
.Sample
);
2824 GEN_SAMPLE_POS_2X(multi
.Sample
);
2827 GEN_SAMPLE_POS_4X(multi
.Sample
);
2830 GEN_SAMPLE_POS_8X(multi
.Sample
);
2840 genX(upload_multisample_state
)(struct brw_context
*brw
)
2842 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
2844 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
2845 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
2849 static const struct brw_tracked_state
genX(multisample_state
) = {
2851 .mesa
= _NEW_MULTISAMPLE
,
2852 .brw
= BRW_NEW_BLORP
|
2854 BRW_NEW_NUM_SAMPLES
,
2856 .emit
= genX(upload_multisample_state
)
2860 /* ---------------------------------------------------------------------- */
2864 genX(upload_color_calc_state
)(struct brw_context
*brw
)
2866 struct gl_context
*ctx
= &brw
->ctx
;
2868 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
2870 cc
.AlphaTestFormat
= ALPHATEST_UNORM8
;
2871 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
2872 ctx
->Color
.AlphaRef
);
2876 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
2877 cc
.BackfaceStencilReferenceValue
=
2878 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
2882 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
2883 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
2884 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
2885 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
2888 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2889 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
2891 ptr
.ColorCalcStatePointerValid
= true;
2896 static const struct brw_tracked_state
genX(color_calc_state
) = {
2898 .mesa
= _NEW_COLOR
|
2900 .brw
= BRW_NEW_BATCH
|
2903 BRW_NEW_STATE_BASE_ADDRESS
,
2905 .emit
= genX(upload_color_calc_state
),
2910 /* ---------------------------------------------------------------------- */
2914 genX(upload_sbe
)(struct brw_context
*brw
)
2916 struct gl_context
*ctx
= &brw
->ctx
;
2917 /* BRW_NEW_FS_PROG_DATA */
2918 const struct brw_wm_prog_data
*wm_prog_data
=
2919 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
2921 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
2923 #define attr_overrides sbe.Attribute
2925 uint32_t urb_entry_read_length
;
2926 uint32_t urb_entry_read_offset
;
2927 uint32_t point_sprite_enables
;
2929 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
2930 sbe
.AttributeSwizzleEnable
= true;
2931 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2934 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2938 * Window coordinates in an FBO are inverted, which means point
2939 * sprite origin must be inverted.
2941 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
2942 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
2944 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
2946 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
2947 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
2948 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
2949 * BRW_NEW_VUE_MAP_GEOM_OUT
2951 genX(calculate_attr_overrides
)(brw
,
2953 &point_sprite_enables
,
2954 &urb_entry_read_length
,
2955 &urb_entry_read_offset
);
2957 /* Typically, the URB entry read length and offset should be programmed
2958 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
2959 * stage which produces geometry. However, we don't know the proper
2960 * value until we call calculate_attr_overrides().
2962 * To fit with our existing code, we override the inherited values and
2963 * specify it here directly, as we did on previous generations.
2965 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
2966 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
2967 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
2968 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2971 sbe
.ForceVertexURBEntryReadLength
= true;
2972 sbe
.ForceVertexURBEntryReadOffset
= true;
2976 /* prepare the active component dwords */
2977 int input_index
= 0;
2978 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
2979 if (!(brw
->fragment_program
->info
.inputs_read
&
2980 BITFIELD64_BIT(attr
))) {
2984 assert(input_index
< 32);
2986 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
2993 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2994 for (int i
= 0; i
< 16; i
++)
2995 sbes
.Attribute
[i
] = attr_overrides
[i
];
2999 #undef attr_overrides
3002 static const struct brw_tracked_state
genX(sbe_state
) = {
3004 .mesa
= _NEW_BUFFERS
|
3009 .brw
= BRW_NEW_BLORP
|
3011 BRW_NEW_FRAGMENT_PROGRAM
|
3012 BRW_NEW_FS_PROG_DATA
|
3013 BRW_NEW_GS_PROG_DATA
|
3014 BRW_NEW_TES_PROG_DATA
|
3015 BRW_NEW_VUE_MAP_GEOM_OUT
|
3016 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3019 .emit
= genX(upload_sbe
),
3023 /* ---------------------------------------------------------------------- */
3027 * Outputs the 3DSTATE_SO_DECL_LIST command.
3029 * The data output is a series of 64-bit entries containing a SO_DECL per
3030 * stream. We only have one stream of rendering coming out of the GS unit, so
3031 * we only emit stream 0 (low 16 bits) SO_DECLs.
3034 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3035 const struct brw_vue_map
*vue_map
)
3037 struct gl_context
*ctx
= &brw
->ctx
;
3038 /* BRW_NEW_TRANSFORM_FEEDBACK */
3039 struct gl_transform_feedback_object
*xfb_obj
=
3040 ctx
->TransformFeedback
.CurrentObject
;
3041 const struct gl_transform_feedback_info
*linked_xfb_info
=
3042 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3043 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3044 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3045 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3046 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3048 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3050 memset(so_decl
, 0, sizeof(so_decl
));
3052 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3053 * command feels strange -- each dword pair contains a SO_DECL per stream.
3055 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3056 int buffer
= linked_xfb_info
->Outputs
[i
].OutputBuffer
;
3057 struct GENX(SO_DECL
) decl
= {0};
3058 int varying
= linked_xfb_info
->Outputs
[i
].OutputRegister
;
3059 const unsigned components
= linked_xfb_info
->Outputs
[i
].NumComponents
;
3060 unsigned component_mask
= (1 << components
) - 1;
3061 unsigned stream_id
= linked_xfb_info
->Outputs
[i
].StreamId
;
3062 unsigned decl_buffer_slot
= buffer
;
3063 assert(stream_id
< MAX_VERTEX_STREAMS
);
3065 /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w
3066 * gl_Layer is stored in VARYING_SLOT_PSIZ.y
3067 * gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
3069 if (varying
== VARYING_SLOT_PSIZ
) {
3070 assert(components
== 1);
3071 component_mask
<<= 3;
3072 } else if (varying
== VARYING_SLOT_LAYER
) {
3073 assert(components
== 1);
3074 component_mask
<<= 1;
3075 } else if (varying
== VARYING_SLOT_VIEWPORT
) {
3076 assert(components
== 1);
3077 component_mask
<<= 2;
3079 component_mask
<<= linked_xfb_info
->Outputs
[i
].ComponentOffset
;
3082 buffer_mask
[stream_id
] |= 1 << buffer
;
3084 decl
.OutputBufferSlot
= decl_buffer_slot
;
3085 if (varying
== VARYING_SLOT_LAYER
|| varying
== VARYING_SLOT_VIEWPORT
) {
3086 decl
.RegisterIndex
= vue_map
->varying_to_slot
[VARYING_SLOT_PSIZ
];
3088 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3089 decl
.RegisterIndex
= vue_map
->varying_to_slot
[varying
];
3091 decl
.ComponentMask
= component_mask
;
3093 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3094 * array. Instead, it simply increments DstOffset for the following
3095 * input by the number of components that should be skipped.
3097 * Our hardware is unusual in that it requires us to program SO_DECLs
3098 * for fake "hole" components, rather than simply taking the offset
3099 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3100 * program as many size = 4 holes as we can, then a final hole to
3101 * accommodate the final 1, 2, or 3 remaining.
3103 int skip_components
=
3104 linked_xfb_info
->Outputs
[i
].DstOffset
- next_offset
[buffer
];
3106 next_offset
[buffer
] += skip_components
;
3108 while (skip_components
>= 4) {
3109 struct GENX(SO_DECL
) *d
= &so_decl
[stream_id
][decls
[stream_id
]++];
3111 d
->OutputBufferSlot
= decl_buffer_slot
;
3112 d
->ComponentMask
= 0xf;
3113 skip_components
-= 4;
3116 if (skip_components
> 0) {
3117 struct GENX(SO_DECL
) *d
= &so_decl
[stream_id
][decls
[stream_id
]++];
3119 d
->OutputBufferSlot
= decl_buffer_slot
;
3120 d
->ComponentMask
= (1 << skip_components
) - 1;
3123 assert(linked_xfb_info
->Outputs
[i
].DstOffset
== next_offset
[buffer
]);
3125 next_offset
[buffer
] += components
;
3127 so_decl
[stream_id
][decls
[stream_id
]++] = decl
;
3129 if (decls
[stream_id
] > max_decls
)
3130 max_decls
= decls
[stream_id
];
3134 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3135 .StreamtoBufferSelects0
= buffer_mask
[0],
3136 .StreamtoBufferSelects1
= buffer_mask
[1],
3137 .StreamtoBufferSelects2
= buffer_mask
[2],
3138 .StreamtoBufferSelects3
= buffer_mask
[3],
3139 .NumEntries0
= decls
[0],
3140 .NumEntries1
= decls
[1],
3141 .NumEntries2
= decls
[2],
3142 .NumEntries3
= decls
[3]);
3144 for (int i
= 0; i
< max_decls
; i
++) {
3145 GENX(SO_DECL_ENTRY_pack
)(
3146 brw
, dw
+ 2 + i
* 2,
3147 &(struct GENX(SO_DECL_ENTRY
)) {
3148 .Stream0Decl
= so_decl
[0][i
],
3149 .Stream1Decl
= so_decl
[1][i
],
3150 .Stream2Decl
= so_decl
[2][i
],
3151 .Stream3Decl
= so_decl
[3][i
],
3157 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3159 struct gl_context
*ctx
= &brw
->ctx
;
3160 /* BRW_NEW_TRANSFORM_FEEDBACK */
3161 struct gl_transform_feedback_object
*xfb_obj
=
3162 ctx
->TransformFeedback
.CurrentObject
;
3164 const struct gl_transform_feedback_info
*linked_xfb_info
=
3165 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3167 struct brw_transform_feedback_object
*brw_obj
=
3168 (struct brw_transform_feedback_object
*) xfb_obj
;
3169 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3172 /* Set up the up to 4 output buffers. These are the ranges defined in the
3173 * gl_transform_feedback_object.
3175 for (int i
= 0; i
< 4; i
++) {
3176 struct intel_buffer_object
*bufferobj
=
3177 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3180 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3181 sob
.SOBufferIndex
= i
;
3186 uint32_t start
= xfb_obj
->Offset
[i
];
3187 assert(start
% 4 == 0);
3188 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3190 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
);
3191 assert(end
<= bo
->size
);
3193 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3194 sob
.SOBufferIndex
= i
;
3196 sob
.SurfaceBaseAddress
= render_bo(bo
, start
);
3198 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3199 sob
.SurfaceEndAddress
= render_bo(bo
, end
);
3201 sob
.SOBufferEnable
= true;
3202 sob
.StreamOffsetWriteEnable
= true;
3203 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3204 sob
.SOBufferMOCS
= mocs_wb
;
3206 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3207 sob
.StreamOutputBufferOffsetAddress
=
3208 instruction_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3210 if (brw_obj
->zero_offsets
) {
3211 /* Zero out the offset and write that to offset_bo */
3212 sob
.StreamOffset
= 0;
3214 /* Use offset_bo as the "Stream Offset." */
3215 sob
.StreamOffset
= 0xFFFFFFFF;
3222 brw_obj
->zero_offsets
= false;
3227 query_active(struct gl_query_object
*q
)
3229 return q
&& q
->Active
;
3233 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3234 const struct brw_vue_map
*vue_map
)
3236 struct gl_context
*ctx
= &brw
->ctx
;
3237 /* BRW_NEW_TRANSFORM_FEEDBACK */
3238 struct gl_transform_feedback_object
*xfb_obj
=
3239 ctx
->TransformFeedback
.CurrentObject
;
3241 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3243 int urb_entry_read_offset
= 0;
3244 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3245 urb_entry_read_offset
;
3247 sos
.SOFunctionEnable
= true;
3248 sos
.SOStatisticsEnable
= true;
3250 /* BRW_NEW_RASTERIZER_DISCARD */
3251 if (ctx
->RasterDiscard
) {
3252 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3253 sos
.RenderingDisable
= true;
3255 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3256 "query active relies on the clipper.");
3261 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3262 sos
.ReorderMode
= TRAILING
;
3265 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3266 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3267 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3268 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3270 const struct gl_transform_feedback_info
*linked_xfb_info
=
3271 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3272 /* Set buffer pitches; 0 means unbound. */
3273 if (xfb_obj
->Buffers
[0])
3274 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3275 if (xfb_obj
->Buffers
[1])
3276 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3277 if (xfb_obj
->Buffers
[2])
3278 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3279 if (xfb_obj
->Buffers
[3])
3280 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3283 /* We always read the whole vertex. This could be reduced at some
3284 * point by reading less and offsetting the register index in the
3287 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3288 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3289 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3290 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3291 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3292 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3293 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3294 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3300 genX(upload_sol
)(struct brw_context
*brw
)
3302 struct gl_context
*ctx
= &brw
->ctx
;
3303 /* BRW_NEW_TRANSFORM_FEEDBACK */
3304 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3307 genX(upload_3dstate_so_buffers
)(brw
);
3309 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3310 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3313 /* Finally, set up the SOL stage. This command must always follow updates to
3314 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3315 * MMIO register updates (current performed by the kernel at each batch
3318 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3321 static const struct brw_tracked_state
genX(sol_state
) = {
3324 .brw
= BRW_NEW_BATCH
|
3326 BRW_NEW_RASTERIZER_DISCARD
|
3327 BRW_NEW_VUE_MAP_GEOM_OUT
|
3328 BRW_NEW_TRANSFORM_FEEDBACK
,
3330 .emit
= genX(upload_sol
),
3334 /* ---------------------------------------------------------------------- */
3338 genX(upload_ps
)(struct brw_context
*brw
)
3340 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3341 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3343 /* BRW_NEW_FS_PROG_DATA */
3344 const struct brw_wm_prog_data
*prog_data
=
3345 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3346 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3351 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3352 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3353 * incorrect for subspans where some of the pixels are unlit. We believe
3354 * the bit just didn't take effect in previous generations.
3356 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3359 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3361 /* BRW_NEW_FS_PROG_DATA */
3362 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3364 if (prog_data
->base
.use_alt_mode
)
3365 ps
.FloatingPointMode
= Alternate
;
3367 /* Haswell requires the sample mask to be set in this packet as well as
3368 * in 3DSTATE_SAMPLE_MASK; the values should match.
3371 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3373 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3376 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3377 * it implicitly scales for different GT levels (which have some # of
3380 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3383 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3385 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3387 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3390 if (prog_data
->base
.nr_params
> 0)
3391 ps
.PushConstantEnable
= true;
3394 /* From the IVB PRM, volume 2 part 1, page 287:
3395 * "This bit is inserted in the PS payload header and made available to
3396 * the DataPort (either via the message header or via header bypass) to
3397 * indicate that oMask data (one or two phases) is included in Render
3398 * Target Write messages. If present, the oMask data is used to mask off
3401 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3403 /* The hardware wedges if you have this bit set but don't turn on any
3404 * dual source blend factors.
3406 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3408 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3409 (ctx
->Color
.BlendEnabled
& 1) &&
3410 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3412 /* BRW_NEW_FS_PROG_DATA */
3413 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3416 /* From the documentation for this packet:
3417 * "If the PS kernel does not need the Position XY Offsets to
3418 * compute a Position Value, then this field should be programmed
3419 * to POSOFFSET_NONE."
3421 * "SW Recommendation: If the PS kernel needs the Position Offsets
3422 * to compute a Position XY value, this field should match Position
3423 * ZW Interpolation Mode to ensure a consistent position.xyzw
3426 * We only require XY sample offsets. So, this recommendation doesn't
3427 * look useful at the moment. We might need this in future.
3429 if (prog_data
->uses_pos_offset
)
3430 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3432 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3434 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3435 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3436 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3437 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3438 prog_data
->base
.dispatch_grf_start_reg
;
3439 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3440 prog_data
->dispatch_grf_start_reg_2
;
3442 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3443 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3444 prog_data
->prog_offset_2
;
3446 if (prog_data
->base
.total_scratch
) {
3447 ps
.ScratchSpaceBasePointer
=
3448 render_bo(stage_state
->scratch_bo
,
3449 ffs(stage_state
->per_thread_scratch
) - 11);
3454 static const struct brw_tracked_state
genX(ps_state
) = {
3456 .mesa
= _NEW_MULTISAMPLE
|
3457 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3460 .brw
= BRW_NEW_BATCH
|
3462 BRW_NEW_FS_PROG_DATA
,
3464 .emit
= genX(upload_ps
),
3468 /* ---------------------------------------------------------------------- */
3472 genX(upload_hs_state
)(struct brw_context
*brw
)
3474 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3475 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3476 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3477 const struct brw_vue_prog_data
*vue_prog_data
=
3478 brw_vue_prog_data(stage_prog_data
);
3480 /* BRW_NEW_TES_PROG_DATA */
3481 struct brw_tcs_prog_data
*tcs_prog_data
=
3482 brw_tcs_prog_data(stage_prog_data
);
3484 if (!tcs_prog_data
) {
3485 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3487 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3488 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3490 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3491 hs
.IncludeVertexHandles
= true;
3493 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3498 static const struct brw_tracked_state
genX(hs_state
) = {
3501 .brw
= BRW_NEW_BATCH
|
3503 BRW_NEW_TCS_PROG_DATA
|
3504 BRW_NEW_TESS_PROGRAMS
,
3506 .emit
= genX(upload_hs_state
),
3510 genX(upload_ds_state
)(struct brw_context
*brw
)
3512 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3513 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3514 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3516 /* BRW_NEW_TES_PROG_DATA */
3517 const struct brw_tes_prog_data
*tes_prog_data
=
3518 brw_tes_prog_data(stage_prog_data
);
3519 const struct brw_vue_prog_data
*vue_prog_data
=
3520 brw_vue_prog_data(stage_prog_data
);
3522 if (!tes_prog_data
) {
3523 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3525 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3526 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3528 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3529 ds
.ComputeWCoordinateEnable
=
3530 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3533 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3534 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3535 ds
.UserClipDistanceCullTestEnableBitmask
=
3536 vue_prog_data
->cull_distance_mask
;
3542 static const struct brw_tracked_state
genX(ds_state
) = {
3545 .brw
= BRW_NEW_BATCH
|
3547 BRW_NEW_TESS_PROGRAMS
|
3548 BRW_NEW_TES_PROG_DATA
,
3550 .emit
= genX(upload_ds_state
),
3553 /* ---------------------------------------------------------------------- */
3556 upload_te_state(struct brw_context
*brw
)
3558 /* BRW_NEW_TESS_PROGRAMS */
3559 bool active
= brw
->tess_eval_program
;
3561 /* BRW_NEW_TES_PROG_DATA */
3562 const struct brw_tes_prog_data
*tes_prog_data
=
3563 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
3566 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
3567 te
.Partitioning
= tes_prog_data
->partitioning
;
3568 te
.OutputTopology
= tes_prog_data
->output_topology
;
3569 te
.TEDomain
= tes_prog_data
->domain
;
3571 te
.MaximumTessellationFactorOdd
= 63.0;
3572 te
.MaximumTessellationFactorNotOdd
= 64.0;
3575 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
3579 static const struct brw_tracked_state
genX(te_state
) = {
3582 .brw
= BRW_NEW_BLORP
|
3584 BRW_NEW_TES_PROG_DATA
|
3585 BRW_NEW_TESS_PROGRAMS
,
3587 .emit
= upload_te_state
,
3590 /* ---------------------------------------------------------------------- */
3593 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
3595 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3596 /* BRW_NEW_TESS_PROGRAMS */
3597 const struct brw_program
*tep
= brw_program_const(brw
->tess_eval_program
);
3600 /* BRW_NEW_TES_PROG_DATA */
3601 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
3602 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
3603 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
3606 upload_constant_state(brw
, stage_state
, tep
, MESA_SHADER_TESS_EVAL
);
3609 static const struct brw_tracked_state
genX(tes_push_constants
) = {
3611 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3612 .brw
= BRW_NEW_BATCH
|
3614 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3615 BRW_NEW_TESS_PROGRAMS
|
3616 BRW_NEW_TES_PROG_DATA
,
3618 .emit
= genX(upload_tes_push_constants
),
3622 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
3624 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3625 /* BRW_NEW_TESS_PROGRAMS */
3626 const struct brw_program
*tcp
= brw_program_const(brw
->tess_ctrl_program
);
3627 bool active
= brw
->tess_eval_program
;
3630 /* BRW_NEW_TCS_PROG_DATA */
3631 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
3633 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
3634 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
3637 upload_constant_state(brw
, stage_state
, active
, MESA_SHADER_TESS_CTRL
);
3640 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
3642 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3643 .brw
= BRW_NEW_BATCH
|
3645 BRW_NEW_DEFAULT_TESS_LEVELS
|
3646 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3647 BRW_NEW_TESS_PROGRAMS
|
3648 BRW_NEW_TCS_PROG_DATA
,
3650 .emit
= genX(upload_tcs_push_constants
),
3655 /* ---------------------------------------------------------------------- */
3659 genX(upload_cs_state
)(struct brw_context
*brw
)
3661 if (!brw
->cs
.base
.prog_data
)
3665 uint32_t *desc
= (uint32_t*) brw_state_batch(
3666 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
3669 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
3670 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
3671 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3672 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3674 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
3675 brw_emit_buffer_surface_state(
3676 brw
, &stage_state
->surf_offset
[
3677 prog_data
->binding_table
.shader_time_start
],
3678 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
3679 brw
->shader_time
.bo
->size
, 1, true);
3682 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
3683 32, &stage_state
->bind_bo_offset
);
3685 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
3686 if (prog_data
->total_scratch
) {
3690 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
3691 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
3693 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 11;
3694 } else if (GEN_IS_HASWELL
) {
3695 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
3696 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
3698 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 12;
3700 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
3701 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
3703 bo_offset
= stage_state
->per_thread_scratch
/ 1024 - 1;
3705 vfe
.ScratchSpaceBasePointer
=
3706 render_bo(stage_state
->scratch_bo
, bo_offset
);
3709 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
3710 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
3711 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;;
3712 vfe
.ResetGatewayTimer
=
3713 Resettingrelativetimerandlatchingtheglobaltimestamp
;
3715 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
3721 /* We are uploading duplicated copies of push constant uniforms for each
3722 * thread. Although the local id data needs to vary per thread, it won't
3723 * change for other uniform data. Unfortunately this duplication is
3724 * required for gen7. As of Haswell, this duplication can be avoided,
3725 * but this older mechanism with duplicated data continues to work.
3727 * FINISHME: As of Haswell, we could make use of the
3728 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
3729 * field to only store one copy of uniform data.
3731 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
3732 * which is described in the GPGPU_WALKER command and in the Broadwell
3733 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
3734 * Operations => GPGPU Mode => Indirect Payload Storage.
3736 * Note: The constant data is built in brw_upload_cs_push_constants
3739 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
3741 const uint32_t vfe_curbe_allocation
=
3742 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
3743 cs_prog_data
->push
.cross_thread
.regs
, 2);
3744 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
3747 if (cs_prog_data
->push
.total
.size
> 0) {
3748 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3749 curbe
.CURBETotalDataLength
=
3750 ALIGN(cs_prog_data
->push
.total
.size
, 64);
3751 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
3755 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
3756 memcpy(bind
, stage_state
->surf_offset
,
3757 prog_data
->binding_table
.size_bytes
);
3758 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
3759 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
3760 .SamplerStatePointer
= stage_state
->sampler_offset
,
3761 .SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4) >> 2,
3762 .BindingTablePointer
= stage_state
->bind_bo_offset
,
3763 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
3764 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
3765 .SharedLocalMemorySize
= encode_slm_size(devinfo
->gen
,
3766 prog_data
->total_shared
),
3767 .BarrierEnable
= cs_prog_data
->uses_barrier
,
3768 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3769 .CrossThreadConstantDataReadLength
=
3770 cs_prog_data
->push
.cross_thread
.regs
,
3774 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
3776 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
3777 load
.InterfaceDescriptorTotalLength
=
3778 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3779 load
.InterfaceDescriptorDataStartAddress
= offset
;
3783 static const struct brw_tracked_state
genX(cs_state
) = {
3785 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3786 .brw
= BRW_NEW_BATCH
|
3788 BRW_NEW_CS_PROG_DATA
|
3789 BRW_NEW_SAMPLER_STATE_TABLE
|
3792 .emit
= genX(upload_cs_state
)
3797 /* ---------------------------------------------------------------------- */
3801 genX(upload_raster
)(struct brw_context
*brw
)
3803 struct gl_context
*ctx
= &brw
->ctx
;
3806 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3809 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
3812 struct gl_point_attrib
*point
= &ctx
->Point
;
3814 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
3815 if (polygon
->_FrontBit
== render_to_fbo
)
3816 raster
.FrontWinding
= CounterClockwise
;
3818 if (polygon
->CullFlag
) {
3819 switch (polygon
->CullFaceMode
) {
3821 raster
.CullMode
= CULLMODE_FRONT
;
3824 raster
.CullMode
= CULLMODE_BACK
;
3826 case GL_FRONT_AND_BACK
:
3827 raster
.CullMode
= CULLMODE_BOTH
;
3830 unreachable("not reached");
3833 raster
.CullMode
= CULLMODE_NONE
;
3836 point
->SmoothFlag
= raster
.SmoothPointEnable
;
3838 raster
.DXMultisampleRasterizationEnable
=
3839 _mesa_is_multisample_enabled(ctx
);
3841 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
3842 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
3843 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
3845 switch (polygon
->FrontMode
) {
3847 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
3850 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
3853 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
3856 unreachable("not reached");
3859 switch (polygon
->BackMode
) {
3861 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
3864 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
3867 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
3870 unreachable("not reached");
3874 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
3877 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
3879 /* _NEW_TRANSFORM */
3880 if (!ctx
->Transform
.DepthClamp
) {
3882 raster
.ViewportZFarClipTestEnable
= true;
3883 raster
.ViewportZNearClipTestEnable
= true;
3885 raster
.ViewportZClipTestEnable
= true;
3889 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
3891 raster
.ConservativeRasterizationEnable
=
3892 ctx
->IntelConservativeRasterization
;
3895 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
3896 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
3898 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
3902 static const struct brw_tracked_state
genX(raster_state
) = {
3904 .mesa
= _NEW_BUFFERS
|
3911 .brw
= BRW_NEW_BLORP
|
3913 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3915 .emit
= genX(upload_raster
),
3919 /* ---------------------------------------------------------------------- */
3923 genX(upload_ps_extra
)(struct brw_context
*brw
)
3925 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
3927 const struct brw_wm_prog_data
*prog_data
=
3928 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3930 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
3931 psx
.PixelShaderValid
= true;
3932 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
3933 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
3934 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
3935 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
3936 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
3937 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
3939 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
3940 if (prog_data
->uses_sample_mask
) {
3942 if (prog_data
->post_depth_coverage
)
3943 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3944 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
3945 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
3947 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3949 psx
.PixelShaderUsesInputCoverageMask
= true;
3953 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3955 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
3956 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
3959 /* The stricter cross-primitive coherency guarantees that the hardware
3960 * gives us with the "Accesses UAV" bit set for at least one shader stage
3961 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
3962 * are redundant within the current image, atomic counter and SSBO GL
3963 * APIs, which all have very loose ordering and coherency requirements
3964 * and generally rely on the application to insert explicit barriers when
3965 * a shader invocation is expected to see the memory writes performed by
3966 * the invocations of some previous primitive. Regardless of the value
3967 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
3968 * cause an in most cases useless DC flush when the lowermost stage with
3969 * the bit set finishes execution.
3971 * It would be nice to disable it, but in some cases we can't because on
3972 * Gen8+ it also has an influence on rasterization via the PS UAV-only
3973 * signal (which could be set independently from the coherency mechanism
3974 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
3975 * determine whether the hardware skips execution of the fragment shader
3976 * or not via the ThreadDispatchEnable signal. However if we know that
3977 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
3978 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
3979 * difference so we may just disable it here.
3981 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
3982 * take into account KillPixels when no depth or stencil writes are
3983 * enabled. In order for occlusion queries to work correctly with no
3984 * attachments, we need to force-enable here.
3986 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
3989 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
3990 !brw_color_buffer_write_enabled(brw
))
3991 psx
.PixelShaderHasUAV
= true;
3995 const struct brw_tracked_state
genX(ps_extra
) = {
3997 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
3998 .brw
= BRW_NEW_BLORP
|
4000 BRW_NEW_FRAGMENT_PROGRAM
|
4001 BRW_NEW_FS_PROG_DATA
|
4002 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4004 .emit
= genX(upload_ps_extra
),
4008 /* ---------------------------------------------------------------------- */
4012 genX(upload_ps_blend
)(struct brw_context
*brw
)
4014 struct gl_context
*ctx
= &brw
->ctx
;
4017 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4018 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4021 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4023 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4024 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4025 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4027 if (!buffer0_is_integer
) {
4028 /* _NEW_MULTISAMPLE */
4029 pb
.AlphaToCoverageEnable
=
4030 _mesa_is_multisample_enabled(ctx
) &&
4031 ctx
->Multisample
.SampleAlphaToCoverage
;
4033 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4036 /* Used for implementing the following bit of GL_EXT_texture_integer:
4037 * "Per-fragment operations that require floating-point color
4038 * components, including multisample alpha operations, alpha test,
4039 * blending, and dithering, have no effect when the corresponding
4040 * colors are written to an integer color buffer."
4042 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4043 * "If drawbuffer zero is not NONE and the buffer it references has an
4044 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4045 * operations are skipped."
4047 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4048 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4049 GLenum eqA
= color
->Blend
[0].EquationA
;
4050 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4051 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4052 GLenum srcA
= color
->Blend
[0].SrcA
;
4053 GLenum dstA
= color
->Blend
[0].DstA
;
4055 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4056 srcRGB
= dstRGB
= GL_ONE
;
4058 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4059 srcA
= dstA
= GL_ONE
;
4061 /* Due to hardware limitations, the destination may have information
4062 * in an alpha channel even when the format specifies no alpha
4063 * channel. In order to avoid getting any incorrect blending due to
4064 * that alpha channel, coerce the blend factors to values that will
4065 * not read the alpha channel, but will instead use the correct
4066 * implicit value for alpha.
4068 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4069 GL_TEXTURE_ALPHA_TYPE
)) {
4070 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4071 srcA
= brw_fix_xRGB_alpha(srcA
);
4072 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4073 dstA
= brw_fix_xRGB_alpha(dstA
);
4076 pb
.ColorBufferBlendEnable
= true;
4077 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4078 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4079 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4080 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4082 pb
.IndependentAlphaBlendEnable
=
4083 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4088 static const struct brw_tracked_state
genX(ps_blend
) = {
4090 .mesa
= _NEW_BUFFERS
|
4093 .brw
= BRW_NEW_BLORP
|
4095 BRW_NEW_FRAGMENT_PROGRAM
,
4097 .emit
= genX(upload_ps_blend
)
4101 /* ---------------------------------------------------------------------- */
4105 genX(emit_vf_topology
)(struct brw_context
*brw
)
4107 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4108 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4112 static const struct brw_tracked_state
genX(vf_topology
) = {
4115 .brw
= BRW_NEW_BLORP
|
4118 .emit
= genX(emit_vf_topology
),
4122 /* ---------------------------------------------------------------------- */
4126 genX(upload_viewport_state_pointers
)(struct brw_context
*brw
)
4128 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
4129 vp
.CCViewportStateChange
= 1;
4130 vp
.SFViewportStateChange
= 1;
4131 vp
.CLIPViewportStateChange
= 1;
4132 vp
.PointertoCLIP_VIEWPORT
= brw
->clip
.vp_offset
;
4133 vp
.PointertoSF_VIEWPORT
= brw
->sf
.vp_offset
;
4134 vp
.PointertoCC_VIEWPORT
= brw
->cc
.vp_offset
;
4138 static const struct brw_tracked_state
genX(viewport_state
) = {
4141 .brw
= BRW_NEW_BATCH
|
4146 BRW_NEW_STATE_BASE_ADDRESS
,
4148 .emit
= genX(upload_viewport_state_pointers
),
4152 /* ---------------------------------------------------------------------- */
4155 genX(init_atoms
)(struct brw_context
*brw
)
4158 static const struct brw_tracked_state
*render_atoms
[] =
4160 /* Once all the programs are done, we know how large urb entry
4161 * sizes need to be and can decide if we need to change the urb
4165 &brw_recalculate_urb_fence
,
4170 /* Surface state setup. Must come before the VS/WM unit. The binding
4171 * table upload must be last.
4173 &brw_vs_pull_constants
,
4174 &brw_wm_pull_constants
,
4175 &brw_renderbuffer_surfaces
,
4176 &brw_renderbuffer_read_surfaces
,
4177 &brw_texture_surfaces
,
4178 &brw_vs_binding_table
,
4179 &brw_wm_binding_table
,
4184 /* These set up state for brw_psp_urb_cbs */
4188 &genX(vs_state
), /* always required, enabled or not */
4194 &brw_invariant_state
,
4196 &brw_binding_table_pointers
,
4197 &brw_blend_constant_color
,
4201 &genX(polygon_stipple
),
4202 &genX(polygon_stipple_offset
),
4204 &genX(line_stipple
),
4208 &genX(drawing_rect
),
4209 &brw_indices
, /* must come before brw_vertices */
4210 &genX(index_buffer
),
4213 &brw_constant_buffer
4216 static const struct brw_tracked_state
*render_atoms
[] =
4218 &genX(sf_clip_viewport
),
4220 /* Command packets: */
4223 &genX(viewport_state
), /* must do after *_vp stages */
4226 &genX(blend_state
), /* must do before cc unit */
4227 &genX(color_calc_state
), /* must do before cc unit */
4228 &genX(depth_stencil_state
), /* must do before cc unit */
4230 &genX(vs_push_constants
), /* Before vs_state */
4231 &genX(gs_push_constants
), /* Before gs_state */
4232 &genX(wm_push_constants
), /* Before wm_state */
4234 /* Surface state setup. Must come before the VS/WM unit. The binding
4235 * table upload must be last.
4237 &brw_vs_pull_constants
,
4238 &brw_vs_ubo_surfaces
,
4239 &brw_gs_pull_constants
,
4240 &brw_gs_ubo_surfaces
,
4241 &brw_wm_pull_constants
,
4242 &brw_wm_ubo_surfaces
,
4243 &gen6_renderbuffer_surfaces
,
4244 &brw_renderbuffer_read_surfaces
,
4245 &brw_texture_surfaces
,
4247 &brw_vs_binding_table
,
4248 &gen6_gs_binding_table
,
4249 &brw_wm_binding_table
,
4254 &gen6_sampler_state
,
4255 &genX(multisample_state
),
4263 &genX(scissor_state
),
4265 &gen6_binding_table_pointers
,
4269 &genX(polygon_stipple
),
4270 &genX(polygon_stipple_offset
),
4272 &genX(line_stipple
),
4274 &genX(drawing_rect
),
4276 &brw_indices
, /* must come before brw_vertices */
4277 &genX(index_buffer
),
4281 static const struct brw_tracked_state
*render_atoms
[] =
4283 /* Command packets: */
4286 &genX(sf_clip_viewport
),
4289 &gen7_push_constant_space
,
4291 &genX(blend_state
), /* must do before cc unit */
4292 &genX(color_calc_state
), /* must do before cc unit */
4293 &genX(depth_stencil_state
), /* must do before cc unit */
4295 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4296 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4297 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4298 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4299 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4301 &genX(vs_push_constants
), /* Before vs_state */
4302 &genX(tcs_push_constants
),
4303 &genX(tes_push_constants
),
4304 &genX(gs_push_constants
), /* Before gs_state */
4305 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4307 /* Surface state setup. Must come before the VS/WM unit. The binding
4308 * table upload must be last.
4310 &brw_vs_pull_constants
,
4311 &brw_vs_ubo_surfaces
,
4312 &brw_vs_abo_surfaces
,
4313 &brw_tcs_pull_constants
,
4314 &brw_tcs_ubo_surfaces
,
4315 &brw_tcs_abo_surfaces
,
4316 &brw_tes_pull_constants
,
4317 &brw_tes_ubo_surfaces
,
4318 &brw_tes_abo_surfaces
,
4319 &brw_gs_pull_constants
,
4320 &brw_gs_ubo_surfaces
,
4321 &brw_gs_abo_surfaces
,
4322 &brw_wm_pull_constants
,
4323 &brw_wm_ubo_surfaces
,
4324 &brw_wm_abo_surfaces
,
4325 &gen6_renderbuffer_surfaces
,
4326 &brw_renderbuffer_read_surfaces
,
4327 &brw_texture_surfaces
,
4328 &brw_vs_binding_table
,
4329 &brw_tcs_binding_table
,
4330 &brw_tes_binding_table
,
4331 &brw_gs_binding_table
,
4332 &brw_wm_binding_table
,
4339 &genX(multisample_state
),
4353 &genX(scissor_state
),
4357 &genX(polygon_stipple
),
4358 &genX(polygon_stipple_offset
),
4360 &genX(line_stipple
),
4362 &genX(drawing_rect
),
4364 &brw_indices
, /* must come before brw_vertices */
4365 &genX(index_buffer
),
4373 static const struct brw_tracked_state
*render_atoms
[] =
4376 &genX(sf_clip_viewport
),
4379 &gen7_push_constant_space
,
4382 &genX(color_calc_state
),
4384 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4385 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4386 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4387 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4388 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4390 &genX(vs_push_constants
), /* Before vs_state */
4391 &genX(tcs_push_constants
),
4392 &genX(tes_push_constants
),
4393 &genX(gs_push_constants
), /* Before gs_state */
4394 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4396 /* Surface state setup. Must come before the VS/WM unit. The binding
4397 * table upload must be last.
4399 &brw_vs_pull_constants
,
4400 &brw_vs_ubo_surfaces
,
4401 &brw_vs_abo_surfaces
,
4402 &brw_tcs_pull_constants
,
4403 &brw_tcs_ubo_surfaces
,
4404 &brw_tcs_abo_surfaces
,
4405 &brw_tes_pull_constants
,
4406 &brw_tes_ubo_surfaces
,
4407 &brw_tes_abo_surfaces
,
4408 &brw_gs_pull_constants
,
4409 &brw_gs_ubo_surfaces
,
4410 &brw_gs_abo_surfaces
,
4411 &brw_wm_pull_constants
,
4412 &brw_wm_ubo_surfaces
,
4413 &brw_wm_abo_surfaces
,
4414 &gen6_renderbuffer_surfaces
,
4415 &brw_renderbuffer_read_surfaces
,
4416 &brw_texture_surfaces
,
4417 &brw_vs_binding_table
,
4418 &brw_tcs_binding_table
,
4419 &brw_tes_binding_table
,
4420 &brw_gs_binding_table
,
4421 &brw_wm_binding_table
,
4428 &genX(multisample_state
),
4437 &genX(raster_state
),
4443 &genX(depth_stencil_state
),
4446 &genX(scissor_state
),
4450 &genX(polygon_stipple
),
4451 &genX(polygon_stipple_offset
),
4453 &genX(line_stipple
),
4455 &genX(drawing_rect
),
4460 &genX(index_buffer
),
4468 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
4469 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
4470 render_atoms
, ARRAY_SIZE(render_atoms
));
4473 static const struct brw_tracked_state
*compute_atoms
[] =
4476 &brw_cs_image_surfaces
,
4477 &gen7_cs_push_constants
,
4478 &brw_cs_pull_constants
,
4479 &brw_cs_ubo_surfaces
,
4480 &brw_cs_abo_surfaces
,
4481 &brw_cs_texture_surfaces
,
4482 &brw_cs_work_groups_surface
,
4487 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
4488 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
4489 compute_atoms
, ARRAY_SIZE(compute_atoms
));