2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 UNUSED
static struct brw_address
124 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
134 static struct brw_address
135 KSP(struct brw_context
*brw
, uint32_t offset
)
137 return ro_bo(brw
->cache
.bo
, offset
);
141 KSP(struct brw_context
*brw
, uint32_t offset
)
147 #include "genxml/genX_pack.h"
149 #define _brw_cmd_length(cmd) cmd ## _length
150 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
151 #define _brw_cmd_header(cmd) cmd ## _header
152 #define _brw_cmd_pack(cmd) cmd ## _pack
154 #define brw_batch_emit(brw, cmd, name) \
155 for (struct cmd name = { _brw_cmd_header(cmd) }, \
156 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
157 __builtin_expect(_dst != NULL, 1); \
158 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
161 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
162 uint32_t *_dw = emit_dwords(brw, n); \
163 struct cmd template = { \
164 _brw_cmd_header(cmd), \
165 .DWordLength = n - _brw_cmd_length_bias(cmd), \
168 _brw_cmd_pack(cmd)(brw, _dw, &template); \
169 _dw + 1; /* Array starts at dw[1] */ \
172 #define brw_state_emit(brw, cmd, align, offset, name) \
173 for (struct cmd name = {}, \
174 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
176 __builtin_expect(_dst != NULL, 1); \
177 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 * Polygon stipple packet
184 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
186 struct gl_context
*ctx
= &brw
->ctx
;
189 if (!ctx
->Polygon
.StippleFlag
)
192 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
193 /* Polygon stipple is provided in OpenGL order, i.e. bottom
194 * row first. If we're rendering to a window (i.e. the
195 * default frame buffer object, 0), then we need to invert
196 * it to match our pixel layout. But if we're rendering
197 * to a FBO (i.e. any named frame buffer object), we *don't*
198 * need to invert - we already match the layout.
200 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
201 for (unsigned i
= 0; i
< 32; i
++)
202 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
204 for (unsigned i
= 0; i
< 32; i
++)
205 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
210 static const struct brw_tracked_state
genX(polygon_stipple
) = {
212 .mesa
= _NEW_POLYGON
|
214 .brw
= BRW_NEW_CONTEXT
,
216 .emit
= genX(upload_polygon_stipple
),
220 * Polygon stipple offset packet
223 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
225 struct gl_context
*ctx
= &brw
->ctx
;
228 if (!ctx
->Polygon
.StippleFlag
)
231 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
234 * If we're drawing to a system window we have to invert the Y axis
235 * in order to match the OpenGL pixel coordinate system, and our
236 * offset must be matched to the window position. If we're drawing
237 * to a user-created FBO then our native pixel coordinate system
238 * works just fine, and there's no window system to worry about.
240 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
241 poly
.PolygonStippleYOffset
=
242 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
247 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
249 .mesa
= _NEW_BUFFERS
|
251 .brw
= BRW_NEW_CONTEXT
,
253 .emit
= genX(upload_polygon_stipple_offset
),
257 * Line stipple packet
260 genX(upload_line_stipple
)(struct brw_context
*brw
)
262 struct gl_context
*ctx
= &brw
->ctx
;
264 if (!ctx
->Line
.StippleFlag
)
267 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
268 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
270 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
271 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
275 static const struct brw_tracked_state
genX(line_stipple
) = {
278 .brw
= BRW_NEW_CONTEXT
,
280 .emit
= genX(upload_line_stipple
),
283 /* Constant single cliprect for framebuffer object or DRI2 drawing */
285 genX(upload_drawing_rect
)(struct brw_context
*brw
)
287 struct gl_context
*ctx
= &brw
->ctx
;
288 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
289 const unsigned int fb_width
= _mesa_geometric_width(fb
);
290 const unsigned int fb_height
= _mesa_geometric_height(fb
);
292 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
293 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
294 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
298 static const struct brw_tracked_state
genX(drawing_rect
) = {
300 .mesa
= _NEW_BUFFERS
,
301 .brw
= BRW_NEW_BLORP
|
304 .emit
= genX(upload_drawing_rect
),
308 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
312 unsigned start_offset
,
317 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
318 .VertexBufferIndex
= buffer_nr
,
319 .BufferPitch
= stride
,
320 .BufferStartingAddress
= ro_bo(bo
, start_offset
),
322 .BufferSize
= end_offset
- start_offset
,
326 .AddressModifyEnable
= true,
330 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
331 .InstanceDataStepRate
= step_rate
,
333 .EndAddress
= ro_bo(bo
, end_offset
- 1),
338 .VertexBufferMOCS
= CNL_MOCS_WB
,
340 .VertexBufferMOCS
= SKL_MOCS_WB
,
342 .VertexBufferMOCS
= BDW_MOCS_WB
,
344 .VertexBufferMOCS
= GEN7_MOCS_L3
,
348 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
349 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
353 is_passthru_format(uint32_t format
)
356 case ISL_FORMAT_R64_PASSTHRU
:
357 case ISL_FORMAT_R64G64_PASSTHRU
:
358 case ISL_FORMAT_R64G64B64_PASSTHRU
:
359 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
367 uploads_needed(uint32_t format
,
370 if (!is_passthru_format(format
))
377 case ISL_FORMAT_R64_PASSTHRU
:
378 case ISL_FORMAT_R64G64_PASSTHRU
:
380 case ISL_FORMAT_R64G64B64_PASSTHRU
:
381 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
384 unreachable("not reached");
389 * Returns the format that we are finally going to use when upload a vertex
390 * element. It will only change if we are using *64*PASSTHRU formats, as for
391 * gen < 8 they need to be splitted on two *32*FLOAT formats.
393 * @upload points in which upload we are. Valid values are [0,1]
396 downsize_format_if_needed(uint32_t format
,
399 assert(upload
== 0 || upload
== 1);
401 if (!is_passthru_format(format
))
404 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
405 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
406 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
407 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
408 * flagging that we want to fill with zeroes this second forced upload.
411 case ISL_FORMAT_R64_PASSTHRU
:
412 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
413 : ISL_FORMAT_R32_FLOAT
;
414 case ISL_FORMAT_R64G64_PASSTHRU
:
415 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
416 : ISL_FORMAT_R32_FLOAT
;
417 case ISL_FORMAT_R64G64B64_PASSTHRU
:
418 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
419 : ISL_FORMAT_R32G32_FLOAT
;
420 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
421 return ISL_FORMAT_R32G32B32A32_FLOAT
;
423 unreachable("not reached");
428 * Returns the number of componentes associated with a format that is used on
429 * a 64 to 32 format split. See downsize_format()
432 upload_format_size(uint32_t upload_format
)
434 switch (upload_format
) {
435 case ISL_FORMAT_R32_FLOAT
:
437 /* downsized_format has returned this one in order to flag that we are
438 * performing a second upload which we want to have filled with
439 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
440 * vertex shader input variables.
444 case ISL_FORMAT_R32G32_FLOAT
:
446 case ISL_FORMAT_R32G32B32A32_FLOAT
:
449 unreachable("not reached");
454 genX(emit_vertices
)(struct brw_context
*brw
)
456 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
459 brw_prepare_vertices(brw
);
460 brw_prepare_shader_draw_parameters(brw
);
463 brw_emit_query_begin(brw
);
466 const struct brw_vs_prog_data
*vs_prog_data
=
467 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
470 struct gl_context
*ctx
= &brw
->ctx
;
471 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
472 ctx
->Polygon
.BackMode
!= GL_FILL
);
474 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
475 unsigned vue
= brw
->vb
.nr_enabled
;
477 /* The element for the edge flags must always be last, so we have to
478 * insert the SGVS before it in that case.
480 if (uses_edge_flag
) {
486 "Trying to insert VID/IID past 33rd vertex element, "
487 "need to reorder the vertex attrbutes.");
489 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
490 if (vs_prog_data
->uses_vertexid
) {
491 vfs
.VertexIDEnable
= true;
492 vfs
.VertexIDComponentNumber
= 2;
493 vfs
.VertexIDElementOffset
= vue
;
496 if (vs_prog_data
->uses_instanceid
) {
497 vfs
.InstanceIDEnable
= true;
498 vfs
.InstanceIDComponentNumber
= 3;
499 vfs
.InstanceIDElementOffset
= vue
;
503 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
504 vfi
.InstancingEnable
= true;
505 vfi
.VertexElementIndex
= vue
;
508 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
511 /* Normally we don't need an element for the SGVS attribute because the
512 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
513 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
514 * we're using draw parameters then we need an element for the those
515 * values. Additionally if there is an edge flag element then the SGVS
516 * can't be inserted past that so we need a dummy element to ensure that
517 * the edge flag is the last one.
519 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
520 vs_prog_data
->uses_baseinstance
||
521 ((vs_prog_data
->uses_instanceid
||
522 vs_prog_data
->uses_vertexid
)
525 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
526 vs_prog_data
->uses_baseinstance
||
527 vs_prog_data
->uses_instanceid
||
528 vs_prog_data
->uses_vertexid
);
530 unsigned nr_elements
=
531 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
534 /* If any of the formats of vb.enabled needs more that one upload, we need
535 * to add it to nr_elements
537 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
538 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
539 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
541 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
546 /* If the VS doesn't read any inputs (calculating vertex position from
547 * a state variable for some reason, for example), emit a single pad
548 * VERTEX_ELEMENT struct and bail.
550 * The stale VB state stays in place, but they don't do anything unless
551 * a VE loads from them.
553 if (nr_elements
== 0) {
554 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
555 1 + GENX(VERTEX_ELEMENT_STATE_length
));
556 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
558 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
559 .Component0Control
= VFCOMP_STORE_0
,
560 .Component1Control
= VFCOMP_STORE_0
,
561 .Component2Control
= VFCOMP_STORE_0
,
562 .Component3Control
= VFCOMP_STORE_1_FP
,
564 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
568 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
569 const bool uses_draw_params
=
570 vs_prog_data
->uses_basevertex
||
571 vs_prog_data
->uses_baseinstance
;
572 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
573 uses_draw_params
+ vs_prog_data
->uses_drawid
;
576 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
578 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
579 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
581 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
582 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
583 /* Prior to Haswell and Bay Trail we have to use 4-component formats
584 * to fake 3-component ones. In particular, we do this for
585 * half-float and 8 and 16-bit integer formats. This means that the
586 * vertex element may poke over the end of the buffer by 2 bytes.
588 const unsigned padding
=
589 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
590 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
591 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
598 if (uses_draw_params
) {
599 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
600 brw
->draw
.draw_params_bo
,
601 brw
->draw
.draw_params_offset
,
602 brw
->draw
.draw_params_bo
->size
,
607 if (vs_prog_data
->uses_drawid
) {
608 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
609 brw
->draw
.draw_id_bo
,
610 brw
->draw
.draw_id_offset
,
611 brw
->draw
.draw_id_bo
->size
,
617 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
618 * presumably for VertexID/InstanceID.
621 assert(nr_elements
<= 34);
622 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
624 assert(nr_elements
<= 18);
627 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
628 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
630 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
631 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
632 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
633 uint32_t comp0
= VFCOMP_STORE_SRC
;
634 uint32_t comp1
= VFCOMP_STORE_SRC
;
635 uint32_t comp2
= VFCOMP_STORE_SRC
;
636 uint32_t comp3
= VFCOMP_STORE_SRC
;
637 const unsigned num_uploads
= GEN_GEN
< 8 ?
638 uploads_needed(format
, input
->is_dual_slot
) : 1;
641 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
642 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
643 * element which has edge flag enabled."
645 assert(!(is_passthru_format(format
) && uses_edge_flag
));
648 /* The gen4 driver expects edgeflag to come in as a float, and passes
649 * that float on to the tests in the clipper. Mesa's current vertex
650 * attribute value for EdgeFlag is stored as a float, which works out.
651 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
652 * integer ubyte. Just rewrite that to convert to a float.
654 * Gen6+ passes edgeflag as sideband along with the vertex, instead
655 * of in the VUE. We have to upload it sideband as the last vertex
656 * element according to the B-Spec.
659 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
660 gen6_edgeflag_input
= input
;
665 for (unsigned c
= 0; c
< num_uploads
; c
++) {
666 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
667 downsize_format_if_needed(format
, c
);
668 /* If we need more that one upload, the offset stride would be 128
669 * bits (16 bytes), as for previous uploads we are using the full
671 const unsigned offset
= input
->offset
+ c
* 16;
673 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
674 upload_format_size(upload_format
) : input
->glarray
->Size
;
677 case 0: comp0
= VFCOMP_STORE_0
;
678 case 1: comp1
= VFCOMP_STORE_0
;
679 case 2: comp2
= VFCOMP_STORE_0
;
681 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
682 comp3
= VFCOMP_STORE_0
;
683 } else if (input
->glarray
->Integer
) {
684 comp3
= VFCOMP_STORE_1_INT
;
686 comp3
= VFCOMP_STORE_1_FP
;
693 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
695 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
696 * formats, 64-bit components are stored in the URB without any
697 * conversion. In this case, vertex elements must be written as 128
698 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
699 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
700 * component into the URB, Component 1 must be specified as
701 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
702 * order to output a 128-bit vertex element, or Components 1-3 must
703 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
704 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
705 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
708 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
709 /* Store vertex elements which correspond to double and dvec2 vertex
710 * shader inputs as 128-bit vertex elements, instead of 256-bits.
712 comp2
= VFCOMP_NOSTORE
;
713 comp3
= VFCOMP_NOSTORE
;
717 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
718 .VertexBufferIndex
= input
->buffer
,
720 .SourceElementFormat
= upload_format
,
721 .SourceElementOffset
= offset
,
722 .Component0Control
= comp0
,
723 .Component1Control
= comp1
,
724 .Component2Control
= comp2
,
725 .Component3Control
= comp3
,
727 .DestinationElementOffset
= i
* 4,
731 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
732 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
736 if (needs_sgvs_element
) {
737 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
739 .Component0Control
= VFCOMP_STORE_0
,
740 .Component1Control
= VFCOMP_STORE_0
,
741 .Component2Control
= VFCOMP_STORE_0
,
742 .Component3Control
= VFCOMP_STORE_0
,
744 .DestinationElementOffset
= i
* 4,
749 if (vs_prog_data
->uses_basevertex
||
750 vs_prog_data
->uses_baseinstance
) {
751 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
752 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
753 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
754 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
757 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
758 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
759 if (vs_prog_data
->uses_basevertex
)
760 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
762 if (vs_prog_data
->uses_baseinstance
)
763 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
765 if (vs_prog_data
->uses_vertexid
)
766 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
768 if (vs_prog_data
->uses_instanceid
)
769 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
772 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
773 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
776 if (vs_prog_data
->uses_drawid
) {
777 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
779 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
780 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32_UINT
,
781 .Component0Control
= VFCOMP_STORE_SRC
,
782 .Component1Control
= VFCOMP_STORE_0
,
783 .Component2Control
= VFCOMP_STORE_0
,
784 .Component3Control
= VFCOMP_STORE_0
,
786 .DestinationElementOffset
= i
* 4,
790 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
791 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
795 if (gen6_edgeflag_input
) {
796 const uint32_t format
=
797 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
799 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
801 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
802 .EdgeFlagEnable
= true,
803 .SourceElementFormat
= format
,
804 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
805 .Component0Control
= VFCOMP_STORE_SRC
,
806 .Component1Control
= VFCOMP_STORE_0
,
807 .Component2Control
= VFCOMP_STORE_0
,
808 .Component3Control
= VFCOMP_STORE_0
,
811 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
812 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
817 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
818 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
819 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
820 unsigned element_index
;
822 /* The edge flag element is reordered to be the last one in the code
823 * above so we need to compensate for that in the element indices used
826 if (input
== gen6_edgeflag_input
)
827 element_index
= nr_elements
- 1;
831 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
832 vfi
.VertexElementIndex
= element_index
;
833 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
834 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
838 if (vs_prog_data
->uses_drawid
) {
839 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
841 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
842 vfi
.VertexElementIndex
= element
;
848 static const struct brw_tracked_state
genX(vertices
) = {
850 .mesa
= _NEW_POLYGON
,
851 .brw
= BRW_NEW_BATCH
|
854 BRW_NEW_VS_PROG_DATA
,
856 .emit
= genX(emit_vertices
),
860 genX(emit_index_buffer
)(struct brw_context
*brw
)
862 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
864 if (index_buffer
== NULL
)
867 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
868 #if GEN_GEN < 8 && !GEN_IS_HASWELL
869 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
871 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
872 ib
.BufferStartingAddress
= ro_bo(brw
->ib
.bo
, 0);
874 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
875 ib
.BufferSize
= brw
->ib
.size
;
877 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
882 static const struct brw_tracked_state
genX(index_buffer
) = {
885 .brw
= BRW_NEW_BATCH
|
887 BRW_NEW_INDEX_BUFFER
,
889 .emit
= genX(emit_index_buffer
),
892 #if GEN_IS_HASWELL || GEN_GEN >= 8
894 genX(upload_cut_index
)(struct brw_context
*brw
)
896 const struct gl_context
*ctx
= &brw
->ctx
;
898 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
899 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
900 vf
.IndexedDrawCutIndexEnable
= true;
901 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
906 const struct brw_tracked_state
genX(cut_index
) = {
908 .mesa
= _NEW_TRANSFORM
,
909 .brw
= BRW_NEW_INDEX_BUFFER
,
911 .emit
= genX(upload_cut_index
),
917 * Determine the appropriate attribute override value to store into the
918 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
919 * override value contains two pieces of information: the location of the
920 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
921 * flag indicating whether to "swizzle" the attribute based on the direction
922 * the triangle is facing.
924 * If an attribute is "swizzled", then the given VUE location is used for
925 * front-facing triangles, and the VUE location that immediately follows is
926 * used for back-facing triangles. We use this to implement the mapping from
927 * gl_FrontColor/gl_BackColor to gl_Color.
929 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
930 * being instructed to begin reading attribute data. It can be set to a
931 * nonzero value to prevent the SF unit from wasting time reading elements of
932 * the VUE that are not needed by the fragment shader. It is measured in
933 * 256-bit increments.
936 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
937 const struct brw_vue_map
*vue_map
,
938 int urb_entry_read_offset
, int fs_attr
,
939 bool two_side_color
, uint32_t *max_source_attr
)
941 /* Find the VUE slot for this attribute. */
942 int slot
= vue_map
->varying_to_slot
[fs_attr
];
944 /* Viewport and Layer are stored in the VUE header. We need to override
945 * them to zero if earlier stages didn't write them, as GL requires that
946 * they read back as zero when not explicitly set.
948 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
949 attr
->ComponentOverrideX
= true;
950 attr
->ComponentOverrideW
= true;
951 attr
->ConstantSource
= CONST_0000
;
953 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
954 attr
->ComponentOverrideY
= true;
955 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
956 attr
->ComponentOverrideZ
= true;
961 /* If there was only a back color written but not front, use back
962 * as the color instead of undefined
964 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
965 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
966 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
967 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
970 /* This attribute does not exist in the VUE--that means that the vertex
971 * shader did not write to it. This means that either:
973 * (a) This attribute is a texture coordinate, and it is going to be
974 * replaced with point coordinates (as a consequence of a call to
975 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
976 * hardware will ignore whatever attribute override we supply.
978 * (b) This attribute is read by the fragment shader but not written by
979 * the vertex shader, so its value is undefined. Therefore the
980 * attribute override we supply doesn't matter.
982 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
983 * previous shader stage.
985 * Note that we don't have to worry about the cases where the attribute
986 * is gl_PointCoord or is undergoing point sprite coordinate
987 * replacement, because in those cases, this function isn't called.
989 * In case (c), we need to program the attribute overrides so that the
990 * primitive ID will be stored in this slot. In every other case, the
991 * attribute override we supply doesn't matter. So just go ahead and
992 * program primitive ID in every case.
994 attr
->ComponentOverrideW
= true;
995 attr
->ComponentOverrideX
= true;
996 attr
->ComponentOverrideY
= true;
997 attr
->ComponentOverrideZ
= true;
998 attr
->ConstantSource
= PRIM_ID
;
1002 /* Compute the location of the attribute relative to urb_entry_read_offset.
1003 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1004 * it counts for two 128-bit VUE slots.
1006 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1007 assert(source_attr
>= 0 && source_attr
< 32);
1009 /* If we are doing two-sided color, and the VUE slot following this one
1010 * represents a back-facing color, then we need to instruct the SF unit to
1011 * do back-facing swizzling.
1013 bool swizzling
= two_side_color
&&
1014 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1015 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1016 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1017 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1019 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1020 if (*max_source_attr
< source_attr
+ swizzling
)
1021 *max_source_attr
= source_attr
+ swizzling
;
1023 attr
->SourceAttribute
= source_attr
;
1025 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1030 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1031 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1032 uint32_t *point_sprite_enables
,
1033 uint32_t *urb_entry_read_length
,
1034 uint32_t *urb_entry_read_offset
)
1036 const struct gl_context
*ctx
= &brw
->ctx
;
1039 const struct gl_point_attrib
*point
= &ctx
->Point
;
1041 /* BRW_NEW_FRAGMENT_PROGRAM */
1042 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1044 /* BRW_NEW_FS_PROG_DATA */
1045 const struct brw_wm_prog_data
*wm_prog_data
=
1046 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1047 uint32_t max_source_attr
= 0;
1049 *point_sprite_enables
= 0;
1052 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1053 &brw
->vue_map_geom_out
);
1055 /* Each URB offset packs two varying slots */
1056 assert(first_slot
% 2 == 0);
1057 *urb_entry_read_offset
= first_slot
/ 2;
1059 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1060 * description of dw10 Point Sprite Texture Coordinate Enable:
1062 * "This field must be programmed to zero when non-point primitives
1065 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1066 * must be programmed to zero when rendering non-point primitives, but
1067 * the IvyBridge PRM does, and if we don't, we get garbage.
1069 * This is not required on Haswell, as the hardware ignores this state
1070 * when drawing non-points -- although we do still need to be careful to
1071 * correctly set the attr overrides.
1074 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1076 bool drawing_points
= brw_is_drawing_points(brw
);
1078 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1079 int input_index
= wm_prog_data
->urb_setup
[attr
];
1081 if (input_index
< 0)
1085 bool point_sprite
= false;
1086 if (drawing_points
) {
1087 if (point
->PointSprite
&&
1088 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1089 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1090 point_sprite
= true;
1093 if (attr
== VARYING_SLOT_PNTC
)
1094 point_sprite
= true;
1097 *point_sprite_enables
|= (1 << input_index
);
1100 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1101 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1103 if (!point_sprite
) {
1104 genX(get_attr_override
)(&attribute
,
1105 &brw
->vue_map_geom_out
,
1106 *urb_entry_read_offset
, attr
,
1107 _mesa_vertex_program_two_side_enabled(ctx
),
1111 /* The hardware can only do the overrides on 16 overrides at a
1112 * time, and the other up to 16 have to be lined up so that the
1113 * input index = the output index. We'll need to do some
1114 * tweaking to make sure that's the case.
1116 if (input_index
< 16)
1117 attr_overrides
[input_index
] = attribute
;
1119 assert(attribute
.SourceAttribute
== input_index
);
1122 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1123 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1125 * "This field should be set to the minimum length required to read the
1126 * maximum source attribute. The maximum source attribute is indicated
1127 * by the maximum value of the enabled Attribute # Source Attribute if
1128 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1129 * enable is not set.
1130 * read_length = ceiling((max_source_attr + 1) / 2)
1132 * [errata] Corruption/Hang possible if length programmed larger than
1135 * Similar text exists for Ivy Bridge.
1137 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1141 /* ---------------------------------------------------------------------- */
1144 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1146 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1148 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1152 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1154 struct gl_context
*ctx
= &brw
->ctx
;
1157 struct intel_renderbuffer
*depth_irb
=
1158 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1161 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1164 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1165 const int b
= stencil
->_BackFace
;
1167 if (depth
->Test
&& depth_irb
) {
1168 ds
->DepthTestEnable
= true;
1169 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1170 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1173 if (brw
->stencil_enabled
) {
1174 ds
->StencilTestEnable
= true;
1175 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1176 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1178 ds
->StencilTestFunction
=
1179 intel_translate_compare_func(stencil
->Function
[0]);
1181 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1182 ds
->StencilPassDepthPassOp
=
1183 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1184 ds
->StencilPassDepthFailOp
=
1185 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1187 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1189 if (brw
->stencil_two_sided
) {
1190 ds
->DoubleSidedStencilEnable
= true;
1191 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1192 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1194 ds
->BackfaceStencilTestFunction
=
1195 intel_translate_compare_func(stencil
->Function
[b
]);
1196 ds
->BackfaceStencilFailOp
=
1197 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1198 ds
->BackfaceStencilPassDepthPassOp
=
1199 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1200 ds
->BackfaceStencilPassDepthFailOp
=
1201 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1204 #if GEN_GEN <= 5 || GEN_GEN >= 9
1205 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1206 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1213 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1216 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1217 set_depth_stencil_bits(brw
, &wmds
);
1221 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1222 set_depth_stencil_bits(brw
, &ds
);
1225 /* Now upload a pointer to the indirect state */
1227 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1228 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1229 ptr
.DEPTH_STENCIL_STATEChange
= true;
1232 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1233 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1239 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1241 .mesa
= _NEW_BUFFERS
|
1244 .brw
= BRW_NEW_BLORP
|
1245 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1247 BRW_NEW_STATE_BASE_ADDRESS
),
1249 .emit
= genX(upload_depth_stencil_state
),
1253 /* ---------------------------------------------------------------------- */
1258 genX(upload_clip_state
)(struct brw_context
*brw
)
1260 struct gl_context
*ctx
= &brw
->ctx
;
1262 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1263 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1264 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1265 clip
.GRFRegisterCount
=
1266 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1267 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1268 clip
.SingleProgramFlow
= true;
1269 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1270 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1272 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1273 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1274 clip
.DispatchGRFStartRegisterForURBData
= 1;
1275 clip
.VertexURBEntryReadOffset
= 0;
1277 /* BRW_NEW_URB_FENCE */
1278 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1279 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1281 if (brw
->urb
.nr_clip_entries
>= 10) {
1282 /* Half of the URB entries go to each thread, and it has to be an
1285 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1287 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1288 * only 2 threads can output VUEs at a time.
1290 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1292 assert(brw
->urb
.nr_clip_entries
>= 5);
1293 clip
.MaximumNumberofThreads
= 1 - 1;
1296 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1297 clip
.UserClipFlagsMustClipEnable
= true;
1298 clip
.GuardbandClipTestEnable
= true;
1300 clip
.ClipperViewportStatePointer
=
1301 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1303 clip
.ScreenSpaceViewportXMin
= -1;
1304 clip
.ScreenSpaceViewportXMax
= 1;
1305 clip
.ScreenSpaceViewportYMin
= -1;
1306 clip
.ScreenSpaceViewportYMax
= 1;
1308 clip
.ViewportXYClipTestEnable
= true;
1309 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1311 /* _NEW_TRANSFORM */
1312 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1313 clip
.UserClipDistanceClipTestEnableBitmask
=
1314 ctx
->Transform
.ClipPlanesEnabled
;
1316 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1319 clip
.UserClipDistanceClipTestEnableBitmask
=
1320 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1323 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1324 clip
.APIMode
= APIMODE_D3D
;
1326 clip
.APIMode
= APIMODE_OGL
;
1328 clip
.GuardbandClipTestEnable
= true;
1330 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1333 clip
.NegativeWClipTestEnable
= true;
1338 const struct brw_tracked_state
genX(clip_state
) = {
1340 .mesa
= _NEW_TRANSFORM
|
1342 .brw
= BRW_NEW_BATCH
|
1344 BRW_NEW_CLIP_PROG_DATA
|
1345 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1346 BRW_NEW_PROGRAM_CACHE
|
1349 .emit
= genX(upload_clip_state
),
1355 genX(upload_clip_state
)(struct brw_context
*brw
)
1357 struct gl_context
*ctx
= &brw
->ctx
;
1360 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1362 /* BRW_NEW_FS_PROG_DATA */
1363 struct brw_wm_prog_data
*wm_prog_data
=
1364 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1366 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1367 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1369 if (wm_prog_data
->barycentric_interp_modes
&
1370 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1371 clip
.NonPerspectiveBarycentricEnable
= true;
1374 clip
.EarlyCullEnable
= true;
1378 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1380 if (ctx
->Polygon
.CullFlag
) {
1381 switch (ctx
->Polygon
.CullFaceMode
) {
1383 clip
.CullMode
= CULLMODE_FRONT
;
1386 clip
.CullMode
= CULLMODE_BACK
;
1388 case GL_FRONT_AND_BACK
:
1389 clip
.CullMode
= CULLMODE_BOTH
;
1392 unreachable("Should not get here: invalid CullFlag");
1395 clip
.CullMode
= CULLMODE_NONE
;
1400 clip
.UserClipDistanceCullTestEnableBitmask
=
1401 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1403 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1407 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1408 clip
.TriangleStripListProvokingVertexSelect
= 0;
1409 clip
.TriangleFanProvokingVertexSelect
= 1;
1410 clip
.LineStripListProvokingVertexSelect
= 0;
1412 clip
.TriangleStripListProvokingVertexSelect
= 2;
1413 clip
.TriangleFanProvokingVertexSelect
= 2;
1414 clip
.LineStripListProvokingVertexSelect
= 1;
1417 /* _NEW_TRANSFORM */
1418 clip
.UserClipDistanceClipTestEnableBitmask
=
1419 ctx
->Transform
.ClipPlanesEnabled
;
1422 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1425 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1426 clip
.APIMode
= APIMODE_D3D
;
1428 clip
.APIMode
= APIMODE_OGL
;
1430 clip
.GuardbandClipTestEnable
= true;
1432 /* BRW_NEW_VIEWPORT_COUNT */
1433 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1435 if (ctx
->RasterDiscard
) {
1436 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1438 perf_debug("Rasterizer discard is currently implemented via the "
1439 "clipper; having the GS not write primitives would "
1440 "likely be faster.\n");
1443 clip
.ClipMode
= CLIPMODE_NORMAL
;
1446 clip
.ClipEnable
= true;
1449 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1451 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1452 clip
.ViewportXYClipTestEnable
= true;
1454 clip
.MinimumPointWidth
= 0.125;
1455 clip
.MaximumPointWidth
= 255.875;
1456 clip
.MaximumVPIndex
= viewport_count
- 1;
1457 if (_mesa_geometric_layers(fb
) == 0)
1458 clip
.ForceZeroRTAIndexEnable
= true;
1462 static const struct brw_tracked_state
genX(clip_state
) = {
1464 .mesa
= _NEW_BUFFERS
|
1468 .brw
= BRW_NEW_BLORP
|
1470 BRW_NEW_FS_PROG_DATA
|
1471 BRW_NEW_GS_PROG_DATA
|
1472 BRW_NEW_VS_PROG_DATA
|
1473 BRW_NEW_META_IN_PROGRESS
|
1475 BRW_NEW_RASTERIZER_DISCARD
|
1476 BRW_NEW_TES_PROG_DATA
|
1477 BRW_NEW_VIEWPORT_COUNT
,
1479 .emit
= genX(upload_clip_state
),
1483 /* ---------------------------------------------------------------------- */
1486 genX(upload_sf
)(struct brw_context
*brw
)
1488 struct gl_context
*ctx
= &brw
->ctx
;
1493 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1494 UNUSED
const bool multisampled_fbo
=
1495 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1499 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1501 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1503 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1504 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1505 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1506 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1507 sf
.DispatchGRFStartRegisterForURBData
= 3;
1508 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1509 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1510 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1511 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1513 /* STATE_PREFETCH command description describes this state as being
1514 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1517 sf
.SetupViewportStateOffset
=
1518 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1520 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1522 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1523 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1525 sf
.MaximumNumberofThreads
=
1526 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1528 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1530 sf
.DestinationOriginHorizontalBias
= 0.5;
1531 sf
.DestinationOriginVerticalBias
= 0.5;
1533 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1534 sf
.StatisticsEnable
= true;
1536 sf
.ViewportTransformEnable
= true;
1540 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1545 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1547 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1548 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1549 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1551 switch (ctx
->Polygon
.FrontMode
) {
1553 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1556 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1559 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1562 unreachable("not reached");
1565 switch (ctx
->Polygon
.BackMode
) {
1567 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1570 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1573 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1576 unreachable("not reached");
1579 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1580 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1582 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1583 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1584 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1587 sf
.ScissorRectangleEnable
= true;
1589 if (ctx
->Polygon
.CullFlag
) {
1590 switch (ctx
->Polygon
.CullFaceMode
) {
1592 sf
.CullMode
= CULLMODE_FRONT
;
1595 sf
.CullMode
= CULLMODE_BACK
;
1597 case GL_FRONT_AND_BACK
:
1598 sf
.CullMode
= CULLMODE_BOTH
;
1601 unreachable("not reached");
1604 sf
.CullMode
= CULLMODE_NONE
;
1608 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1615 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1617 if (devinfo
->is_cherryview
)
1618 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1620 sf
.LineWidth
= brw_get_line_width(brw
);
1622 sf
.LineWidth
= brw_get_line_width(brw
);
1625 if (ctx
->Line
.SmoothFlag
) {
1626 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1628 sf
.AntiAliasingEnable
= true;
1632 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1633 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1634 /* Clamp to the hardware limits */
1635 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1637 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1638 if (use_state_point_size(brw
))
1639 sf
.PointWidthSource
= State
;
1642 /* _NEW_POINT | _NEW_MULTISAMPLE */
1643 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1644 !ctx
->Point
.PointSprite
)
1645 sf
.SmoothPointEnable
= true;
1650 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1652 const bool multisampled_fbo
=
1653 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1654 if (multisampled_fbo
)
1655 sf
.SmoothPointEnable
= false;
1658 #if GEN_IS_G4X || GEN_GEN >= 5
1659 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1663 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1664 sf
.TriangleStripListProvokingVertexSelect
= 2;
1665 sf
.TriangleFanProvokingVertexSelect
= 2;
1666 sf
.LineStripListProvokingVertexSelect
= 1;
1668 sf
.TriangleFanProvokingVertexSelect
= 1;
1672 /* BRW_NEW_FS_PROG_DATA */
1673 const struct brw_wm_prog_data
*wm_prog_data
=
1674 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1676 sf
.AttributeSwizzleEnable
= true;
1677 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1680 * Window coordinates in an FBO are inverted, which means point
1681 * sprite origin must be inverted, too.
1683 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1684 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1686 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1689 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1690 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1692 uint32_t urb_entry_read_length
;
1693 uint32_t urb_entry_read_offset
;
1694 uint32_t point_sprite_enables
;
1695 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1696 &urb_entry_read_length
,
1697 &urb_entry_read_offset
);
1698 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1699 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1700 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1701 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1706 static const struct brw_tracked_state
genX(sf_state
) = {
1708 .mesa
= _NEW_LIGHT
|
1712 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1713 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1714 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1715 .brw
= BRW_NEW_BLORP
|
1716 BRW_NEW_VUE_MAP_GEOM_OUT
|
1717 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1718 BRW_NEW_PROGRAM_CACHE
|
1719 BRW_NEW_SF_PROG_DATA
|
1723 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1724 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1725 BRW_NEW_GS_PROG_DATA
|
1727 BRW_NEW_TES_PROG_DATA
1729 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1730 BRW_NEW_FRAGMENT_PROGRAM
1733 .emit
= genX(upload_sf
),
1736 /* ---------------------------------------------------------------------- */
1739 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1741 struct gl_context
*ctx
= &brw
->ctx
;
1742 /* BRW_NEW_FRAGMENT_PROGRAM */
1743 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1747 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1748 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1749 uint64_t outputs_written
= fp
->info
.outputs_written
;
1752 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1753 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1754 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1763 genX(upload_wm
)(struct brw_context
*brw
)
1765 struct gl_context
*ctx
= &brw
->ctx
;
1767 /* BRW_NEW_FS_PROG_DATA */
1768 const struct brw_wm_prog_data
*wm_prog_data
=
1769 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1771 UNUSED
bool writes_depth
=
1772 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1773 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1774 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1777 /* We can't fold this into gen6_upload_wm_push_constants(), because
1778 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1779 * (3DSTATE_CONSTANT_PS [DevSNB]):
1781 * "[DevSNB]: This packet must be followed by WM_STATE."
1783 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1784 if (wm_prog_data
->base
.nr_params
!= 0) {
1785 wmcp
.Buffer0Valid
= true;
1786 /* Pointer to the WM constant buffer. Covered by the set of
1787 * state flags from gen6_upload_wm_push_constants.
1789 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1790 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1796 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1797 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1798 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1800 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1801 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1803 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1804 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1805 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1806 /* These two fields should be the same pre-gen6, which is why we
1807 * only have one hardware field to program for both dispatch
1810 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1811 wm_prog_data
->dispatch_grf_start_reg_2
);
1814 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1815 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1817 if (stage_state
->sampler_count
)
1818 wm
.SamplerStatePointer
=
1819 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1821 if (wm_prog_data
->prog_offset_2
)
1822 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1825 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1826 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1827 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1828 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1829 wm
.EarlyDepthTestEnable
= true;
1830 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1831 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1834 if (ctx
->Polygon
.OffsetFill
) {
1835 wm
.GlobalDepthOffsetEnable
= true;
1836 /* Something weird going on with legacy_global_depth_bias,
1837 * offset_constant, scaling and MRD. This value passes glean
1838 * but gives some odd results elsewere (eg. the
1839 * quad-offset-units test).
1841 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1843 /* This is the only value that passes glean:
1845 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1848 wm
.DepthCoefficientURBReadOffset
= 1;
1851 /* BRW_NEW_STATS_WM */
1852 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1855 if (wm_prog_data
->base
.use_alt_mode
)
1856 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1858 wm
.SamplerCount
= GEN_GEN
== 5 ?
1859 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1861 wm
.BindingTableEntryCount
=
1862 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1863 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1864 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1865 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1866 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1867 wm_prog_data
->base
.dispatch_grf_start_reg
;
1869 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1870 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1874 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1875 wm
.KernelStartPointer2
=
1876 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1881 wm
.DualSourceBlendEnable
=
1882 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1883 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1884 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1885 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1887 /* From the SNB PRM, volume 2 part 1, page 281:
1888 * "If the PS kernel does not need the Position XY Offsets
1889 * to compute a Position XY value, then this field should be
1890 * programmed to POSOFFSET_NONE."
1892 * "SW Recommendation: If the PS kernel needs the Position Offsets
1893 * to compute a Position XY value, this field should match Position
1894 * ZW Interpolation Mode to ensure a consistent position.xyzw
1896 * We only require XY sample offsets. So, this recommendation doesn't
1897 * look useful at the moment. We might need this in future.
1899 if (wm_prog_data
->uses_pos_offset
)
1900 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1902 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1904 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1905 wm_prog_data
->dispatch_grf_start_reg_2
;
1908 if (wm_prog_data
->base
.total_scratch
) {
1909 wm
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
1910 wm
.PerThreadScratchSpace
=
1911 ffs(stage_state
->per_thread_scratch
) - 11;
1914 wm
.PixelShaderComputedDepth
= writes_depth
;
1918 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1921 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1926 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1929 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1931 if (multisampled_fbo
) {
1932 /* _NEW_MULTISAMPLE */
1933 if (ctx
->Multisample
.Enabled
)
1934 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1936 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1938 if (wm_prog_data
->persample_dispatch
)
1939 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1941 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1943 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1944 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1947 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1948 if (wm_prog_data
->uses_kill
||
1949 _mesa_is_alpha_test_enabled(ctx
) ||
1950 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1951 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1952 wm
.PixelShaderKillsPixel
= true;
1955 /* _NEW_BUFFERS | _NEW_COLOR */
1956 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1957 wm
.PixelShaderKillsPixel
||
1958 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1959 wm
.ThreadDispatchEnable
= true;
1963 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1964 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1967 /* The "UAV access enable" bits are unnecessary on HSW because they only
1968 * seem to have an effect on the HW-assisted coherency mechanism which we
1969 * don't need, and the rasterization-related UAV_ONLY flag and the
1970 * DISPATCH_ENABLE bit can be set independently from it.
1971 * C.f. gen8_upload_ps_extra().
1973 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1977 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1978 wm_prog_data
->has_side_effects
)
1984 /* BRW_NEW_FS_PROG_DATA */
1985 if (wm_prog_data
->early_fragment_tests
)
1986 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1987 else if (wm_prog_data
->has_side_effects
)
1988 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1993 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
1994 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
1995 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1998 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
2003 static const struct brw_tracked_state
genX(wm_state
) = {
2007 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
2010 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2011 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2012 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2013 .brw
= BRW_NEW_BLORP
|
2014 BRW_NEW_FS_PROG_DATA
|
2015 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2016 BRW_NEW_FRAGMENT_PROGRAM
|
2017 BRW_NEW_PROGRAM_CACHE
|
2018 BRW_NEW_SAMPLER_STATE_TABLE
|
2021 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2023 .emit
= genX(upload_wm
),
2026 /* ---------------------------------------------------------------------- */
2028 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2029 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2030 pkt.SamplerCount = \
2031 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2032 pkt.BindingTableEntryCount = \
2033 stage_prog_data->binding_table.size_bytes / 4; \
2034 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2036 if (stage_prog_data->total_scratch) { \
2037 pkt.ScratchSpaceBasePointer = rw_bo(stage_state->scratch_bo, 0); \
2038 pkt.PerThreadScratchSpace = \
2039 ffs(stage_state->per_thread_scratch) - 11; \
2042 pkt.DispatchGRFStartRegisterForURBData = \
2043 stage_prog_data->dispatch_grf_start_reg; \
2044 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2045 pkt.prefix##URBEntryReadOffset = 0; \
2047 pkt.StatisticsEnable = true; \
2051 genX(upload_vs_state
)(struct brw_context
*brw
)
2053 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2054 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2055 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2057 /* BRW_NEW_VS_PROG_DATA */
2058 const struct brw_vue_prog_data
*vue_prog_data
=
2059 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2060 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2062 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2063 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2066 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2067 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2069 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2070 * command that causes the VS Function Enable to toggle. Pipeline
2071 * flush can be executed by sending a PIPE_CONTROL command with CS
2072 * stall bit set and a post sync operation.
2074 * We've already done such a flush at the start of state upload, so we
2075 * don't need to do another one here.
2077 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2078 if (stage_state
->push_const_size
!= 0) {
2079 cvs
.Buffer0Valid
= true;
2080 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2081 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2086 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2087 gen7_emit_vs_workaround_flush(brw
);
2090 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2092 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2093 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2095 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2097 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2100 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2101 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2102 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2104 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2105 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2107 vs
.MaximumNumberofThreads
=
2108 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2110 vs
.StatisticsEnable
= false;
2111 vs
.SamplerStatePointer
=
2112 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2116 /* Force single program flow on Ironlake. We cannot reliably get
2117 * all applications working without it. See:
2118 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2120 * The most notable and reliably failing application is the Humus
2123 vs
.SingleProgramFlow
= true;
2124 vs
.SamplerCount
= 0; /* hardware requirement */
2128 vs
.SIMD8DispatchEnable
=
2129 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2131 vs
.UserClipDistanceCullTestEnableBitmask
=
2132 vue_prog_data
->cull_distance_mask
;
2137 /* Based on my reading of the simulator, the VS constants don't get
2138 * pulled into the VS FF unit until an appropriate pipeline flush
2139 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2140 * references to them into a little FIFO. The flushes are common,
2141 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2142 * the primitive to use the wrong constants. Then the FIFO
2143 * containing the constant setup gets added to again on the next
2144 * constants change, and eventually when a flush does happen the
2145 * unit is overwhelmed by constant changes and dies.
2147 * To avoid this, send a PIPE_CONTROL down the line that will
2148 * update the unit immediately loading the constants. The flush
2149 * type bits here were those set by the STATE_BASE_ADDRESS whose
2150 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2151 * bug reports that led to this workaround, and may be more than
2152 * what is strictly required to avoid the issue.
2154 brw_emit_pipe_control_flush(brw
,
2155 PIPE_CONTROL_DEPTH_STALL
|
2156 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2157 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2161 static const struct brw_tracked_state
genX(vs_state
) = {
2163 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2164 .brw
= BRW_NEW_BATCH
|
2167 BRW_NEW_VS_PROG_DATA
|
2168 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2169 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2170 BRW_NEW_PROGRAM_CACHE
|
2171 BRW_NEW_SAMPLER_STATE_TABLE
|
2175 .emit
= genX(upload_vs_state
),
2178 /* ---------------------------------------------------------------------- */
2181 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2183 struct gl_context
*ctx
= &brw
->ctx
;
2185 /* BRW_NEW_VIEWPORT_COUNT */
2186 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2188 struct GENX(CC_VIEWPORT
) ccv
;
2189 uint32_t cc_vp_offset
;
2191 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2194 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2195 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2196 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2197 if (ctx
->Transform
.DepthClamp
) {
2198 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2199 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2201 ccv
.MinimumDepth
= 0.0;
2202 ccv
.MaximumDepth
= 1.0;
2204 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2205 cc_map
+= GENX(CC_VIEWPORT_length
);
2209 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2210 ptr
.CCViewportPointer
= cc_vp_offset
;
2213 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2214 vp
.CCViewportStateChange
= 1;
2215 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2218 brw
->cc
.vp_offset
= cc_vp_offset
;
2219 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2223 const struct brw_tracked_state
genX(cc_vp
) = {
2225 .mesa
= _NEW_TRANSFORM
|
2227 .brw
= BRW_NEW_BATCH
|
2229 BRW_NEW_VIEWPORT_COUNT
,
2231 .emit
= genX(upload_cc_viewport
)
2234 /* ---------------------------------------------------------------------- */
2237 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2238 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2239 struct GENX(SCISSOR_RECT
) *sc
)
2243 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2244 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2245 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2246 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2247 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2249 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2250 /* If the scissor was out of bounds and got clamped to 0 width/height
2251 * at the bounds, the subtraction of 1 from maximums could produce a
2252 * negative number and thus not clip anything. Instead, just provide
2253 * a min > max scissor inside the bounds, which produces the expected
2256 sc
->ScissorRectangleXMin
= 1;
2257 sc
->ScissorRectangleXMax
= 0;
2258 sc
->ScissorRectangleYMin
= 1;
2259 sc
->ScissorRectangleYMax
= 0;
2260 } else if (render_to_fbo
) {
2261 /* texmemory: Y=0=bottom */
2262 sc
->ScissorRectangleXMin
= bbox
[0];
2263 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2264 sc
->ScissorRectangleYMin
= bbox
[2];
2265 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2267 /* memory: Y=0=top */
2268 sc
->ScissorRectangleXMin
= bbox
[0];
2269 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2270 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2271 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2277 genX(upload_scissor_state
)(struct brw_context
*brw
)
2279 struct gl_context
*ctx
= &brw
->ctx
;
2280 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2281 struct GENX(SCISSOR_RECT
) scissor
;
2282 uint32_t scissor_state_offset
;
2283 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2284 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2285 uint32_t *scissor_map
;
2287 /* BRW_NEW_VIEWPORT_COUNT */
2288 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2290 scissor_map
= brw_state_batch(
2291 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2292 32, &scissor_state_offset
);
2294 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2296 /* The scissor only needs to handle the intersection of drawable and
2297 * scissor rect. Clipping to the boundaries of static shared buffers
2298 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2300 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2301 * inclusive but max is exclusive.
2303 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2304 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2305 GENX(SCISSOR_RECT_pack
)(
2306 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2309 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2310 ptr
.ScissorRectPointer
= scissor_state_offset
;
2314 static const struct brw_tracked_state
genX(scissor_state
) = {
2316 .mesa
= _NEW_BUFFERS
|
2319 .brw
= BRW_NEW_BATCH
|
2321 BRW_NEW_VIEWPORT_COUNT
,
2323 .emit
= genX(upload_scissor_state
),
2327 /* ---------------------------------------------------------------------- */
2330 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2331 float m00
, float m11
, float m30
, float m31
,
2332 float *xmin
, float *xmax
,
2333 float *ymin
, float *ymax
)
2335 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2336 * Strips and Fans documentation:
2338 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2339 * fixed-point "guardband" range supported by the rasterization hardware"
2343 * "In almost all circumstances, if an object’s vertices are actually
2344 * modified by this clamping (i.e., had X or Y coordinates outside of
2345 * the guardband extent the rendered object will not match the intended
2346 * result. Therefore software should take steps to ensure that this does
2347 * not happen - e.g., by clipping objects such that they do not exceed
2348 * these limits after the Drawing Rectangle is applied."
2350 * I believe the fundamental restriction is that the rasterizer (in
2351 * the SF/WM stages) have a limit on the number of pixels that can be
2352 * rasterized. We need to ensure any coordinates beyond the rasterizer
2353 * limit are handled by the clipper. So effectively that limit becomes
2354 * the clipper's guardband size.
2356 * It goes on to say:
2358 * "In addition, in order to be correctly rendered, objects must have a
2359 * screenspace bounding box not exceeding 8K in the X or Y direction.
2360 * This additional restriction must also be comprehended by software,
2361 * i.e., enforced by use of clipping."
2363 * This makes no sense. Gen7+ hardware supports 16K render targets,
2364 * and you definitely need to be able to draw polygons that fill the
2365 * surface. Our assumption is that the rasterizer was limited to 8K
2366 * on Sandybridge, which only supports 8K surfaces, and it was actually
2367 * increased to 16K on Ivybridge and later.
2369 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2371 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2373 if (m00
!= 0 && m11
!= 0) {
2374 /* First, we compute the screen-space render area */
2375 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2376 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2377 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2378 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2380 /* We want the guardband to be centered on that */
2381 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2382 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2383 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2384 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2386 /* Now we need it in native device coordinates */
2387 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2388 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2389 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2390 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2392 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2393 * flipped upside-down. X should be fine though.
2395 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2396 *xmin
= ndc_gb_xmin
;
2397 *xmax
= ndc_gb_xmax
;
2398 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2399 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2401 /* The viewport scales to 0, so nothing will be rendered. */
2410 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2412 struct gl_context
*ctx
= &brw
->ctx
;
2413 float y_scale
, y_bias
;
2415 /* BRW_NEW_VIEWPORT_COUNT */
2416 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2419 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2420 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2421 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2425 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2426 uint32_t sf_clip_vp_offset
;
2427 uint32_t *sf_clip_map
=
2428 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2429 64, &sf_clip_vp_offset
);
2431 struct GENX(SF_VIEWPORT
) sfv
;
2432 struct GENX(CLIP_VIEWPORT
) clv
;
2433 uint32_t sf_vp_offset
, clip_vp_offset
;
2435 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2437 uint32_t *clip_map
=
2438 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2439 32, &clip_vp_offset
);
2443 if (render_to_fbo
) {
2448 y_bias
= (float)fb_height
;
2451 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2452 /* _NEW_VIEWPORT: Guardband Clipping */
2453 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2454 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2456 sfv
.ViewportMatrixElementm00
= scale
[0];
2457 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2458 sfv
.ViewportMatrixElementm22
= scale
[2],
2459 sfv
.ViewportMatrixElementm30
= translate
[0],
2460 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2461 sfv
.ViewportMatrixElementm32
= translate
[2],
2462 brw_calculate_guardband_size(fb_width
, fb_height
,
2463 sfv
.ViewportMatrixElementm00
,
2464 sfv
.ViewportMatrixElementm11
,
2465 sfv
.ViewportMatrixElementm30
,
2466 sfv
.ViewportMatrixElementm31
,
2467 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2470 clv
.XMinClipGuardband
= gb_xmin
;
2471 clv
.XMaxClipGuardband
= gb_xmax
;
2472 clv
.YMinClipGuardband
= gb_ymin
;
2473 clv
.YMaxClipGuardband
= gb_ymax
;
2476 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2477 &sfv
.ScissorRectangle
);
2479 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2480 * The hardware will take the intersection of the drawing rectangle,
2481 * scissor rectangle, and the viewport extents. We don't need to be
2482 * smart, and can therefore just program the viewport extents.
2484 const float viewport_Xmax
=
2485 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2486 const float viewport_Ymax
=
2487 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2489 if (render_to_fbo
) {
2490 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2491 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2492 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2493 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2495 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2496 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2497 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2498 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2503 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2504 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2506 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2507 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2508 sf_map
+= GENX(SF_VIEWPORT_length
);
2509 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2514 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2515 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2518 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2519 vp
.SFViewportStateChange
= 1;
2520 vp
.CLIPViewportStateChange
= 1;
2521 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2522 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2525 brw
->sf
.vp_offset
= sf_vp_offset
;
2526 brw
->clip
.vp_offset
= clip_vp_offset
;
2527 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2531 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2533 .mesa
= _NEW_BUFFERS
|
2535 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2536 .brw
= BRW_NEW_BATCH
|
2538 BRW_NEW_VIEWPORT_COUNT
,
2540 .emit
= genX(upload_sf_clip_viewport
),
2543 /* ---------------------------------------------------------------------- */
2546 genX(upload_gs_state
)(struct brw_context
*brw
)
2548 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2549 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2550 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2551 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2552 /* BRW_NEW_GEOMETRY_PROGRAM */
2553 bool active
= GEN_GEN
>= 6 && gs_prog
;
2555 /* BRW_NEW_GS_PROG_DATA */
2556 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2557 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2558 brw_vue_prog_data(stage_prog_data
);
2560 const struct brw_gs_prog_data
*gs_prog_data
=
2561 brw_gs_prog_data(stage_prog_data
);
2565 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2566 if (active
&& stage_state
->push_const_size
!= 0) {
2567 cgs
.Buffer0Valid
= true;
2568 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2569 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2574 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2576 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2577 * Geometry > Geometry Shader > State:
2579 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2580 * whole fixed function pipeline when the GS enable changes value in
2583 * The hardware architects have clarified that in this context "flush the
2584 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2587 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2588 gen7_emit_cs_stall_flush(brw
);
2592 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2594 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2595 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2600 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2603 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2604 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2605 gs
.ControlDataHeaderSize
=
2606 gs_prog_data
->control_data_header_size_hwords
;
2608 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2609 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2611 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2613 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2616 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2617 * Ivy Bridge and Haswell.
2619 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2620 * strip to be delivered to the geometry shader in an order that does
2621 * not strictly follow the OpenGL spec, but preserves triangle
2622 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2623 * the geometry shader sees triangles:
2625 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2627 * (Clearing the bit is even worse, because it fails to preserve
2630 * Triangle strips with adjacency always ordered in a way that preserves
2631 * triangle orientation but does not strictly follow the OpenGL spec,
2632 * regardless of the setting of this bit.
2634 * On Haswell, both triangle strips and triangle strips with adjacency
2635 * are always ordered in a way that preserves triangle orientation.
2636 * Setting this bit causes the ordering to strictly follow the OpenGL
2639 * So in either case we want to set the bit. Unfortunately on Ivy
2640 * Bridge this will get the order close to correct but not perfect.
2642 gs
.ReorderMode
= TRAILING
;
2643 gs
.MaximumNumberofThreads
=
2644 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2645 : (devinfo
->max_gs_threads
- 1);
2648 gs
.SOStatisticsEnable
= true;
2649 if (gs_prog
->info
.has_transform_feedback_varyings
)
2650 gs
.SVBIPayloadEnable
= true;
2652 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2653 * was previously done for gen6.
2655 * TODO: test with both disabled to see if the HW is behaving
2656 * as expected, like in gen7.
2658 gs
.SingleProgramFlow
= true;
2659 gs
.VectorMaskEnable
= true;
2663 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2665 if (gs_prog_data
->static_vertex_count
!= -1) {
2666 gs
.StaticOutput
= true;
2667 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2669 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2671 gs
.UserClipDistanceCullTestEnableBitmask
=
2672 vue_prog_data
->cull_distance_mask
;
2674 const int urb_entry_write_offset
= 1;
2675 const uint32_t urb_entry_output_length
=
2676 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2677 urb_entry_write_offset
;
2679 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2680 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2686 if (!active
&& brw
->ff_gs
.prog_active
) {
2687 /* In gen6, transform feedback for the VS stage is done with an
2688 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2691 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2692 gs
.SingleProgramFlow
= true;
2693 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2694 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2697 gs
.GRFRegisterCount
=
2698 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2699 /* BRW_NEW_URB_FENCE */
2700 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2701 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2702 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2703 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2706 gs
.VectorMaskEnable
= true;
2707 gs
.SVBIPayloadEnable
= true;
2708 gs
.SVBIPostIncrementEnable
= true;
2709 gs
.SVBIPostIncrementValue
=
2710 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2711 gs
.SOStatisticsEnable
= true;
2712 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2716 if (!active
&& !brw
->ff_gs
.prog_active
) {
2718 gs
.DispatchGRFStartRegisterForURBData
= 1;
2720 gs
.IncludeVertexHandles
= true;
2726 gs
.StatisticsEnable
= true;
2728 #if GEN_GEN == 5 || GEN_GEN == 6
2729 gs
.RenderingEnabled
= true;
2732 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2737 brw
->gs
.enabled
= active
;
2741 static const struct brw_tracked_state
genX(gs_state
) = {
2743 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2744 .brw
= BRW_NEW_BATCH
|
2746 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2747 BRW_NEW_PROGRAM_CACHE
|
2749 BRW_NEW_VIEWPORT_COUNT
2751 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2752 BRW_NEW_GEOMETRY_PROGRAM
|
2753 BRW_NEW_GS_PROG_DATA
2755 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2757 .emit
= genX(upload_gs_state
),
2760 /* ---------------------------------------------------------------------- */
2762 UNUSED
static GLenum
2763 fix_dual_blend_alpha_to_one(GLenum function
)
2769 case GL_ONE_MINUS_SRC1_ALPHA
:
2776 #define blend_factor(x) brw_translate_blend_factor(x)
2777 #define blend_eqn(x) brw_translate_blend_equation(x)
2780 * Modify blend function to force destination alpha to 1.0
2782 * If \c function specifies a blend function that uses destination alpha,
2783 * replace it with a function that hard-wires destination alpha to 1.0. This
2784 * is used when rendering to xRGB targets.
2787 brw_fix_xRGB_alpha(GLenum function
)
2793 case GL_ONE_MINUS_DST_ALPHA
:
2794 case GL_SRC_ALPHA_SATURATE
:
2802 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2804 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2808 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2811 struct gl_context
*ctx
= &brw
->ctx
;
2814 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2816 bool independent_alpha_blend
= false;
2818 /* Used for implementing the following bit of GL_EXT_texture_integer:
2819 * "Per-fragment operations that require floating-point color
2820 * components, including multisample alpha operations, alpha test,
2821 * blending, and dithering, have no effect when the corresponding
2822 * colors are written to an integer color buffer."
2824 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2826 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2827 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2830 if (ctx
->Color
.ColorLogicOpEnabled
) {
2831 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2832 : GL_UNSIGNED_NORMALIZED
;
2833 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2834 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2835 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2837 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2838 _mesa_enum_to_string(rb_type
));
2839 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2840 entry
->LogicOpEnable
= true;
2841 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2843 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2844 && (GEN_GEN
<= 5 || !integer
)) {
2845 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2846 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2847 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2848 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2849 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2850 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2852 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2853 srcRGB
= dstRGB
= GL_ONE
;
2855 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2856 srcA
= dstA
= GL_ONE
;
2858 /* Due to hardware limitations, the destination may have information
2859 * in an alpha channel even when the format specifies no alpha
2860 * channel. In order to avoid getting any incorrect blending due to
2861 * that alpha channel, coerce the blend factors to values that will
2862 * not read the alpha channel, but will instead use the correct
2863 * implicit value for alpha.
2865 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2866 GL_TEXTURE_ALPHA_TYPE
)) {
2867 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2868 srcA
= brw_fix_xRGB_alpha(srcA
);
2869 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2870 dstA
= brw_fix_xRGB_alpha(dstA
);
2873 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2874 * "If Dual Source Blending is enabled, this bit must be disabled."
2876 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2877 * and leave it enabled anyway.
2879 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2880 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2881 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2882 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2883 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2886 entry
->ColorBufferBlendEnable
= true;
2887 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2888 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2889 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2890 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2891 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2892 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2894 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2895 independent_alpha_blend
= true;
2898 return independent_alpha_blend
;
2903 genX(upload_blend_state
)(struct brw_context
*brw
)
2905 struct gl_context
*ctx
= &brw
->ctx
;
2908 /* We need at least one BLEND_STATE written, because we might do
2909 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2910 * for computed depth or alpha test), which will do an FB write
2911 * with render target 0, which will reference BLEND_STATE[0] for
2912 * alpha test enable.
2914 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2915 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2916 nr_draw_buffers
= 1;
2918 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2920 size
+= GENX(BLEND_STATE_length
) * 4;
2923 uint32_t *blend_map
;
2924 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2927 struct GENX(BLEND_STATE
) blend
= { 0 };
2930 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2931 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2934 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2935 * "If drawbuffer zero is not NONE and the buffer it references has an
2936 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2937 * operations are skipped."
2939 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2940 /* _NEW_MULTISAMPLE */
2941 if (_mesa_is_multisample_enabled(ctx
)) {
2942 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2943 blend
.AlphaToCoverageEnable
= true;
2944 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2946 if (ctx
->Multisample
.SampleAlphaToOne
)
2947 blend
.AlphaToOneEnable
= true;
2951 if (ctx
->Color
.AlphaEnabled
) {
2952 blend
.AlphaTestEnable
= true;
2953 blend
.AlphaTestFunction
=
2954 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2957 if (ctx
->Color
.DitherFlag
) {
2958 blend
.ColorDitherEnable
= true;
2963 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2964 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2968 blend
.IndependentAlphaBlendEnable
=
2969 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
2970 blend
.IndependentAlphaBlendEnable
;
2972 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2973 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2975 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2976 * clamping in the fragment shader. For its clamping of
2977 * blending, the spec says:
2979 * "RESOLVED: For fixed-point color buffers, the inputs and
2980 * the result of the blending equation are clamped. For
2981 * floating-point color buffers, no clamping occurs."
2983 * So, generally, we want clamping to the render target's range.
2984 * And, good news, the hardware tables for both pre- and
2985 * post-blend color clamping are either ignored, or any are
2986 * allowed, or clamping is required but RT range clamping is a
2989 entry
.PreBlendColorClampEnable
= true;
2990 entry
.PostBlendColorClampEnable
= true;
2991 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2993 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
2994 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
2995 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
2996 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
2999 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
3001 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3007 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3011 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3012 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3013 ptr
.BLEND_STATEChange
= true;
3016 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3017 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3019 ptr
.BlendStatePointerValid
= true;
3025 static const struct brw_tracked_state
genX(blend_state
) = {
3027 .mesa
= _NEW_BUFFERS
|
3030 .brw
= BRW_NEW_BATCH
|
3032 BRW_NEW_STATE_BASE_ADDRESS
,
3034 .emit
= genX(upload_blend_state
),
3038 /* ---------------------------------------------------------------------- */
3041 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3042 [MESA_SHADER_VERTEX
] = 21,
3043 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3044 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3045 [MESA_SHADER_GEOMETRY
] = 22,
3046 [MESA_SHADER_FRAGMENT
] = 23,
3047 [MESA_SHADER_COMPUTE
] = 0,
3051 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3053 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3054 struct gl_context
*ctx
= &brw
->ctx
;
3056 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3058 struct brw_stage_state
*stage_states
[] = {
3066 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3067 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3068 gen7_emit_vs_workaround_flush(brw
);
3070 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3071 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3072 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3074 if (!stage_state
->push_constants_dirty
)
3077 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3078 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3079 if (stage_state
->prog_data
) {
3080 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3081 /* The Skylake PRM contains the following restriction:
3083 * "The driver must ensure The following case does not occur
3084 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3085 * buffer 3 read length equal to zero committed followed by a
3086 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3089 * To avoid this, we program the buffers in the highest slots.
3090 * This way, slot 0 is only used if slot 3 is also used.
3094 for (int i
= 3; i
>= 0; i
--) {
3095 const struct brw_ubo_range
*range
=
3096 &stage_state
->prog_data
->ubo_ranges
[i
];
3098 if (range
->length
== 0)
3101 const struct gl_uniform_block
*block
=
3102 prog
->sh
.UniformBlocks
[range
->block
];
3103 const struct gl_buffer_binding
*binding
=
3104 &ctx
->UniformBufferBindings
[block
->Binding
];
3106 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3107 static unsigned msg_id
= 0;
3108 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3109 MESA_DEBUG_TYPE_UNDEFINED
,
3110 MESA_DEBUG_SEVERITY_HIGH
,
3111 "UBO %d unbound, %s shader uniform data "
3112 "will be undefined.",
3114 _mesa_shader_stage_to_string(stage
));
3118 assert(binding
->Offset
% 32 == 0);
3120 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3121 intel_buffer_object(binding
->BufferObject
),
3122 binding
->Offset
, range
->length
* 32, false);
3124 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3125 pkt
.ConstantBody
.Buffer
[n
] =
3126 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3130 if (stage_state
->push_const_size
> 0) {
3132 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3133 pkt
.ConstantBody
.Buffer
[n
] =
3134 ro_bo(stage_state
->push_const_bo
,
3135 stage_state
->push_const_offset
);
3138 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3139 pkt
.ConstantBody
.Buffer
[0].offset
=
3140 stage_state
->push_const_offset
| mocs
;
3145 stage_state
->push_constants_dirty
= false;
3146 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3150 const struct brw_tracked_state
genX(push_constant_packets
) = {
3153 .brw
= BRW_NEW_DRAW_CALL
,
3155 .emit
= genX(upload_push_constant_packets
),
3161 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3163 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3165 /* BRW_NEW_VERTEX_PROGRAM */
3166 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3167 /* BRW_NEW_VS_PROG_DATA */
3168 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3170 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3173 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3175 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3177 .brw
= BRW_NEW_BATCH
|
3179 BRW_NEW_VERTEX_PROGRAM
|
3180 BRW_NEW_VS_PROG_DATA
,
3182 .emit
= genX(upload_vs_push_constants
),
3186 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3188 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3190 /* BRW_NEW_GEOMETRY_PROGRAM */
3191 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3193 /* BRW_NEW_GS_PROG_DATA */
3194 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3196 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3199 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3201 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3203 .brw
= BRW_NEW_BATCH
|
3205 BRW_NEW_GEOMETRY_PROGRAM
|
3206 BRW_NEW_GS_PROG_DATA
,
3208 .emit
= genX(upload_gs_push_constants
),
3212 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3214 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3215 /* BRW_NEW_FRAGMENT_PROGRAM */
3216 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3217 /* BRW_NEW_FS_PROG_DATA */
3218 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3220 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3223 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3225 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3226 .brw
= BRW_NEW_BATCH
|
3228 BRW_NEW_FRAGMENT_PROGRAM
|
3229 BRW_NEW_FS_PROG_DATA
,
3231 .emit
= genX(upload_wm_push_constants
),
3235 /* ---------------------------------------------------------------------- */
3239 genX(determine_sample_mask
)(struct brw_context
*brw
)
3241 struct gl_context
*ctx
= &brw
->ctx
;
3242 float coverage
= 1.0f
;
3243 float coverage_invert
= false;
3244 unsigned sample_mask
= ~0u;
3246 /* BRW_NEW_NUM_SAMPLES */
3247 unsigned num_samples
= brw
->num_samples
;
3249 if (_mesa_is_multisample_enabled(ctx
)) {
3250 if (ctx
->Multisample
.SampleCoverage
) {
3251 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3252 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3254 if (ctx
->Multisample
.SampleMask
) {
3255 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3259 if (num_samples
> 1) {
3260 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3261 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3262 if (coverage_invert
)
3263 coverage_bits
^= (1 << num_samples
) - 1;
3264 return coverage_bits
& sample_mask
;
3271 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3272 unsigned num_samples
)
3274 unsigned log2_samples
= ffs(num_samples
) - 1;
3276 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3277 multi
.PixelLocation
= CENTER
;
3278 multi
.NumberofMultisamples
= log2_samples
;
3280 GEN_SAMPLE_POS_4X(multi
.Sample
);
3282 switch (num_samples
) {
3284 GEN_SAMPLE_POS_1X(multi
.Sample
);
3287 GEN_SAMPLE_POS_2X(multi
.Sample
);
3290 GEN_SAMPLE_POS_4X(multi
.Sample
);
3293 GEN_SAMPLE_POS_8X(multi
.Sample
);
3303 genX(upload_multisample_state
)(struct brw_context
*brw
)
3305 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3307 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3309 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3310 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3314 static const struct brw_tracked_state
genX(multisample_state
) = {
3316 .mesa
= _NEW_MULTISAMPLE
|
3317 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3318 .brw
= BRW_NEW_BLORP
|
3320 BRW_NEW_NUM_SAMPLES
,
3322 .emit
= genX(upload_multisample_state
)
3326 /* ---------------------------------------------------------------------- */
3329 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3331 struct gl_context
*ctx
= &brw
->ctx
;
3333 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3335 cc
.IndependentAlphaBlendEnable
=
3336 set_blend_entry_bits(brw
, &cc
, 0, false);
3337 set_depth_stencil_bits(brw
, &cc
);
3339 if (ctx
->Color
.AlphaEnabled
&&
3340 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3341 cc
.AlphaTestEnable
= true;
3342 cc
.AlphaTestFunction
=
3343 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3346 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3348 cc
.StatisticsEnable
= brw
->stats_wm
;
3350 cc
.CCViewportStatePointer
=
3351 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3354 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3355 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3356 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3357 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3361 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3362 cc
.BackfaceStencilReferenceValue
=
3363 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3369 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3370 ctx
->Color
.AlphaRef
);
3374 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3375 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3377 ptr
.ColorCalcStatePointerValid
= true;
3381 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3385 static const struct brw_tracked_state
genX(color_calc_state
) = {
3387 .mesa
= _NEW_COLOR
|
3389 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3392 .brw
= BRW_NEW_BATCH
|
3394 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3396 : BRW_NEW_CC_STATE
|
3397 BRW_NEW_STATE_BASE_ADDRESS
),
3399 .emit
= genX(upload_color_calc_state
),
3403 /* ---------------------------------------------------------------------- */
3407 genX(upload_sbe
)(struct brw_context
*brw
)
3409 struct gl_context
*ctx
= &brw
->ctx
;
3410 /* BRW_NEW_FRAGMENT_PROGRAM */
3411 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3412 /* BRW_NEW_FS_PROG_DATA */
3413 const struct brw_wm_prog_data
*wm_prog_data
=
3414 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3416 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3418 #define attr_overrides sbe.Attribute
3420 uint32_t urb_entry_read_length
;
3421 uint32_t urb_entry_read_offset
;
3422 uint32_t point_sprite_enables
;
3424 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3425 sbe
.AttributeSwizzleEnable
= true;
3426 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3429 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3433 * Window coordinates in an FBO are inverted, which means point
3434 * sprite origin must be inverted.
3436 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3437 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3439 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3441 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3442 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3443 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3444 * BRW_NEW_VUE_MAP_GEOM_OUT
3446 genX(calculate_attr_overrides
)(brw
,
3448 &point_sprite_enables
,
3449 &urb_entry_read_length
,
3450 &urb_entry_read_offset
);
3452 /* Typically, the URB entry read length and offset should be programmed
3453 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3454 * stage which produces geometry. However, we don't know the proper
3455 * value until we call calculate_attr_overrides().
3457 * To fit with our existing code, we override the inherited values and
3458 * specify it here directly, as we did on previous generations.
3460 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3461 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3462 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3463 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3466 sbe
.ForceVertexURBEntryReadLength
= true;
3467 sbe
.ForceVertexURBEntryReadOffset
= true;
3471 /* prepare the active component dwords */
3472 const int num_inputs
= urb_entry_read_length
* 2;
3473 for (int input_index
= 0; input_index
< num_inputs
; input_index
++) {
3474 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3480 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3481 for (int i
= 0; i
< 16; i
++)
3482 sbes
.Attribute
[i
] = attr_overrides
[i
];
3486 #undef attr_overrides
3489 static const struct brw_tracked_state
genX(sbe_state
) = {
3491 .mesa
= _NEW_BUFFERS
|
3496 .brw
= BRW_NEW_BLORP
|
3498 BRW_NEW_FRAGMENT_PROGRAM
|
3499 BRW_NEW_FS_PROG_DATA
|
3500 BRW_NEW_GS_PROG_DATA
|
3501 BRW_NEW_TES_PROG_DATA
|
3502 BRW_NEW_VUE_MAP_GEOM_OUT
|
3503 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3506 .emit
= genX(upload_sbe
),
3510 /* ---------------------------------------------------------------------- */
3514 * Outputs the 3DSTATE_SO_DECL_LIST command.
3516 * The data output is a series of 64-bit entries containing a SO_DECL per
3517 * stream. We only have one stream of rendering coming out of the GS unit, so
3518 * we only emit stream 0 (low 16 bits) SO_DECLs.
3521 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3522 const struct brw_vue_map
*vue_map
)
3524 struct gl_context
*ctx
= &brw
->ctx
;
3525 /* BRW_NEW_TRANSFORM_FEEDBACK */
3526 struct gl_transform_feedback_object
*xfb_obj
=
3527 ctx
->TransformFeedback
.CurrentObject
;
3528 const struct gl_transform_feedback_info
*linked_xfb_info
=
3529 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3530 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3531 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3532 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3533 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3535 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3537 memset(so_decl
, 0, sizeof(so_decl
));
3539 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3540 * command feels strange -- each dword pair contains a SO_DECL per stream.
3542 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3543 const struct gl_transform_feedback_output
*output
=
3544 &linked_xfb_info
->Outputs
[i
];
3545 const int buffer
= output
->OutputBuffer
;
3546 const int varying
= output
->OutputRegister
;
3547 const unsigned stream_id
= output
->StreamId
;
3548 assert(stream_id
< MAX_VERTEX_STREAMS
);
3550 buffer_mask
[stream_id
] |= 1 << buffer
;
3552 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3554 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3555 * array. Instead, it simply increments DstOffset for the following
3556 * input by the number of components that should be skipped.
3558 * Our hardware is unusual in that it requires us to program SO_DECLs
3559 * for fake "hole" components, rather than simply taking the offset
3560 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3561 * program as many size = 4 holes as we can, then a final hole to
3562 * accommodate the final 1, 2, or 3 remaining.
3564 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3566 while (skip_components
> 0) {
3567 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3569 .OutputBufferSlot
= output
->OutputBuffer
,
3570 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3572 skip_components
-= 4;
3575 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3577 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3578 .OutputBufferSlot
= output
->OutputBuffer
,
3579 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3581 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3584 if (decls
[stream_id
] > max_decls
)
3585 max_decls
= decls
[stream_id
];
3589 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3590 .StreamtoBufferSelects0
= buffer_mask
[0],
3591 .StreamtoBufferSelects1
= buffer_mask
[1],
3592 .StreamtoBufferSelects2
= buffer_mask
[2],
3593 .StreamtoBufferSelects3
= buffer_mask
[3],
3594 .NumEntries0
= decls
[0],
3595 .NumEntries1
= decls
[1],
3596 .NumEntries2
= decls
[2],
3597 .NumEntries3
= decls
[3]);
3599 for (int i
= 0; i
< max_decls
; i
++) {
3600 GENX(SO_DECL_ENTRY_pack
)(
3601 brw
, dw
+ 2 + i
* 2,
3602 &(struct GENX(SO_DECL_ENTRY
)) {
3603 .Stream0Decl
= so_decl
[0][i
],
3604 .Stream1Decl
= so_decl
[1][i
],
3605 .Stream2Decl
= so_decl
[2][i
],
3606 .Stream3Decl
= so_decl
[3][i
],
3612 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3614 struct gl_context
*ctx
= &brw
->ctx
;
3615 /* BRW_NEW_TRANSFORM_FEEDBACK */
3616 struct gl_transform_feedback_object
*xfb_obj
=
3617 ctx
->TransformFeedback
.CurrentObject
;
3619 const struct gl_transform_feedback_info
*linked_xfb_info
=
3620 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3622 struct brw_transform_feedback_object
*brw_obj
=
3623 (struct brw_transform_feedback_object
*) xfb_obj
;
3624 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3627 /* Set up the up to 4 output buffers. These are the ranges defined in the
3628 * gl_transform_feedback_object.
3630 for (int i
= 0; i
< 4; i
++) {
3631 struct intel_buffer_object
*bufferobj
=
3632 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3635 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3636 sob
.SOBufferIndex
= i
;
3641 uint32_t start
= xfb_obj
->Offset
[i
];
3642 assert(start
% 4 == 0);
3643 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3645 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3646 assert(end
<= bo
->size
);
3648 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3649 sob
.SOBufferIndex
= i
;
3651 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3653 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3654 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3656 sob
.SOBufferEnable
= true;
3657 sob
.StreamOffsetWriteEnable
= true;
3658 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3659 sob
.SOBufferMOCS
= mocs_wb
;
3661 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3662 sob
.StreamOutputBufferOffsetAddress
=
3663 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3665 if (brw_obj
->zero_offsets
) {
3666 /* Zero out the offset and write that to offset_bo */
3667 sob
.StreamOffset
= 0;
3669 /* Use offset_bo as the "Stream Offset." */
3670 sob
.StreamOffset
= 0xFFFFFFFF;
3677 brw_obj
->zero_offsets
= false;
3682 query_active(struct gl_query_object
*q
)
3684 return q
&& q
->Active
;
3688 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3689 const struct brw_vue_map
*vue_map
)
3691 struct gl_context
*ctx
= &brw
->ctx
;
3692 /* BRW_NEW_TRANSFORM_FEEDBACK */
3693 struct gl_transform_feedback_object
*xfb_obj
=
3694 ctx
->TransformFeedback
.CurrentObject
;
3696 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3698 int urb_entry_read_offset
= 0;
3699 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3700 urb_entry_read_offset
;
3702 sos
.SOFunctionEnable
= true;
3703 sos
.SOStatisticsEnable
= true;
3705 /* BRW_NEW_RASTERIZER_DISCARD */
3706 if (ctx
->RasterDiscard
) {
3707 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3708 sos
.RenderingDisable
= true;
3710 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3711 "query active relies on the clipper.\n");
3716 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3717 sos
.ReorderMode
= TRAILING
;
3720 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3721 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3722 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3723 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3725 const struct gl_transform_feedback_info
*linked_xfb_info
=
3726 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3727 /* Set buffer pitches; 0 means unbound. */
3728 if (xfb_obj
->Buffers
[0])
3729 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3730 if (xfb_obj
->Buffers
[1])
3731 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3732 if (xfb_obj
->Buffers
[2])
3733 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3734 if (xfb_obj
->Buffers
[3])
3735 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3738 /* We always read the whole vertex. This could be reduced at some
3739 * point by reading less and offsetting the register index in the
3742 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3743 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3744 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3745 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3746 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3747 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3748 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3749 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3755 genX(upload_sol
)(struct brw_context
*brw
)
3757 struct gl_context
*ctx
= &brw
->ctx
;
3758 /* BRW_NEW_TRANSFORM_FEEDBACK */
3759 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3762 genX(upload_3dstate_so_buffers
)(brw
);
3764 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3765 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3768 /* Finally, set up the SOL stage. This command must always follow updates to
3769 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3770 * MMIO register updates (current performed by the kernel at each batch
3773 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3776 static const struct brw_tracked_state
genX(sol_state
) = {
3779 .brw
= BRW_NEW_BATCH
|
3781 BRW_NEW_RASTERIZER_DISCARD
|
3782 BRW_NEW_VUE_MAP_GEOM_OUT
|
3783 BRW_NEW_TRANSFORM_FEEDBACK
,
3785 .emit
= genX(upload_sol
),
3789 /* ---------------------------------------------------------------------- */
3793 genX(upload_ps
)(struct brw_context
*brw
)
3795 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3796 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3798 /* BRW_NEW_FS_PROG_DATA */
3799 const struct brw_wm_prog_data
*prog_data
=
3800 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3801 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3806 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3807 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3808 * incorrect for subspans where some of the pixels are unlit. We believe
3809 * the bit just didn't take effect in previous generations.
3811 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3814 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3816 /* BRW_NEW_FS_PROG_DATA */
3817 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3819 if (prog_data
->base
.use_alt_mode
)
3820 ps
.FloatingPointMode
= Alternate
;
3822 /* Haswell requires the sample mask to be set in this packet as well as
3823 * in 3DSTATE_SAMPLE_MASK; the values should match.
3826 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3828 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3831 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3832 * it implicitly scales for different GT levels (which have some # of
3835 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3838 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3840 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3842 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3845 if (prog_data
->base
.nr_params
> 0 ||
3846 prog_data
->base
.ubo_ranges
[0].length
> 0)
3847 ps
.PushConstantEnable
= true;
3850 /* From the IVB PRM, volume 2 part 1, page 287:
3851 * "This bit is inserted in the PS payload header and made available to
3852 * the DataPort (either via the message header or via header bypass) to
3853 * indicate that oMask data (one or two phases) is included in Render
3854 * Target Write messages. If present, the oMask data is used to mask off
3857 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3859 /* The hardware wedges if you have this bit set but don't turn on any
3860 * dual source blend factors.
3862 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3864 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3865 (ctx
->Color
.BlendEnabled
& 1) &&
3866 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3868 /* BRW_NEW_FS_PROG_DATA */
3869 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3872 /* From the documentation for this packet:
3873 * "If the PS kernel does not need the Position XY Offsets to
3874 * compute a Position Value, then this field should be programmed
3875 * to POSOFFSET_NONE."
3877 * "SW Recommendation: If the PS kernel needs the Position Offsets
3878 * to compute a Position XY value, this field should match Position
3879 * ZW Interpolation Mode to ensure a consistent position.xyzw
3882 * We only require XY sample offsets. So, this recommendation doesn't
3883 * look useful at the moment. We might need this in future.
3885 if (prog_data
->uses_pos_offset
)
3886 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3888 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3890 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3891 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3892 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3893 prog_data
->base
.dispatch_grf_start_reg
;
3894 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3895 prog_data
->dispatch_grf_start_reg_2
;
3897 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3898 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3899 prog_data
->prog_offset_2
;
3901 if (prog_data
->base
.total_scratch
) {
3902 ps
.ScratchSpaceBasePointer
=
3903 rw_bo(stage_state
->scratch_bo
,
3904 ffs(stage_state
->per_thread_scratch
) - 11);
3909 static const struct brw_tracked_state
genX(ps_state
) = {
3911 .mesa
= _NEW_MULTISAMPLE
|
3912 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3915 .brw
= BRW_NEW_BATCH
|
3917 BRW_NEW_FS_PROG_DATA
,
3919 .emit
= genX(upload_ps
),
3923 /* ---------------------------------------------------------------------- */
3927 genX(upload_hs_state
)(struct brw_context
*brw
)
3929 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3930 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3931 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3932 const struct brw_vue_prog_data
*vue_prog_data
=
3933 brw_vue_prog_data(stage_prog_data
);
3935 /* BRW_NEW_TES_PROG_DATA */
3936 struct brw_tcs_prog_data
*tcs_prog_data
=
3937 brw_tcs_prog_data(stage_prog_data
);
3939 if (!tcs_prog_data
) {
3940 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3942 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3943 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3945 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3946 hs
.IncludeVertexHandles
= true;
3948 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3953 static const struct brw_tracked_state
genX(hs_state
) = {
3956 .brw
= BRW_NEW_BATCH
|
3958 BRW_NEW_TCS_PROG_DATA
|
3959 BRW_NEW_TESS_PROGRAMS
,
3961 .emit
= genX(upload_hs_state
),
3965 genX(upload_ds_state
)(struct brw_context
*brw
)
3967 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3968 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3969 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3971 /* BRW_NEW_TES_PROG_DATA */
3972 const struct brw_tes_prog_data
*tes_prog_data
=
3973 brw_tes_prog_data(stage_prog_data
);
3974 const struct brw_vue_prog_data
*vue_prog_data
=
3975 brw_vue_prog_data(stage_prog_data
);
3977 if (!tes_prog_data
) {
3978 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3980 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3981 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3983 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3984 ds
.ComputeWCoordinateEnable
=
3985 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3988 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3989 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3990 ds
.UserClipDistanceCullTestEnableBitmask
=
3991 vue_prog_data
->cull_distance_mask
;
3997 static const struct brw_tracked_state
genX(ds_state
) = {
4000 .brw
= BRW_NEW_BATCH
|
4002 BRW_NEW_TESS_PROGRAMS
|
4003 BRW_NEW_TES_PROG_DATA
,
4005 .emit
= genX(upload_ds_state
),
4008 /* ---------------------------------------------------------------------- */
4011 upload_te_state(struct brw_context
*brw
)
4013 /* BRW_NEW_TESS_PROGRAMS */
4014 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4016 /* BRW_NEW_TES_PROG_DATA */
4017 const struct brw_tes_prog_data
*tes_prog_data
=
4018 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4021 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4022 te
.Partitioning
= tes_prog_data
->partitioning
;
4023 te
.OutputTopology
= tes_prog_data
->output_topology
;
4024 te
.TEDomain
= tes_prog_data
->domain
;
4026 te
.MaximumTessellationFactorOdd
= 63.0;
4027 te
.MaximumTessellationFactorNotOdd
= 64.0;
4030 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4034 static const struct brw_tracked_state
genX(te_state
) = {
4037 .brw
= BRW_NEW_BLORP
|
4039 BRW_NEW_TES_PROG_DATA
|
4040 BRW_NEW_TESS_PROGRAMS
,
4042 .emit
= upload_te_state
,
4045 /* ---------------------------------------------------------------------- */
4048 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4050 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4051 /* BRW_NEW_TESS_PROGRAMS */
4052 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4054 /* BRW_NEW_TES_PROG_DATA */
4055 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4056 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4059 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4061 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4062 .brw
= BRW_NEW_BATCH
|
4064 BRW_NEW_TESS_PROGRAMS
|
4065 BRW_NEW_TES_PROG_DATA
,
4067 .emit
= genX(upload_tes_push_constants
),
4071 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4073 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4074 /* BRW_NEW_TESS_PROGRAMS */
4075 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4077 /* BRW_NEW_TCS_PROG_DATA */
4078 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4080 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4083 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4085 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4086 .brw
= BRW_NEW_BATCH
|
4088 BRW_NEW_DEFAULT_TESS_LEVELS
|
4089 BRW_NEW_TESS_PROGRAMS
|
4090 BRW_NEW_TCS_PROG_DATA
,
4092 .emit
= genX(upload_tcs_push_constants
),
4097 /* ---------------------------------------------------------------------- */
4101 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4103 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4105 /* BRW_NEW_COMPUTE_PROGRAM */
4106 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4109 /* BRW_NEW_CS_PROG_DATA */
4110 struct brw_cs_prog_data
*cs_prog_data
=
4111 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4113 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4114 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4118 const struct brw_tracked_state
genX(cs_push_constants
) = {
4120 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4121 .brw
= BRW_NEW_BATCH
|
4123 BRW_NEW_COMPUTE_PROGRAM
|
4124 BRW_NEW_CS_PROG_DATA
,
4126 .emit
= genX(upload_cs_push_constants
),
4130 * Creates a new CS constant buffer reflecting the current CS program's
4131 * constants, if needed by the CS program.
4134 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4136 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4138 /* BRW_NEW_COMPUTE_PROGRAM */
4139 struct brw_program
*cp
=
4140 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4142 /* BRW_NEW_CS_PROG_DATA */
4143 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4145 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4146 /* _NEW_PROGRAM_CONSTANTS */
4147 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4148 stage_state
, prog_data
);
4151 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4153 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4154 .brw
= BRW_NEW_BATCH
|
4156 BRW_NEW_COMPUTE_PROGRAM
|
4157 BRW_NEW_CS_PROG_DATA
,
4159 .emit
= genX(upload_cs_pull_constants
),
4163 genX(upload_cs_state
)(struct brw_context
*brw
)
4165 if (!brw
->cs
.base
.prog_data
)
4169 uint32_t *desc
= (uint32_t*) brw_state_batch(
4170 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4173 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4174 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4175 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4176 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4178 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4179 brw_emit_buffer_surface_state(
4180 brw
, &stage_state
->surf_offset
[
4181 prog_data
->binding_table
.shader_time_start
],
4182 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4183 brw
->shader_time
.bo
->size
, 1,
4187 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4188 32, &stage_state
->bind_bo_offset
);
4190 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4192 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4193 * the only bits that are changed are scoreboard related: Scoreboard
4194 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4195 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4197 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4198 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4200 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4202 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4203 if (prog_data
->total_scratch
) {
4204 uint32_t per_thread_scratch_value
;
4207 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4208 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4210 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4211 } else if (GEN_IS_HASWELL
) {
4212 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4213 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4215 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4217 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4218 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4220 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4222 vfe
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
4223 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4226 /* If brw->screen->subslice_total is greater than one, then
4227 * devinfo->max_cs_threads stores number of threads per sub-slice;
4228 * thus we need to multiply by that number by subslices to get
4229 * the actual maximum number of threads; the -1 is because the HW
4230 * has a bias of 1 (would not make sense to say the maximum number
4233 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4234 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4235 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4236 vfe
.ResetGatewayTimer
=
4237 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4239 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4245 /* We are uploading duplicated copies of push constant uniforms for each
4246 * thread. Although the local id data needs to vary per thread, it won't
4247 * change for other uniform data. Unfortunately this duplication is
4248 * required for gen7. As of Haswell, this duplication can be avoided,
4249 * but this older mechanism with duplicated data continues to work.
4251 * FINISHME: As of Haswell, we could make use of the
4252 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4253 * field to only store one copy of uniform data.
4255 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4256 * which is described in the GPGPU_WALKER command and in the Broadwell
4257 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4258 * Operations => GPGPU Mode => Indirect Payload Storage.
4260 * Note: The constant data is built in brw_upload_cs_push_constants
4263 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4265 const uint32_t vfe_curbe_allocation
=
4266 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4267 cs_prog_data
->push
.cross_thread
.regs
, 2);
4268 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4271 if (cs_prog_data
->push
.total
.size
> 0) {
4272 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4273 curbe
.CURBETotalDataLength
=
4274 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4275 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4279 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4280 memcpy(bind
, stage_state
->surf_offset
,
4281 prog_data
->binding_table
.size_bytes
);
4282 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4283 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4284 .SamplerStatePointer
= stage_state
->sampler_offset
,
4285 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4286 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4287 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4288 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4289 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4290 prog_data
->total_shared
),
4291 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4292 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4293 .CrossThreadConstantDataReadLength
=
4294 cs_prog_data
->push
.cross_thread
.regs
,
4298 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4300 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4301 load
.InterfaceDescriptorTotalLength
=
4302 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4303 load
.InterfaceDescriptorDataStartAddress
= offset
;
4307 static const struct brw_tracked_state
genX(cs_state
) = {
4309 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4310 .brw
= BRW_NEW_BATCH
|
4312 BRW_NEW_CS_PROG_DATA
|
4313 BRW_NEW_SAMPLER_STATE_TABLE
|
4316 .emit
= genX(upload_cs_state
)
4321 /* ---------------------------------------------------------------------- */
4325 genX(upload_raster
)(struct brw_context
*brw
)
4327 const struct gl_context
*ctx
= &brw
->ctx
;
4330 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4333 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4336 const struct gl_point_attrib
*point
= &ctx
->Point
;
4338 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4339 if (brw
->polygon_front_bit
== render_to_fbo
)
4340 raster
.FrontWinding
= CounterClockwise
;
4342 if (polygon
->CullFlag
) {
4343 switch (polygon
->CullFaceMode
) {
4345 raster
.CullMode
= CULLMODE_FRONT
;
4348 raster
.CullMode
= CULLMODE_BACK
;
4350 case GL_FRONT_AND_BACK
:
4351 raster
.CullMode
= CULLMODE_BOTH
;
4354 unreachable("not reached");
4357 raster
.CullMode
= CULLMODE_NONE
;
4360 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4362 raster
.DXMultisampleRasterizationEnable
=
4363 _mesa_is_multisample_enabled(ctx
);
4365 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4366 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4367 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4369 switch (polygon
->FrontMode
) {
4371 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4374 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4377 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4380 unreachable("not reached");
4383 switch (polygon
->BackMode
) {
4385 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4388 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4391 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4394 unreachable("not reached");
4398 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4402 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4404 const bool multisampled_fbo
=
4405 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4406 if (multisampled_fbo
)
4407 raster
.AntialiasingEnable
= false;
4411 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4413 /* _NEW_TRANSFORM */
4414 if (!ctx
->Transform
.DepthClamp
) {
4416 raster
.ViewportZFarClipTestEnable
= true;
4417 raster
.ViewportZNearClipTestEnable
= true;
4419 raster
.ViewportZClipTestEnable
= true;
4423 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4425 raster
.ConservativeRasterizationEnable
=
4426 ctx
->IntelConservativeRasterization
;
4429 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4430 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4432 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4436 static const struct brw_tracked_state
genX(raster_state
) = {
4438 .mesa
= _NEW_BUFFERS
|
4445 .brw
= BRW_NEW_BLORP
|
4447 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4449 .emit
= genX(upload_raster
),
4453 /* ---------------------------------------------------------------------- */
4457 genX(upload_ps_extra
)(struct brw_context
*brw
)
4459 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4461 const struct brw_wm_prog_data
*prog_data
=
4462 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4464 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4465 psx
.PixelShaderValid
= true;
4466 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4467 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4468 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4469 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4470 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4471 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4473 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4474 if (prog_data
->uses_sample_mask
) {
4476 if (prog_data
->post_depth_coverage
)
4477 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4478 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4479 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4481 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4483 psx
.PixelShaderUsesInputCoverageMask
= true;
4487 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4489 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4490 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4493 /* The stricter cross-primitive coherency guarantees that the hardware
4494 * gives us with the "Accesses UAV" bit set for at least one shader stage
4495 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4496 * are redundant within the current image, atomic counter and SSBO GL
4497 * APIs, which all have very loose ordering and coherency requirements
4498 * and generally rely on the application to insert explicit barriers when
4499 * a shader invocation is expected to see the memory writes performed by
4500 * the invocations of some previous primitive. Regardless of the value
4501 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4502 * cause an in most cases useless DC flush when the lowermost stage with
4503 * the bit set finishes execution.
4505 * It would be nice to disable it, but in some cases we can't because on
4506 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4507 * signal (which could be set independently from the coherency mechanism
4508 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4509 * determine whether the hardware skips execution of the fragment shader
4510 * or not via the ThreadDispatchEnable signal. However if we know that
4511 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4512 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4513 * difference so we may just disable it here.
4515 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4516 * take into account KillPixels when no depth or stencil writes are
4517 * enabled. In order for occlusion queries to work correctly with no
4518 * attachments, we need to force-enable here.
4520 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4523 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4524 !brw_color_buffer_write_enabled(brw
))
4525 psx
.PixelShaderHasUAV
= true;
4529 const struct brw_tracked_state
genX(ps_extra
) = {
4531 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4532 .brw
= BRW_NEW_BLORP
|
4534 BRW_NEW_FRAGMENT_PROGRAM
|
4535 BRW_NEW_FS_PROG_DATA
|
4536 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4538 .emit
= genX(upload_ps_extra
),
4542 /* ---------------------------------------------------------------------- */
4546 genX(upload_ps_blend
)(struct brw_context
*brw
)
4548 struct gl_context
*ctx
= &brw
->ctx
;
4551 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4552 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4555 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4557 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4558 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4559 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4561 bool alpha_to_one
= false;
4563 if (!buffer0_is_integer
) {
4564 /* _NEW_MULTISAMPLE */
4566 if (_mesa_is_multisample_enabled(ctx
)) {
4567 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4568 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4571 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4574 /* Used for implementing the following bit of GL_EXT_texture_integer:
4575 * "Per-fragment operations that require floating-point color
4576 * components, including multisample alpha operations, alpha test,
4577 * blending, and dithering, have no effect when the corresponding
4578 * colors are written to an integer color buffer."
4580 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4581 * "If drawbuffer zero is not NONE and the buffer it references has an
4582 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4583 * operations are skipped."
4585 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4586 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4587 GLenum eqA
= color
->Blend
[0].EquationA
;
4588 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4589 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4590 GLenum srcA
= color
->Blend
[0].SrcA
;
4591 GLenum dstA
= color
->Blend
[0].DstA
;
4593 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4594 srcRGB
= dstRGB
= GL_ONE
;
4596 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4597 srcA
= dstA
= GL_ONE
;
4599 /* Due to hardware limitations, the destination may have information
4600 * in an alpha channel even when the format specifies no alpha
4601 * channel. In order to avoid getting any incorrect blending due to
4602 * that alpha channel, coerce the blend factors to values that will
4603 * not read the alpha channel, but will instead use the correct
4604 * implicit value for alpha.
4606 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4607 GL_TEXTURE_ALPHA_TYPE
)) {
4608 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4609 srcA
= brw_fix_xRGB_alpha(srcA
);
4610 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4611 dstA
= brw_fix_xRGB_alpha(dstA
);
4614 /* Alpha to One doesn't work with Dual Color Blending. Override
4615 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4617 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4618 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4619 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4620 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4621 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4624 pb
.ColorBufferBlendEnable
= true;
4625 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4626 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4627 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4628 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4630 pb
.IndependentAlphaBlendEnable
=
4631 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4636 static const struct brw_tracked_state
genX(ps_blend
) = {
4638 .mesa
= _NEW_BUFFERS
|
4641 .brw
= BRW_NEW_BLORP
|
4643 BRW_NEW_FRAGMENT_PROGRAM
,
4645 .emit
= genX(upload_ps_blend
)
4649 /* ---------------------------------------------------------------------- */
4653 genX(emit_vf_topology
)(struct brw_context
*brw
)
4655 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4656 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4660 static const struct brw_tracked_state
genX(vf_topology
) = {
4663 .brw
= BRW_NEW_BLORP
|
4666 .emit
= genX(emit_vf_topology
),
4670 /* ---------------------------------------------------------------------- */
4674 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4676 uint32_t offset_in_bytes
,
4679 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4680 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4681 mi_rpc
.ReportID
= report_id
;
4686 /* ---------------------------------------------------------------------- */
4689 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4692 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4693 struct brw_stage_state
*stage_state
)
4696 static const uint16_t packet_headers
[] = {
4697 [MESA_SHADER_VERTEX
] = 43,
4698 [MESA_SHADER_TESS_CTRL
] = 44,
4699 [MESA_SHADER_TESS_EVAL
] = 45,
4700 [MESA_SHADER_GEOMETRY
] = 46,
4701 [MESA_SHADER_FRAGMENT
] = 47,
4704 /* Ivybridge requires a workaround flush before VS packets. */
4705 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4706 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4707 gen7_emit_vs_workaround_flush(brw
);
4710 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4711 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4712 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4718 has_component(mesa_format format
, int i
)
4720 if (_mesa_is_format_color_format(format
))
4721 return _mesa_format_has_color_component(format
, i
);
4723 /* depth and stencil have only one component */
4728 * Upload SAMPLER_BORDER_COLOR_STATE.
4731 genX(upload_default_color
)(struct brw_context
*brw
,
4732 const struct gl_sampler_object
*sampler
,
4733 mesa_format format
, GLenum base_format
,
4734 bool is_integer_format
, bool is_stencil_sampling
,
4735 uint32_t *sdc_offset
)
4737 union gl_color_union color
;
4739 switch (base_format
) {
4740 case GL_DEPTH_COMPONENT
:
4741 /* GL specs that border color for depth textures is taken from the
4742 * R channel, while the hardware uses A. Spam R into all the
4743 * channels for safety.
4745 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4746 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4747 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4748 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4754 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4757 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4758 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4759 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4760 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4763 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4764 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4765 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4766 color
.ui
[3] = float_as_int(1.0);
4768 case GL_LUMINANCE_ALPHA
:
4769 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4770 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4771 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4772 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4775 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4776 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4777 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4778 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4782 /* In some cases we use an RGBA surface format for GL RGB textures,
4783 * where we've initialized the A channel to 1.0. We also have to set
4784 * the border color alpha to 1.0 in that case.
4786 if (base_format
== GL_RGB
)
4787 color
.ui
[3] = float_as_int(1.0);
4792 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4796 uint32_t *sdc
= brw_state_batch(
4797 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4798 alignment
, sdc_offset
);
4800 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4802 #define ASSIGN(dst, src) \
4807 #define ASSIGNu16(dst, src) \
4809 dst = (uint16_t)src; \
4812 #define ASSIGNu8(dst, src) \
4814 dst = (uint8_t)src; \
4817 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4818 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4819 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4820 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4821 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4824 /* On Broadwell, the border color is represented as four 32-bit floats,
4825 * integers, or unsigned values, interpreted according to the surface
4826 * format. This matches the sampler->BorderColor union exactly; just
4827 * memcpy the values.
4829 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4830 #elif GEN_IS_HASWELL
4831 if (is_integer_format
|| is_stencil_sampling
) {
4832 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4833 const int bits_per_channel
=
4834 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4836 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4837 * "If any color channel is missing from the surface format,
4838 * corresponding border color should be programmed as zero and if
4839 * alpha channel is missing, corresponding Alpha border color should
4840 * be programmed as 1."
4842 unsigned c
[4] = { 0, 0, 0, 1 };
4843 for (int i
= 0; i
< 4; i
++) {
4844 if (has_component(format
, i
))
4848 switch (bits_per_channel
) {
4850 /* Copy RGBA in order. */
4851 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4854 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4856 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4859 if (base_format
== GL_RG
) {
4860 /* Careful inspection of the tables reveals that for RG32 formats,
4861 * the green channel needs to go where blue normally belongs.
4863 state
.BorderColor32bitRed
= c
[0];
4864 state
.BorderColor32bitBlue
= c
[1];
4865 state
.BorderColor32bitAlpha
= 1;
4867 /* Copy RGBA in order. */
4868 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4872 assert(!"Invalid number of bits per channel in integer format.");
4876 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4878 #elif GEN_GEN == 5 || GEN_GEN == 6
4879 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4880 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4881 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4883 #define MESA_FLOAT_TO_HALF(dst, src) \
4884 dst = _mesa_float_to_half(src);
4886 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4888 #undef MESA_FLOAT_TO_HALF
4890 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4891 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4892 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4893 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4895 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4897 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4899 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4903 #undef BORDER_COLOR_ATTR
4905 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4909 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4916 /* GL_CLAMP is the weird mode where coordinates are clamped to
4917 * [0.0, 1.0], so linear filtering of coordinates outside of
4918 * [0.0, 1.0] give you half edge texel value and half border
4921 * Gen8+ supports this natively.
4923 return TCM_HALF_BORDER
;
4925 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4926 * and set clamp_border here, which gets the result desired.
4927 * We just use clamp(_to_edge) for nearest, because for nearest
4928 * clamping to 1.0 gives border color instead of the desired
4934 return TCM_CLAMP_BORDER
;
4936 case GL_CLAMP_TO_EDGE
:
4938 case GL_CLAMP_TO_BORDER
:
4939 return TCM_CLAMP_BORDER
;
4940 case GL_MIRRORED_REPEAT
:
4942 case GL_MIRROR_CLAMP_TO_EDGE
:
4943 return TCM_MIRROR_ONCE
;
4950 * Return true if the given wrap mode requires the border color to exist.
4953 wrap_mode_needs_border_color(unsigned wrap_mode
)
4956 return wrap_mode
== TCM_CLAMP_BORDER
||
4957 wrap_mode
== TCM_HALF_BORDER
;
4959 return wrap_mode
== TCM_CLAMP_BORDER
;
4964 * Sets the sampler state for a single unit based off of the sampler key
4968 genX(update_sampler_state
)(struct brw_context
*brw
,
4969 GLenum target
, bool tex_cube_map_seamless
,
4970 GLfloat tex_unit_lod_bias
,
4971 mesa_format format
, GLenum base_format
,
4972 const struct gl_texture_object
*texObj
,
4973 const struct gl_sampler_object
*sampler
,
4974 uint32_t *sampler_state
,
4975 uint32_t batch_offset_for_sampler_state
)
4977 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
4979 /* Select min and mip filters. */
4980 switch (sampler
->MinFilter
) {
4982 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4983 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4986 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4987 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4989 case GL_NEAREST_MIPMAP_NEAREST
:
4990 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4991 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4993 case GL_LINEAR_MIPMAP_NEAREST
:
4994 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4995 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4997 case GL_NEAREST_MIPMAP_LINEAR
:
4998 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4999 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5001 case GL_LINEAR_MIPMAP_LINEAR
:
5002 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5003 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5006 unreachable("not reached");
5009 /* Select mag filter. */
5010 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5011 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5013 /* Enable anisotropic filtering if desired. */
5014 samp_st
.MaximumAnisotropy
= RATIO21
;
5016 if (sampler
->MaxAnisotropy
> 1.0f
) {
5017 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5018 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5019 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5020 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5022 if (sampler
->MaxAnisotropy
> 2.0f
) {
5023 samp_st
.MaximumAnisotropy
=
5024 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5028 /* Set address rounding bits if not using nearest filtering. */
5029 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5030 samp_st
.UAddressMinFilterRoundingEnable
= true;
5031 samp_st
.VAddressMinFilterRoundingEnable
= true;
5032 samp_st
.RAddressMinFilterRoundingEnable
= true;
5035 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5036 samp_st
.UAddressMagFilterRoundingEnable
= true;
5037 samp_st
.VAddressMagFilterRoundingEnable
= true;
5038 samp_st
.RAddressMagFilterRoundingEnable
= true;
5041 bool either_nearest
=
5042 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5043 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
5044 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
5045 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
5047 if (target
== GL_TEXTURE_CUBE_MAP
||
5048 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5049 /* Cube maps must use the same wrap mode for all three coordinate
5050 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5052 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5053 * integer formats. Fall back to CLAMP for now.
5055 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5056 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5065 } else if (target
== GL_TEXTURE_1D
) {
5066 /* There's a bug in 1D texture sampling - it actually pays
5067 * attention to the wrap_t value, though it should not.
5068 * Override the wrap_t value here to GL_REPEAT to keep
5069 * any nonexistent border pixels from floating in.
5074 samp_st
.TCXAddressControlMode
= wrap_s
;
5075 samp_st
.TCYAddressControlMode
= wrap_t
;
5076 samp_st
.TCZAddressControlMode
= wrap_r
;
5078 samp_st
.ShadowFunction
=
5079 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5080 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5083 /* Set shadow function. */
5084 samp_st
.AnisotropicAlgorithm
=
5085 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5086 EWAApproximation
: LEGACY
;
5090 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5093 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5094 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5095 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5096 samp_st
.TextureLODBias
=
5097 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5100 samp_st
.BaseMipLevel
=
5101 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5102 samp_st
.MinandMagStateNotEqual
=
5103 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5106 /* Upload the border color if necessary. If not, just point it at
5107 * offset 0 (the start of the batch) - the color should be ignored,
5108 * but that address won't fault in case something reads it anyway.
5110 uint32_t border_color_offset
= 0;
5111 if (wrap_mode_needs_border_color(wrap_s
) ||
5112 wrap_mode_needs_border_color(wrap_t
) ||
5113 wrap_mode_needs_border_color(wrap_r
)) {
5114 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5115 texObj
->_IsIntegerFormat
,
5116 texObj
->StencilSampling
,
5117 &border_color_offset
);
5120 samp_st
.BorderColorPointer
=
5121 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5123 samp_st
.BorderColorPointer
= border_color_offset
;
5127 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5129 samp_st
.LODPreClampEnable
= true;
5132 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5136 update_sampler_state(struct brw_context
*brw
,
5138 uint32_t *sampler_state
,
5139 uint32_t batch_offset_for_sampler_state
)
5141 struct gl_context
*ctx
= &brw
->ctx
;
5142 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5143 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5144 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5146 /* These don't use samplers at all. */
5147 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5150 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5151 genX(update_sampler_state
)(brw
, texObj
->Target
,
5152 ctx
->Texture
.CubeMapSeamless
,
5154 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5156 sampler_state
, batch_offset_for_sampler_state
);
5160 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5161 struct gl_program
*prog
,
5162 struct brw_stage_state
*stage_state
)
5164 struct gl_context
*ctx
= &brw
->ctx
;
5165 uint32_t sampler_count
= stage_state
->sampler_count
;
5167 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5169 if (sampler_count
== 0)
5172 /* SAMPLER_STATE is 4 DWords on all platforms. */
5173 const int dwords
= GENX(SAMPLER_STATE_length
);
5174 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5176 uint32_t *sampler_state
= brw_state_batch(brw
,
5177 sampler_count
* size_in_bytes
,
5178 32, &stage_state
->sampler_offset
);
5179 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5181 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
5183 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5184 if (SamplersUsed
& (1 << s
)) {
5185 const unsigned unit
= prog
->SamplerUnits
[s
];
5186 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5187 update_sampler_state(brw
, unit
, sampler_state
,
5188 batch_offset_for_sampler_state
);
5192 sampler_state
+= dwords
;
5193 batch_offset_for_sampler_state
+= size_in_bytes
;
5196 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5197 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5198 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5200 /* Flag that the sampler state table pointer has changed; later atoms
5203 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5208 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5210 /* BRW_NEW_FRAGMENT_PROGRAM */
5211 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5212 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5215 static const struct brw_tracked_state
genX(fs_samplers
) = {
5217 .mesa
= _NEW_TEXTURE
,
5218 .brw
= BRW_NEW_BATCH
|
5220 BRW_NEW_FRAGMENT_PROGRAM
,
5222 .emit
= genX(upload_fs_samplers
),
5226 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5228 /* BRW_NEW_VERTEX_PROGRAM */
5229 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5230 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5233 static const struct brw_tracked_state
genX(vs_samplers
) = {
5235 .mesa
= _NEW_TEXTURE
,
5236 .brw
= BRW_NEW_BATCH
|
5238 BRW_NEW_VERTEX_PROGRAM
,
5240 .emit
= genX(upload_vs_samplers
),
5245 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5247 /* BRW_NEW_GEOMETRY_PROGRAM */
5248 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5252 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5256 static const struct brw_tracked_state
genX(gs_samplers
) = {
5258 .mesa
= _NEW_TEXTURE
,
5259 .brw
= BRW_NEW_BATCH
|
5261 BRW_NEW_GEOMETRY_PROGRAM
,
5263 .emit
= genX(upload_gs_samplers
),
5269 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5271 /* BRW_NEW_TESS_PROGRAMS */
5272 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5276 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5279 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5281 .mesa
= _NEW_TEXTURE
,
5282 .brw
= BRW_NEW_BATCH
|
5284 BRW_NEW_TESS_PROGRAMS
,
5286 .emit
= genX(upload_tcs_samplers
),
5292 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5294 /* BRW_NEW_TESS_PROGRAMS */
5295 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5299 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5302 static const struct brw_tracked_state
genX(tes_samplers
) = {
5304 .mesa
= _NEW_TEXTURE
,
5305 .brw
= BRW_NEW_BATCH
|
5307 BRW_NEW_TESS_PROGRAMS
,
5309 .emit
= genX(upload_tes_samplers
),
5315 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5317 /* BRW_NEW_COMPUTE_PROGRAM */
5318 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5322 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5325 const struct brw_tracked_state
genX(cs_samplers
) = {
5327 .mesa
= _NEW_TEXTURE
,
5328 .brw
= BRW_NEW_BATCH
|
5330 BRW_NEW_COMPUTE_PROGRAM
,
5332 .emit
= genX(upload_cs_samplers
),
5336 /* ---------------------------------------------------------------------- */
5340 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5342 struct gl_context
*ctx
= &brw
->ctx
;
5344 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5345 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5346 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5347 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5348 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5352 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5355 .brw
= BRW_NEW_CONTEXT
|
5358 .emit
= genX(upload_blend_constant_color
)
5362 /* ---------------------------------------------------------------------- */
5365 genX(init_atoms
)(struct brw_context
*brw
)
5368 static const struct brw_tracked_state
*render_atoms
[] =
5370 /* Once all the programs are done, we know how large urb entry
5371 * sizes need to be and can decide if we need to change the urb
5375 &brw_recalculate_urb_fence
,
5378 &genX(color_calc_state
),
5380 /* Surface state setup. Must come before the VS/WM unit. The binding
5381 * table upload must be last.
5383 &brw_vs_pull_constants
,
5384 &brw_wm_pull_constants
,
5385 &brw_renderbuffer_surfaces
,
5386 &brw_renderbuffer_read_surfaces
,
5387 &brw_texture_surfaces
,
5388 &brw_vs_binding_table
,
5389 &brw_wm_binding_table
,
5394 /* These set up state for brw_psp_urb_cbs */
5396 &genX(sf_clip_viewport
),
5398 &genX(vs_state
), /* always required, enabled or not */
5404 &brw_binding_table_pointers
,
5405 &genX(blend_constant_color
),
5409 &genX(polygon_stipple
),
5410 &genX(polygon_stipple_offset
),
5412 &genX(line_stipple
),
5416 &genX(drawing_rect
),
5417 &brw_indices
, /* must come before brw_vertices */
5418 &genX(index_buffer
),
5421 &brw_constant_buffer
5424 static const struct brw_tracked_state
*render_atoms
[] =
5426 &genX(sf_clip_viewport
),
5428 /* Command packets: */
5433 &genX(blend_state
), /* must do before cc unit */
5434 &genX(color_calc_state
), /* must do before cc unit */
5435 &genX(depth_stencil_state
), /* must do before cc unit */
5437 &genX(vs_push_constants
), /* Before vs_state */
5438 &genX(gs_push_constants
), /* Before gs_state */
5439 &genX(wm_push_constants
), /* Before wm_state */
5441 /* Surface state setup. Must come before the VS/WM unit. The binding
5442 * table upload must be last.
5444 &brw_vs_pull_constants
,
5445 &brw_vs_ubo_surfaces
,
5446 &brw_gs_pull_constants
,
5447 &brw_gs_ubo_surfaces
,
5448 &brw_wm_pull_constants
,
5449 &brw_wm_ubo_surfaces
,
5450 &gen6_renderbuffer_surfaces
,
5451 &brw_renderbuffer_read_surfaces
,
5452 &brw_texture_surfaces
,
5454 &brw_vs_binding_table
,
5455 &gen6_gs_binding_table
,
5456 &brw_wm_binding_table
,
5461 &gen6_sampler_state
,
5462 &genX(multisample_state
),
5470 &genX(scissor_state
),
5472 &gen6_binding_table_pointers
,
5476 &genX(polygon_stipple
),
5477 &genX(polygon_stipple_offset
),
5479 &genX(line_stipple
),
5481 &genX(drawing_rect
),
5483 &brw_indices
, /* must come before brw_vertices */
5484 &genX(index_buffer
),
5488 static const struct brw_tracked_state
*render_atoms
[] =
5490 /* Command packets: */
5493 &genX(sf_clip_viewport
),
5496 &gen7_push_constant_space
,
5498 &genX(blend_state
), /* must do before cc unit */
5499 &genX(color_calc_state
), /* must do before cc unit */
5500 &genX(depth_stencil_state
), /* must do before cc unit */
5502 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5503 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5504 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5505 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5506 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5508 &genX(vs_push_constants
), /* Before vs_state */
5509 &genX(tcs_push_constants
),
5510 &genX(tes_push_constants
),
5511 &genX(gs_push_constants
), /* Before gs_state */
5512 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5514 /* Surface state setup. Must come before the VS/WM unit. The binding
5515 * table upload must be last.
5517 &brw_vs_pull_constants
,
5518 &brw_vs_ubo_surfaces
,
5519 &brw_tcs_pull_constants
,
5520 &brw_tcs_ubo_surfaces
,
5521 &brw_tes_pull_constants
,
5522 &brw_tes_ubo_surfaces
,
5523 &brw_gs_pull_constants
,
5524 &brw_gs_ubo_surfaces
,
5525 &brw_wm_pull_constants
,
5526 &brw_wm_ubo_surfaces
,
5527 &gen6_renderbuffer_surfaces
,
5528 &brw_renderbuffer_read_surfaces
,
5529 &brw_texture_surfaces
,
5531 &genX(push_constant_packets
),
5533 &brw_vs_binding_table
,
5534 &brw_tcs_binding_table
,
5535 &brw_tes_binding_table
,
5536 &brw_gs_binding_table
,
5537 &brw_wm_binding_table
,
5541 &genX(tcs_samplers
),
5542 &genX(tes_samplers
),
5544 &genX(multisample_state
),
5558 &genX(scissor_state
),
5562 &genX(polygon_stipple
),
5563 &genX(polygon_stipple_offset
),
5565 &genX(line_stipple
),
5567 &genX(drawing_rect
),
5569 &brw_indices
, /* must come before brw_vertices */
5570 &genX(index_buffer
),
5578 static const struct brw_tracked_state
*render_atoms
[] =
5581 &genX(sf_clip_viewport
),
5584 &gen7_push_constant_space
,
5587 &genX(color_calc_state
),
5589 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5590 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5591 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5592 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5593 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5595 &genX(vs_push_constants
), /* Before vs_state */
5596 &genX(tcs_push_constants
),
5597 &genX(tes_push_constants
),
5598 &genX(gs_push_constants
), /* Before gs_state */
5599 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5601 /* Surface state setup. Must come before the VS/WM unit. The binding
5602 * table upload must be last.
5604 &brw_vs_pull_constants
,
5605 &brw_vs_ubo_surfaces
,
5606 &brw_tcs_pull_constants
,
5607 &brw_tcs_ubo_surfaces
,
5608 &brw_tes_pull_constants
,
5609 &brw_tes_ubo_surfaces
,
5610 &brw_gs_pull_constants
,
5611 &brw_gs_ubo_surfaces
,
5612 &brw_wm_pull_constants
,
5613 &brw_wm_ubo_surfaces
,
5614 &gen6_renderbuffer_surfaces
,
5615 &brw_renderbuffer_read_surfaces
,
5616 &brw_texture_surfaces
,
5618 &genX(push_constant_packets
),
5620 &brw_vs_binding_table
,
5621 &brw_tcs_binding_table
,
5622 &brw_tes_binding_table
,
5623 &brw_gs_binding_table
,
5624 &brw_wm_binding_table
,
5628 &genX(tcs_samplers
),
5629 &genX(tes_samplers
),
5631 &genX(multisample_state
),
5640 &genX(raster_state
),
5646 &genX(depth_stencil_state
),
5649 &genX(scissor_state
),
5653 &genX(polygon_stipple
),
5654 &genX(polygon_stipple_offset
),
5656 &genX(line_stipple
),
5658 &genX(drawing_rect
),
5663 &genX(index_buffer
),
5671 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5672 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5673 render_atoms
, ARRAY_SIZE(render_atoms
));
5676 static const struct brw_tracked_state
*compute_atoms
[] =
5679 &brw_cs_image_surfaces
,
5680 &genX(cs_push_constants
),
5681 &genX(cs_pull_constants
),
5682 &brw_cs_ubo_surfaces
,
5683 &brw_cs_texture_surfaces
,
5684 &brw_cs_work_groups_surface
,
5689 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5690 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5691 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5693 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);