2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 UNUSED
static struct brw_address
124 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
134 static struct brw_address
135 KSP(struct brw_context
*brw
, uint32_t offset
)
137 return ro_bo(brw
->cache
.bo
, offset
);
141 KSP(struct brw_context
*brw
, uint32_t offset
)
147 #include "genxml/genX_pack.h"
149 #define _brw_cmd_length(cmd) cmd ## _length
150 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
151 #define _brw_cmd_header(cmd) cmd ## _header
152 #define _brw_cmd_pack(cmd) cmd ## _pack
154 #define brw_batch_emit(brw, cmd, name) \
155 for (struct cmd name = { _brw_cmd_header(cmd) }, \
156 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
157 __builtin_expect(_dst != NULL, 1); \
158 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
161 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
162 uint32_t *_dw = emit_dwords(brw, n); \
163 struct cmd template = { \
164 _brw_cmd_header(cmd), \
165 .DWordLength = n - _brw_cmd_length_bias(cmd), \
168 _brw_cmd_pack(cmd)(brw, _dw, &template); \
169 _dw + 1; /* Array starts at dw[1] */ \
172 #define brw_state_emit(brw, cmd, align, offset, name) \
173 for (struct cmd name = {}, \
174 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
176 __builtin_expect(_dst != NULL, 1); \
177 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 * Polygon stipple packet
184 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
186 struct gl_context
*ctx
= &brw
->ctx
;
189 if (!ctx
->Polygon
.StippleFlag
)
192 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
193 /* Polygon stipple is provided in OpenGL order, i.e. bottom
194 * row first. If we're rendering to a window (i.e. the
195 * default frame buffer object, 0), then we need to invert
196 * it to match our pixel layout. But if we're rendering
197 * to a FBO (i.e. any named frame buffer object), we *don't*
198 * need to invert - we already match the layout.
200 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
201 for (unsigned i
= 0; i
< 32; i
++)
202 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
204 for (unsigned i
= 0; i
< 32; i
++)
205 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
210 static const struct brw_tracked_state
genX(polygon_stipple
) = {
212 .mesa
= _NEW_POLYGON
|
214 .brw
= BRW_NEW_CONTEXT
,
216 .emit
= genX(upload_polygon_stipple
),
220 * Polygon stipple offset packet
223 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
225 struct gl_context
*ctx
= &brw
->ctx
;
228 if (!ctx
->Polygon
.StippleFlag
)
231 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
234 * If we're drawing to a system window we have to invert the Y axis
235 * in order to match the OpenGL pixel coordinate system, and our
236 * offset must be matched to the window position. If we're drawing
237 * to a user-created FBO then our native pixel coordinate system
238 * works just fine, and there's no window system to worry about.
240 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
241 poly
.PolygonStippleYOffset
=
242 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
247 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
249 .mesa
= _NEW_BUFFERS
|
251 .brw
= BRW_NEW_CONTEXT
,
253 .emit
= genX(upload_polygon_stipple_offset
),
257 * Line stipple packet
260 genX(upload_line_stipple
)(struct brw_context
*brw
)
262 struct gl_context
*ctx
= &brw
->ctx
;
264 if (!ctx
->Line
.StippleFlag
)
267 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
268 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
270 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
271 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
275 static const struct brw_tracked_state
genX(line_stipple
) = {
278 .brw
= BRW_NEW_CONTEXT
,
280 .emit
= genX(upload_line_stipple
),
283 /* Constant single cliprect for framebuffer object or DRI2 drawing */
285 genX(upload_drawing_rect
)(struct brw_context
*brw
)
287 struct gl_context
*ctx
= &brw
->ctx
;
288 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
289 const unsigned int fb_width
= _mesa_geometric_width(fb
);
290 const unsigned int fb_height
= _mesa_geometric_height(fb
);
292 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
293 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
294 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
298 static const struct brw_tracked_state
genX(drawing_rect
) = {
300 .mesa
= _NEW_BUFFERS
,
301 .brw
= BRW_NEW_BLORP
|
304 .emit
= genX(upload_drawing_rect
),
308 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
312 unsigned start_offset
,
317 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
318 .VertexBufferIndex
= buffer_nr
,
319 .BufferPitch
= stride
,
320 .BufferStartingAddress
= ro_bo(bo
, start_offset
),
322 .BufferSize
= end_offset
- start_offset
,
326 .AddressModifyEnable
= true,
330 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
331 .InstanceDataStepRate
= step_rate
,
333 .EndAddress
= ro_bo(bo
, end_offset
- 1),
338 .VertexBufferMOCS
= CNL_MOCS_WB
,
340 .VertexBufferMOCS
= SKL_MOCS_WB
,
342 .VertexBufferMOCS
= BDW_MOCS_WB
,
344 .VertexBufferMOCS
= GEN7_MOCS_L3
,
348 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
349 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
353 is_passthru_format(uint32_t format
)
356 case ISL_FORMAT_R64_PASSTHRU
:
357 case ISL_FORMAT_R64G64_PASSTHRU
:
358 case ISL_FORMAT_R64G64B64_PASSTHRU
:
359 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
367 uploads_needed(uint32_t format
,
370 if (!is_passthru_format(format
))
377 case ISL_FORMAT_R64_PASSTHRU
:
378 case ISL_FORMAT_R64G64_PASSTHRU
:
380 case ISL_FORMAT_R64G64B64_PASSTHRU
:
381 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
384 unreachable("not reached");
389 * Returns the format that we are finally going to use when upload a vertex
390 * element. It will only change if we are using *64*PASSTHRU formats, as for
391 * gen < 8 they need to be splitted on two *32*FLOAT formats.
393 * @upload points in which upload we are. Valid values are [0,1]
396 downsize_format_if_needed(uint32_t format
,
399 assert(upload
== 0 || upload
== 1);
401 if (!is_passthru_format(format
))
404 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
405 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
406 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
407 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
408 * flagging that we want to fill with zeroes this second forced upload.
411 case ISL_FORMAT_R64_PASSTHRU
:
412 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
413 : ISL_FORMAT_R32_FLOAT
;
414 case ISL_FORMAT_R64G64_PASSTHRU
:
415 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
416 : ISL_FORMAT_R32_FLOAT
;
417 case ISL_FORMAT_R64G64B64_PASSTHRU
:
418 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
419 : ISL_FORMAT_R32G32_FLOAT
;
420 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
421 return ISL_FORMAT_R32G32B32A32_FLOAT
;
423 unreachable("not reached");
428 * Returns the number of componentes associated with a format that is used on
429 * a 64 to 32 format split. See downsize_format()
432 upload_format_size(uint32_t upload_format
)
434 switch (upload_format
) {
435 case ISL_FORMAT_R32_FLOAT
:
437 /* downsized_format has returned this one in order to flag that we are
438 * performing a second upload which we want to have filled with
439 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
440 * vertex shader input variables.
444 case ISL_FORMAT_R32G32_FLOAT
:
446 case ISL_FORMAT_R32G32B32A32_FLOAT
:
449 unreachable("not reached");
454 genX(emit_vertices
)(struct brw_context
*brw
)
456 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
459 brw_prepare_vertices(brw
);
460 brw_prepare_shader_draw_parameters(brw
);
463 brw_emit_query_begin(brw
);
466 const struct brw_vs_prog_data
*vs_prog_data
=
467 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
470 struct gl_context
*ctx
= &brw
->ctx
;
471 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
472 ctx
->Polygon
.BackMode
!= GL_FILL
);
474 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
475 unsigned vue
= brw
->vb
.nr_enabled
;
477 /* The element for the edge flags must always be last, so we have to
478 * insert the SGVS before it in that case.
480 if (uses_edge_flag
) {
486 "Trying to insert VID/IID past 33rd vertex element, "
487 "need to reorder the vertex attrbutes.");
489 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
490 if (vs_prog_data
->uses_vertexid
) {
491 vfs
.VertexIDEnable
= true;
492 vfs
.VertexIDComponentNumber
= 2;
493 vfs
.VertexIDElementOffset
= vue
;
496 if (vs_prog_data
->uses_instanceid
) {
497 vfs
.InstanceIDEnable
= true;
498 vfs
.InstanceIDComponentNumber
= 3;
499 vfs
.InstanceIDElementOffset
= vue
;
503 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
504 vfi
.InstancingEnable
= true;
505 vfi
.VertexElementIndex
= vue
;
508 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
512 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
513 vs_prog_data
->uses_baseinstance
||
514 vs_prog_data
->uses_instanceid
||
515 vs_prog_data
->uses_vertexid
);
517 unsigned nr_elements
=
518 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
521 /* If any of the formats of vb.enabled needs more that one upload, we need
522 * to add it to nr_elements
524 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
525 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
526 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
528 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
533 /* If the VS doesn't read any inputs (calculating vertex position from
534 * a state variable for some reason, for example), emit a single pad
535 * VERTEX_ELEMENT struct and bail.
537 * The stale VB state stays in place, but they don't do anything unless
538 * a VE loads from them.
540 if (nr_elements
== 0) {
541 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
542 1 + GENX(VERTEX_ELEMENT_STATE_length
));
543 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
545 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
546 .Component0Control
= VFCOMP_STORE_0
,
547 .Component1Control
= VFCOMP_STORE_0
,
548 .Component2Control
= VFCOMP_STORE_0
,
549 .Component3Control
= VFCOMP_STORE_1_FP
,
551 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
555 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
556 const bool uses_draw_params
=
557 vs_prog_data
->uses_basevertex
||
558 vs_prog_data
->uses_baseinstance
;
559 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
560 uses_draw_params
+ vs_prog_data
->uses_drawid
;
563 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
565 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
566 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
568 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
569 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
570 /* Prior to Haswell and Bay Trail we have to use 4-component formats
571 * to fake 3-component ones. In particular, we do this for
572 * half-float and 8 and 16-bit integer formats. This means that the
573 * vertex element may poke over the end of the buffer by 2 bytes.
575 const unsigned padding
=
576 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
577 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
578 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
585 if (uses_draw_params
) {
586 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
587 brw
->draw
.draw_params_bo
,
588 brw
->draw
.draw_params_offset
,
589 brw
->draw
.draw_params_bo
->size
,
594 if (vs_prog_data
->uses_drawid
) {
595 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
596 brw
->draw
.draw_id_bo
,
597 brw
->draw
.draw_id_offset
,
598 brw
->draw
.draw_id_bo
->size
,
604 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
605 * presumably for VertexID/InstanceID.
608 assert(nr_elements
<= 34);
609 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
611 assert(nr_elements
<= 18);
614 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
615 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
617 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
618 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
619 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
620 uint32_t comp0
= VFCOMP_STORE_SRC
;
621 uint32_t comp1
= VFCOMP_STORE_SRC
;
622 uint32_t comp2
= VFCOMP_STORE_SRC
;
623 uint32_t comp3
= VFCOMP_STORE_SRC
;
624 const unsigned num_uploads
= GEN_GEN
< 8 ?
625 uploads_needed(format
, input
->is_dual_slot
) : 1;
628 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
629 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
630 * element which has edge flag enabled."
632 assert(!(is_passthru_format(format
) && uses_edge_flag
));
635 /* The gen4 driver expects edgeflag to come in as a float, and passes
636 * that float on to the tests in the clipper. Mesa's current vertex
637 * attribute value for EdgeFlag is stored as a float, which works out.
638 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
639 * integer ubyte. Just rewrite that to convert to a float.
641 * Gen6+ passes edgeflag as sideband along with the vertex, instead
642 * of in the VUE. We have to upload it sideband as the last vertex
643 * element according to the B-Spec.
646 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
647 gen6_edgeflag_input
= input
;
652 for (unsigned c
= 0; c
< num_uploads
; c
++) {
653 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
654 downsize_format_if_needed(format
, c
);
655 /* If we need more that one upload, the offset stride would be 128
656 * bits (16 bytes), as for previous uploads we are using the full
658 const unsigned offset
= input
->offset
+ c
* 16;
660 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
661 upload_format_size(upload_format
) : input
->glarray
->Size
;
664 case 0: comp0
= VFCOMP_STORE_0
;
665 case 1: comp1
= VFCOMP_STORE_0
;
666 case 2: comp2
= VFCOMP_STORE_0
;
668 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
669 comp3
= VFCOMP_STORE_0
;
670 } else if (input
->glarray
->Integer
) {
671 comp3
= VFCOMP_STORE_1_INT
;
673 comp3
= VFCOMP_STORE_1_FP
;
680 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
682 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
683 * formats, 64-bit components are stored in the URB without any
684 * conversion. In this case, vertex elements must be written as 128
685 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
686 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
687 * component into the URB, Component 1 must be specified as
688 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
689 * order to output a 128-bit vertex element, or Components 1-3 must
690 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
691 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
692 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
695 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
696 /* Store vertex elements which correspond to double and dvec2 vertex
697 * shader inputs as 128-bit vertex elements, instead of 256-bits.
699 comp2
= VFCOMP_NOSTORE
;
700 comp3
= VFCOMP_NOSTORE
;
704 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
705 .VertexBufferIndex
= input
->buffer
,
707 .SourceElementFormat
= upload_format
,
708 .SourceElementOffset
= offset
,
709 .Component0Control
= comp0
,
710 .Component1Control
= comp1
,
711 .Component2Control
= comp2
,
712 .Component3Control
= comp3
,
714 .DestinationElementOffset
= i
* 4,
718 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
719 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
723 if (needs_sgvs_element
) {
724 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
726 .Component0Control
= VFCOMP_STORE_0
,
727 .Component1Control
= VFCOMP_STORE_0
,
728 .Component2Control
= VFCOMP_STORE_0
,
729 .Component3Control
= VFCOMP_STORE_0
,
731 .DestinationElementOffset
= i
* 4,
736 if (vs_prog_data
->uses_basevertex
||
737 vs_prog_data
->uses_baseinstance
) {
738 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
739 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
740 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
741 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
744 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
745 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
746 if (vs_prog_data
->uses_basevertex
)
747 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
749 if (vs_prog_data
->uses_baseinstance
)
750 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
752 if (vs_prog_data
->uses_vertexid
)
753 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
755 if (vs_prog_data
->uses_instanceid
)
756 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
759 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
760 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
763 if (vs_prog_data
->uses_drawid
) {
764 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
766 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
767 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32_UINT
,
768 .Component0Control
= VFCOMP_STORE_SRC
,
769 .Component1Control
= VFCOMP_STORE_0
,
770 .Component2Control
= VFCOMP_STORE_0
,
771 .Component3Control
= VFCOMP_STORE_0
,
773 .DestinationElementOffset
= i
* 4,
777 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
778 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
782 if (gen6_edgeflag_input
) {
783 const uint32_t format
=
784 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
786 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
788 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
789 .EdgeFlagEnable
= true,
790 .SourceElementFormat
= format
,
791 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
792 .Component0Control
= VFCOMP_STORE_SRC
,
793 .Component1Control
= VFCOMP_STORE_0
,
794 .Component2Control
= VFCOMP_STORE_0
,
795 .Component3Control
= VFCOMP_STORE_0
,
798 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
799 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
804 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
805 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
806 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
807 unsigned element_index
;
809 /* The edge flag element is reordered to be the last one in the code
810 * above so we need to compensate for that in the element indices used
813 if (input
== gen6_edgeflag_input
)
814 element_index
= nr_elements
- 1;
818 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
819 vfi
.VertexElementIndex
= element_index
;
820 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
821 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
825 if (vs_prog_data
->uses_drawid
) {
826 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
828 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
829 vfi
.VertexElementIndex
= element
;
835 static const struct brw_tracked_state
genX(vertices
) = {
837 .mesa
= _NEW_POLYGON
,
838 .brw
= BRW_NEW_BATCH
|
841 BRW_NEW_VS_PROG_DATA
,
843 .emit
= genX(emit_vertices
),
847 genX(emit_index_buffer
)(struct brw_context
*brw
)
849 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
851 if (index_buffer
== NULL
)
854 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
855 #if GEN_GEN < 8 && !GEN_IS_HASWELL
856 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
858 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
859 ib
.BufferStartingAddress
= ro_bo(brw
->ib
.bo
, 0);
861 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
862 ib
.BufferSize
= brw
->ib
.size
;
864 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
869 static const struct brw_tracked_state
genX(index_buffer
) = {
872 .brw
= BRW_NEW_BATCH
|
874 BRW_NEW_INDEX_BUFFER
,
876 .emit
= genX(emit_index_buffer
),
879 #if GEN_IS_HASWELL || GEN_GEN >= 8
881 genX(upload_cut_index
)(struct brw_context
*brw
)
883 const struct gl_context
*ctx
= &brw
->ctx
;
885 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
886 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
887 vf
.IndexedDrawCutIndexEnable
= true;
888 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
893 const struct brw_tracked_state
genX(cut_index
) = {
895 .mesa
= _NEW_TRANSFORM
,
896 .brw
= BRW_NEW_INDEX_BUFFER
,
898 .emit
= genX(upload_cut_index
),
904 * Determine the appropriate attribute override value to store into the
905 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
906 * override value contains two pieces of information: the location of the
907 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
908 * flag indicating whether to "swizzle" the attribute based on the direction
909 * the triangle is facing.
911 * If an attribute is "swizzled", then the given VUE location is used for
912 * front-facing triangles, and the VUE location that immediately follows is
913 * used for back-facing triangles. We use this to implement the mapping from
914 * gl_FrontColor/gl_BackColor to gl_Color.
916 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
917 * being instructed to begin reading attribute data. It can be set to a
918 * nonzero value to prevent the SF unit from wasting time reading elements of
919 * the VUE that are not needed by the fragment shader. It is measured in
920 * 256-bit increments.
923 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
924 const struct brw_vue_map
*vue_map
,
925 int urb_entry_read_offset
, int fs_attr
,
926 bool two_side_color
, uint32_t *max_source_attr
)
928 /* Find the VUE slot for this attribute. */
929 int slot
= vue_map
->varying_to_slot
[fs_attr
];
931 /* Viewport and Layer are stored in the VUE header. We need to override
932 * them to zero if earlier stages didn't write them, as GL requires that
933 * they read back as zero when not explicitly set.
935 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
936 attr
->ComponentOverrideX
= true;
937 attr
->ComponentOverrideW
= true;
938 attr
->ConstantSource
= CONST_0000
;
940 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
941 attr
->ComponentOverrideY
= true;
942 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
943 attr
->ComponentOverrideZ
= true;
948 /* If there was only a back color written but not front, use back
949 * as the color instead of undefined
951 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
952 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
953 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
954 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
957 /* This attribute does not exist in the VUE--that means that the vertex
958 * shader did not write to it. This means that either:
960 * (a) This attribute is a texture coordinate, and it is going to be
961 * replaced with point coordinates (as a consequence of a call to
962 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
963 * hardware will ignore whatever attribute override we supply.
965 * (b) This attribute is read by the fragment shader but not written by
966 * the vertex shader, so its value is undefined. Therefore the
967 * attribute override we supply doesn't matter.
969 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
970 * previous shader stage.
972 * Note that we don't have to worry about the cases where the attribute
973 * is gl_PointCoord or is undergoing point sprite coordinate
974 * replacement, because in those cases, this function isn't called.
976 * In case (c), we need to program the attribute overrides so that the
977 * primitive ID will be stored in this slot. In every other case, the
978 * attribute override we supply doesn't matter. So just go ahead and
979 * program primitive ID in every case.
981 attr
->ComponentOverrideW
= true;
982 attr
->ComponentOverrideX
= true;
983 attr
->ComponentOverrideY
= true;
984 attr
->ComponentOverrideZ
= true;
985 attr
->ConstantSource
= PRIM_ID
;
989 /* Compute the location of the attribute relative to urb_entry_read_offset.
990 * Each increment of urb_entry_read_offset represents a 256-bit value, so
991 * it counts for two 128-bit VUE slots.
993 int source_attr
= slot
- 2 * urb_entry_read_offset
;
994 assert(source_attr
>= 0 && source_attr
< 32);
996 /* If we are doing two-sided color, and the VUE slot following this one
997 * represents a back-facing color, then we need to instruct the SF unit to
998 * do back-facing swizzling.
1000 bool swizzling
= two_side_color
&&
1001 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1002 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1003 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1004 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1006 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1007 if (*max_source_attr
< source_attr
+ swizzling
)
1008 *max_source_attr
= source_attr
+ swizzling
;
1010 attr
->SourceAttribute
= source_attr
;
1012 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1017 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1018 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1019 uint32_t *point_sprite_enables
,
1020 uint32_t *urb_entry_read_length
,
1021 uint32_t *urb_entry_read_offset
)
1023 const struct gl_context
*ctx
= &brw
->ctx
;
1026 const struct gl_point_attrib
*point
= &ctx
->Point
;
1028 /* BRW_NEW_FRAGMENT_PROGRAM */
1029 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1031 /* BRW_NEW_FS_PROG_DATA */
1032 const struct brw_wm_prog_data
*wm_prog_data
=
1033 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1034 uint32_t max_source_attr
= 0;
1036 *point_sprite_enables
= 0;
1039 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1040 &brw
->vue_map_geom_out
);
1042 /* Each URB offset packs two varying slots */
1043 assert(first_slot
% 2 == 0);
1044 *urb_entry_read_offset
= first_slot
/ 2;
1046 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1047 * description of dw10 Point Sprite Texture Coordinate Enable:
1049 * "This field must be programmed to zero when non-point primitives
1052 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1053 * must be programmed to zero when rendering non-point primitives, but
1054 * the IvyBridge PRM does, and if we don't, we get garbage.
1056 * This is not required on Haswell, as the hardware ignores this state
1057 * when drawing non-points -- although we do still need to be careful to
1058 * correctly set the attr overrides.
1061 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1063 bool drawing_points
= brw_is_drawing_points(brw
);
1065 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1066 int input_index
= wm_prog_data
->urb_setup
[attr
];
1068 if (input_index
< 0)
1072 bool point_sprite
= false;
1073 if (drawing_points
) {
1074 if (point
->PointSprite
&&
1075 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1076 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1077 point_sprite
= true;
1080 if (attr
== VARYING_SLOT_PNTC
)
1081 point_sprite
= true;
1084 *point_sprite_enables
|= (1 << input_index
);
1087 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1088 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1090 if (!point_sprite
) {
1091 genX(get_attr_override
)(&attribute
,
1092 &brw
->vue_map_geom_out
,
1093 *urb_entry_read_offset
, attr
,
1094 _mesa_vertex_program_two_side_enabled(ctx
),
1098 /* The hardware can only do the overrides on 16 overrides at a
1099 * time, and the other up to 16 have to be lined up so that the
1100 * input index = the output index. We'll need to do some
1101 * tweaking to make sure that's the case.
1103 if (input_index
< 16)
1104 attr_overrides
[input_index
] = attribute
;
1106 assert(attribute
.SourceAttribute
== input_index
);
1109 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1110 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1112 * "This field should be set to the minimum length required to read the
1113 * maximum source attribute. The maximum source attribute is indicated
1114 * by the maximum value of the enabled Attribute # Source Attribute if
1115 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1116 * enable is not set.
1117 * read_length = ceiling((max_source_attr + 1) / 2)
1119 * [errata] Corruption/Hang possible if length programmed larger than
1122 * Similar text exists for Ivy Bridge.
1124 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1128 /* ---------------------------------------------------------------------- */
1131 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1133 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1135 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1139 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1141 struct gl_context
*ctx
= &brw
->ctx
;
1144 struct intel_renderbuffer
*depth_irb
=
1145 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1148 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1151 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1152 const int b
= stencil
->_BackFace
;
1154 if (depth
->Test
&& depth_irb
) {
1155 ds
->DepthTestEnable
= true;
1156 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1157 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1160 if (brw
->stencil_enabled
) {
1161 ds
->StencilTestEnable
= true;
1162 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1163 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1165 ds
->StencilTestFunction
=
1166 intel_translate_compare_func(stencil
->Function
[0]);
1168 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1169 ds
->StencilPassDepthPassOp
=
1170 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1171 ds
->StencilPassDepthFailOp
=
1172 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1174 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1176 if (brw
->stencil_two_sided
) {
1177 ds
->DoubleSidedStencilEnable
= true;
1178 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1179 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1181 ds
->BackfaceStencilTestFunction
=
1182 intel_translate_compare_func(stencil
->Function
[b
]);
1183 ds
->BackfaceStencilFailOp
=
1184 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1185 ds
->BackfaceStencilPassDepthPassOp
=
1186 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1187 ds
->BackfaceStencilPassDepthFailOp
=
1188 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1191 #if GEN_GEN <= 5 || GEN_GEN >= 9
1192 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1193 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1200 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1203 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1204 set_depth_stencil_bits(brw
, &wmds
);
1208 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1209 set_depth_stencil_bits(brw
, &ds
);
1212 /* Now upload a pointer to the indirect state */
1214 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1215 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1216 ptr
.DEPTH_STENCIL_STATEChange
= true;
1219 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1220 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1226 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1228 .mesa
= _NEW_BUFFERS
|
1231 .brw
= BRW_NEW_BLORP
|
1232 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1234 BRW_NEW_STATE_BASE_ADDRESS
),
1236 .emit
= genX(upload_depth_stencil_state
),
1240 /* ---------------------------------------------------------------------- */
1245 genX(upload_clip_state
)(struct brw_context
*brw
)
1247 struct gl_context
*ctx
= &brw
->ctx
;
1249 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1250 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1251 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1252 clip
.GRFRegisterCount
=
1253 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1254 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1255 clip
.SingleProgramFlow
= true;
1256 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1257 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1259 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1260 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1261 clip
.DispatchGRFStartRegisterForURBData
= 1;
1262 clip
.VertexURBEntryReadOffset
= 0;
1264 /* BRW_NEW_URB_FENCE */
1265 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1266 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1268 if (brw
->urb
.nr_clip_entries
>= 10) {
1269 /* Half of the URB entries go to each thread, and it has to be an
1272 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1274 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1275 * only 2 threads can output VUEs at a time.
1277 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1279 assert(brw
->urb
.nr_clip_entries
>= 5);
1280 clip
.MaximumNumberofThreads
= 1 - 1;
1283 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1284 clip
.UserClipFlagsMustClipEnable
= true;
1285 clip
.GuardbandClipTestEnable
= true;
1287 clip
.ClipperViewportStatePointer
=
1288 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1290 clip
.ScreenSpaceViewportXMin
= -1;
1291 clip
.ScreenSpaceViewportXMax
= 1;
1292 clip
.ScreenSpaceViewportYMin
= -1;
1293 clip
.ScreenSpaceViewportYMax
= 1;
1295 clip
.ViewportXYClipTestEnable
= true;
1296 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1298 /* _NEW_TRANSFORM */
1299 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1300 clip
.UserClipDistanceClipTestEnableBitmask
=
1301 ctx
->Transform
.ClipPlanesEnabled
;
1303 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1306 clip
.UserClipDistanceClipTestEnableBitmask
=
1307 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1310 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1311 clip
.APIMode
= APIMODE_D3D
;
1313 clip
.APIMode
= APIMODE_OGL
;
1315 clip
.GuardbandClipTestEnable
= true;
1317 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1320 clip
.NegativeWClipTestEnable
= true;
1325 const struct brw_tracked_state
genX(clip_state
) = {
1327 .mesa
= _NEW_TRANSFORM
|
1329 .brw
= BRW_NEW_BATCH
|
1331 BRW_NEW_CLIP_PROG_DATA
|
1332 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1333 BRW_NEW_PROGRAM_CACHE
|
1336 .emit
= genX(upload_clip_state
),
1342 genX(upload_clip_state
)(struct brw_context
*brw
)
1344 struct gl_context
*ctx
= &brw
->ctx
;
1347 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1349 /* BRW_NEW_FS_PROG_DATA */
1350 struct brw_wm_prog_data
*wm_prog_data
=
1351 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1353 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1354 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1356 if (wm_prog_data
->barycentric_interp_modes
&
1357 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1358 clip
.NonPerspectiveBarycentricEnable
= true;
1361 clip
.EarlyCullEnable
= true;
1365 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1367 if (ctx
->Polygon
.CullFlag
) {
1368 switch (ctx
->Polygon
.CullFaceMode
) {
1370 clip
.CullMode
= CULLMODE_FRONT
;
1373 clip
.CullMode
= CULLMODE_BACK
;
1375 case GL_FRONT_AND_BACK
:
1376 clip
.CullMode
= CULLMODE_BOTH
;
1379 unreachable("Should not get here: invalid CullFlag");
1382 clip
.CullMode
= CULLMODE_NONE
;
1387 clip
.UserClipDistanceCullTestEnableBitmask
=
1388 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1390 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1394 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1395 clip
.TriangleStripListProvokingVertexSelect
= 0;
1396 clip
.TriangleFanProvokingVertexSelect
= 1;
1397 clip
.LineStripListProvokingVertexSelect
= 0;
1399 clip
.TriangleStripListProvokingVertexSelect
= 2;
1400 clip
.TriangleFanProvokingVertexSelect
= 2;
1401 clip
.LineStripListProvokingVertexSelect
= 1;
1404 /* _NEW_TRANSFORM */
1405 clip
.UserClipDistanceClipTestEnableBitmask
=
1406 ctx
->Transform
.ClipPlanesEnabled
;
1409 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1412 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1413 clip
.APIMode
= APIMODE_D3D
;
1415 clip
.APIMode
= APIMODE_OGL
;
1417 clip
.GuardbandClipTestEnable
= true;
1419 /* BRW_NEW_VIEWPORT_COUNT */
1420 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1422 if (ctx
->RasterDiscard
) {
1423 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1425 perf_debug("Rasterizer discard is currently implemented via the "
1426 "clipper; having the GS not write primitives would "
1427 "likely be faster.\n");
1430 clip
.ClipMode
= CLIPMODE_NORMAL
;
1433 clip
.ClipEnable
= true;
1436 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1438 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1439 clip
.ViewportXYClipTestEnable
= true;
1441 clip
.MinimumPointWidth
= 0.125;
1442 clip
.MaximumPointWidth
= 255.875;
1443 clip
.MaximumVPIndex
= viewport_count
- 1;
1444 if (_mesa_geometric_layers(fb
) == 0)
1445 clip
.ForceZeroRTAIndexEnable
= true;
1449 static const struct brw_tracked_state
genX(clip_state
) = {
1451 .mesa
= _NEW_BUFFERS
|
1455 .brw
= BRW_NEW_BLORP
|
1457 BRW_NEW_FS_PROG_DATA
|
1458 BRW_NEW_GS_PROG_DATA
|
1459 BRW_NEW_VS_PROG_DATA
|
1460 BRW_NEW_META_IN_PROGRESS
|
1462 BRW_NEW_RASTERIZER_DISCARD
|
1463 BRW_NEW_TES_PROG_DATA
|
1464 BRW_NEW_VIEWPORT_COUNT
,
1466 .emit
= genX(upload_clip_state
),
1470 /* ---------------------------------------------------------------------- */
1473 genX(upload_sf
)(struct brw_context
*brw
)
1475 struct gl_context
*ctx
= &brw
->ctx
;
1480 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1481 UNUSED
const bool multisampled_fbo
=
1482 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1486 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1488 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1490 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1491 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1492 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1493 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1494 sf
.DispatchGRFStartRegisterForURBData
= 3;
1495 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1496 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1497 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1498 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1500 /* STATE_PREFETCH command description describes this state as being
1501 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1504 sf
.SetupViewportStateOffset
=
1505 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1507 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1509 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1510 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1512 sf
.MaximumNumberofThreads
=
1513 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1515 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1517 sf
.DestinationOriginHorizontalBias
= 0.5;
1518 sf
.DestinationOriginVerticalBias
= 0.5;
1520 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1521 sf
.StatisticsEnable
= true;
1523 sf
.ViewportTransformEnable
= true;
1527 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1532 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1534 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1535 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1536 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1538 switch (ctx
->Polygon
.FrontMode
) {
1540 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1543 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1546 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1549 unreachable("not reached");
1552 switch (ctx
->Polygon
.BackMode
) {
1554 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1557 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1560 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1563 unreachable("not reached");
1566 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1567 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1569 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1570 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1571 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1574 sf
.ScissorRectangleEnable
= true;
1576 if (ctx
->Polygon
.CullFlag
) {
1577 switch (ctx
->Polygon
.CullFaceMode
) {
1579 sf
.CullMode
= CULLMODE_FRONT
;
1582 sf
.CullMode
= CULLMODE_BACK
;
1584 case GL_FRONT_AND_BACK
:
1585 sf
.CullMode
= CULLMODE_BOTH
;
1588 unreachable("not reached");
1591 sf
.CullMode
= CULLMODE_NONE
;
1595 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1602 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1604 if (devinfo
->is_cherryview
)
1605 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1607 sf
.LineWidth
= brw_get_line_width(brw
);
1609 sf
.LineWidth
= brw_get_line_width(brw
);
1612 if (ctx
->Line
.SmoothFlag
) {
1613 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1615 sf
.AntiAliasingEnable
= true;
1619 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1620 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1621 /* Clamp to the hardware limits */
1622 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1624 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1625 if (use_state_point_size(brw
))
1626 sf
.PointWidthSource
= State
;
1629 /* _NEW_POINT | _NEW_MULTISAMPLE */
1630 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1631 !ctx
->Point
.PointSprite
)
1632 sf
.SmoothPointEnable
= true;
1637 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1639 const bool multisampled_fbo
=
1640 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1641 if (multisampled_fbo
)
1642 sf
.SmoothPointEnable
= false;
1645 #if GEN_IS_G4X || GEN_GEN >= 5
1646 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1650 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1651 sf
.TriangleStripListProvokingVertexSelect
= 2;
1652 sf
.TriangleFanProvokingVertexSelect
= 2;
1653 sf
.LineStripListProvokingVertexSelect
= 1;
1655 sf
.TriangleFanProvokingVertexSelect
= 1;
1659 /* BRW_NEW_FS_PROG_DATA */
1660 const struct brw_wm_prog_data
*wm_prog_data
=
1661 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1663 sf
.AttributeSwizzleEnable
= true;
1664 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1667 * Window coordinates in an FBO are inverted, which means point
1668 * sprite origin must be inverted, too.
1670 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1671 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1673 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1676 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1677 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1679 uint32_t urb_entry_read_length
;
1680 uint32_t urb_entry_read_offset
;
1681 uint32_t point_sprite_enables
;
1682 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1683 &urb_entry_read_length
,
1684 &urb_entry_read_offset
);
1685 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1686 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1687 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1688 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1693 static const struct brw_tracked_state
genX(sf_state
) = {
1695 .mesa
= _NEW_LIGHT
|
1699 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1700 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1701 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1702 .brw
= BRW_NEW_BLORP
|
1703 BRW_NEW_VUE_MAP_GEOM_OUT
|
1704 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1705 BRW_NEW_PROGRAM_CACHE
|
1706 BRW_NEW_SF_PROG_DATA
|
1710 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1711 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1712 BRW_NEW_GS_PROG_DATA
|
1714 BRW_NEW_TES_PROG_DATA
1716 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1717 BRW_NEW_FRAGMENT_PROGRAM
1720 .emit
= genX(upload_sf
),
1723 /* ---------------------------------------------------------------------- */
1726 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1728 struct gl_context
*ctx
= &brw
->ctx
;
1729 /* BRW_NEW_FRAGMENT_PROGRAM */
1730 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1734 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1735 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1736 uint64_t outputs_written
= fp
->info
.outputs_written
;
1739 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1740 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1741 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1750 genX(upload_wm
)(struct brw_context
*brw
)
1752 struct gl_context
*ctx
= &brw
->ctx
;
1754 /* BRW_NEW_FS_PROG_DATA */
1755 const struct brw_wm_prog_data
*wm_prog_data
=
1756 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1758 UNUSED
bool writes_depth
=
1759 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1760 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1761 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1764 /* We can't fold this into gen6_upload_wm_push_constants(), because
1765 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1766 * (3DSTATE_CONSTANT_PS [DevSNB]):
1768 * "[DevSNB]: This packet must be followed by WM_STATE."
1770 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1771 if (wm_prog_data
->base
.nr_params
!= 0) {
1772 wmcp
.Buffer0Valid
= true;
1773 /* Pointer to the WM constant buffer. Covered by the set of
1774 * state flags from gen6_upload_wm_push_constants.
1776 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1777 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1783 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1784 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1785 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1787 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1788 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1790 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1791 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1792 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1793 /* These two fields should be the same pre-gen6, which is why we
1794 * only have one hardware field to program for both dispatch
1797 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1798 wm_prog_data
->dispatch_grf_start_reg_2
);
1801 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1802 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1804 if (stage_state
->sampler_count
)
1805 wm
.SamplerStatePointer
=
1806 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1808 if (wm_prog_data
->prog_offset_2
)
1809 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1812 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1813 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1814 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1815 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1816 wm
.EarlyDepthTestEnable
= true;
1817 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1818 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1821 if (ctx
->Polygon
.OffsetFill
) {
1822 wm
.GlobalDepthOffsetEnable
= true;
1823 /* Something weird going on with legacy_global_depth_bias,
1824 * offset_constant, scaling and MRD. This value passes glean
1825 * but gives some odd results elsewere (eg. the
1826 * quad-offset-units test).
1828 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1830 /* This is the only value that passes glean:
1832 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1835 wm
.DepthCoefficientURBReadOffset
= 1;
1838 /* BRW_NEW_STATS_WM */
1839 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1842 if (wm_prog_data
->base
.use_alt_mode
)
1843 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1845 wm
.SamplerCount
= GEN_GEN
== 5 ?
1846 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1848 wm
.BindingTableEntryCount
=
1849 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1850 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1851 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1852 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1853 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1854 wm_prog_data
->base
.dispatch_grf_start_reg
;
1856 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1857 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1861 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1862 wm
.KernelStartPointer2
=
1863 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1868 wm
.DualSourceBlendEnable
=
1869 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1870 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1871 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1872 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1874 /* From the SNB PRM, volume 2 part 1, page 281:
1875 * "If the PS kernel does not need the Position XY Offsets
1876 * to compute a Position XY value, then this field should be
1877 * programmed to POSOFFSET_NONE."
1879 * "SW Recommendation: If the PS kernel needs the Position Offsets
1880 * to compute a Position XY value, this field should match Position
1881 * ZW Interpolation Mode to ensure a consistent position.xyzw
1883 * We only require XY sample offsets. So, this recommendation doesn't
1884 * look useful at the moment. We might need this in future.
1886 if (wm_prog_data
->uses_pos_offset
)
1887 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1889 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1891 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1892 wm_prog_data
->dispatch_grf_start_reg_2
;
1895 if (wm_prog_data
->base
.total_scratch
) {
1896 wm
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
1897 wm
.PerThreadScratchSpace
=
1898 ffs(stage_state
->per_thread_scratch
) - 11;
1901 wm
.PixelShaderComputedDepth
= writes_depth
;
1905 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1908 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1913 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1916 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1918 if (multisampled_fbo
) {
1919 /* _NEW_MULTISAMPLE */
1920 if (ctx
->Multisample
.Enabled
)
1921 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1923 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1925 if (wm_prog_data
->persample_dispatch
)
1926 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1928 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1930 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1931 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1934 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1935 if (wm_prog_data
->uses_kill
||
1936 _mesa_is_alpha_test_enabled(ctx
) ||
1937 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1938 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1939 wm
.PixelShaderKillsPixel
= true;
1942 /* _NEW_BUFFERS | _NEW_COLOR */
1943 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1944 wm
.PixelShaderKillsPixel
||
1945 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1946 wm
.ThreadDispatchEnable
= true;
1950 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1951 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1954 /* The "UAV access enable" bits are unnecessary on HSW because they only
1955 * seem to have an effect on the HW-assisted coherency mechanism which we
1956 * don't need, and the rasterization-related UAV_ONLY flag and the
1957 * DISPATCH_ENABLE bit can be set independently from it.
1958 * C.f. gen8_upload_ps_extra().
1960 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1964 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1965 wm_prog_data
->has_side_effects
)
1971 /* BRW_NEW_FS_PROG_DATA */
1972 if (wm_prog_data
->early_fragment_tests
)
1973 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1974 else if (wm_prog_data
->has_side_effects
)
1975 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1980 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
1981 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
1982 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1985 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
1990 static const struct brw_tracked_state
genX(wm_state
) = {
1994 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1997 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
1998 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
1999 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2000 .brw
= BRW_NEW_BLORP
|
2001 BRW_NEW_FS_PROG_DATA
|
2002 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2003 BRW_NEW_FRAGMENT_PROGRAM
|
2004 BRW_NEW_PROGRAM_CACHE
|
2005 BRW_NEW_SAMPLER_STATE_TABLE
|
2008 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2010 .emit
= genX(upload_wm
),
2013 /* ---------------------------------------------------------------------- */
2015 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2016 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2017 pkt.SamplerCount = \
2018 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2019 pkt.BindingTableEntryCount = \
2020 stage_prog_data->binding_table.size_bytes / 4; \
2021 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2023 if (stage_prog_data->total_scratch) { \
2024 pkt.ScratchSpaceBasePointer = rw_bo(stage_state->scratch_bo, 0); \
2025 pkt.PerThreadScratchSpace = \
2026 ffs(stage_state->per_thread_scratch) - 11; \
2029 pkt.DispatchGRFStartRegisterForURBData = \
2030 stage_prog_data->dispatch_grf_start_reg; \
2031 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2032 pkt.prefix##URBEntryReadOffset = 0; \
2034 pkt.StatisticsEnable = true; \
2038 genX(upload_vs_state
)(struct brw_context
*brw
)
2040 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2041 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2042 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2044 /* BRW_NEW_VS_PROG_DATA */
2045 const struct brw_vue_prog_data
*vue_prog_data
=
2046 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2047 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2049 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2050 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2053 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2054 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2056 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2057 * command that causes the VS Function Enable to toggle. Pipeline
2058 * flush can be executed by sending a PIPE_CONTROL command with CS
2059 * stall bit set and a post sync operation.
2061 * We've already done such a flush at the start of state upload, so we
2062 * don't need to do another one here.
2064 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2065 if (stage_state
->push_const_size
!= 0) {
2066 cvs
.Buffer0Valid
= true;
2067 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2068 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2073 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2074 gen7_emit_vs_workaround_flush(brw
);
2077 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2079 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2080 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2082 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2084 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2087 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2088 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2089 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2091 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2092 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2094 vs
.MaximumNumberofThreads
=
2095 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2097 vs
.StatisticsEnable
= false;
2098 vs
.SamplerStatePointer
=
2099 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2103 /* Force single program flow on Ironlake. We cannot reliably get
2104 * all applications working without it. See:
2105 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2107 * The most notable and reliably failing application is the Humus
2110 vs
.SingleProgramFlow
= true;
2111 vs
.SamplerCount
= 0; /* hardware requirement */
2115 vs
.SIMD8DispatchEnable
=
2116 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2118 vs
.UserClipDistanceCullTestEnableBitmask
=
2119 vue_prog_data
->cull_distance_mask
;
2124 /* Based on my reading of the simulator, the VS constants don't get
2125 * pulled into the VS FF unit until an appropriate pipeline flush
2126 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2127 * references to them into a little FIFO. The flushes are common,
2128 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2129 * the primitive to use the wrong constants. Then the FIFO
2130 * containing the constant setup gets added to again on the next
2131 * constants change, and eventually when a flush does happen the
2132 * unit is overwhelmed by constant changes and dies.
2134 * To avoid this, send a PIPE_CONTROL down the line that will
2135 * update the unit immediately loading the constants. The flush
2136 * type bits here were those set by the STATE_BASE_ADDRESS whose
2137 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2138 * bug reports that led to this workaround, and may be more than
2139 * what is strictly required to avoid the issue.
2141 brw_emit_pipe_control_flush(brw
,
2142 PIPE_CONTROL_DEPTH_STALL
|
2143 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2144 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2148 static const struct brw_tracked_state
genX(vs_state
) = {
2150 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2151 .brw
= BRW_NEW_BATCH
|
2154 BRW_NEW_VS_PROG_DATA
|
2155 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2156 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2157 BRW_NEW_PROGRAM_CACHE
|
2158 BRW_NEW_SAMPLER_STATE_TABLE
|
2162 .emit
= genX(upload_vs_state
),
2165 /* ---------------------------------------------------------------------- */
2168 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2170 struct gl_context
*ctx
= &brw
->ctx
;
2172 /* BRW_NEW_VIEWPORT_COUNT */
2173 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2175 struct GENX(CC_VIEWPORT
) ccv
;
2176 uint32_t cc_vp_offset
;
2178 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2181 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2182 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2183 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2184 if (ctx
->Transform
.DepthClamp
) {
2185 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2186 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2188 ccv
.MinimumDepth
= 0.0;
2189 ccv
.MaximumDepth
= 1.0;
2191 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2192 cc_map
+= GENX(CC_VIEWPORT_length
);
2196 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2197 ptr
.CCViewportPointer
= cc_vp_offset
;
2200 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2201 vp
.CCViewportStateChange
= 1;
2202 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2205 brw
->cc
.vp_offset
= cc_vp_offset
;
2206 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2210 const struct brw_tracked_state
genX(cc_vp
) = {
2212 .mesa
= _NEW_TRANSFORM
|
2214 .brw
= BRW_NEW_BATCH
|
2216 BRW_NEW_VIEWPORT_COUNT
,
2218 .emit
= genX(upload_cc_viewport
)
2221 /* ---------------------------------------------------------------------- */
2224 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2225 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2226 struct GENX(SCISSOR_RECT
) *sc
)
2230 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2231 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2232 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2233 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2234 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2236 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2237 /* If the scissor was out of bounds and got clamped to 0 width/height
2238 * at the bounds, the subtraction of 1 from maximums could produce a
2239 * negative number and thus not clip anything. Instead, just provide
2240 * a min > max scissor inside the bounds, which produces the expected
2243 sc
->ScissorRectangleXMin
= 1;
2244 sc
->ScissorRectangleXMax
= 0;
2245 sc
->ScissorRectangleYMin
= 1;
2246 sc
->ScissorRectangleYMax
= 0;
2247 } else if (render_to_fbo
) {
2248 /* texmemory: Y=0=bottom */
2249 sc
->ScissorRectangleXMin
= bbox
[0];
2250 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2251 sc
->ScissorRectangleYMin
= bbox
[2];
2252 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2254 /* memory: Y=0=top */
2255 sc
->ScissorRectangleXMin
= bbox
[0];
2256 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2257 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2258 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2264 genX(upload_scissor_state
)(struct brw_context
*brw
)
2266 struct gl_context
*ctx
= &brw
->ctx
;
2267 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2268 struct GENX(SCISSOR_RECT
) scissor
;
2269 uint32_t scissor_state_offset
;
2270 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2271 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2272 uint32_t *scissor_map
;
2274 /* BRW_NEW_VIEWPORT_COUNT */
2275 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2277 scissor_map
= brw_state_batch(
2278 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2279 32, &scissor_state_offset
);
2281 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2283 /* The scissor only needs to handle the intersection of drawable and
2284 * scissor rect. Clipping to the boundaries of static shared buffers
2285 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2287 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2288 * inclusive but max is exclusive.
2290 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2291 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2292 GENX(SCISSOR_RECT_pack
)(
2293 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2296 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2297 ptr
.ScissorRectPointer
= scissor_state_offset
;
2301 static const struct brw_tracked_state
genX(scissor_state
) = {
2303 .mesa
= _NEW_BUFFERS
|
2306 .brw
= BRW_NEW_BATCH
|
2308 BRW_NEW_VIEWPORT_COUNT
,
2310 .emit
= genX(upload_scissor_state
),
2314 /* ---------------------------------------------------------------------- */
2317 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2318 float m00
, float m11
, float m30
, float m31
,
2319 float *xmin
, float *xmax
,
2320 float *ymin
, float *ymax
)
2322 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2323 * Strips and Fans documentation:
2325 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2326 * fixed-point "guardband" range supported by the rasterization hardware"
2330 * "In almost all circumstances, if an object’s vertices are actually
2331 * modified by this clamping (i.e., had X or Y coordinates outside of
2332 * the guardband extent the rendered object will not match the intended
2333 * result. Therefore software should take steps to ensure that this does
2334 * not happen - e.g., by clipping objects such that they do not exceed
2335 * these limits after the Drawing Rectangle is applied."
2337 * I believe the fundamental restriction is that the rasterizer (in
2338 * the SF/WM stages) have a limit on the number of pixels that can be
2339 * rasterized. We need to ensure any coordinates beyond the rasterizer
2340 * limit are handled by the clipper. So effectively that limit becomes
2341 * the clipper's guardband size.
2343 * It goes on to say:
2345 * "In addition, in order to be correctly rendered, objects must have a
2346 * screenspace bounding box not exceeding 8K in the X or Y direction.
2347 * This additional restriction must also be comprehended by software,
2348 * i.e., enforced by use of clipping."
2350 * This makes no sense. Gen7+ hardware supports 16K render targets,
2351 * and you definitely need to be able to draw polygons that fill the
2352 * surface. Our assumption is that the rasterizer was limited to 8K
2353 * on Sandybridge, which only supports 8K surfaces, and it was actually
2354 * increased to 16K on Ivybridge and later.
2356 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2358 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2360 if (m00
!= 0 && m11
!= 0) {
2361 /* First, we compute the screen-space render area */
2362 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2363 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2364 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2365 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2367 /* We want the guardband to be centered on that */
2368 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2369 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2370 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2371 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2373 /* Now we need it in native device coordinates */
2374 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2375 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2376 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2377 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2379 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2380 * flipped upside-down. X should be fine though.
2382 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2383 *xmin
= ndc_gb_xmin
;
2384 *xmax
= ndc_gb_xmax
;
2385 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2386 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2388 /* The viewport scales to 0, so nothing will be rendered. */
2397 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2399 struct gl_context
*ctx
= &brw
->ctx
;
2400 float y_scale
, y_bias
;
2402 /* BRW_NEW_VIEWPORT_COUNT */
2403 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2406 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2407 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2408 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2412 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2413 uint32_t sf_clip_vp_offset
;
2414 uint32_t *sf_clip_map
=
2415 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2416 64, &sf_clip_vp_offset
);
2418 struct GENX(SF_VIEWPORT
) sfv
;
2419 struct GENX(CLIP_VIEWPORT
) clv
;
2420 uint32_t sf_vp_offset
, clip_vp_offset
;
2422 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2424 uint32_t *clip_map
=
2425 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2426 32, &clip_vp_offset
);
2430 if (render_to_fbo
) {
2435 y_bias
= (float)fb_height
;
2438 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2439 /* _NEW_VIEWPORT: Guardband Clipping */
2440 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2441 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2443 sfv
.ViewportMatrixElementm00
= scale
[0];
2444 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2445 sfv
.ViewportMatrixElementm22
= scale
[2],
2446 sfv
.ViewportMatrixElementm30
= translate
[0],
2447 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2448 sfv
.ViewportMatrixElementm32
= translate
[2],
2449 brw_calculate_guardband_size(fb_width
, fb_height
,
2450 sfv
.ViewportMatrixElementm00
,
2451 sfv
.ViewportMatrixElementm11
,
2452 sfv
.ViewportMatrixElementm30
,
2453 sfv
.ViewportMatrixElementm31
,
2454 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2457 clv
.XMinClipGuardband
= gb_xmin
;
2458 clv
.XMaxClipGuardband
= gb_xmax
;
2459 clv
.YMinClipGuardband
= gb_ymin
;
2460 clv
.YMaxClipGuardband
= gb_ymax
;
2463 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2464 &sfv
.ScissorRectangle
);
2466 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2467 * The hardware will take the intersection of the drawing rectangle,
2468 * scissor rectangle, and the viewport extents. We don't need to be
2469 * smart, and can therefore just program the viewport extents.
2471 const float viewport_Xmax
=
2472 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2473 const float viewport_Ymax
=
2474 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2476 if (render_to_fbo
) {
2477 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2478 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2479 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2480 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2482 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2483 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2484 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2485 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2490 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2491 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2493 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2494 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2495 sf_map
+= GENX(SF_VIEWPORT_length
);
2496 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2501 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2502 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2505 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2506 vp
.SFViewportStateChange
= 1;
2507 vp
.CLIPViewportStateChange
= 1;
2508 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2509 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2512 brw
->sf
.vp_offset
= sf_vp_offset
;
2513 brw
->clip
.vp_offset
= clip_vp_offset
;
2514 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2518 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2520 .mesa
= _NEW_BUFFERS
|
2522 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2523 .brw
= BRW_NEW_BATCH
|
2525 BRW_NEW_VIEWPORT_COUNT
,
2527 .emit
= genX(upload_sf_clip_viewport
),
2530 /* ---------------------------------------------------------------------- */
2533 genX(upload_gs_state
)(struct brw_context
*brw
)
2535 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2536 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2537 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2538 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2539 /* BRW_NEW_GEOMETRY_PROGRAM */
2540 bool active
= GEN_GEN
>= 6 && gs_prog
;
2542 /* BRW_NEW_GS_PROG_DATA */
2543 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2544 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2545 brw_vue_prog_data(stage_prog_data
);
2547 const struct brw_gs_prog_data
*gs_prog_data
=
2548 brw_gs_prog_data(stage_prog_data
);
2552 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2553 if (active
&& stage_state
->push_const_size
!= 0) {
2554 cgs
.Buffer0Valid
= true;
2555 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2556 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2561 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2563 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2564 * Geometry > Geometry Shader > State:
2566 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2567 * whole fixed function pipeline when the GS enable changes value in
2570 * The hardware architects have clarified that in this context "flush the
2571 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2574 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2575 gen7_emit_cs_stall_flush(brw
);
2579 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2581 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2582 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2587 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2590 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2591 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2592 gs
.ControlDataHeaderSize
=
2593 gs_prog_data
->control_data_header_size_hwords
;
2595 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2596 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2598 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2600 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2603 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2604 * Ivy Bridge and Haswell.
2606 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2607 * strip to be delivered to the geometry shader in an order that does
2608 * not strictly follow the OpenGL spec, but preserves triangle
2609 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2610 * the geometry shader sees triangles:
2612 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2614 * (Clearing the bit is even worse, because it fails to preserve
2617 * Triangle strips with adjacency always ordered in a way that preserves
2618 * triangle orientation but does not strictly follow the OpenGL spec,
2619 * regardless of the setting of this bit.
2621 * On Haswell, both triangle strips and triangle strips with adjacency
2622 * are always ordered in a way that preserves triangle orientation.
2623 * Setting this bit causes the ordering to strictly follow the OpenGL
2626 * So in either case we want to set the bit. Unfortunately on Ivy
2627 * Bridge this will get the order close to correct but not perfect.
2629 gs
.ReorderMode
= TRAILING
;
2630 gs
.MaximumNumberofThreads
=
2631 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2632 : (devinfo
->max_gs_threads
- 1);
2635 gs
.SOStatisticsEnable
= true;
2636 if (gs_prog
->info
.has_transform_feedback_varyings
)
2637 gs
.SVBIPayloadEnable
= true;
2639 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2640 * was previously done for gen6.
2642 * TODO: test with both disabled to see if the HW is behaving
2643 * as expected, like in gen7.
2645 gs
.SingleProgramFlow
= true;
2646 gs
.VectorMaskEnable
= true;
2650 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2652 if (gs_prog_data
->static_vertex_count
!= -1) {
2653 gs
.StaticOutput
= true;
2654 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2656 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2658 gs
.UserClipDistanceCullTestEnableBitmask
=
2659 vue_prog_data
->cull_distance_mask
;
2661 const int urb_entry_write_offset
= 1;
2662 const uint32_t urb_entry_output_length
=
2663 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2664 urb_entry_write_offset
;
2666 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2667 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2673 if (!active
&& brw
->ff_gs
.prog_active
) {
2674 /* In gen6, transform feedback for the VS stage is done with an
2675 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2678 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2679 gs
.SingleProgramFlow
= true;
2680 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2681 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2684 gs
.GRFRegisterCount
=
2685 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2686 /* BRW_NEW_URB_FENCE */
2687 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2688 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2689 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2690 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2693 gs
.VectorMaskEnable
= true;
2694 gs
.SVBIPayloadEnable
= true;
2695 gs
.SVBIPostIncrementEnable
= true;
2696 gs
.SVBIPostIncrementValue
=
2697 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2698 gs
.SOStatisticsEnable
= true;
2699 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2703 if (!active
&& !brw
->ff_gs
.prog_active
) {
2705 gs
.DispatchGRFStartRegisterForURBData
= 1;
2707 gs
.IncludeVertexHandles
= true;
2713 gs
.StatisticsEnable
= true;
2715 #if GEN_GEN == 5 || GEN_GEN == 6
2716 gs
.RenderingEnabled
= true;
2719 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2724 brw
->gs
.enabled
= active
;
2728 static const struct brw_tracked_state
genX(gs_state
) = {
2730 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2731 .brw
= BRW_NEW_BATCH
|
2733 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2734 BRW_NEW_PROGRAM_CACHE
|
2736 BRW_NEW_VIEWPORT_COUNT
2738 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2739 BRW_NEW_GEOMETRY_PROGRAM
|
2740 BRW_NEW_GS_PROG_DATA
2742 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2744 .emit
= genX(upload_gs_state
),
2747 /* ---------------------------------------------------------------------- */
2749 UNUSED
static GLenum
2750 fix_dual_blend_alpha_to_one(GLenum function
)
2756 case GL_ONE_MINUS_SRC1_ALPHA
:
2763 #define blend_factor(x) brw_translate_blend_factor(x)
2764 #define blend_eqn(x) brw_translate_blend_equation(x)
2767 * Modify blend function to force destination alpha to 1.0
2769 * If \c function specifies a blend function that uses destination alpha,
2770 * replace it with a function that hard-wires destination alpha to 1.0. This
2771 * is used when rendering to xRGB targets.
2774 brw_fix_xRGB_alpha(GLenum function
)
2780 case GL_ONE_MINUS_DST_ALPHA
:
2781 case GL_SRC_ALPHA_SATURATE
:
2789 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2791 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2795 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2798 struct gl_context
*ctx
= &brw
->ctx
;
2801 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2803 bool independent_alpha_blend
= false;
2805 /* Used for implementing the following bit of GL_EXT_texture_integer:
2806 * "Per-fragment operations that require floating-point color
2807 * components, including multisample alpha operations, alpha test,
2808 * blending, and dithering, have no effect when the corresponding
2809 * colors are written to an integer color buffer."
2811 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2813 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2814 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2817 if (ctx
->Color
.ColorLogicOpEnabled
) {
2818 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2819 : GL_UNSIGNED_NORMALIZED
;
2820 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2821 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2822 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2824 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2825 _mesa_enum_to_string(rb_type
));
2826 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2827 entry
->LogicOpEnable
= true;
2828 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2830 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2831 && (GEN_GEN
<= 5 || !integer
)) {
2832 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2833 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2834 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2835 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2836 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2837 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2839 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2840 srcRGB
= dstRGB
= GL_ONE
;
2842 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2843 srcA
= dstA
= GL_ONE
;
2845 /* Due to hardware limitations, the destination may have information
2846 * in an alpha channel even when the format specifies no alpha
2847 * channel. In order to avoid getting any incorrect blending due to
2848 * that alpha channel, coerce the blend factors to values that will
2849 * not read the alpha channel, but will instead use the correct
2850 * implicit value for alpha.
2852 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2853 GL_TEXTURE_ALPHA_TYPE
)) {
2854 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2855 srcA
= brw_fix_xRGB_alpha(srcA
);
2856 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2857 dstA
= brw_fix_xRGB_alpha(dstA
);
2860 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2861 * "If Dual Source Blending is enabled, this bit must be disabled."
2863 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2864 * and leave it enabled anyway.
2866 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2867 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2868 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2869 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2870 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2873 entry
->ColorBufferBlendEnable
= true;
2874 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2875 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2876 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2877 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2878 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2879 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2881 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2882 independent_alpha_blend
= true;
2885 return independent_alpha_blend
;
2890 genX(upload_blend_state
)(struct brw_context
*brw
)
2892 struct gl_context
*ctx
= &brw
->ctx
;
2895 /* We need at least one BLEND_STATE written, because we might do
2896 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2897 * for computed depth or alpha test), which will do an FB write
2898 * with render target 0, which will reference BLEND_STATE[0] for
2899 * alpha test enable.
2901 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2902 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2903 nr_draw_buffers
= 1;
2905 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2907 size
+= GENX(BLEND_STATE_length
) * 4;
2910 uint32_t *blend_map
;
2911 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2914 struct GENX(BLEND_STATE
) blend
= { 0 };
2917 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2918 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2921 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2922 * "If drawbuffer zero is not NONE and the buffer it references has an
2923 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2924 * operations are skipped."
2926 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2927 /* _NEW_MULTISAMPLE */
2928 if (_mesa_is_multisample_enabled(ctx
)) {
2929 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2930 blend
.AlphaToCoverageEnable
= true;
2931 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2933 if (ctx
->Multisample
.SampleAlphaToOne
)
2934 blend
.AlphaToOneEnable
= true;
2938 if (ctx
->Color
.AlphaEnabled
) {
2939 blend
.AlphaTestEnable
= true;
2940 blend
.AlphaTestFunction
=
2941 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2944 if (ctx
->Color
.DitherFlag
) {
2945 blend
.ColorDitherEnable
= true;
2950 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2951 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2955 blend
.IndependentAlphaBlendEnable
=
2956 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
2957 blend
.IndependentAlphaBlendEnable
;
2959 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2960 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2962 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2963 * clamping in the fragment shader. For its clamping of
2964 * blending, the spec says:
2966 * "RESOLVED: For fixed-point color buffers, the inputs and
2967 * the result of the blending equation are clamped. For
2968 * floating-point color buffers, no clamping occurs."
2970 * So, generally, we want clamping to the render target's range.
2971 * And, good news, the hardware tables for both pre- and
2972 * post-blend color clamping are either ignored, or any are
2973 * allowed, or clamping is required but RT range clamping is a
2976 entry
.PreBlendColorClampEnable
= true;
2977 entry
.PostBlendColorClampEnable
= true;
2978 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2980 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
2981 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
2982 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
2983 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
2986 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2988 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2994 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2998 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2999 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3000 ptr
.BLEND_STATEChange
= true;
3003 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3004 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3006 ptr
.BlendStatePointerValid
= true;
3012 static const struct brw_tracked_state
genX(blend_state
) = {
3014 .mesa
= _NEW_BUFFERS
|
3017 .brw
= BRW_NEW_BATCH
|
3019 BRW_NEW_STATE_BASE_ADDRESS
,
3021 .emit
= genX(upload_blend_state
),
3025 /* ---------------------------------------------------------------------- */
3028 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3029 [MESA_SHADER_VERTEX
] = 21,
3030 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3031 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3032 [MESA_SHADER_GEOMETRY
] = 22,
3033 [MESA_SHADER_FRAGMENT
] = 23,
3034 [MESA_SHADER_COMPUTE
] = 0,
3038 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3040 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3041 struct gl_context
*ctx
= &brw
->ctx
;
3043 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3045 struct brw_stage_state
*stage_states
[] = {
3053 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3054 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3055 gen7_emit_vs_workaround_flush(brw
);
3057 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3058 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3059 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3061 if (!stage_state
->push_constants_dirty
)
3064 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3065 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3066 if (stage_state
->prog_data
) {
3067 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3068 /* The Skylake PRM contains the following restriction:
3070 * "The driver must ensure The following case does not occur
3071 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3072 * buffer 3 read length equal to zero committed followed by a
3073 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3076 * To avoid this, we program the buffers in the highest slots.
3077 * This way, slot 0 is only used if slot 3 is also used.
3081 for (int i
= 3; i
>= 0; i
--) {
3082 const struct brw_ubo_range
*range
=
3083 &stage_state
->prog_data
->ubo_ranges
[i
];
3085 if (range
->length
== 0)
3088 const struct gl_uniform_block
*block
=
3089 prog
->sh
.UniformBlocks
[range
->block
];
3090 const struct gl_buffer_binding
*binding
=
3091 &ctx
->UniformBufferBindings
[block
->Binding
];
3093 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3094 static unsigned msg_id
= 0;
3095 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3096 MESA_DEBUG_TYPE_UNDEFINED
,
3097 MESA_DEBUG_SEVERITY_HIGH
,
3098 "UBO %d unbound, %s shader uniform data "
3099 "will be undefined.",
3101 _mesa_shader_stage_to_string(stage
));
3105 assert(binding
->Offset
% 32 == 0);
3107 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3108 intel_buffer_object(binding
->BufferObject
),
3109 binding
->Offset
, range
->length
* 32, false);
3111 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3112 pkt
.ConstantBody
.Buffer
[n
] =
3113 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3117 if (stage_state
->push_const_size
> 0) {
3119 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3120 pkt
.ConstantBody
.Buffer
[n
] =
3121 ro_bo(stage_state
->push_const_bo
,
3122 stage_state
->push_const_offset
);
3125 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3126 pkt
.ConstantBody
.Buffer
[0].offset
=
3127 stage_state
->push_const_offset
| mocs
;
3132 stage_state
->push_constants_dirty
= false;
3133 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3137 const struct brw_tracked_state
genX(push_constant_packets
) = {
3140 .brw
= BRW_NEW_DRAW_CALL
,
3142 .emit
= genX(upload_push_constant_packets
),
3148 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3150 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3152 /* BRW_NEW_VERTEX_PROGRAM */
3153 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3154 /* BRW_NEW_VS_PROG_DATA */
3155 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3157 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3160 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3162 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3164 .brw
= BRW_NEW_BATCH
|
3166 BRW_NEW_VERTEX_PROGRAM
|
3167 BRW_NEW_VS_PROG_DATA
,
3169 .emit
= genX(upload_vs_push_constants
),
3173 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3175 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3177 /* BRW_NEW_GEOMETRY_PROGRAM */
3178 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3180 /* BRW_NEW_GS_PROG_DATA */
3181 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3183 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3186 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3188 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3190 .brw
= BRW_NEW_BATCH
|
3192 BRW_NEW_GEOMETRY_PROGRAM
|
3193 BRW_NEW_GS_PROG_DATA
,
3195 .emit
= genX(upload_gs_push_constants
),
3199 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3201 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3202 /* BRW_NEW_FRAGMENT_PROGRAM */
3203 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3204 /* BRW_NEW_FS_PROG_DATA */
3205 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3207 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3210 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3212 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3213 .brw
= BRW_NEW_BATCH
|
3215 BRW_NEW_FRAGMENT_PROGRAM
|
3216 BRW_NEW_FS_PROG_DATA
,
3218 .emit
= genX(upload_wm_push_constants
),
3222 /* ---------------------------------------------------------------------- */
3226 genX(determine_sample_mask
)(struct brw_context
*brw
)
3228 struct gl_context
*ctx
= &brw
->ctx
;
3229 float coverage
= 1.0f
;
3230 float coverage_invert
= false;
3231 unsigned sample_mask
= ~0u;
3233 /* BRW_NEW_NUM_SAMPLES */
3234 unsigned num_samples
= brw
->num_samples
;
3236 if (_mesa_is_multisample_enabled(ctx
)) {
3237 if (ctx
->Multisample
.SampleCoverage
) {
3238 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3239 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3241 if (ctx
->Multisample
.SampleMask
) {
3242 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3246 if (num_samples
> 1) {
3247 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3248 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3249 if (coverage_invert
)
3250 coverage_bits
^= (1 << num_samples
) - 1;
3251 return coverage_bits
& sample_mask
;
3258 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3259 unsigned num_samples
)
3261 unsigned log2_samples
= ffs(num_samples
) - 1;
3263 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3264 multi
.PixelLocation
= CENTER
;
3265 multi
.NumberofMultisamples
= log2_samples
;
3267 GEN_SAMPLE_POS_4X(multi
.Sample
);
3269 switch (num_samples
) {
3271 GEN_SAMPLE_POS_1X(multi
.Sample
);
3274 GEN_SAMPLE_POS_2X(multi
.Sample
);
3277 GEN_SAMPLE_POS_4X(multi
.Sample
);
3280 GEN_SAMPLE_POS_8X(multi
.Sample
);
3290 genX(upload_multisample_state
)(struct brw_context
*brw
)
3292 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3294 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3296 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3297 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3301 static const struct brw_tracked_state
genX(multisample_state
) = {
3303 .mesa
= _NEW_MULTISAMPLE
|
3304 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3305 .brw
= BRW_NEW_BLORP
|
3307 BRW_NEW_NUM_SAMPLES
,
3309 .emit
= genX(upload_multisample_state
)
3313 /* ---------------------------------------------------------------------- */
3316 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3318 struct gl_context
*ctx
= &brw
->ctx
;
3320 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3322 cc
.IndependentAlphaBlendEnable
=
3323 set_blend_entry_bits(brw
, &cc
, 0, false);
3324 set_depth_stencil_bits(brw
, &cc
);
3326 if (ctx
->Color
.AlphaEnabled
&&
3327 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3328 cc
.AlphaTestEnable
= true;
3329 cc
.AlphaTestFunction
=
3330 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3333 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3335 cc
.StatisticsEnable
= brw
->stats_wm
;
3337 cc
.CCViewportStatePointer
=
3338 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3341 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3342 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3343 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3344 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3348 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3349 cc
.BackfaceStencilReferenceValue
=
3350 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3356 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3357 ctx
->Color
.AlphaRef
);
3361 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3362 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3364 ptr
.ColorCalcStatePointerValid
= true;
3368 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3372 static const struct brw_tracked_state
genX(color_calc_state
) = {
3374 .mesa
= _NEW_COLOR
|
3376 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3379 .brw
= BRW_NEW_BATCH
|
3381 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3383 : BRW_NEW_CC_STATE
|
3384 BRW_NEW_STATE_BASE_ADDRESS
),
3386 .emit
= genX(upload_color_calc_state
),
3390 /* ---------------------------------------------------------------------- */
3394 genX(upload_sbe
)(struct brw_context
*brw
)
3396 struct gl_context
*ctx
= &brw
->ctx
;
3397 /* BRW_NEW_FRAGMENT_PROGRAM */
3398 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3399 /* BRW_NEW_FS_PROG_DATA */
3400 const struct brw_wm_prog_data
*wm_prog_data
=
3401 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3403 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3405 #define attr_overrides sbe.Attribute
3407 uint32_t urb_entry_read_length
;
3408 uint32_t urb_entry_read_offset
;
3409 uint32_t point_sprite_enables
;
3411 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3412 sbe
.AttributeSwizzleEnable
= true;
3413 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3416 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3420 * Window coordinates in an FBO are inverted, which means point
3421 * sprite origin must be inverted.
3423 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3424 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3426 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3428 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3429 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3430 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3431 * BRW_NEW_VUE_MAP_GEOM_OUT
3433 genX(calculate_attr_overrides
)(brw
,
3435 &point_sprite_enables
,
3436 &urb_entry_read_length
,
3437 &urb_entry_read_offset
);
3439 /* Typically, the URB entry read length and offset should be programmed
3440 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3441 * stage which produces geometry. However, we don't know the proper
3442 * value until we call calculate_attr_overrides().
3444 * To fit with our existing code, we override the inherited values and
3445 * specify it here directly, as we did on previous generations.
3447 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3448 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3449 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3450 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3453 sbe
.ForceVertexURBEntryReadLength
= true;
3454 sbe
.ForceVertexURBEntryReadOffset
= true;
3458 /* prepare the active component dwords */
3459 const int num_inputs
= urb_entry_read_length
* 2;
3460 for (int input_index
= 0; input_index
< num_inputs
; input_index
++) {
3461 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3467 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3468 for (int i
= 0; i
< 16; i
++)
3469 sbes
.Attribute
[i
] = attr_overrides
[i
];
3473 #undef attr_overrides
3476 static const struct brw_tracked_state
genX(sbe_state
) = {
3478 .mesa
= _NEW_BUFFERS
|
3483 .brw
= BRW_NEW_BLORP
|
3485 BRW_NEW_FRAGMENT_PROGRAM
|
3486 BRW_NEW_FS_PROG_DATA
|
3487 BRW_NEW_GS_PROG_DATA
|
3488 BRW_NEW_TES_PROG_DATA
|
3489 BRW_NEW_VUE_MAP_GEOM_OUT
|
3490 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3493 .emit
= genX(upload_sbe
),
3497 /* ---------------------------------------------------------------------- */
3501 * Outputs the 3DSTATE_SO_DECL_LIST command.
3503 * The data output is a series of 64-bit entries containing a SO_DECL per
3504 * stream. We only have one stream of rendering coming out of the GS unit, so
3505 * we only emit stream 0 (low 16 bits) SO_DECLs.
3508 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3509 const struct brw_vue_map
*vue_map
)
3511 struct gl_context
*ctx
= &brw
->ctx
;
3512 /* BRW_NEW_TRANSFORM_FEEDBACK */
3513 struct gl_transform_feedback_object
*xfb_obj
=
3514 ctx
->TransformFeedback
.CurrentObject
;
3515 const struct gl_transform_feedback_info
*linked_xfb_info
=
3516 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3517 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3518 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3519 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3520 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3522 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3524 memset(so_decl
, 0, sizeof(so_decl
));
3526 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3527 * command feels strange -- each dword pair contains a SO_DECL per stream.
3529 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3530 const struct gl_transform_feedback_output
*output
=
3531 &linked_xfb_info
->Outputs
[i
];
3532 const int buffer
= output
->OutputBuffer
;
3533 const int varying
= output
->OutputRegister
;
3534 const unsigned stream_id
= output
->StreamId
;
3535 assert(stream_id
< MAX_VERTEX_STREAMS
);
3537 buffer_mask
[stream_id
] |= 1 << buffer
;
3539 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3541 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3542 * array. Instead, it simply increments DstOffset for the following
3543 * input by the number of components that should be skipped.
3545 * Our hardware is unusual in that it requires us to program SO_DECLs
3546 * for fake "hole" components, rather than simply taking the offset
3547 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3548 * program as many size = 4 holes as we can, then a final hole to
3549 * accommodate the final 1, 2, or 3 remaining.
3551 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3553 while (skip_components
> 0) {
3554 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3556 .OutputBufferSlot
= output
->OutputBuffer
,
3557 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3559 skip_components
-= 4;
3562 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3564 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3565 .OutputBufferSlot
= output
->OutputBuffer
,
3566 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3568 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3571 if (decls
[stream_id
] > max_decls
)
3572 max_decls
= decls
[stream_id
];
3576 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3577 .StreamtoBufferSelects0
= buffer_mask
[0],
3578 .StreamtoBufferSelects1
= buffer_mask
[1],
3579 .StreamtoBufferSelects2
= buffer_mask
[2],
3580 .StreamtoBufferSelects3
= buffer_mask
[3],
3581 .NumEntries0
= decls
[0],
3582 .NumEntries1
= decls
[1],
3583 .NumEntries2
= decls
[2],
3584 .NumEntries3
= decls
[3]);
3586 for (int i
= 0; i
< max_decls
; i
++) {
3587 GENX(SO_DECL_ENTRY_pack
)(
3588 brw
, dw
+ 2 + i
* 2,
3589 &(struct GENX(SO_DECL_ENTRY
)) {
3590 .Stream0Decl
= so_decl
[0][i
],
3591 .Stream1Decl
= so_decl
[1][i
],
3592 .Stream2Decl
= so_decl
[2][i
],
3593 .Stream3Decl
= so_decl
[3][i
],
3599 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3601 struct gl_context
*ctx
= &brw
->ctx
;
3602 /* BRW_NEW_TRANSFORM_FEEDBACK */
3603 struct gl_transform_feedback_object
*xfb_obj
=
3604 ctx
->TransformFeedback
.CurrentObject
;
3606 const struct gl_transform_feedback_info
*linked_xfb_info
=
3607 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3609 struct brw_transform_feedback_object
*brw_obj
=
3610 (struct brw_transform_feedback_object
*) xfb_obj
;
3611 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3614 /* Set up the up to 4 output buffers. These are the ranges defined in the
3615 * gl_transform_feedback_object.
3617 for (int i
= 0; i
< 4; i
++) {
3618 struct intel_buffer_object
*bufferobj
=
3619 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3622 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3623 sob
.SOBufferIndex
= i
;
3628 uint32_t start
= xfb_obj
->Offset
[i
];
3629 assert(start
% 4 == 0);
3630 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3632 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3633 assert(end
<= bo
->size
);
3635 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3636 sob
.SOBufferIndex
= i
;
3638 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3640 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3641 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3643 sob
.SOBufferEnable
= true;
3644 sob
.StreamOffsetWriteEnable
= true;
3645 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3646 sob
.SOBufferMOCS
= mocs_wb
;
3648 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3649 sob
.StreamOutputBufferOffsetAddress
=
3650 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3652 if (brw_obj
->zero_offsets
) {
3653 /* Zero out the offset and write that to offset_bo */
3654 sob
.StreamOffset
= 0;
3656 /* Use offset_bo as the "Stream Offset." */
3657 sob
.StreamOffset
= 0xFFFFFFFF;
3664 brw_obj
->zero_offsets
= false;
3669 query_active(struct gl_query_object
*q
)
3671 return q
&& q
->Active
;
3675 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3676 const struct brw_vue_map
*vue_map
)
3678 struct gl_context
*ctx
= &brw
->ctx
;
3679 /* BRW_NEW_TRANSFORM_FEEDBACK */
3680 struct gl_transform_feedback_object
*xfb_obj
=
3681 ctx
->TransformFeedback
.CurrentObject
;
3683 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3685 int urb_entry_read_offset
= 0;
3686 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3687 urb_entry_read_offset
;
3689 sos
.SOFunctionEnable
= true;
3690 sos
.SOStatisticsEnable
= true;
3692 /* BRW_NEW_RASTERIZER_DISCARD */
3693 if (ctx
->RasterDiscard
) {
3694 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3695 sos
.RenderingDisable
= true;
3697 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3698 "query active relies on the clipper.\n");
3703 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3704 sos
.ReorderMode
= TRAILING
;
3707 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3708 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3709 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3710 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3712 const struct gl_transform_feedback_info
*linked_xfb_info
=
3713 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3714 /* Set buffer pitches; 0 means unbound. */
3715 if (xfb_obj
->Buffers
[0])
3716 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3717 if (xfb_obj
->Buffers
[1])
3718 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3719 if (xfb_obj
->Buffers
[2])
3720 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3721 if (xfb_obj
->Buffers
[3])
3722 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3725 /* We always read the whole vertex. This could be reduced at some
3726 * point by reading less and offsetting the register index in the
3729 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3730 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3731 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3732 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3733 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3734 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3735 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3736 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3742 genX(upload_sol
)(struct brw_context
*brw
)
3744 struct gl_context
*ctx
= &brw
->ctx
;
3745 /* BRW_NEW_TRANSFORM_FEEDBACK */
3746 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3749 genX(upload_3dstate_so_buffers
)(brw
);
3751 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3752 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3755 /* Finally, set up the SOL stage. This command must always follow updates to
3756 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3757 * MMIO register updates (current performed by the kernel at each batch
3760 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3763 static const struct brw_tracked_state
genX(sol_state
) = {
3766 .brw
= BRW_NEW_BATCH
|
3768 BRW_NEW_RASTERIZER_DISCARD
|
3769 BRW_NEW_VUE_MAP_GEOM_OUT
|
3770 BRW_NEW_TRANSFORM_FEEDBACK
,
3772 .emit
= genX(upload_sol
),
3776 /* ---------------------------------------------------------------------- */
3780 genX(upload_ps
)(struct brw_context
*brw
)
3782 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3783 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3785 /* BRW_NEW_FS_PROG_DATA */
3786 const struct brw_wm_prog_data
*prog_data
=
3787 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3788 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3793 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3794 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3795 * incorrect for subspans where some of the pixels are unlit. We believe
3796 * the bit just didn't take effect in previous generations.
3798 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3801 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3803 /* BRW_NEW_FS_PROG_DATA */
3804 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3806 if (prog_data
->base
.use_alt_mode
)
3807 ps
.FloatingPointMode
= Alternate
;
3809 /* Haswell requires the sample mask to be set in this packet as well as
3810 * in 3DSTATE_SAMPLE_MASK; the values should match.
3813 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3815 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3818 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3819 * it implicitly scales for different GT levels (which have some # of
3822 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3825 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3827 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3829 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3832 if (prog_data
->base
.nr_params
> 0 ||
3833 prog_data
->base
.ubo_ranges
[0].length
> 0)
3834 ps
.PushConstantEnable
= true;
3837 /* From the IVB PRM, volume 2 part 1, page 287:
3838 * "This bit is inserted in the PS payload header and made available to
3839 * the DataPort (either via the message header or via header bypass) to
3840 * indicate that oMask data (one or two phases) is included in Render
3841 * Target Write messages. If present, the oMask data is used to mask off
3844 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3846 /* The hardware wedges if you have this bit set but don't turn on any
3847 * dual source blend factors.
3849 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3851 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3852 (ctx
->Color
.BlendEnabled
& 1) &&
3853 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3855 /* BRW_NEW_FS_PROG_DATA */
3856 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3859 /* From the documentation for this packet:
3860 * "If the PS kernel does not need the Position XY Offsets to
3861 * compute a Position Value, then this field should be programmed
3862 * to POSOFFSET_NONE."
3864 * "SW Recommendation: If the PS kernel needs the Position Offsets
3865 * to compute a Position XY value, this field should match Position
3866 * ZW Interpolation Mode to ensure a consistent position.xyzw
3869 * We only require XY sample offsets. So, this recommendation doesn't
3870 * look useful at the moment. We might need this in future.
3872 if (prog_data
->uses_pos_offset
)
3873 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3875 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3877 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3878 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3879 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3880 prog_data
->base
.dispatch_grf_start_reg
;
3881 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3882 prog_data
->dispatch_grf_start_reg_2
;
3884 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3885 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3886 prog_data
->prog_offset_2
;
3888 if (prog_data
->base
.total_scratch
) {
3889 ps
.ScratchSpaceBasePointer
=
3890 rw_bo(stage_state
->scratch_bo
,
3891 ffs(stage_state
->per_thread_scratch
) - 11);
3896 static const struct brw_tracked_state
genX(ps_state
) = {
3898 .mesa
= _NEW_MULTISAMPLE
|
3899 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3902 .brw
= BRW_NEW_BATCH
|
3904 BRW_NEW_FS_PROG_DATA
,
3906 .emit
= genX(upload_ps
),
3910 /* ---------------------------------------------------------------------- */
3914 genX(upload_hs_state
)(struct brw_context
*brw
)
3916 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3917 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3918 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3919 const struct brw_vue_prog_data
*vue_prog_data
=
3920 brw_vue_prog_data(stage_prog_data
);
3922 /* BRW_NEW_TES_PROG_DATA */
3923 struct brw_tcs_prog_data
*tcs_prog_data
=
3924 brw_tcs_prog_data(stage_prog_data
);
3926 if (!tcs_prog_data
) {
3927 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3929 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3930 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3932 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3933 hs
.IncludeVertexHandles
= true;
3935 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3940 static const struct brw_tracked_state
genX(hs_state
) = {
3943 .brw
= BRW_NEW_BATCH
|
3945 BRW_NEW_TCS_PROG_DATA
|
3946 BRW_NEW_TESS_PROGRAMS
,
3948 .emit
= genX(upload_hs_state
),
3952 genX(upload_ds_state
)(struct brw_context
*brw
)
3954 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3955 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3956 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3958 /* BRW_NEW_TES_PROG_DATA */
3959 const struct brw_tes_prog_data
*tes_prog_data
=
3960 brw_tes_prog_data(stage_prog_data
);
3961 const struct brw_vue_prog_data
*vue_prog_data
=
3962 brw_vue_prog_data(stage_prog_data
);
3964 if (!tes_prog_data
) {
3965 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3967 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3968 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3970 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3971 ds
.ComputeWCoordinateEnable
=
3972 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3975 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3976 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3977 ds
.UserClipDistanceCullTestEnableBitmask
=
3978 vue_prog_data
->cull_distance_mask
;
3984 static const struct brw_tracked_state
genX(ds_state
) = {
3987 .brw
= BRW_NEW_BATCH
|
3989 BRW_NEW_TESS_PROGRAMS
|
3990 BRW_NEW_TES_PROG_DATA
,
3992 .emit
= genX(upload_ds_state
),
3995 /* ---------------------------------------------------------------------- */
3998 upload_te_state(struct brw_context
*brw
)
4000 /* BRW_NEW_TESS_PROGRAMS */
4001 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4003 /* BRW_NEW_TES_PROG_DATA */
4004 const struct brw_tes_prog_data
*tes_prog_data
=
4005 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4008 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4009 te
.Partitioning
= tes_prog_data
->partitioning
;
4010 te
.OutputTopology
= tes_prog_data
->output_topology
;
4011 te
.TEDomain
= tes_prog_data
->domain
;
4013 te
.MaximumTessellationFactorOdd
= 63.0;
4014 te
.MaximumTessellationFactorNotOdd
= 64.0;
4017 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4021 static const struct brw_tracked_state
genX(te_state
) = {
4024 .brw
= BRW_NEW_BLORP
|
4026 BRW_NEW_TES_PROG_DATA
|
4027 BRW_NEW_TESS_PROGRAMS
,
4029 .emit
= upload_te_state
,
4032 /* ---------------------------------------------------------------------- */
4035 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4037 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4038 /* BRW_NEW_TESS_PROGRAMS */
4039 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4041 /* BRW_NEW_TES_PROG_DATA */
4042 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4043 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4046 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4048 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4049 .brw
= BRW_NEW_BATCH
|
4051 BRW_NEW_TESS_PROGRAMS
|
4052 BRW_NEW_TES_PROG_DATA
,
4054 .emit
= genX(upload_tes_push_constants
),
4058 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4060 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4061 /* BRW_NEW_TESS_PROGRAMS */
4062 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4064 /* BRW_NEW_TCS_PROG_DATA */
4065 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4067 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4070 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4072 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4073 .brw
= BRW_NEW_BATCH
|
4075 BRW_NEW_DEFAULT_TESS_LEVELS
|
4076 BRW_NEW_TESS_PROGRAMS
|
4077 BRW_NEW_TCS_PROG_DATA
,
4079 .emit
= genX(upload_tcs_push_constants
),
4084 /* ---------------------------------------------------------------------- */
4088 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4090 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4092 /* BRW_NEW_COMPUTE_PROGRAM */
4093 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4096 /* BRW_NEW_CS_PROG_DATA */
4097 struct brw_cs_prog_data
*cs_prog_data
=
4098 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4100 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4101 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4105 const struct brw_tracked_state
genX(cs_push_constants
) = {
4107 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4108 .brw
= BRW_NEW_BATCH
|
4110 BRW_NEW_COMPUTE_PROGRAM
|
4111 BRW_NEW_CS_PROG_DATA
,
4113 .emit
= genX(upload_cs_push_constants
),
4117 * Creates a new CS constant buffer reflecting the current CS program's
4118 * constants, if needed by the CS program.
4121 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4123 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4125 /* BRW_NEW_COMPUTE_PROGRAM */
4126 struct brw_program
*cp
=
4127 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4129 /* BRW_NEW_CS_PROG_DATA */
4130 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4132 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4133 /* _NEW_PROGRAM_CONSTANTS */
4134 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4135 stage_state
, prog_data
);
4138 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4140 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4141 .brw
= BRW_NEW_BATCH
|
4143 BRW_NEW_COMPUTE_PROGRAM
|
4144 BRW_NEW_CS_PROG_DATA
,
4146 .emit
= genX(upload_cs_pull_constants
),
4150 genX(upload_cs_state
)(struct brw_context
*brw
)
4152 if (!brw
->cs
.base
.prog_data
)
4156 uint32_t *desc
= (uint32_t*) brw_state_batch(
4157 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4160 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4161 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4162 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4163 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4165 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4166 brw_emit_buffer_surface_state(
4167 brw
, &stage_state
->surf_offset
[
4168 prog_data
->binding_table
.shader_time_start
],
4169 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4170 brw
->shader_time
.bo
->size
, 1,
4174 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4175 32, &stage_state
->bind_bo_offset
);
4177 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4179 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4180 * the only bits that are changed are scoreboard related: Scoreboard
4181 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4182 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4184 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4185 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4187 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4189 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4190 if (prog_data
->total_scratch
) {
4191 uint32_t per_thread_scratch_value
;
4194 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4195 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4197 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4198 } else if (GEN_IS_HASWELL
) {
4199 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4200 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4202 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4204 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4205 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4207 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4209 vfe
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
4210 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4213 /* If brw->screen->subslice_total is greater than one, then
4214 * devinfo->max_cs_threads stores number of threads per sub-slice;
4215 * thus we need to multiply by that number by subslices to get
4216 * the actual maximum number of threads; the -1 is because the HW
4217 * has a bias of 1 (would not make sense to say the maximum number
4220 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4221 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4222 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4224 vfe
.ResetGatewayTimer
=
4225 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4228 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4234 /* We are uploading duplicated copies of push constant uniforms for each
4235 * thread. Although the local id data needs to vary per thread, it won't
4236 * change for other uniform data. Unfortunately this duplication is
4237 * required for gen7. As of Haswell, this duplication can be avoided,
4238 * but this older mechanism with duplicated data continues to work.
4240 * FINISHME: As of Haswell, we could make use of the
4241 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4242 * field to only store one copy of uniform data.
4244 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4245 * which is described in the GPGPU_WALKER command and in the Broadwell
4246 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4247 * Operations => GPGPU Mode => Indirect Payload Storage.
4249 * Note: The constant data is built in brw_upload_cs_push_constants
4252 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4254 const uint32_t vfe_curbe_allocation
=
4255 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4256 cs_prog_data
->push
.cross_thread
.regs
, 2);
4257 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4260 if (cs_prog_data
->push
.total
.size
> 0) {
4261 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4262 curbe
.CURBETotalDataLength
=
4263 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4264 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4268 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4269 memcpy(bind
, stage_state
->surf_offset
,
4270 prog_data
->binding_table
.size_bytes
);
4271 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4272 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4273 .SamplerStatePointer
= stage_state
->sampler_offset
,
4274 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4275 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4276 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4277 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4278 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4279 prog_data
->total_shared
),
4280 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4281 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4282 .CrossThreadConstantDataReadLength
=
4283 cs_prog_data
->push
.cross_thread
.regs
,
4287 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4289 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4290 load
.InterfaceDescriptorTotalLength
=
4291 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4292 load
.InterfaceDescriptorDataStartAddress
= offset
;
4296 static const struct brw_tracked_state
genX(cs_state
) = {
4298 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4299 .brw
= BRW_NEW_BATCH
|
4301 BRW_NEW_CS_PROG_DATA
|
4302 BRW_NEW_SAMPLER_STATE_TABLE
|
4305 .emit
= genX(upload_cs_state
)
4310 /* ---------------------------------------------------------------------- */
4314 genX(upload_raster
)(struct brw_context
*brw
)
4316 const struct gl_context
*ctx
= &brw
->ctx
;
4319 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4322 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4325 const struct gl_point_attrib
*point
= &ctx
->Point
;
4327 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4328 if (brw
->polygon_front_bit
== render_to_fbo
)
4329 raster
.FrontWinding
= CounterClockwise
;
4331 if (polygon
->CullFlag
) {
4332 switch (polygon
->CullFaceMode
) {
4334 raster
.CullMode
= CULLMODE_FRONT
;
4337 raster
.CullMode
= CULLMODE_BACK
;
4339 case GL_FRONT_AND_BACK
:
4340 raster
.CullMode
= CULLMODE_BOTH
;
4343 unreachable("not reached");
4346 raster
.CullMode
= CULLMODE_NONE
;
4349 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4351 raster
.DXMultisampleRasterizationEnable
=
4352 _mesa_is_multisample_enabled(ctx
);
4354 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4355 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4356 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4358 switch (polygon
->FrontMode
) {
4360 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4363 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4366 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4369 unreachable("not reached");
4372 switch (polygon
->BackMode
) {
4374 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4377 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4380 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4383 unreachable("not reached");
4387 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4391 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4393 const bool multisampled_fbo
=
4394 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4395 if (multisampled_fbo
)
4396 raster
.AntialiasingEnable
= false;
4400 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4402 /* _NEW_TRANSFORM */
4403 if (!ctx
->Transform
.DepthClamp
) {
4405 raster
.ViewportZFarClipTestEnable
= true;
4406 raster
.ViewportZNearClipTestEnable
= true;
4408 raster
.ViewportZClipTestEnable
= true;
4412 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4414 raster
.ConservativeRasterizationEnable
=
4415 ctx
->IntelConservativeRasterization
;
4418 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4419 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4421 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4425 static const struct brw_tracked_state
genX(raster_state
) = {
4427 .mesa
= _NEW_BUFFERS
|
4434 .brw
= BRW_NEW_BLORP
|
4436 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4438 .emit
= genX(upload_raster
),
4442 /* ---------------------------------------------------------------------- */
4446 genX(upload_ps_extra
)(struct brw_context
*brw
)
4448 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4450 const struct brw_wm_prog_data
*prog_data
=
4451 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4453 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4454 psx
.PixelShaderValid
= true;
4455 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4456 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4457 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4458 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4459 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4460 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4462 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4463 if (prog_data
->uses_sample_mask
) {
4465 if (prog_data
->post_depth_coverage
)
4466 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4467 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4468 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4470 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4472 psx
.PixelShaderUsesInputCoverageMask
= true;
4476 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4478 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4479 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4482 /* The stricter cross-primitive coherency guarantees that the hardware
4483 * gives us with the "Accesses UAV" bit set for at least one shader stage
4484 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4485 * are redundant within the current image, atomic counter and SSBO GL
4486 * APIs, which all have very loose ordering and coherency requirements
4487 * and generally rely on the application to insert explicit barriers when
4488 * a shader invocation is expected to see the memory writes performed by
4489 * the invocations of some previous primitive. Regardless of the value
4490 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4491 * cause an in most cases useless DC flush when the lowermost stage with
4492 * the bit set finishes execution.
4494 * It would be nice to disable it, but in some cases we can't because on
4495 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4496 * signal (which could be set independently from the coherency mechanism
4497 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4498 * determine whether the hardware skips execution of the fragment shader
4499 * or not via the ThreadDispatchEnable signal. However if we know that
4500 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4501 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4502 * difference so we may just disable it here.
4504 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4505 * take into account KillPixels when no depth or stencil writes are
4506 * enabled. In order for occlusion queries to work correctly with no
4507 * attachments, we need to force-enable here.
4509 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4512 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4513 !brw_color_buffer_write_enabled(brw
))
4514 psx
.PixelShaderHasUAV
= true;
4518 const struct brw_tracked_state
genX(ps_extra
) = {
4520 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4521 .brw
= BRW_NEW_BLORP
|
4523 BRW_NEW_FRAGMENT_PROGRAM
|
4524 BRW_NEW_FS_PROG_DATA
|
4525 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4527 .emit
= genX(upload_ps_extra
),
4531 /* ---------------------------------------------------------------------- */
4535 genX(upload_ps_blend
)(struct brw_context
*brw
)
4537 struct gl_context
*ctx
= &brw
->ctx
;
4540 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4541 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4544 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4546 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4547 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4548 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4550 bool alpha_to_one
= false;
4552 if (!buffer0_is_integer
) {
4553 /* _NEW_MULTISAMPLE */
4555 if (_mesa_is_multisample_enabled(ctx
)) {
4556 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4557 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4560 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4563 /* Used for implementing the following bit of GL_EXT_texture_integer:
4564 * "Per-fragment operations that require floating-point color
4565 * components, including multisample alpha operations, alpha test,
4566 * blending, and dithering, have no effect when the corresponding
4567 * colors are written to an integer color buffer."
4569 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4570 * "If drawbuffer zero is not NONE and the buffer it references has an
4571 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4572 * operations are skipped."
4574 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4575 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4576 GLenum eqA
= color
->Blend
[0].EquationA
;
4577 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4578 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4579 GLenum srcA
= color
->Blend
[0].SrcA
;
4580 GLenum dstA
= color
->Blend
[0].DstA
;
4582 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4583 srcRGB
= dstRGB
= GL_ONE
;
4585 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4586 srcA
= dstA
= GL_ONE
;
4588 /* Due to hardware limitations, the destination may have information
4589 * in an alpha channel even when the format specifies no alpha
4590 * channel. In order to avoid getting any incorrect blending due to
4591 * that alpha channel, coerce the blend factors to values that will
4592 * not read the alpha channel, but will instead use the correct
4593 * implicit value for alpha.
4595 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4596 GL_TEXTURE_ALPHA_TYPE
)) {
4597 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4598 srcA
= brw_fix_xRGB_alpha(srcA
);
4599 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4600 dstA
= brw_fix_xRGB_alpha(dstA
);
4603 /* Alpha to One doesn't work with Dual Color Blending. Override
4604 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4606 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4607 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4608 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4609 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4610 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4613 pb
.ColorBufferBlendEnable
= true;
4614 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4615 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4616 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4617 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4619 pb
.IndependentAlphaBlendEnable
=
4620 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4625 static const struct brw_tracked_state
genX(ps_blend
) = {
4627 .mesa
= _NEW_BUFFERS
|
4630 .brw
= BRW_NEW_BLORP
|
4632 BRW_NEW_FRAGMENT_PROGRAM
,
4634 .emit
= genX(upload_ps_blend
)
4638 /* ---------------------------------------------------------------------- */
4642 genX(emit_vf_topology
)(struct brw_context
*brw
)
4644 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4645 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4649 static const struct brw_tracked_state
genX(vf_topology
) = {
4652 .brw
= BRW_NEW_BLORP
|
4655 .emit
= genX(emit_vf_topology
),
4659 /* ---------------------------------------------------------------------- */
4663 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4665 uint32_t offset_in_bytes
,
4668 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4669 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4670 mi_rpc
.ReportID
= report_id
;
4675 /* ---------------------------------------------------------------------- */
4678 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4681 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4682 struct brw_stage_state
*stage_state
)
4685 static const uint16_t packet_headers
[] = {
4686 [MESA_SHADER_VERTEX
] = 43,
4687 [MESA_SHADER_TESS_CTRL
] = 44,
4688 [MESA_SHADER_TESS_EVAL
] = 45,
4689 [MESA_SHADER_GEOMETRY
] = 46,
4690 [MESA_SHADER_FRAGMENT
] = 47,
4693 /* Ivybridge requires a workaround flush before VS packets. */
4694 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4695 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4696 gen7_emit_vs_workaround_flush(brw
);
4699 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4700 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4701 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4707 has_component(mesa_format format
, int i
)
4709 if (_mesa_is_format_color_format(format
))
4710 return _mesa_format_has_color_component(format
, i
);
4712 /* depth and stencil have only one component */
4717 * Upload SAMPLER_BORDER_COLOR_STATE.
4720 genX(upload_default_color
)(struct brw_context
*brw
,
4721 const struct gl_sampler_object
*sampler
,
4722 mesa_format format
, GLenum base_format
,
4723 bool is_integer_format
, bool is_stencil_sampling
,
4724 uint32_t *sdc_offset
)
4726 union gl_color_union color
;
4728 switch (base_format
) {
4729 case GL_DEPTH_COMPONENT
:
4730 /* GL specs that border color for depth textures is taken from the
4731 * R channel, while the hardware uses A. Spam R into all the
4732 * channels for safety.
4734 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4735 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4736 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4737 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4743 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4746 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4747 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4748 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4749 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4752 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4753 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4754 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4755 color
.ui
[3] = float_as_int(1.0);
4757 case GL_LUMINANCE_ALPHA
:
4758 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4759 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4760 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4761 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4764 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4765 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4766 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4767 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4771 /* In some cases we use an RGBA surface format for GL RGB textures,
4772 * where we've initialized the A channel to 1.0. We also have to set
4773 * the border color alpha to 1.0 in that case.
4775 if (base_format
== GL_RGB
)
4776 color
.ui
[3] = float_as_int(1.0);
4781 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4785 uint32_t *sdc
= brw_state_batch(
4786 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4787 alignment
, sdc_offset
);
4789 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4791 #define ASSIGN(dst, src) \
4796 #define ASSIGNu16(dst, src) \
4798 dst = (uint16_t)src; \
4801 #define ASSIGNu8(dst, src) \
4803 dst = (uint8_t)src; \
4806 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4807 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4808 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4809 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4810 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4813 /* On Broadwell, the border color is represented as four 32-bit floats,
4814 * integers, or unsigned values, interpreted according to the surface
4815 * format. This matches the sampler->BorderColor union exactly; just
4816 * memcpy the values.
4818 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4819 #elif GEN_IS_HASWELL
4820 if (is_integer_format
|| is_stencil_sampling
) {
4821 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4822 const int bits_per_channel
=
4823 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4825 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4826 * "If any color channel is missing from the surface format,
4827 * corresponding border color should be programmed as zero and if
4828 * alpha channel is missing, corresponding Alpha border color should
4829 * be programmed as 1."
4831 unsigned c
[4] = { 0, 0, 0, 1 };
4832 for (int i
= 0; i
< 4; i
++) {
4833 if (has_component(format
, i
))
4837 switch (bits_per_channel
) {
4839 /* Copy RGBA in order. */
4840 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4843 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4845 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4848 if (base_format
== GL_RG
) {
4849 /* Careful inspection of the tables reveals that for RG32 formats,
4850 * the green channel needs to go where blue normally belongs.
4852 state
.BorderColor32bitRed
= c
[0];
4853 state
.BorderColor32bitBlue
= c
[1];
4854 state
.BorderColor32bitAlpha
= 1;
4856 /* Copy RGBA in order. */
4857 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4861 assert(!"Invalid number of bits per channel in integer format.");
4865 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4867 #elif GEN_GEN == 5 || GEN_GEN == 6
4868 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4869 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4870 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4872 #define MESA_FLOAT_TO_HALF(dst, src) \
4873 dst = _mesa_float_to_half(src);
4875 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4877 #undef MESA_FLOAT_TO_HALF
4879 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4880 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4881 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4882 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4884 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4886 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4888 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4892 #undef BORDER_COLOR_ATTR
4894 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4898 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4905 /* GL_CLAMP is the weird mode where coordinates are clamped to
4906 * [0.0, 1.0], so linear filtering of coordinates outside of
4907 * [0.0, 1.0] give you half edge texel value and half border
4910 * Gen8+ supports this natively.
4912 return TCM_HALF_BORDER
;
4914 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4915 * and set clamp_border here, which gets the result desired.
4916 * We just use clamp(_to_edge) for nearest, because for nearest
4917 * clamping to 1.0 gives border color instead of the desired
4923 return TCM_CLAMP_BORDER
;
4925 case GL_CLAMP_TO_EDGE
:
4927 case GL_CLAMP_TO_BORDER
:
4928 return TCM_CLAMP_BORDER
;
4929 case GL_MIRRORED_REPEAT
:
4931 case GL_MIRROR_CLAMP_TO_EDGE
:
4932 return TCM_MIRROR_ONCE
;
4939 * Return true if the given wrap mode requires the border color to exist.
4942 wrap_mode_needs_border_color(unsigned wrap_mode
)
4945 return wrap_mode
== TCM_CLAMP_BORDER
||
4946 wrap_mode
== TCM_HALF_BORDER
;
4948 return wrap_mode
== TCM_CLAMP_BORDER
;
4953 * Sets the sampler state for a single unit based off of the sampler key
4957 genX(update_sampler_state
)(struct brw_context
*brw
,
4958 GLenum target
, bool tex_cube_map_seamless
,
4959 GLfloat tex_unit_lod_bias
,
4960 mesa_format format
, GLenum base_format
,
4961 const struct gl_texture_object
*texObj
,
4962 const struct gl_sampler_object
*sampler
,
4963 uint32_t *sampler_state
,
4964 uint32_t batch_offset_for_sampler_state
)
4966 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
4968 /* Select min and mip filters. */
4969 switch (sampler
->MinFilter
) {
4971 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4972 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4975 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4976 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4978 case GL_NEAREST_MIPMAP_NEAREST
:
4979 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4980 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4982 case GL_LINEAR_MIPMAP_NEAREST
:
4983 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4984 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4986 case GL_NEAREST_MIPMAP_LINEAR
:
4987 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4988 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4990 case GL_LINEAR_MIPMAP_LINEAR
:
4991 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4992 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4995 unreachable("not reached");
4998 /* Select mag filter. */
4999 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5000 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5002 /* Enable anisotropic filtering if desired. */
5003 samp_st
.MaximumAnisotropy
= RATIO21
;
5005 if (sampler
->MaxAnisotropy
> 1.0f
) {
5006 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5007 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5008 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5009 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5011 if (sampler
->MaxAnisotropy
> 2.0f
) {
5012 samp_st
.MaximumAnisotropy
=
5013 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5017 /* Set address rounding bits if not using nearest filtering. */
5018 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5019 samp_st
.UAddressMinFilterRoundingEnable
= true;
5020 samp_st
.VAddressMinFilterRoundingEnable
= true;
5021 samp_st
.RAddressMinFilterRoundingEnable
= true;
5024 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5025 samp_st
.UAddressMagFilterRoundingEnable
= true;
5026 samp_st
.VAddressMagFilterRoundingEnable
= true;
5027 samp_st
.RAddressMagFilterRoundingEnable
= true;
5030 bool either_nearest
=
5031 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5032 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
5033 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
5034 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
5036 if (target
== GL_TEXTURE_CUBE_MAP
||
5037 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5038 /* Cube maps must use the same wrap mode for all three coordinate
5039 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5041 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5042 * integer formats. Fall back to CLAMP for now.
5044 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5045 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5054 } else if (target
== GL_TEXTURE_1D
) {
5055 /* There's a bug in 1D texture sampling - it actually pays
5056 * attention to the wrap_t value, though it should not.
5057 * Override the wrap_t value here to GL_REPEAT to keep
5058 * any nonexistent border pixels from floating in.
5063 samp_st
.TCXAddressControlMode
= wrap_s
;
5064 samp_st
.TCYAddressControlMode
= wrap_t
;
5065 samp_st
.TCZAddressControlMode
= wrap_r
;
5067 samp_st
.ShadowFunction
=
5068 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5069 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5072 /* Set shadow function. */
5073 samp_st
.AnisotropicAlgorithm
=
5074 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5075 EWAApproximation
: LEGACY
;
5079 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5082 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5083 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5084 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5085 samp_st
.TextureLODBias
=
5086 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5089 samp_st
.BaseMipLevel
=
5090 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5091 samp_st
.MinandMagStateNotEqual
=
5092 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5095 /* Upload the border color if necessary. If not, just point it at
5096 * offset 0 (the start of the batch) - the color should be ignored,
5097 * but that address won't fault in case something reads it anyway.
5099 uint32_t border_color_offset
= 0;
5100 if (wrap_mode_needs_border_color(wrap_s
) ||
5101 wrap_mode_needs_border_color(wrap_t
) ||
5102 wrap_mode_needs_border_color(wrap_r
)) {
5103 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5104 texObj
->_IsIntegerFormat
,
5105 texObj
->StencilSampling
,
5106 &border_color_offset
);
5109 samp_st
.BorderColorPointer
=
5110 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5112 samp_st
.BorderColorPointer
= border_color_offset
;
5116 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5118 samp_st
.LODPreClampEnable
= true;
5121 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5125 update_sampler_state(struct brw_context
*brw
,
5127 uint32_t *sampler_state
,
5128 uint32_t batch_offset_for_sampler_state
)
5130 struct gl_context
*ctx
= &brw
->ctx
;
5131 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5132 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5133 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5135 /* These don't use samplers at all. */
5136 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5139 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5140 genX(update_sampler_state
)(brw
, texObj
->Target
,
5141 ctx
->Texture
.CubeMapSeamless
,
5143 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5145 sampler_state
, batch_offset_for_sampler_state
);
5149 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5150 struct gl_program
*prog
,
5151 struct brw_stage_state
*stage_state
)
5153 struct gl_context
*ctx
= &brw
->ctx
;
5154 uint32_t sampler_count
= stage_state
->sampler_count
;
5156 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5158 if (sampler_count
== 0)
5161 /* SAMPLER_STATE is 4 DWords on all platforms. */
5162 const int dwords
= GENX(SAMPLER_STATE_length
);
5163 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5165 uint32_t *sampler_state
= brw_state_batch(brw
,
5166 sampler_count
* size_in_bytes
,
5167 32, &stage_state
->sampler_offset
);
5168 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5170 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
5172 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5173 if (SamplersUsed
& (1 << s
)) {
5174 const unsigned unit
= prog
->SamplerUnits
[s
];
5175 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5176 update_sampler_state(brw
, unit
, sampler_state
,
5177 batch_offset_for_sampler_state
);
5181 sampler_state
+= dwords
;
5182 batch_offset_for_sampler_state
+= size_in_bytes
;
5185 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5186 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5187 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5189 /* Flag that the sampler state table pointer has changed; later atoms
5192 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5197 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5199 /* BRW_NEW_FRAGMENT_PROGRAM */
5200 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5201 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5204 static const struct brw_tracked_state
genX(fs_samplers
) = {
5206 .mesa
= _NEW_TEXTURE
,
5207 .brw
= BRW_NEW_BATCH
|
5209 BRW_NEW_FRAGMENT_PROGRAM
,
5211 .emit
= genX(upload_fs_samplers
),
5215 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5217 /* BRW_NEW_VERTEX_PROGRAM */
5218 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5219 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5222 static const struct brw_tracked_state
genX(vs_samplers
) = {
5224 .mesa
= _NEW_TEXTURE
,
5225 .brw
= BRW_NEW_BATCH
|
5227 BRW_NEW_VERTEX_PROGRAM
,
5229 .emit
= genX(upload_vs_samplers
),
5234 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5236 /* BRW_NEW_GEOMETRY_PROGRAM */
5237 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5241 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5245 static const struct brw_tracked_state
genX(gs_samplers
) = {
5247 .mesa
= _NEW_TEXTURE
,
5248 .brw
= BRW_NEW_BATCH
|
5250 BRW_NEW_GEOMETRY_PROGRAM
,
5252 .emit
= genX(upload_gs_samplers
),
5258 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5260 /* BRW_NEW_TESS_PROGRAMS */
5261 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5265 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5268 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5270 .mesa
= _NEW_TEXTURE
,
5271 .brw
= BRW_NEW_BATCH
|
5273 BRW_NEW_TESS_PROGRAMS
,
5275 .emit
= genX(upload_tcs_samplers
),
5281 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5283 /* BRW_NEW_TESS_PROGRAMS */
5284 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5288 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5291 static const struct brw_tracked_state
genX(tes_samplers
) = {
5293 .mesa
= _NEW_TEXTURE
,
5294 .brw
= BRW_NEW_BATCH
|
5296 BRW_NEW_TESS_PROGRAMS
,
5298 .emit
= genX(upload_tes_samplers
),
5304 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5306 /* BRW_NEW_COMPUTE_PROGRAM */
5307 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5311 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5314 const struct brw_tracked_state
genX(cs_samplers
) = {
5316 .mesa
= _NEW_TEXTURE
,
5317 .brw
= BRW_NEW_BATCH
|
5319 BRW_NEW_COMPUTE_PROGRAM
,
5321 .emit
= genX(upload_cs_samplers
),
5325 /* ---------------------------------------------------------------------- */
5329 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5331 struct gl_context
*ctx
= &brw
->ctx
;
5333 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5334 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5335 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5336 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5337 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5341 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5344 .brw
= BRW_NEW_CONTEXT
|
5347 .emit
= genX(upload_blend_constant_color
)
5351 /* ---------------------------------------------------------------------- */
5354 genX(init_atoms
)(struct brw_context
*brw
)
5357 static const struct brw_tracked_state
*render_atoms
[] =
5359 /* Once all the programs are done, we know how large urb entry
5360 * sizes need to be and can decide if we need to change the urb
5364 &brw_recalculate_urb_fence
,
5367 &genX(color_calc_state
),
5369 /* Surface state setup. Must come before the VS/WM unit. The binding
5370 * table upload must be last.
5372 &brw_vs_pull_constants
,
5373 &brw_wm_pull_constants
,
5374 &brw_renderbuffer_surfaces
,
5375 &brw_renderbuffer_read_surfaces
,
5376 &brw_texture_surfaces
,
5377 &brw_vs_binding_table
,
5378 &brw_wm_binding_table
,
5383 /* These set up state for brw_psp_urb_cbs */
5385 &genX(sf_clip_viewport
),
5387 &genX(vs_state
), /* always required, enabled or not */
5393 &brw_binding_table_pointers
,
5394 &genX(blend_constant_color
),
5398 &genX(polygon_stipple
),
5399 &genX(polygon_stipple_offset
),
5401 &genX(line_stipple
),
5405 &genX(drawing_rect
),
5406 &brw_indices
, /* must come before brw_vertices */
5407 &genX(index_buffer
),
5410 &brw_constant_buffer
5413 static const struct brw_tracked_state
*render_atoms
[] =
5415 &genX(sf_clip_viewport
),
5417 /* Command packets: */
5422 &genX(blend_state
), /* must do before cc unit */
5423 &genX(color_calc_state
), /* must do before cc unit */
5424 &genX(depth_stencil_state
), /* must do before cc unit */
5426 &genX(vs_push_constants
), /* Before vs_state */
5427 &genX(gs_push_constants
), /* Before gs_state */
5428 &genX(wm_push_constants
), /* Before wm_state */
5430 /* Surface state setup. Must come before the VS/WM unit. The binding
5431 * table upload must be last.
5433 &brw_vs_pull_constants
,
5434 &brw_vs_ubo_surfaces
,
5435 &brw_gs_pull_constants
,
5436 &brw_gs_ubo_surfaces
,
5437 &brw_wm_pull_constants
,
5438 &brw_wm_ubo_surfaces
,
5439 &gen6_renderbuffer_surfaces
,
5440 &brw_renderbuffer_read_surfaces
,
5441 &brw_texture_surfaces
,
5443 &brw_vs_binding_table
,
5444 &gen6_gs_binding_table
,
5445 &brw_wm_binding_table
,
5450 &gen6_sampler_state
,
5451 &genX(multisample_state
),
5459 &genX(scissor_state
),
5461 &gen6_binding_table_pointers
,
5465 &genX(polygon_stipple
),
5466 &genX(polygon_stipple_offset
),
5468 &genX(line_stipple
),
5470 &genX(drawing_rect
),
5472 &brw_indices
, /* must come before brw_vertices */
5473 &genX(index_buffer
),
5477 static const struct brw_tracked_state
*render_atoms
[] =
5479 /* Command packets: */
5482 &genX(sf_clip_viewport
),
5485 &gen7_push_constant_space
,
5487 &genX(blend_state
), /* must do before cc unit */
5488 &genX(color_calc_state
), /* must do before cc unit */
5489 &genX(depth_stencil_state
), /* must do before cc unit */
5491 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5492 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5493 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5494 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5495 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5497 &genX(vs_push_constants
), /* Before vs_state */
5498 &genX(tcs_push_constants
),
5499 &genX(tes_push_constants
),
5500 &genX(gs_push_constants
), /* Before gs_state */
5501 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5503 /* Surface state setup. Must come before the VS/WM unit. The binding
5504 * table upload must be last.
5506 &brw_vs_pull_constants
,
5507 &brw_vs_ubo_surfaces
,
5508 &brw_tcs_pull_constants
,
5509 &brw_tcs_ubo_surfaces
,
5510 &brw_tes_pull_constants
,
5511 &brw_tes_ubo_surfaces
,
5512 &brw_gs_pull_constants
,
5513 &brw_gs_ubo_surfaces
,
5514 &brw_wm_pull_constants
,
5515 &brw_wm_ubo_surfaces
,
5516 &gen6_renderbuffer_surfaces
,
5517 &brw_renderbuffer_read_surfaces
,
5518 &brw_texture_surfaces
,
5520 &genX(push_constant_packets
),
5522 &brw_vs_binding_table
,
5523 &brw_tcs_binding_table
,
5524 &brw_tes_binding_table
,
5525 &brw_gs_binding_table
,
5526 &brw_wm_binding_table
,
5530 &genX(tcs_samplers
),
5531 &genX(tes_samplers
),
5533 &genX(multisample_state
),
5547 &genX(scissor_state
),
5551 &genX(polygon_stipple
),
5552 &genX(polygon_stipple_offset
),
5554 &genX(line_stipple
),
5556 &genX(drawing_rect
),
5558 &brw_indices
, /* must come before brw_vertices */
5559 &genX(index_buffer
),
5567 static const struct brw_tracked_state
*render_atoms
[] =
5570 &genX(sf_clip_viewport
),
5573 &gen7_push_constant_space
,
5576 &genX(color_calc_state
),
5578 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5579 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5580 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5581 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5582 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5584 &genX(vs_push_constants
), /* Before vs_state */
5585 &genX(tcs_push_constants
),
5586 &genX(tes_push_constants
),
5587 &genX(gs_push_constants
), /* Before gs_state */
5588 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5590 /* Surface state setup. Must come before the VS/WM unit. The binding
5591 * table upload must be last.
5593 &brw_vs_pull_constants
,
5594 &brw_vs_ubo_surfaces
,
5595 &brw_tcs_pull_constants
,
5596 &brw_tcs_ubo_surfaces
,
5597 &brw_tes_pull_constants
,
5598 &brw_tes_ubo_surfaces
,
5599 &brw_gs_pull_constants
,
5600 &brw_gs_ubo_surfaces
,
5601 &brw_wm_pull_constants
,
5602 &brw_wm_ubo_surfaces
,
5603 &gen6_renderbuffer_surfaces
,
5604 &brw_renderbuffer_read_surfaces
,
5605 &brw_texture_surfaces
,
5607 &genX(push_constant_packets
),
5609 &brw_vs_binding_table
,
5610 &brw_tcs_binding_table
,
5611 &brw_tes_binding_table
,
5612 &brw_gs_binding_table
,
5613 &brw_wm_binding_table
,
5617 &genX(tcs_samplers
),
5618 &genX(tes_samplers
),
5620 &genX(multisample_state
),
5629 &genX(raster_state
),
5635 &genX(depth_stencil_state
),
5638 &genX(scissor_state
),
5642 &genX(polygon_stipple
),
5643 &genX(polygon_stipple_offset
),
5645 &genX(line_stipple
),
5647 &genX(drawing_rect
),
5652 &genX(index_buffer
),
5660 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5661 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5662 render_atoms
, ARRAY_SIZE(render_atoms
));
5665 static const struct brw_tracked_state
*compute_atoms
[] =
5668 &brw_cs_image_surfaces
,
5669 &genX(cs_push_constants
),
5670 &genX(cs_pull_constants
),
5671 &brw_cs_ubo_surfaces
,
5672 &brw_cs_texture_surfaces
,
5673 &brw_cs_work_groups_surface
,
5678 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5679 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5680 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5682 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);