2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_defines.h"
41 #include "brw_multisample_state.h"
42 #include "brw_state.h"
46 #include "intel_batchbuffer.h"
47 #include "intel_buffer_objects.h"
48 #include "intel_fbo.h"
50 #include "main/enums.h"
51 #include "main/fbobject.h"
52 #include "main/framebuffer.h"
53 #include "main/glformats.h"
54 #include "main/samplerobj.h"
55 #include "main/shaderapi.h"
56 #include "main/stencil.h"
57 #include "main/transformfeedback.h"
58 #include "main/varray.h"
59 #include "main/viewport.h"
60 #include "util/half_float.h"
63 emit_dwords(struct brw_context
*brw
, unsigned n
)
65 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
66 uint32_t *map
= brw
->batch
.map_next
;
67 brw
->batch
.map_next
+= n
;
68 intel_batchbuffer_advance(brw
);
78 #define __gen_address_type struct brw_address
79 #define __gen_user_data struct brw_context
82 __gen_combine_address(struct brw_context
*brw
, void *location
,
83 struct brw_address address
, uint32_t delta
)
85 struct intel_batchbuffer
*batch
= &brw
->batch
;
88 if (address
.bo
== NULL
) {
89 return address
.offset
+ delta
;
91 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
92 offset
= (char *) location
- (char *) brw
->batch
.state_map
;
93 return brw_state_reloc(batch
, offset
, address
.bo
,
94 address
.offset
+ delta
,
98 assert(!brw_ptr_in_state_buffer(batch
, location
));
100 offset
= (char *) location
- (char *) brw
->batch
.map
;
101 return brw_batch_reloc(batch
, offset
, address
.bo
,
102 address
.offset
+ delta
,
103 address
.reloc_flags
);
107 static struct brw_address
108 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
110 return (struct brw_address
) {
113 .reloc_flags
= RELOC_WRITE
,
117 static struct brw_address
118 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
120 return (struct brw_address
) {
126 UNUSED
static struct brw_address
127 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
129 return (struct brw_address
) {
132 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
137 static struct brw_address
138 KSP(struct brw_context
*brw
, uint32_t offset
)
140 return ro_bo(brw
->cache
.bo
, offset
);
144 KSP(struct brw_context
*brw
, uint32_t offset
)
150 #include "genxml/genX_pack.h"
152 #define _brw_cmd_length(cmd) cmd ## _length
153 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
154 #define _brw_cmd_header(cmd) cmd ## _header
155 #define _brw_cmd_pack(cmd) cmd ## _pack
157 #define brw_batch_emit(brw, cmd, name) \
158 for (struct cmd name = { _brw_cmd_header(cmd) }, \
159 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
160 __builtin_expect(_dst != NULL, 1); \
161 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
164 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
165 uint32_t *_dw = emit_dwords(brw, n); \
166 struct cmd template = { \
167 _brw_cmd_header(cmd), \
168 .DWordLength = n - _brw_cmd_length_bias(cmd), \
171 _brw_cmd_pack(cmd)(brw, _dw, &template); \
172 _dw + 1; /* Array starts at dw[1] */ \
175 #define brw_state_emit(brw, cmd, align, offset, name) \
176 for (struct cmd name = {}, \
177 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
179 __builtin_expect(_dst != NULL, 1); \
180 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
184 * Polygon stipple packet
187 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
189 struct gl_context
*ctx
= &brw
->ctx
;
192 if (!ctx
->Polygon
.StippleFlag
)
195 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
196 /* Polygon stipple is provided in OpenGL order, i.e. bottom
197 * row first. If we're rendering to a window (i.e. the
198 * default frame buffer object, 0), then we need to invert
199 * it to match our pixel layout. But if we're rendering
200 * to a FBO (i.e. any named frame buffer object), we *don't*
201 * need to invert - we already match the layout.
203 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
204 for (unsigned i
= 0; i
< 32; i
++)
205 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
207 for (unsigned i
= 0; i
< 32; i
++)
208 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
213 static const struct brw_tracked_state
genX(polygon_stipple
) = {
215 .mesa
= _NEW_POLYGON
|
217 .brw
= BRW_NEW_CONTEXT
,
219 .emit
= genX(upload_polygon_stipple
),
223 * Polygon stipple offset packet
226 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
228 struct gl_context
*ctx
= &brw
->ctx
;
231 if (!ctx
->Polygon
.StippleFlag
)
234 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
237 * If we're drawing to a system window we have to invert the Y axis
238 * in order to match the OpenGL pixel coordinate system, and our
239 * offset must be matched to the window position. If we're drawing
240 * to a user-created FBO then our native pixel coordinate system
241 * works just fine, and there's no window system to worry about.
243 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
244 poly
.PolygonStippleYOffset
=
245 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
250 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
252 .mesa
= _NEW_BUFFERS
|
254 .brw
= BRW_NEW_CONTEXT
,
256 .emit
= genX(upload_polygon_stipple_offset
),
260 * Line stipple packet
263 genX(upload_line_stipple
)(struct brw_context
*brw
)
265 struct gl_context
*ctx
= &brw
->ctx
;
267 if (!ctx
->Line
.StippleFlag
)
270 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
271 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
273 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
274 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
278 static const struct brw_tracked_state
genX(line_stipple
) = {
281 .brw
= BRW_NEW_CONTEXT
,
283 .emit
= genX(upload_line_stipple
),
286 /* Constant single cliprect for framebuffer object or DRI2 drawing */
288 genX(upload_drawing_rect
)(struct brw_context
*brw
)
290 struct gl_context
*ctx
= &brw
->ctx
;
291 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
292 const unsigned int fb_width
= _mesa_geometric_width(fb
);
293 const unsigned int fb_height
= _mesa_geometric_height(fb
);
295 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
296 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
297 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
301 static const struct brw_tracked_state
genX(drawing_rect
) = {
303 .mesa
= _NEW_BUFFERS
,
304 .brw
= BRW_NEW_BLORP
|
307 .emit
= genX(upload_drawing_rect
),
311 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
315 unsigned start_offset
,
320 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
321 .VertexBufferIndex
= buffer_nr
,
322 .BufferPitch
= stride
,
323 .BufferStartingAddress
= ro_bo(bo
, start_offset
),
325 .BufferSize
= end_offset
- start_offset
,
329 .AddressModifyEnable
= true,
333 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
334 .InstanceDataStepRate
= step_rate
,
336 .EndAddress
= ro_bo(bo
, end_offset
- 1),
341 .VertexBufferMOCS
= CNL_MOCS_WB
,
343 .VertexBufferMOCS
= SKL_MOCS_WB
,
345 .VertexBufferMOCS
= BDW_MOCS_WB
,
347 .VertexBufferMOCS
= GEN7_MOCS_L3
,
351 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
352 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
356 is_passthru_format(uint32_t format
)
359 case ISL_FORMAT_R64_PASSTHRU
:
360 case ISL_FORMAT_R64G64_PASSTHRU
:
361 case ISL_FORMAT_R64G64B64_PASSTHRU
:
362 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
370 uploads_needed(uint32_t format
)
372 if (!is_passthru_format(format
))
376 case ISL_FORMAT_R64_PASSTHRU
:
377 case ISL_FORMAT_R64G64_PASSTHRU
:
379 case ISL_FORMAT_R64G64B64_PASSTHRU
:
380 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
383 unreachable("not reached");
388 * Returns the format that we are finally going to use when upload a vertex
389 * element. It will only change if we are using *64*PASSTHRU formats, as for
390 * gen < 8 they need to be splitted on two *32*FLOAT formats.
392 * @upload points in which upload we are. Valid values are [0,1]
395 downsize_format_if_needed(uint32_t format
,
398 assert(upload
== 0 || upload
== 1);
400 if (!is_passthru_format(format
))
404 case ISL_FORMAT_R64_PASSTHRU
:
405 return ISL_FORMAT_R32G32_FLOAT
;
406 case ISL_FORMAT_R64G64_PASSTHRU
:
407 return ISL_FORMAT_R32G32B32A32_FLOAT
;
408 case ISL_FORMAT_R64G64B64_PASSTHRU
:
409 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
410 : ISL_FORMAT_R32G32_FLOAT
;
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
412 return ISL_FORMAT_R32G32B32A32_FLOAT
;
414 unreachable("not reached");
419 * Returns the number of componentes associated with a format that is used on
420 * a 64 to 32 format split. See downsize_format()
423 upload_format_size(uint32_t upload_format
)
425 switch (upload_format
) {
426 case ISL_FORMAT_R32G32_FLOAT
:
428 case ISL_FORMAT_R32G32B32A32_FLOAT
:
431 unreachable("not reached");
436 genX(emit_vertices
)(struct brw_context
*brw
)
438 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
441 brw_prepare_vertices(brw
);
442 brw_prepare_shader_draw_parameters(brw
);
445 brw_emit_query_begin(brw
);
448 const struct brw_vs_prog_data
*vs_prog_data
=
449 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
452 struct gl_context
*ctx
= &brw
->ctx
;
453 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
454 ctx
->Polygon
.BackMode
!= GL_FILL
);
456 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
457 unsigned vue
= brw
->vb
.nr_enabled
;
459 /* The element for the edge flags must always be last, so we have to
460 * insert the SGVS before it in that case.
462 if (uses_edge_flag
) {
468 "Trying to insert VID/IID past 33rd vertex element, "
469 "need to reorder the vertex attrbutes.");
471 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
472 if (vs_prog_data
->uses_vertexid
) {
473 vfs
.VertexIDEnable
= true;
474 vfs
.VertexIDComponentNumber
= 2;
475 vfs
.VertexIDElementOffset
= vue
;
478 if (vs_prog_data
->uses_instanceid
) {
479 vfs
.InstanceIDEnable
= true;
480 vfs
.InstanceIDComponentNumber
= 3;
481 vfs
.InstanceIDElementOffset
= vue
;
485 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
486 vfi
.InstancingEnable
= true;
487 vfi
.VertexElementIndex
= vue
;
490 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
493 /* Normally we don't need an element for the SGVS attribute because the
494 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
495 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
496 * we're using draw parameters then we need an element for the those
497 * values. Additionally if there is an edge flag element then the SGVS
498 * can't be inserted past that so we need a dummy element to ensure that
499 * the edge flag is the last one.
501 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
502 vs_prog_data
->uses_baseinstance
||
503 ((vs_prog_data
->uses_instanceid
||
504 vs_prog_data
->uses_vertexid
)
507 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
508 vs_prog_data
->uses_baseinstance
||
509 vs_prog_data
->uses_instanceid
||
510 vs_prog_data
->uses_vertexid
);
512 unsigned nr_elements
=
513 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
516 /* If any of the formats of vb.enabled needs more that one upload, we need
517 * to add it to nr_elements
519 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
520 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
521 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
523 if (uploads_needed(format
) > 1)
528 /* If the VS doesn't read any inputs (calculating vertex position from
529 * a state variable for some reason, for example), emit a single pad
530 * VERTEX_ELEMENT struct and bail.
532 * The stale VB state stays in place, but they don't do anything unless
533 * a VE loads from them.
535 if (nr_elements
== 0) {
536 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
537 1 + GENX(VERTEX_ELEMENT_STATE_length
));
538 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
540 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
541 .Component0Control
= VFCOMP_STORE_0
,
542 .Component1Control
= VFCOMP_STORE_0
,
543 .Component2Control
= VFCOMP_STORE_0
,
544 .Component3Control
= VFCOMP_STORE_1_FP
,
546 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
550 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
551 const bool uses_draw_params
=
552 vs_prog_data
->uses_basevertex
||
553 vs_prog_data
->uses_baseinstance
;
554 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
555 uses_draw_params
+ vs_prog_data
->uses_drawid
;
558 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
560 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
561 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
563 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
564 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
565 /* Prior to Haswell and Bay Trail we have to use 4-component formats
566 * to fake 3-component ones. In particular, we do this for
567 * half-float and 8 and 16-bit integer formats. This means that the
568 * vertex element may poke over the end of the buffer by 2 bytes.
570 const unsigned padding
=
571 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
572 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
573 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
580 if (uses_draw_params
) {
581 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
582 brw
->draw
.draw_params_bo
,
583 brw
->draw
.draw_params_offset
,
584 brw
->draw
.draw_params_bo
->size
,
589 if (vs_prog_data
->uses_drawid
) {
590 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
591 brw
->draw
.draw_id_bo
,
592 brw
->draw
.draw_id_offset
,
593 brw
->draw
.draw_id_bo
->size
,
599 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
600 * presumably for VertexID/InstanceID.
603 assert(nr_elements
<= 34);
604 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
606 assert(nr_elements
<= 18);
609 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
610 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
612 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
613 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
614 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
615 uint32_t comp0
= VFCOMP_STORE_SRC
;
616 uint32_t comp1
= VFCOMP_STORE_SRC
;
617 uint32_t comp2
= VFCOMP_STORE_SRC
;
618 uint32_t comp3
= VFCOMP_STORE_SRC
;
619 const unsigned num_uploads
= GEN_GEN
< 8 ? uploads_needed(format
) : 1;
622 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
623 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
624 * element which has edge flag enabled."
626 assert(!(is_passthru_format(format
) && uses_edge_flag
));
629 /* The gen4 driver expects edgeflag to come in as a float, and passes
630 * that float on to the tests in the clipper. Mesa's current vertex
631 * attribute value for EdgeFlag is stored as a float, which works out.
632 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
633 * integer ubyte. Just rewrite that to convert to a float.
635 * Gen6+ passes edgeflag as sideband along with the vertex, instead
636 * of in the VUE. We have to upload it sideband as the last vertex
637 * element according to the B-Spec.
640 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
641 gen6_edgeflag_input
= input
;
646 for (unsigned c
= 0; c
< num_uploads
; c
++) {
647 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
648 downsize_format_if_needed(format
, c
);
649 /* If we need more that one upload, the offset stride would be 128
650 * bits (16 bytes), as for previous uploads we are using the full
652 const unsigned offset
= input
->offset
+ c
* 16;
654 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
655 upload_format_size(upload_format
) : input
->glarray
->Size
;
658 case 0: comp0
= VFCOMP_STORE_0
;
659 case 1: comp1
= VFCOMP_STORE_0
;
660 case 2: comp2
= VFCOMP_STORE_0
;
662 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
663 comp3
= VFCOMP_STORE_0
;
664 } else if (input
->glarray
->Integer
) {
665 comp3
= VFCOMP_STORE_1_INT
;
667 comp3
= VFCOMP_STORE_1_FP
;
674 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
676 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
677 * formats, 64-bit components are stored in the URB without any
678 * conversion. In this case, vertex elements must be written as 128
679 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
680 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
681 * component into the URB, Component 1 must be specified as
682 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
683 * order to output a 128-bit vertex element, or Components 1-3 must
684 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
685 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
686 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
689 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
690 /* Store vertex elements which correspond to double and dvec2 vertex
691 * shader inputs as 128-bit vertex elements, instead of 256-bits.
693 comp2
= VFCOMP_NOSTORE
;
694 comp3
= VFCOMP_NOSTORE
;
698 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
699 .VertexBufferIndex
= input
->buffer
,
701 .SourceElementFormat
= upload_format
,
702 .SourceElementOffset
= offset
,
703 .Component0Control
= comp0
,
704 .Component1Control
= comp1
,
705 .Component2Control
= comp2
,
706 .Component3Control
= comp3
,
708 .DestinationElementOffset
= i
* 4,
712 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
713 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
717 if (needs_sgvs_element
) {
718 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
720 .Component0Control
= VFCOMP_STORE_0
,
721 .Component1Control
= VFCOMP_STORE_0
,
722 .Component2Control
= VFCOMP_STORE_0
,
723 .Component3Control
= VFCOMP_STORE_0
,
725 .DestinationElementOffset
= i
* 4,
730 if (vs_prog_data
->uses_basevertex
||
731 vs_prog_data
->uses_baseinstance
) {
732 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
733 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
734 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
735 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
738 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
739 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
740 if (vs_prog_data
->uses_basevertex
)
741 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
743 if (vs_prog_data
->uses_baseinstance
)
744 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
746 if (vs_prog_data
->uses_vertexid
)
747 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
749 if (vs_prog_data
->uses_instanceid
)
750 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
753 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
754 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
757 if (vs_prog_data
->uses_drawid
) {
758 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
760 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
761 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32_UINT
,
762 .Component0Control
= VFCOMP_STORE_SRC
,
763 .Component1Control
= VFCOMP_STORE_0
,
764 .Component2Control
= VFCOMP_STORE_0
,
765 .Component3Control
= VFCOMP_STORE_0
,
767 .DestinationElementOffset
= i
* 4,
771 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
772 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
776 if (gen6_edgeflag_input
) {
777 const uint32_t format
=
778 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
780 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
782 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
783 .EdgeFlagEnable
= true,
784 .SourceElementFormat
= format
,
785 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
786 .Component0Control
= VFCOMP_STORE_SRC
,
787 .Component1Control
= VFCOMP_STORE_0
,
788 .Component2Control
= VFCOMP_STORE_0
,
789 .Component3Control
= VFCOMP_STORE_0
,
792 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
793 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
798 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
799 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
800 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
801 unsigned element_index
;
803 /* The edge flag element is reordered to be the last one in the code
804 * above so we need to compensate for that in the element indices used
807 if (input
== gen6_edgeflag_input
)
808 element_index
= nr_elements
- 1;
812 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
813 vfi
.VertexElementIndex
= element_index
;
814 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
815 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
819 if (vs_prog_data
->uses_drawid
) {
820 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
822 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
823 vfi
.VertexElementIndex
= element
;
829 static const struct brw_tracked_state
genX(vertices
) = {
831 .mesa
= _NEW_POLYGON
,
832 .brw
= BRW_NEW_BATCH
|
835 BRW_NEW_VS_PROG_DATA
,
837 .emit
= genX(emit_vertices
),
841 genX(emit_index_buffer
)(struct brw_context
*brw
)
843 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
845 if (index_buffer
== NULL
)
848 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
849 #if GEN_GEN < 8 && !GEN_IS_HASWELL
850 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
852 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
853 ib
.BufferStartingAddress
= ro_bo(brw
->ib
.bo
, 0);
855 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
856 ib
.BufferSize
= brw
->ib
.size
;
858 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
863 static const struct brw_tracked_state
genX(index_buffer
) = {
866 .brw
= BRW_NEW_BATCH
|
868 BRW_NEW_INDEX_BUFFER
,
870 .emit
= genX(emit_index_buffer
),
873 #if GEN_IS_HASWELL || GEN_GEN >= 8
875 genX(upload_cut_index
)(struct brw_context
*brw
)
877 const struct gl_context
*ctx
= &brw
->ctx
;
879 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
880 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
881 vf
.IndexedDrawCutIndexEnable
= true;
882 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
887 const struct brw_tracked_state
genX(cut_index
) = {
889 .mesa
= _NEW_TRANSFORM
,
890 .brw
= BRW_NEW_INDEX_BUFFER
,
892 .emit
= genX(upload_cut_index
),
898 * Determine the appropriate attribute override value to store into the
899 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
900 * override value contains two pieces of information: the location of the
901 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
902 * flag indicating whether to "swizzle" the attribute based on the direction
903 * the triangle is facing.
905 * If an attribute is "swizzled", then the given VUE location is used for
906 * front-facing triangles, and the VUE location that immediately follows is
907 * used for back-facing triangles. We use this to implement the mapping from
908 * gl_FrontColor/gl_BackColor to gl_Color.
910 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
911 * being instructed to begin reading attribute data. It can be set to a
912 * nonzero value to prevent the SF unit from wasting time reading elements of
913 * the VUE that are not needed by the fragment shader. It is measured in
914 * 256-bit increments.
917 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
918 const struct brw_vue_map
*vue_map
,
919 int urb_entry_read_offset
, int fs_attr
,
920 bool two_side_color
, uint32_t *max_source_attr
)
922 /* Find the VUE slot for this attribute. */
923 int slot
= vue_map
->varying_to_slot
[fs_attr
];
925 /* Viewport and Layer are stored in the VUE header. We need to override
926 * them to zero if earlier stages didn't write them, as GL requires that
927 * they read back as zero when not explicitly set.
929 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
930 attr
->ComponentOverrideX
= true;
931 attr
->ComponentOverrideW
= true;
932 attr
->ConstantSource
= CONST_0000
;
934 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
935 attr
->ComponentOverrideY
= true;
936 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
937 attr
->ComponentOverrideZ
= true;
942 /* If there was only a back color written but not front, use back
943 * as the color instead of undefined
945 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
946 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
947 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
948 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
951 /* This attribute does not exist in the VUE--that means that the vertex
952 * shader did not write to it. This means that either:
954 * (a) This attribute is a texture coordinate, and it is going to be
955 * replaced with point coordinates (as a consequence of a call to
956 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
957 * hardware will ignore whatever attribute override we supply.
959 * (b) This attribute is read by the fragment shader but not written by
960 * the vertex shader, so its value is undefined. Therefore the
961 * attribute override we supply doesn't matter.
963 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
964 * previous shader stage.
966 * Note that we don't have to worry about the cases where the attribute
967 * is gl_PointCoord or is undergoing point sprite coordinate
968 * replacement, because in those cases, this function isn't called.
970 * In case (c), we need to program the attribute overrides so that the
971 * primitive ID will be stored in this slot. In every other case, the
972 * attribute override we supply doesn't matter. So just go ahead and
973 * program primitive ID in every case.
975 attr
->ComponentOverrideW
= true;
976 attr
->ComponentOverrideX
= true;
977 attr
->ComponentOverrideY
= true;
978 attr
->ComponentOverrideZ
= true;
979 attr
->ConstantSource
= PRIM_ID
;
983 /* Compute the location of the attribute relative to urb_entry_read_offset.
984 * Each increment of urb_entry_read_offset represents a 256-bit value, so
985 * it counts for two 128-bit VUE slots.
987 int source_attr
= slot
- 2 * urb_entry_read_offset
;
988 assert(source_attr
>= 0 && source_attr
< 32);
990 /* If we are doing two-sided color, and the VUE slot following this one
991 * represents a back-facing color, then we need to instruct the SF unit to
992 * do back-facing swizzling.
994 bool swizzling
= two_side_color
&&
995 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
996 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
997 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
998 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1000 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1001 if (*max_source_attr
< source_attr
+ swizzling
)
1002 *max_source_attr
= source_attr
+ swizzling
;
1004 attr
->SourceAttribute
= source_attr
;
1006 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1011 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1012 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1013 uint32_t *point_sprite_enables
,
1014 uint32_t *urb_entry_read_length
,
1015 uint32_t *urb_entry_read_offset
)
1017 const struct gl_context
*ctx
= &brw
->ctx
;
1020 const struct gl_point_attrib
*point
= &ctx
->Point
;
1022 /* BRW_NEW_FRAGMENT_PROGRAM */
1023 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1025 /* BRW_NEW_FS_PROG_DATA */
1026 const struct brw_wm_prog_data
*wm_prog_data
=
1027 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1028 uint32_t max_source_attr
= 0;
1030 *point_sprite_enables
= 0;
1033 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1034 &brw
->vue_map_geom_out
);
1036 /* Each URB offset packs two varying slots */
1037 assert(first_slot
% 2 == 0);
1038 *urb_entry_read_offset
= first_slot
/ 2;
1040 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1041 * description of dw10 Point Sprite Texture Coordinate Enable:
1043 * "This field must be programmed to zero when non-point primitives
1046 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1047 * must be programmed to zero when rendering non-point primitives, but
1048 * the IvyBridge PRM does, and if we don't, we get garbage.
1050 * This is not required on Haswell, as the hardware ignores this state
1051 * when drawing non-points -- although we do still need to be careful to
1052 * correctly set the attr overrides.
1055 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1057 bool drawing_points
= brw_is_drawing_points(brw
);
1059 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1060 int input_index
= wm_prog_data
->urb_setup
[attr
];
1062 if (input_index
< 0)
1066 bool point_sprite
= false;
1067 if (drawing_points
) {
1068 if (point
->PointSprite
&&
1069 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1070 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1071 point_sprite
= true;
1074 if (attr
== VARYING_SLOT_PNTC
)
1075 point_sprite
= true;
1078 *point_sprite_enables
|= (1 << input_index
);
1081 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1082 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1084 if (!point_sprite
) {
1085 genX(get_attr_override
)(&attribute
,
1086 &brw
->vue_map_geom_out
,
1087 *urb_entry_read_offset
, attr
,
1088 _mesa_vertex_program_two_side_enabled(ctx
),
1092 /* The hardware can only do the overrides on 16 overrides at a
1093 * time, and the other up to 16 have to be lined up so that the
1094 * input index = the output index. We'll need to do some
1095 * tweaking to make sure that's the case.
1097 if (input_index
< 16)
1098 attr_overrides
[input_index
] = attribute
;
1100 assert(attribute
.SourceAttribute
== input_index
);
1103 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1104 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1106 * "This field should be set to the minimum length required to read the
1107 * maximum source attribute. The maximum source attribute is indicated
1108 * by the maximum value of the enabled Attribute # Source Attribute if
1109 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1110 * enable is not set.
1111 * read_length = ceiling((max_source_attr + 1) / 2)
1113 * [errata] Corruption/Hang possible if length programmed larger than
1116 * Similar text exists for Ivy Bridge.
1118 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1122 /* ---------------------------------------------------------------------- */
1125 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1127 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1129 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1133 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1135 struct gl_context
*ctx
= &brw
->ctx
;
1138 struct intel_renderbuffer
*depth_irb
=
1139 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1142 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1145 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1146 const int b
= stencil
->_BackFace
;
1148 if (depth
->Test
&& depth_irb
) {
1149 ds
->DepthTestEnable
= true;
1150 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1151 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1154 if (brw
->stencil_enabled
) {
1155 ds
->StencilTestEnable
= true;
1156 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1157 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1159 ds
->StencilTestFunction
=
1160 intel_translate_compare_func(stencil
->Function
[0]);
1162 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1163 ds
->StencilPassDepthPassOp
=
1164 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1165 ds
->StencilPassDepthFailOp
=
1166 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1168 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1170 if (brw
->stencil_two_sided
) {
1171 ds
->DoubleSidedStencilEnable
= true;
1172 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1173 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1175 ds
->BackfaceStencilTestFunction
=
1176 intel_translate_compare_func(stencil
->Function
[b
]);
1177 ds
->BackfaceStencilFailOp
=
1178 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1179 ds
->BackfaceStencilPassDepthPassOp
=
1180 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1181 ds
->BackfaceStencilPassDepthFailOp
=
1182 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1185 #if GEN_GEN <= 5 || GEN_GEN >= 9
1186 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1187 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1194 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1197 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1198 set_depth_stencil_bits(brw
, &wmds
);
1202 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1203 set_depth_stencil_bits(brw
, &ds
);
1206 /* Now upload a pointer to the indirect state */
1208 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1209 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1210 ptr
.DEPTH_STENCIL_STATEChange
= true;
1213 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1214 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1220 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1222 .mesa
= _NEW_BUFFERS
|
1225 .brw
= BRW_NEW_BLORP
|
1226 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1228 BRW_NEW_STATE_BASE_ADDRESS
),
1230 .emit
= genX(upload_depth_stencil_state
),
1234 /* ---------------------------------------------------------------------- */
1239 genX(upload_clip_state
)(struct brw_context
*brw
)
1241 struct gl_context
*ctx
= &brw
->ctx
;
1243 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1244 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1245 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1246 clip
.GRFRegisterCount
=
1247 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1248 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1249 clip
.SingleProgramFlow
= true;
1250 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1251 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1253 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1254 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1255 clip
.DispatchGRFStartRegisterForURBData
= 1;
1256 clip
.VertexURBEntryReadOffset
= 0;
1258 /* BRW_NEW_URB_FENCE */
1259 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1260 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1262 if (brw
->urb
.nr_clip_entries
>= 10) {
1263 /* Half of the URB entries go to each thread, and it has to be an
1266 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1268 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1269 * only 2 threads can output VUEs at a time.
1271 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1273 assert(brw
->urb
.nr_clip_entries
>= 5);
1274 clip
.MaximumNumberofThreads
= 1 - 1;
1277 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1278 clip
.UserClipFlagsMustClipEnable
= true;
1279 clip
.GuardbandClipTestEnable
= true;
1281 clip
.ClipperViewportStatePointer
=
1282 ro_bo(brw
->batch
.state_bo
, brw
->clip
.vp_offset
);
1284 clip
.ScreenSpaceViewportXMin
= -1;
1285 clip
.ScreenSpaceViewportXMax
= 1;
1286 clip
.ScreenSpaceViewportYMin
= -1;
1287 clip
.ScreenSpaceViewportYMax
= 1;
1289 clip
.ViewportXYClipTestEnable
= true;
1290 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1292 /* _NEW_TRANSFORM */
1293 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1294 clip
.UserClipDistanceClipTestEnableBitmask
=
1295 ctx
->Transform
.ClipPlanesEnabled
;
1297 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1300 clip
.UserClipDistanceClipTestEnableBitmask
=
1301 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1304 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1305 clip
.APIMode
= APIMODE_D3D
;
1307 clip
.APIMode
= APIMODE_OGL
;
1309 clip
.GuardbandClipTestEnable
= true;
1311 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1314 clip
.NegativeWClipTestEnable
= true;
1319 const struct brw_tracked_state
genX(clip_state
) = {
1321 .mesa
= _NEW_TRANSFORM
|
1323 .brw
= BRW_NEW_BATCH
|
1325 BRW_NEW_CLIP_PROG_DATA
|
1326 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1327 BRW_NEW_PROGRAM_CACHE
|
1330 .emit
= genX(upload_clip_state
),
1336 genX(upload_clip_state
)(struct brw_context
*brw
)
1338 struct gl_context
*ctx
= &brw
->ctx
;
1341 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1343 /* BRW_NEW_FS_PROG_DATA */
1344 struct brw_wm_prog_data
*wm_prog_data
=
1345 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1347 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1348 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1350 if (wm_prog_data
->barycentric_interp_modes
&
1351 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1352 clip
.NonPerspectiveBarycentricEnable
= true;
1355 clip
.EarlyCullEnable
= true;
1359 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1361 if (ctx
->Polygon
.CullFlag
) {
1362 switch (ctx
->Polygon
.CullFaceMode
) {
1364 clip
.CullMode
= CULLMODE_FRONT
;
1367 clip
.CullMode
= CULLMODE_BACK
;
1369 case GL_FRONT_AND_BACK
:
1370 clip
.CullMode
= CULLMODE_BOTH
;
1373 unreachable("Should not get here: invalid CullFlag");
1376 clip
.CullMode
= CULLMODE_NONE
;
1381 clip
.UserClipDistanceCullTestEnableBitmask
=
1382 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1384 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1388 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1389 clip
.TriangleStripListProvokingVertexSelect
= 0;
1390 clip
.TriangleFanProvokingVertexSelect
= 1;
1391 clip
.LineStripListProvokingVertexSelect
= 0;
1393 clip
.TriangleStripListProvokingVertexSelect
= 2;
1394 clip
.TriangleFanProvokingVertexSelect
= 2;
1395 clip
.LineStripListProvokingVertexSelect
= 1;
1398 /* _NEW_TRANSFORM */
1399 clip
.UserClipDistanceClipTestEnableBitmask
=
1400 ctx
->Transform
.ClipPlanesEnabled
;
1403 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1406 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1407 clip
.APIMode
= APIMODE_D3D
;
1409 clip
.APIMode
= APIMODE_OGL
;
1411 clip
.GuardbandClipTestEnable
= true;
1413 /* BRW_NEW_VIEWPORT_COUNT */
1414 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1416 if (ctx
->RasterDiscard
) {
1417 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1419 perf_debug("Rasterizer discard is currently implemented via the "
1420 "clipper; having the GS not write primitives would "
1421 "likely be faster.\n");
1424 clip
.ClipMode
= CLIPMODE_NORMAL
;
1427 clip
.ClipEnable
= true;
1430 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1432 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1433 clip
.ViewportXYClipTestEnable
= true;
1435 clip
.MinimumPointWidth
= 0.125;
1436 clip
.MaximumPointWidth
= 255.875;
1437 clip
.MaximumVPIndex
= viewport_count
- 1;
1438 if (_mesa_geometric_layers(fb
) == 0)
1439 clip
.ForceZeroRTAIndexEnable
= true;
1443 static const struct brw_tracked_state
genX(clip_state
) = {
1445 .mesa
= _NEW_BUFFERS
|
1449 .brw
= BRW_NEW_BLORP
|
1451 BRW_NEW_FS_PROG_DATA
|
1452 BRW_NEW_GS_PROG_DATA
|
1453 BRW_NEW_VS_PROG_DATA
|
1454 BRW_NEW_META_IN_PROGRESS
|
1456 BRW_NEW_RASTERIZER_DISCARD
|
1457 BRW_NEW_TES_PROG_DATA
|
1458 BRW_NEW_VIEWPORT_COUNT
,
1460 .emit
= genX(upload_clip_state
),
1464 /* ---------------------------------------------------------------------- */
1467 genX(upload_sf
)(struct brw_context
*brw
)
1469 struct gl_context
*ctx
= &brw
->ctx
;
1474 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1475 UNUSED
const bool multisampled_fbo
=
1476 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1480 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1482 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1484 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1485 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1486 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1487 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1488 sf
.DispatchGRFStartRegisterForURBData
= 3;
1489 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1490 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1491 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1492 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1494 /* STATE_PREFETCH command description describes this state as being
1495 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1498 sf
.SetupViewportStateOffset
=
1499 ro_bo(brw
->batch
.state_bo
, brw
->sf
.vp_offset
);
1501 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1503 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1504 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1506 sf
.MaximumNumberofThreads
=
1507 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1509 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1511 sf
.DestinationOriginHorizontalBias
= 0.5;
1512 sf
.DestinationOriginVerticalBias
= 0.5;
1514 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1515 sf
.StatisticsEnable
= true;
1517 sf
.ViewportTransformEnable
= true;
1521 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1526 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1528 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1529 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1530 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1532 switch (ctx
->Polygon
.FrontMode
) {
1534 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1537 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1540 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1543 unreachable("not reached");
1546 switch (ctx
->Polygon
.BackMode
) {
1548 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1551 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1554 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1557 unreachable("not reached");
1560 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1561 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1563 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1564 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1565 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1568 sf
.ScissorRectangleEnable
= true;
1570 if (ctx
->Polygon
.CullFlag
) {
1571 switch (ctx
->Polygon
.CullFaceMode
) {
1573 sf
.CullMode
= CULLMODE_FRONT
;
1576 sf
.CullMode
= CULLMODE_BACK
;
1578 case GL_FRONT_AND_BACK
:
1579 sf
.CullMode
= CULLMODE_BOTH
;
1582 unreachable("not reached");
1585 sf
.CullMode
= CULLMODE_NONE
;
1589 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1596 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1598 if (devinfo
->is_cherryview
)
1599 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1601 sf
.LineWidth
= brw_get_line_width(brw
);
1603 sf
.LineWidth
= brw_get_line_width(brw
);
1606 if (ctx
->Line
.SmoothFlag
) {
1607 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1609 sf
.AntiAliasingEnable
= true;
1613 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1614 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1615 /* Clamp to the hardware limits */
1616 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1618 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1619 if (use_state_point_size(brw
))
1620 sf
.PointWidthSource
= State
;
1623 /* _NEW_POINT | _NEW_MULTISAMPLE */
1624 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1625 !ctx
->Point
.PointSprite
)
1626 sf
.SmoothPointEnable
= true;
1629 #if GEN_IS_G4X || GEN_GEN >= 5
1630 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1634 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1635 sf
.TriangleStripListProvokingVertexSelect
= 2;
1636 sf
.TriangleFanProvokingVertexSelect
= 2;
1637 sf
.LineStripListProvokingVertexSelect
= 1;
1639 sf
.TriangleFanProvokingVertexSelect
= 1;
1643 /* BRW_NEW_FS_PROG_DATA */
1644 const struct brw_wm_prog_data
*wm_prog_data
=
1645 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1647 sf
.AttributeSwizzleEnable
= true;
1648 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1651 * Window coordinates in an FBO are inverted, which means point
1652 * sprite origin must be inverted, too.
1654 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1655 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1657 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1660 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1661 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1663 uint32_t urb_entry_read_length
;
1664 uint32_t urb_entry_read_offset
;
1665 uint32_t point_sprite_enables
;
1666 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1667 &urb_entry_read_length
,
1668 &urb_entry_read_offset
);
1669 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1670 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1671 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1672 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1677 static const struct brw_tracked_state
genX(sf_state
) = {
1679 .mesa
= _NEW_LIGHT
|
1683 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1684 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1685 .brw
= BRW_NEW_BLORP
|
1686 BRW_NEW_VUE_MAP_GEOM_OUT
|
1687 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1688 BRW_NEW_PROGRAM_CACHE
|
1689 BRW_NEW_SF_PROG_DATA
|
1693 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1694 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1695 BRW_NEW_GS_PROG_DATA
|
1697 BRW_NEW_TES_PROG_DATA
1699 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1700 BRW_NEW_FRAGMENT_PROGRAM
1703 .emit
= genX(upload_sf
),
1706 /* ---------------------------------------------------------------------- */
1709 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1711 struct gl_context
*ctx
= &brw
->ctx
;
1712 /* BRW_NEW_FRAGMENT_PROGRAM */
1713 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1717 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1718 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1719 uint64_t outputs_written
= fp
->info
.outputs_written
;
1722 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1723 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1724 (ctx
->Color
.ColorMask
[i
][0] ||
1725 ctx
->Color
.ColorMask
[i
][1] ||
1726 ctx
->Color
.ColorMask
[i
][2] ||
1727 ctx
->Color
.ColorMask
[i
][3])) {
1736 genX(upload_wm
)(struct brw_context
*brw
)
1738 struct gl_context
*ctx
= &brw
->ctx
;
1740 /* BRW_NEW_FS_PROG_DATA */
1741 const struct brw_wm_prog_data
*wm_prog_data
=
1742 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1744 UNUSED
bool writes_depth
=
1745 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1746 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1747 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1750 /* We can't fold this into gen6_upload_wm_push_constants(), because
1751 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1752 * (3DSTATE_CONSTANT_PS [DevSNB]):
1754 * "[DevSNB]: This packet must be followed by WM_STATE."
1756 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1757 if (wm_prog_data
->base
.nr_params
!= 0) {
1758 wmcp
.Buffer0Valid
= true;
1759 /* Pointer to the WM constant buffer. Covered by the set of
1760 * state flags from gen6_upload_wm_push_constants.
1762 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1763 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1769 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1770 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1771 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1773 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1774 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1776 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1777 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1778 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1779 /* These two fields should be the same pre-gen6, which is why we
1780 * only have one hardware field to program for both dispatch
1783 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1784 wm_prog_data
->dispatch_grf_start_reg_2
);
1787 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1788 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1790 if (stage_state
->sampler_count
)
1791 wm
.SamplerStatePointer
=
1792 ro_bo(brw
->batch
.state_bo
, stage_state
->sampler_offset
);
1794 if (wm_prog_data
->prog_offset_2
)
1795 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1798 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1799 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1800 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1801 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1802 wm
.EarlyDepthTestEnable
= true;
1803 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1804 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1807 if (ctx
->Polygon
.OffsetFill
) {
1808 wm
.GlobalDepthOffsetEnable
= true;
1809 /* Something weird going on with legacy_global_depth_bias,
1810 * offset_constant, scaling and MRD. This value passes glean
1811 * but gives some odd results elsewere (eg. the
1812 * quad-offset-units test).
1814 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1816 /* This is the only value that passes glean:
1818 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1821 wm
.DepthCoefficientURBReadOffset
= 1;
1824 /* BRW_NEW_STATS_WM */
1825 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1828 if (wm_prog_data
->base
.use_alt_mode
)
1829 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1831 wm
.SamplerCount
= GEN_GEN
== 5 ?
1832 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1834 wm
.BindingTableEntryCount
=
1835 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1836 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1837 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1838 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1839 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1840 wm_prog_data
->base
.dispatch_grf_start_reg
;
1842 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1843 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1847 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1848 wm
.KernelStartPointer2
=
1849 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1854 wm
.DualSourceBlendEnable
=
1855 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1856 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1857 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1858 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1860 /* From the SNB PRM, volume 2 part 1, page 281:
1861 * "If the PS kernel does not need the Position XY Offsets
1862 * to compute a Position XY value, then this field should be
1863 * programmed to POSOFFSET_NONE."
1865 * "SW Recommendation: If the PS kernel needs the Position Offsets
1866 * to compute a Position XY value, this field should match Position
1867 * ZW Interpolation Mode to ensure a consistent position.xyzw
1869 * We only require XY sample offsets. So, this recommendation doesn't
1870 * look useful at the moment. We might need this in future.
1872 if (wm_prog_data
->uses_pos_offset
)
1873 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1875 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1877 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1878 wm_prog_data
->dispatch_grf_start_reg_2
;
1881 if (wm_prog_data
->base
.total_scratch
) {
1882 wm
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
1883 wm
.PerThreadScratchSpace
=
1884 ffs(stage_state
->per_thread_scratch
) - 11;
1887 wm
.PixelShaderComputedDepth
= writes_depth
;
1891 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1894 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1899 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1902 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1904 if (multisampled_fbo
) {
1905 /* _NEW_MULTISAMPLE */
1906 if (ctx
->Multisample
.Enabled
)
1907 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1909 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1911 if (wm_prog_data
->persample_dispatch
)
1912 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1914 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1916 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1917 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1920 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1921 if (wm_prog_data
->uses_kill
||
1922 _mesa_is_alpha_test_enabled(ctx
) ||
1923 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1924 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1925 wm
.PixelShaderKillsPixel
= true;
1928 /* _NEW_BUFFERS | _NEW_COLOR */
1929 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1930 wm
.PixelShaderKillsPixel
||
1931 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1932 wm
.ThreadDispatchEnable
= true;
1936 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1937 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1940 /* The "UAV access enable" bits are unnecessary on HSW because they only
1941 * seem to have an effect on the HW-assisted coherency mechanism which we
1942 * don't need, and the rasterization-related UAV_ONLY flag and the
1943 * DISPATCH_ENABLE bit can be set independently from it.
1944 * C.f. gen8_upload_ps_extra().
1946 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1950 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1951 wm_prog_data
->has_side_effects
)
1957 /* BRW_NEW_FS_PROG_DATA */
1958 if (wm_prog_data
->early_fragment_tests
)
1959 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1960 else if (wm_prog_data
->has_side_effects
)
1961 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1966 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
1967 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
1968 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1971 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
1976 static const struct brw_tracked_state
genX(wm_state
) = {
1980 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1983 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
1984 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
1985 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
1986 .brw
= BRW_NEW_BLORP
|
1987 BRW_NEW_FS_PROG_DATA
|
1988 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1989 BRW_NEW_FRAGMENT_PROGRAM
|
1990 BRW_NEW_PROGRAM_CACHE
|
1991 BRW_NEW_SAMPLER_STATE_TABLE
|
1994 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
1996 .emit
= genX(upload_wm
),
1999 /* ---------------------------------------------------------------------- */
2001 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2002 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2003 pkt.SamplerCount = \
2004 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2005 pkt.BindingTableEntryCount = \
2006 stage_prog_data->binding_table.size_bytes / 4; \
2007 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2009 if (stage_prog_data->total_scratch) { \
2010 pkt.ScratchSpaceBasePointer = rw_bo(stage_state->scratch_bo, 0); \
2011 pkt.PerThreadScratchSpace = \
2012 ffs(stage_state->per_thread_scratch) - 11; \
2015 pkt.DispatchGRFStartRegisterForURBData = \
2016 stage_prog_data->dispatch_grf_start_reg; \
2017 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2018 pkt.prefix##URBEntryReadOffset = 0; \
2020 pkt.StatisticsEnable = true; \
2024 genX(upload_vs_state
)(struct brw_context
*brw
)
2026 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2027 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2028 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2030 /* BRW_NEW_VS_PROG_DATA */
2031 const struct brw_vue_prog_data
*vue_prog_data
=
2032 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2033 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2035 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2036 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2039 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2040 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2042 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2043 * command that causes the VS Function Enable to toggle. Pipeline
2044 * flush can be executed by sending a PIPE_CONTROL command with CS
2045 * stall bit set and a post sync operation.
2047 * We've already done such a flush at the start of state upload, so we
2048 * don't need to do another one here.
2050 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2051 if (stage_state
->push_const_size
!= 0) {
2052 cvs
.Buffer0Valid
= true;
2053 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2054 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2059 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2060 gen7_emit_vs_workaround_flush(brw
);
2063 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2065 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2066 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2068 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2070 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2073 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2074 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2075 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2077 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2078 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2080 vs
.MaximumNumberofThreads
=
2081 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2083 vs
.StatisticsEnable
= false;
2084 vs
.SamplerStatePointer
=
2085 ro_bo(brw
->batch
.state_bo
, stage_state
->sampler_offset
);
2089 /* Force single program flow on Ironlake. We cannot reliably get
2090 * all applications working without it. See:
2091 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2093 * The most notable and reliably failing application is the Humus
2096 vs
.SingleProgramFlow
= true;
2097 vs
.SamplerCount
= 0; /* hardware requirement */
2101 vs
.SIMD8DispatchEnable
=
2102 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2104 vs
.UserClipDistanceCullTestEnableBitmask
=
2105 vue_prog_data
->cull_distance_mask
;
2110 /* Based on my reading of the simulator, the VS constants don't get
2111 * pulled into the VS FF unit until an appropriate pipeline flush
2112 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2113 * references to them into a little FIFO. The flushes are common,
2114 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2115 * the primitive to use the wrong constants. Then the FIFO
2116 * containing the constant setup gets added to again on the next
2117 * constants change, and eventually when a flush does happen the
2118 * unit is overwhelmed by constant changes and dies.
2120 * To avoid this, send a PIPE_CONTROL down the line that will
2121 * update the unit immediately loading the constants. The flush
2122 * type bits here were those set by the STATE_BASE_ADDRESS whose
2123 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2124 * bug reports that led to this workaround, and may be more than
2125 * what is strictly required to avoid the issue.
2127 brw_emit_pipe_control_flush(brw
,
2128 PIPE_CONTROL_DEPTH_STALL
|
2129 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2130 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2134 static const struct brw_tracked_state
genX(vs_state
) = {
2136 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2137 .brw
= BRW_NEW_BATCH
|
2140 BRW_NEW_VS_PROG_DATA
|
2141 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2142 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2143 BRW_NEW_PROGRAM_CACHE
|
2144 BRW_NEW_SAMPLER_STATE_TABLE
|
2148 .emit
= genX(upload_vs_state
),
2151 /* ---------------------------------------------------------------------- */
2154 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2156 struct gl_context
*ctx
= &brw
->ctx
;
2158 /* BRW_NEW_VIEWPORT_COUNT */
2159 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2161 struct GENX(CC_VIEWPORT
) ccv
;
2162 uint32_t cc_vp_offset
;
2164 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2167 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2168 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2169 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2170 if (ctx
->Transform
.DepthClamp
) {
2171 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2172 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2174 ccv
.MinimumDepth
= 0.0;
2175 ccv
.MaximumDepth
= 1.0;
2177 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2178 cc_map
+= GENX(CC_VIEWPORT_length
);
2182 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2183 ptr
.CCViewportPointer
= cc_vp_offset
;
2186 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2187 vp
.CCViewportStateChange
= 1;
2188 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2191 brw
->cc
.vp_offset
= cc_vp_offset
;
2192 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2196 const struct brw_tracked_state
genX(cc_vp
) = {
2198 .mesa
= _NEW_TRANSFORM
|
2200 .brw
= BRW_NEW_BATCH
|
2202 BRW_NEW_VIEWPORT_COUNT
,
2204 .emit
= genX(upload_cc_viewport
)
2207 /* ---------------------------------------------------------------------- */
2210 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2211 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2212 struct GENX(SCISSOR_RECT
) *sc
)
2216 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2217 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2218 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2219 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2220 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2222 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2223 /* If the scissor was out of bounds and got clamped to 0 width/height
2224 * at the bounds, the subtraction of 1 from maximums could produce a
2225 * negative number and thus not clip anything. Instead, just provide
2226 * a min > max scissor inside the bounds, which produces the expected
2229 sc
->ScissorRectangleXMin
= 1;
2230 sc
->ScissorRectangleXMax
= 0;
2231 sc
->ScissorRectangleYMin
= 1;
2232 sc
->ScissorRectangleYMax
= 0;
2233 } else if (render_to_fbo
) {
2234 /* texmemory: Y=0=bottom */
2235 sc
->ScissorRectangleXMin
= bbox
[0];
2236 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2237 sc
->ScissorRectangleYMin
= bbox
[2];
2238 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2240 /* memory: Y=0=top */
2241 sc
->ScissorRectangleXMin
= bbox
[0];
2242 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2243 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2244 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2250 genX(upload_scissor_state
)(struct brw_context
*brw
)
2252 struct gl_context
*ctx
= &brw
->ctx
;
2253 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2254 struct GENX(SCISSOR_RECT
) scissor
;
2255 uint32_t scissor_state_offset
;
2256 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2257 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2258 uint32_t *scissor_map
;
2260 /* BRW_NEW_VIEWPORT_COUNT */
2261 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2263 scissor_map
= brw_state_batch(
2264 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2265 32, &scissor_state_offset
);
2267 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2269 /* The scissor only needs to handle the intersection of drawable and
2270 * scissor rect. Clipping to the boundaries of static shared buffers
2271 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2273 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2274 * inclusive but max is exclusive.
2276 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2277 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2278 GENX(SCISSOR_RECT_pack
)(
2279 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2282 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2283 ptr
.ScissorRectPointer
= scissor_state_offset
;
2287 static const struct brw_tracked_state
genX(scissor_state
) = {
2289 .mesa
= _NEW_BUFFERS
|
2292 .brw
= BRW_NEW_BATCH
|
2294 BRW_NEW_VIEWPORT_COUNT
,
2296 .emit
= genX(upload_scissor_state
),
2300 /* ---------------------------------------------------------------------- */
2303 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2304 float m00
, float m11
, float m30
, float m31
,
2305 float *xmin
, float *xmax
,
2306 float *ymin
, float *ymax
)
2308 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2309 * Strips and Fans documentation:
2311 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2312 * fixed-point "guardband" range supported by the rasterization hardware"
2316 * "In almost all circumstances, if an object’s vertices are actually
2317 * modified by this clamping (i.e., had X or Y coordinates outside of
2318 * the guardband extent the rendered object will not match the intended
2319 * result. Therefore software should take steps to ensure that this does
2320 * not happen - e.g., by clipping objects such that they do not exceed
2321 * these limits after the Drawing Rectangle is applied."
2323 * I believe the fundamental restriction is that the rasterizer (in
2324 * the SF/WM stages) have a limit on the number of pixels that can be
2325 * rasterized. We need to ensure any coordinates beyond the rasterizer
2326 * limit are handled by the clipper. So effectively that limit becomes
2327 * the clipper's guardband size.
2329 * It goes on to say:
2331 * "In addition, in order to be correctly rendered, objects must have a
2332 * screenspace bounding box not exceeding 8K in the X or Y direction.
2333 * This additional restriction must also be comprehended by software,
2334 * i.e., enforced by use of clipping."
2336 * This makes no sense. Gen7+ hardware supports 16K render targets,
2337 * and you definitely need to be able to draw polygons that fill the
2338 * surface. Our assumption is that the rasterizer was limited to 8K
2339 * on Sandybridge, which only supports 8K surfaces, and it was actually
2340 * increased to 16K on Ivybridge and later.
2342 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2344 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2346 if (m00
!= 0 && m11
!= 0) {
2347 /* First, we compute the screen-space render area */
2348 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2349 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2350 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2351 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2353 /* We want the guardband to be centered on that */
2354 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2355 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2356 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2357 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2359 /* Now we need it in native device coordinates */
2360 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2361 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2362 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2363 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2365 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2366 * flipped upside-down. X should be fine though.
2368 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2369 *xmin
= ndc_gb_xmin
;
2370 *xmax
= ndc_gb_xmax
;
2371 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2372 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2374 /* The viewport scales to 0, so nothing will be rendered. */
2383 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2385 struct gl_context
*ctx
= &brw
->ctx
;
2386 float y_scale
, y_bias
;
2388 /* BRW_NEW_VIEWPORT_COUNT */
2389 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2392 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2393 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2394 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2398 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2399 uint32_t sf_clip_vp_offset
;
2400 uint32_t *sf_clip_map
=
2401 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2402 64, &sf_clip_vp_offset
);
2404 struct GENX(SF_VIEWPORT
) sfv
;
2405 struct GENX(CLIP_VIEWPORT
) clv
;
2406 uint32_t sf_vp_offset
, clip_vp_offset
;
2408 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2410 uint32_t *clip_map
=
2411 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2412 32, &clip_vp_offset
);
2416 if (render_to_fbo
) {
2421 y_bias
= (float)fb_height
;
2424 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2425 /* _NEW_VIEWPORT: Guardband Clipping */
2426 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2427 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2429 sfv
.ViewportMatrixElementm00
= scale
[0];
2430 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2431 sfv
.ViewportMatrixElementm22
= scale
[2],
2432 sfv
.ViewportMatrixElementm30
= translate
[0],
2433 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2434 sfv
.ViewportMatrixElementm32
= translate
[2],
2435 brw_calculate_guardband_size(fb_width
, fb_height
,
2436 sfv
.ViewportMatrixElementm00
,
2437 sfv
.ViewportMatrixElementm11
,
2438 sfv
.ViewportMatrixElementm30
,
2439 sfv
.ViewportMatrixElementm31
,
2440 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2443 clv
.XMinClipGuardband
= gb_xmin
;
2444 clv
.XMaxClipGuardband
= gb_xmax
;
2445 clv
.YMinClipGuardband
= gb_ymin
;
2446 clv
.YMaxClipGuardband
= gb_ymax
;
2449 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2450 &sfv
.ScissorRectangle
);
2452 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2453 * The hardware will take the intersection of the drawing rectangle,
2454 * scissor rectangle, and the viewport extents. We don't need to be
2455 * smart, and can therefore just program the viewport extents.
2457 const float viewport_Xmax
=
2458 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2459 const float viewport_Ymax
=
2460 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2462 if (render_to_fbo
) {
2463 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2464 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2465 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2466 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2468 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2469 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2470 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2471 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2476 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2477 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2479 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2480 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2481 sf_map
+= GENX(SF_VIEWPORT_length
);
2482 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2487 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2488 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2491 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2492 vp
.SFViewportStateChange
= 1;
2493 vp
.CLIPViewportStateChange
= 1;
2494 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2495 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2498 brw
->sf
.vp_offset
= sf_vp_offset
;
2499 brw
->clip
.vp_offset
= clip_vp_offset
;
2500 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2504 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2506 .mesa
= _NEW_BUFFERS
|
2508 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2509 .brw
= BRW_NEW_BATCH
|
2511 BRW_NEW_VIEWPORT_COUNT
,
2513 .emit
= genX(upload_sf_clip_viewport
),
2516 /* ---------------------------------------------------------------------- */
2519 genX(upload_gs_state
)(struct brw_context
*brw
)
2521 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2522 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2523 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2524 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2525 /* BRW_NEW_GEOMETRY_PROGRAM */
2526 bool active
= GEN_GEN
>= 6 && gs_prog
;
2528 /* BRW_NEW_GS_PROG_DATA */
2529 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2530 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2531 brw_vue_prog_data(stage_prog_data
);
2533 const struct brw_gs_prog_data
*gs_prog_data
=
2534 brw_gs_prog_data(stage_prog_data
);
2538 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2539 if (active
&& stage_state
->push_const_size
!= 0) {
2540 cgs
.Buffer0Valid
= true;
2541 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2542 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2547 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2549 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2550 * Geometry > Geometry Shader > State:
2552 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2553 * whole fixed function pipeline when the GS enable changes value in
2556 * The hardware architects have clarified that in this context "flush the
2557 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2560 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2561 gen7_emit_cs_stall_flush(brw
);
2565 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2567 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2568 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2573 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2576 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2577 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2578 gs
.ControlDataHeaderSize
=
2579 gs_prog_data
->control_data_header_size_hwords
;
2581 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2582 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2584 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2586 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2589 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2590 * Ivy Bridge and Haswell.
2592 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2593 * strip to be delivered to the geometry shader in an order that does
2594 * not strictly follow the OpenGL spec, but preserves triangle
2595 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2596 * the geometry shader sees triangles:
2598 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2600 * (Clearing the bit is even worse, because it fails to preserve
2603 * Triangle strips with adjacency always ordered in a way that preserves
2604 * triangle orientation but does not strictly follow the OpenGL spec,
2605 * regardless of the setting of this bit.
2607 * On Haswell, both triangle strips and triangle strips with adjacency
2608 * are always ordered in a way that preserves triangle orientation.
2609 * Setting this bit causes the ordering to strictly follow the OpenGL
2612 * So in either case we want to set the bit. Unfortunately on Ivy
2613 * Bridge this will get the order close to correct but not perfect.
2615 gs
.ReorderMode
= TRAILING
;
2616 gs
.MaximumNumberofThreads
=
2617 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2618 : (devinfo
->max_gs_threads
- 1);
2621 gs
.SOStatisticsEnable
= true;
2622 if (gs_prog
->info
.has_transform_feedback_varyings
)
2623 gs
.SVBIPayloadEnable
= true;
2625 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2626 * was previously done for gen6.
2628 * TODO: test with both disabled to see if the HW is behaving
2629 * as expected, like in gen7.
2631 gs
.SingleProgramFlow
= true;
2632 gs
.VectorMaskEnable
= true;
2636 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2638 if (gs_prog_data
->static_vertex_count
!= -1) {
2639 gs
.StaticOutput
= true;
2640 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2642 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2644 gs
.UserClipDistanceCullTestEnableBitmask
=
2645 vue_prog_data
->cull_distance_mask
;
2647 const int urb_entry_write_offset
= 1;
2648 const uint32_t urb_entry_output_length
=
2649 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2650 urb_entry_write_offset
;
2652 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2653 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2659 if (!active
&& brw
->ff_gs
.prog_active
) {
2660 /* In gen6, transform feedback for the VS stage is done with an
2661 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2664 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2665 gs
.SingleProgramFlow
= true;
2666 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2667 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2670 gs
.GRFRegisterCount
=
2671 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2672 /* BRW_NEW_URB_FENCE */
2673 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2674 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2675 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2676 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2679 gs
.VectorMaskEnable
= true;
2680 gs
.SVBIPayloadEnable
= true;
2681 gs
.SVBIPostIncrementEnable
= true;
2682 gs
.SVBIPostIncrementValue
=
2683 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2684 gs
.SOStatisticsEnable
= true;
2685 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2689 if (!active
&& !brw
->ff_gs
.prog_active
) {
2691 gs
.DispatchGRFStartRegisterForURBData
= 1;
2693 gs
.IncludeVertexHandles
= true;
2699 gs
.StatisticsEnable
= true;
2701 #if GEN_GEN == 5 || GEN_GEN == 6
2702 gs
.RenderingEnabled
= true;
2705 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2710 brw
->gs
.enabled
= active
;
2714 static const struct brw_tracked_state
genX(gs_state
) = {
2716 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2717 .brw
= BRW_NEW_BATCH
|
2719 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2720 BRW_NEW_PROGRAM_CACHE
|
2722 BRW_NEW_VIEWPORT_COUNT
2724 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2725 BRW_NEW_GEOMETRY_PROGRAM
|
2726 BRW_NEW_GS_PROG_DATA
2728 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2730 .emit
= genX(upload_gs_state
),
2733 /* ---------------------------------------------------------------------- */
2735 UNUSED
static GLenum
2736 fix_dual_blend_alpha_to_one(GLenum function
)
2742 case GL_ONE_MINUS_SRC1_ALPHA
:
2749 #define blend_factor(x) brw_translate_blend_factor(x)
2750 #define blend_eqn(x) brw_translate_blend_equation(x)
2753 * Modify blend function to force destination alpha to 1.0
2755 * If \c function specifies a blend function that uses destination alpha,
2756 * replace it with a function that hard-wires destination alpha to 1.0. This
2757 * is used when rendering to xRGB targets.
2760 brw_fix_xRGB_alpha(GLenum function
)
2766 case GL_ONE_MINUS_DST_ALPHA
:
2767 case GL_SRC_ALPHA_SATURATE
:
2775 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2777 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2781 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2784 struct gl_context
*ctx
= &brw
->ctx
;
2787 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2789 bool independent_alpha_blend
= false;
2791 /* Used for implementing the following bit of GL_EXT_texture_integer:
2792 * "Per-fragment operations that require floating-point color
2793 * components, including multisample alpha operations, alpha test,
2794 * blending, and dithering, have no effect when the corresponding
2795 * colors are written to an integer color buffer."
2797 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2799 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2800 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2803 if (ctx
->Color
.ColorLogicOpEnabled
) {
2804 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2805 : GL_UNSIGNED_NORMALIZED
;
2806 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2807 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2808 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2810 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2811 _mesa_enum_to_string(rb_type
));
2812 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2813 entry
->LogicOpEnable
= true;
2814 entry
->LogicOpFunction
=
2815 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2817 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2818 && (GEN_GEN
<= 5 || !integer
)) {
2819 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2820 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2821 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2822 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2823 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2824 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2826 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2827 srcRGB
= dstRGB
= GL_ONE
;
2829 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2830 srcA
= dstA
= GL_ONE
;
2832 /* Due to hardware limitations, the destination may have information
2833 * in an alpha channel even when the format specifies no alpha
2834 * channel. In order to avoid getting any incorrect blending due to
2835 * that alpha channel, coerce the blend factors to values that will
2836 * not read the alpha channel, but will instead use the correct
2837 * implicit value for alpha.
2839 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2840 GL_TEXTURE_ALPHA_TYPE
)) {
2841 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2842 srcA
= brw_fix_xRGB_alpha(srcA
);
2843 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2844 dstA
= brw_fix_xRGB_alpha(dstA
);
2847 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2848 * "If Dual Source Blending is enabled, this bit must be disabled."
2850 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2851 * and leave it enabled anyway.
2853 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2854 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2855 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2856 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2857 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2860 entry
->ColorBufferBlendEnable
= true;
2861 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2862 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2863 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2864 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2865 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2866 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2868 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2869 independent_alpha_blend
= true;
2872 return independent_alpha_blend
;
2877 genX(upload_blend_state
)(struct brw_context
*brw
)
2879 struct gl_context
*ctx
= &brw
->ctx
;
2882 /* We need at least one BLEND_STATE written, because we might do
2883 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2884 * for computed depth or alpha test), which will do an FB write
2885 * with render target 0, which will reference BLEND_STATE[0] for
2886 * alpha test enable.
2888 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2889 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2890 nr_draw_buffers
= 1;
2892 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2894 size
+= GENX(BLEND_STATE_length
) * 4;
2897 uint32_t *blend_map
;
2898 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2901 struct GENX(BLEND_STATE
) blend
= { 0 };
2904 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2905 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2908 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2909 * "If drawbuffer zero is not NONE and the buffer it references has an
2910 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2911 * operations are skipped."
2913 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2914 /* _NEW_MULTISAMPLE */
2915 if (_mesa_is_multisample_enabled(ctx
)) {
2916 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2917 blend
.AlphaToCoverageEnable
= true;
2918 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2920 if (ctx
->Multisample
.SampleAlphaToOne
)
2921 blend
.AlphaToOneEnable
= true;
2925 if (ctx
->Color
.AlphaEnabled
) {
2926 blend
.AlphaTestEnable
= true;
2927 blend
.AlphaTestFunction
=
2928 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2931 if (ctx
->Color
.DitherFlag
) {
2932 blend
.ColorDitherEnable
= true;
2937 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2938 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2942 blend
.IndependentAlphaBlendEnable
=
2943 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
2944 blend
.IndependentAlphaBlendEnable
;
2946 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2947 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2949 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2950 * clamping in the fragment shader. For its clamping of
2951 * blending, the spec says:
2953 * "RESOLVED: For fixed-point color buffers, the inputs and
2954 * the result of the blending equation are clamped. For
2955 * floating-point color buffers, no clamping occurs."
2957 * So, generally, we want clamping to the render target's range.
2958 * And, good news, the hardware tables for both pre- and
2959 * post-blend color clamping are either ignored, or any are
2960 * allowed, or clamping is required but RT range clamping is a
2963 entry
.PreBlendColorClampEnable
= true;
2964 entry
.PostBlendColorClampEnable
= true;
2965 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2967 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2968 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2969 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2970 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2973 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2975 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2981 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2985 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2986 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2987 ptr
.BLEND_STATEChange
= true;
2990 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2991 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2993 ptr
.BlendStatePointerValid
= true;
2999 static const struct brw_tracked_state
genX(blend_state
) = {
3001 .mesa
= _NEW_BUFFERS
|
3004 .brw
= BRW_NEW_BATCH
|
3006 BRW_NEW_STATE_BASE_ADDRESS
,
3008 .emit
= genX(upload_blend_state
),
3012 /* ---------------------------------------------------------------------- */
3015 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3016 [MESA_SHADER_VERTEX
] = 21,
3017 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3018 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3019 [MESA_SHADER_GEOMETRY
] = 22,
3020 [MESA_SHADER_FRAGMENT
] = 23,
3021 [MESA_SHADER_COMPUTE
] = 0,
3025 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3027 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3028 struct gl_context
*ctx
= &brw
->ctx
;
3030 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3032 struct brw_stage_state
*stage_states
[] = {
3040 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3041 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3042 gen7_emit_vs_workaround_flush(brw
);
3044 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3045 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3046 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3048 if (!stage_state
->push_constants_dirty
)
3051 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3052 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3053 if (stage_state
->prog_data
) {
3054 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3055 /* The Skylake PRM contains the following restriction:
3057 * "The driver must ensure The following case does not occur
3058 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3059 * buffer 3 read length equal to zero committed followed by a
3060 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3063 * To avoid this, we program the buffers in the highest slots.
3064 * This way, slot 0 is only used if slot 3 is also used.
3068 for (int i
= 3; i
>= 0; i
--) {
3069 const struct brw_ubo_range
*range
=
3070 &stage_state
->prog_data
->ubo_ranges
[i
];
3072 if (range
->length
== 0)
3075 const struct gl_uniform_block
*block
=
3076 prog
->sh
.UniformBlocks
[range
->block
];
3077 const struct gl_buffer_binding
*binding
=
3078 &ctx
->UniformBufferBindings
[block
->Binding
];
3080 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3081 static unsigned msg_id
= 0;
3082 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3083 MESA_DEBUG_TYPE_UNDEFINED
,
3084 MESA_DEBUG_SEVERITY_HIGH
,
3085 "UBO %d unbound, %s shader uniform data "
3086 "will be undefined.",
3088 _mesa_shader_stage_to_string(stage
));
3092 assert(binding
->Offset
% 32 == 0);
3094 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3095 intel_buffer_object(binding
->BufferObject
),
3096 binding
->Offset
, range
->length
* 32, false);
3098 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3099 pkt
.ConstantBody
.Buffer
[n
] =
3100 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3104 if (stage_state
->push_const_size
> 0) {
3106 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3107 pkt
.ConstantBody
.Buffer
[n
] =
3108 ro_bo(stage_state
->push_const_bo
,
3109 stage_state
->push_const_offset
);
3112 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3113 pkt
.ConstantBody
.Buffer
[0].offset
=
3114 stage_state
->push_const_offset
| mocs
;
3119 stage_state
->push_constants_dirty
= false;
3122 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3125 const struct brw_tracked_state
genX(push_constant_packets
) = {
3128 .brw
= BRW_NEW_DRAW_CALL
,
3130 .emit
= genX(upload_push_constant_packets
),
3136 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3138 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3140 /* BRW_NEW_VERTEX_PROGRAM */
3141 const struct brw_program
*vp
=
3142 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
3143 /* BRW_NEW_VS_PROG_DATA */
3144 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3146 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
3147 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
3150 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3152 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3154 .brw
= BRW_NEW_BATCH
|
3156 BRW_NEW_VERTEX_PROGRAM
|
3157 BRW_NEW_VS_PROG_DATA
,
3159 .emit
= genX(upload_vs_push_constants
),
3163 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3165 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3167 /* BRW_NEW_GEOMETRY_PROGRAM */
3168 const struct brw_program
*gp
=
3169 brw_program_const(brw
->programs
[MESA_SHADER_GEOMETRY
]);
3172 /* BRW_NEW_GS_PROG_DATA */
3173 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3175 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
3176 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
3180 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3182 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3184 .brw
= BRW_NEW_BATCH
|
3186 BRW_NEW_GEOMETRY_PROGRAM
|
3187 BRW_NEW_GS_PROG_DATA
,
3189 .emit
= genX(upload_gs_push_constants
),
3193 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3195 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3196 /* BRW_NEW_FRAGMENT_PROGRAM */
3197 const struct brw_program
*fp
=
3198 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
3199 /* BRW_NEW_FS_PROG_DATA */
3200 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3202 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
3204 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
3207 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3209 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3210 .brw
= BRW_NEW_BATCH
|
3212 BRW_NEW_FRAGMENT_PROGRAM
|
3213 BRW_NEW_FS_PROG_DATA
,
3215 .emit
= genX(upload_wm_push_constants
),
3219 /* ---------------------------------------------------------------------- */
3223 genX(determine_sample_mask
)(struct brw_context
*brw
)
3225 struct gl_context
*ctx
= &brw
->ctx
;
3226 float coverage
= 1.0f
;
3227 float coverage_invert
= false;
3228 unsigned sample_mask
= ~0u;
3230 /* BRW_NEW_NUM_SAMPLES */
3231 unsigned num_samples
= brw
->num_samples
;
3233 if (_mesa_is_multisample_enabled(ctx
)) {
3234 if (ctx
->Multisample
.SampleCoverage
) {
3235 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3236 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3238 if (ctx
->Multisample
.SampleMask
) {
3239 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3243 if (num_samples
> 1) {
3244 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3245 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3246 if (coverage_invert
)
3247 coverage_bits
^= (1 << num_samples
) - 1;
3248 return coverage_bits
& sample_mask
;
3255 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3256 unsigned num_samples
)
3258 unsigned log2_samples
= ffs(num_samples
) - 1;
3260 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3261 multi
.PixelLocation
= CENTER
;
3262 multi
.NumberofMultisamples
= log2_samples
;
3264 GEN_SAMPLE_POS_4X(multi
.Sample
);
3266 switch (num_samples
) {
3268 GEN_SAMPLE_POS_1X(multi
.Sample
);
3271 GEN_SAMPLE_POS_2X(multi
.Sample
);
3274 GEN_SAMPLE_POS_4X(multi
.Sample
);
3277 GEN_SAMPLE_POS_8X(multi
.Sample
);
3287 genX(upload_multisample_state
)(struct brw_context
*brw
)
3289 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3291 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3293 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3294 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3298 static const struct brw_tracked_state
genX(multisample_state
) = {
3300 .mesa
= _NEW_MULTISAMPLE
,
3301 .brw
= BRW_NEW_BLORP
|
3303 BRW_NEW_NUM_SAMPLES
,
3305 .emit
= genX(upload_multisample_state
)
3309 /* ---------------------------------------------------------------------- */
3312 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3314 struct gl_context
*ctx
= &brw
->ctx
;
3316 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3318 cc
.IndependentAlphaBlendEnable
=
3319 set_blend_entry_bits(brw
, &cc
, 0, false);
3320 set_depth_stencil_bits(brw
, &cc
);
3322 if (ctx
->Color
.AlphaEnabled
&&
3323 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3324 cc
.AlphaTestEnable
= true;
3325 cc
.AlphaTestFunction
=
3326 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3329 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3331 cc
.StatisticsEnable
= brw
->stats_wm
;
3333 cc
.CCViewportStatePointer
=
3334 ro_bo(brw
->batch
.state_bo
, brw
->cc
.vp_offset
);
3337 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3338 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3339 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3340 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3344 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3345 cc
.BackfaceStencilReferenceValue
=
3346 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3352 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3353 ctx
->Color
.AlphaRef
);
3357 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3358 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3360 ptr
.ColorCalcStatePointerValid
= true;
3364 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3368 static const struct brw_tracked_state
genX(color_calc_state
) = {
3370 .mesa
= _NEW_COLOR
|
3372 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3375 .brw
= BRW_NEW_BATCH
|
3377 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3379 : BRW_NEW_CC_STATE
|
3380 BRW_NEW_STATE_BASE_ADDRESS
),
3382 .emit
= genX(upload_color_calc_state
),
3386 /* ---------------------------------------------------------------------- */
3390 genX(upload_sbe
)(struct brw_context
*brw
)
3392 struct gl_context
*ctx
= &brw
->ctx
;
3393 /* BRW_NEW_FRAGMENT_PROGRAM */
3394 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3395 /* BRW_NEW_FS_PROG_DATA */
3396 const struct brw_wm_prog_data
*wm_prog_data
=
3397 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3399 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3401 #define attr_overrides sbe.Attribute
3403 uint32_t urb_entry_read_length
;
3404 uint32_t urb_entry_read_offset
;
3405 uint32_t point_sprite_enables
;
3407 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3408 sbe
.AttributeSwizzleEnable
= true;
3409 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3412 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3416 * Window coordinates in an FBO are inverted, which means point
3417 * sprite origin must be inverted.
3419 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3420 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3422 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3424 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3425 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3426 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3427 * BRW_NEW_VUE_MAP_GEOM_OUT
3429 genX(calculate_attr_overrides
)(brw
,
3431 &point_sprite_enables
,
3432 &urb_entry_read_length
,
3433 &urb_entry_read_offset
);
3435 /* Typically, the URB entry read length and offset should be programmed
3436 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3437 * stage which produces geometry. However, we don't know the proper
3438 * value until we call calculate_attr_overrides().
3440 * To fit with our existing code, we override the inherited values and
3441 * specify it here directly, as we did on previous generations.
3443 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3444 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3445 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3446 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3449 sbe
.ForceVertexURBEntryReadLength
= true;
3450 sbe
.ForceVertexURBEntryReadOffset
= true;
3454 /* prepare the active component dwords */
3455 int input_index
= 0;
3456 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
3457 if (!(fp
->info
.inputs_read
& BITFIELD64_BIT(attr
)))
3460 assert(input_index
< 32);
3462 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3469 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3470 for (int i
= 0; i
< 16; i
++)
3471 sbes
.Attribute
[i
] = attr_overrides
[i
];
3475 #undef attr_overrides
3478 static const struct brw_tracked_state
genX(sbe_state
) = {
3480 .mesa
= _NEW_BUFFERS
|
3485 .brw
= BRW_NEW_BLORP
|
3487 BRW_NEW_FRAGMENT_PROGRAM
|
3488 BRW_NEW_FS_PROG_DATA
|
3489 BRW_NEW_GS_PROG_DATA
|
3490 BRW_NEW_TES_PROG_DATA
|
3491 BRW_NEW_VUE_MAP_GEOM_OUT
|
3492 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3495 .emit
= genX(upload_sbe
),
3499 /* ---------------------------------------------------------------------- */
3503 * Outputs the 3DSTATE_SO_DECL_LIST command.
3505 * The data output is a series of 64-bit entries containing a SO_DECL per
3506 * stream. We only have one stream of rendering coming out of the GS unit, so
3507 * we only emit stream 0 (low 16 bits) SO_DECLs.
3510 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3511 const struct brw_vue_map
*vue_map
)
3513 struct gl_context
*ctx
= &brw
->ctx
;
3514 /* BRW_NEW_TRANSFORM_FEEDBACK */
3515 struct gl_transform_feedback_object
*xfb_obj
=
3516 ctx
->TransformFeedback
.CurrentObject
;
3517 const struct gl_transform_feedback_info
*linked_xfb_info
=
3518 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3519 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3520 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3521 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3522 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3524 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3526 memset(so_decl
, 0, sizeof(so_decl
));
3528 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3529 * command feels strange -- each dword pair contains a SO_DECL per stream.
3531 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3532 const struct gl_transform_feedback_output
*output
=
3533 &linked_xfb_info
->Outputs
[i
];
3534 const int buffer
= output
->OutputBuffer
;
3535 const int varying
= output
->OutputRegister
;
3536 const unsigned stream_id
= output
->StreamId
;
3537 assert(stream_id
< MAX_VERTEX_STREAMS
);
3539 buffer_mask
[stream_id
] |= 1 << buffer
;
3541 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3543 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3544 * array. Instead, it simply increments DstOffset for the following
3545 * input by the number of components that should be skipped.
3547 * Our hardware is unusual in that it requires us to program SO_DECLs
3548 * for fake "hole" components, rather than simply taking the offset
3549 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3550 * program as many size = 4 holes as we can, then a final hole to
3551 * accommodate the final 1, 2, or 3 remaining.
3553 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3555 while (skip_components
> 0) {
3556 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3558 .OutputBufferSlot
= output
->OutputBuffer
,
3559 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3561 skip_components
-= 4;
3564 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3566 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3567 .OutputBufferSlot
= output
->OutputBuffer
,
3568 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3570 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3573 if (decls
[stream_id
] > max_decls
)
3574 max_decls
= decls
[stream_id
];
3578 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3579 .StreamtoBufferSelects0
= buffer_mask
[0],
3580 .StreamtoBufferSelects1
= buffer_mask
[1],
3581 .StreamtoBufferSelects2
= buffer_mask
[2],
3582 .StreamtoBufferSelects3
= buffer_mask
[3],
3583 .NumEntries0
= decls
[0],
3584 .NumEntries1
= decls
[1],
3585 .NumEntries2
= decls
[2],
3586 .NumEntries3
= decls
[3]);
3588 for (int i
= 0; i
< max_decls
; i
++) {
3589 GENX(SO_DECL_ENTRY_pack
)(
3590 brw
, dw
+ 2 + i
* 2,
3591 &(struct GENX(SO_DECL_ENTRY
)) {
3592 .Stream0Decl
= so_decl
[0][i
],
3593 .Stream1Decl
= so_decl
[1][i
],
3594 .Stream2Decl
= so_decl
[2][i
],
3595 .Stream3Decl
= so_decl
[3][i
],
3601 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3603 struct gl_context
*ctx
= &brw
->ctx
;
3604 /* BRW_NEW_TRANSFORM_FEEDBACK */
3605 struct gl_transform_feedback_object
*xfb_obj
=
3606 ctx
->TransformFeedback
.CurrentObject
;
3608 const struct gl_transform_feedback_info
*linked_xfb_info
=
3609 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3611 struct brw_transform_feedback_object
*brw_obj
=
3612 (struct brw_transform_feedback_object
*) xfb_obj
;
3613 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3616 /* Set up the up to 4 output buffers. These are the ranges defined in the
3617 * gl_transform_feedback_object.
3619 for (int i
= 0; i
< 4; i
++) {
3620 struct intel_buffer_object
*bufferobj
=
3621 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3624 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3625 sob
.SOBufferIndex
= i
;
3630 uint32_t start
= xfb_obj
->Offset
[i
];
3631 assert(start
% 4 == 0);
3632 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3634 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3635 assert(end
<= bo
->size
);
3637 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3638 sob
.SOBufferIndex
= i
;
3640 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3642 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3643 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3645 sob
.SOBufferEnable
= true;
3646 sob
.StreamOffsetWriteEnable
= true;
3647 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3648 sob
.SOBufferMOCS
= mocs_wb
;
3650 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3651 sob
.StreamOutputBufferOffsetAddress
=
3652 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3654 if (brw_obj
->zero_offsets
) {
3655 /* Zero out the offset and write that to offset_bo */
3656 sob
.StreamOffset
= 0;
3658 /* Use offset_bo as the "Stream Offset." */
3659 sob
.StreamOffset
= 0xFFFFFFFF;
3666 brw_obj
->zero_offsets
= false;
3671 query_active(struct gl_query_object
*q
)
3673 return q
&& q
->Active
;
3677 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3678 const struct brw_vue_map
*vue_map
)
3680 struct gl_context
*ctx
= &brw
->ctx
;
3681 /* BRW_NEW_TRANSFORM_FEEDBACK */
3682 struct gl_transform_feedback_object
*xfb_obj
=
3683 ctx
->TransformFeedback
.CurrentObject
;
3685 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3687 int urb_entry_read_offset
= 0;
3688 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3689 urb_entry_read_offset
;
3691 sos
.SOFunctionEnable
= true;
3692 sos
.SOStatisticsEnable
= true;
3694 /* BRW_NEW_RASTERIZER_DISCARD */
3695 if (ctx
->RasterDiscard
) {
3696 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3697 sos
.RenderingDisable
= true;
3699 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3700 "query active relies on the clipper.\n");
3705 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3706 sos
.ReorderMode
= TRAILING
;
3709 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3710 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3711 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3712 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3714 const struct gl_transform_feedback_info
*linked_xfb_info
=
3715 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3716 /* Set buffer pitches; 0 means unbound. */
3717 if (xfb_obj
->Buffers
[0])
3718 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3719 if (xfb_obj
->Buffers
[1])
3720 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3721 if (xfb_obj
->Buffers
[2])
3722 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3723 if (xfb_obj
->Buffers
[3])
3724 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3727 /* We always read the whole vertex. This could be reduced at some
3728 * point by reading less and offsetting the register index in the
3731 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3732 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3733 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3734 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3735 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3736 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3737 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3738 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3744 genX(upload_sol
)(struct brw_context
*brw
)
3746 struct gl_context
*ctx
= &brw
->ctx
;
3747 /* BRW_NEW_TRANSFORM_FEEDBACK */
3748 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3751 genX(upload_3dstate_so_buffers
)(brw
);
3753 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3754 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3757 /* Finally, set up the SOL stage. This command must always follow updates to
3758 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3759 * MMIO register updates (current performed by the kernel at each batch
3762 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3765 static const struct brw_tracked_state
genX(sol_state
) = {
3768 .brw
= BRW_NEW_BATCH
|
3770 BRW_NEW_RASTERIZER_DISCARD
|
3771 BRW_NEW_VUE_MAP_GEOM_OUT
|
3772 BRW_NEW_TRANSFORM_FEEDBACK
,
3774 .emit
= genX(upload_sol
),
3778 /* ---------------------------------------------------------------------- */
3782 genX(upload_ps
)(struct brw_context
*brw
)
3784 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3785 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3787 /* BRW_NEW_FS_PROG_DATA */
3788 const struct brw_wm_prog_data
*prog_data
=
3789 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3790 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3795 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3796 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3797 * incorrect for subspans where some of the pixels are unlit. We believe
3798 * the bit just didn't take effect in previous generations.
3800 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3803 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3805 /* BRW_NEW_FS_PROG_DATA */
3806 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3808 if (prog_data
->base
.use_alt_mode
)
3809 ps
.FloatingPointMode
= Alternate
;
3811 /* Haswell requires the sample mask to be set in this packet as well as
3812 * in 3DSTATE_SAMPLE_MASK; the values should match.
3815 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3817 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3820 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3821 * it implicitly scales for different GT levels (which have some # of
3824 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3827 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3829 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3831 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3834 if (prog_data
->base
.nr_params
> 0 ||
3835 prog_data
->base
.ubo_ranges
[0].length
> 0)
3836 ps
.PushConstantEnable
= true;
3839 /* From the IVB PRM, volume 2 part 1, page 287:
3840 * "This bit is inserted in the PS payload header and made available to
3841 * the DataPort (either via the message header or via header bypass) to
3842 * indicate that oMask data (one or two phases) is included in Render
3843 * Target Write messages. If present, the oMask data is used to mask off
3846 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3848 /* The hardware wedges if you have this bit set but don't turn on any
3849 * dual source blend factors.
3851 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3853 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3854 (ctx
->Color
.BlendEnabled
& 1) &&
3855 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3857 /* BRW_NEW_FS_PROG_DATA */
3858 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3861 /* From the documentation for this packet:
3862 * "If the PS kernel does not need the Position XY Offsets to
3863 * compute a Position Value, then this field should be programmed
3864 * to POSOFFSET_NONE."
3866 * "SW Recommendation: If the PS kernel needs the Position Offsets
3867 * to compute a Position XY value, this field should match Position
3868 * ZW Interpolation Mode to ensure a consistent position.xyzw
3871 * We only require XY sample offsets. So, this recommendation doesn't
3872 * look useful at the moment. We might need this in future.
3874 if (prog_data
->uses_pos_offset
)
3875 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3877 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3879 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3880 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3881 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3882 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3883 prog_data
->base
.dispatch_grf_start_reg
;
3884 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3885 prog_data
->dispatch_grf_start_reg_2
;
3887 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3888 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3889 prog_data
->prog_offset_2
;
3891 if (prog_data
->base
.total_scratch
) {
3892 ps
.ScratchSpaceBasePointer
=
3893 rw_bo(stage_state
->scratch_bo
,
3894 ffs(stage_state
->per_thread_scratch
) - 11);
3899 static const struct brw_tracked_state
genX(ps_state
) = {
3901 .mesa
= _NEW_MULTISAMPLE
|
3902 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3905 .brw
= BRW_NEW_BATCH
|
3907 BRW_NEW_FS_PROG_DATA
,
3909 .emit
= genX(upload_ps
),
3913 /* ---------------------------------------------------------------------- */
3917 genX(upload_hs_state
)(struct brw_context
*brw
)
3919 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3920 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3921 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3922 const struct brw_vue_prog_data
*vue_prog_data
=
3923 brw_vue_prog_data(stage_prog_data
);
3925 /* BRW_NEW_TES_PROG_DATA */
3926 struct brw_tcs_prog_data
*tcs_prog_data
=
3927 brw_tcs_prog_data(stage_prog_data
);
3929 if (!tcs_prog_data
) {
3930 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3932 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3933 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3935 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3936 hs
.IncludeVertexHandles
= true;
3938 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3943 static const struct brw_tracked_state
genX(hs_state
) = {
3946 .brw
= BRW_NEW_BATCH
|
3948 BRW_NEW_TCS_PROG_DATA
|
3949 BRW_NEW_TESS_PROGRAMS
,
3951 .emit
= genX(upload_hs_state
),
3955 genX(upload_ds_state
)(struct brw_context
*brw
)
3957 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3958 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3959 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3961 /* BRW_NEW_TES_PROG_DATA */
3962 const struct brw_tes_prog_data
*tes_prog_data
=
3963 brw_tes_prog_data(stage_prog_data
);
3964 const struct brw_vue_prog_data
*vue_prog_data
=
3965 brw_vue_prog_data(stage_prog_data
);
3967 if (!tes_prog_data
) {
3968 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3970 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3971 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3973 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3974 ds
.ComputeWCoordinateEnable
=
3975 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3978 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3979 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3980 ds
.UserClipDistanceCullTestEnableBitmask
=
3981 vue_prog_data
->cull_distance_mask
;
3987 static const struct brw_tracked_state
genX(ds_state
) = {
3990 .brw
= BRW_NEW_BATCH
|
3992 BRW_NEW_TESS_PROGRAMS
|
3993 BRW_NEW_TES_PROG_DATA
,
3995 .emit
= genX(upload_ds_state
),
3998 /* ---------------------------------------------------------------------- */
4001 upload_te_state(struct brw_context
*brw
)
4003 /* BRW_NEW_TESS_PROGRAMS */
4004 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4006 /* BRW_NEW_TES_PROG_DATA */
4007 const struct brw_tes_prog_data
*tes_prog_data
=
4008 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4011 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4012 te
.Partitioning
= tes_prog_data
->partitioning
;
4013 te
.OutputTopology
= tes_prog_data
->output_topology
;
4014 te
.TEDomain
= tes_prog_data
->domain
;
4016 te
.MaximumTessellationFactorOdd
= 63.0;
4017 te
.MaximumTessellationFactorNotOdd
= 64.0;
4020 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4024 static const struct brw_tracked_state
genX(te_state
) = {
4027 .brw
= BRW_NEW_BLORP
|
4029 BRW_NEW_TES_PROG_DATA
|
4030 BRW_NEW_TESS_PROGRAMS
,
4032 .emit
= upload_te_state
,
4035 /* ---------------------------------------------------------------------- */
4038 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4040 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4041 /* BRW_NEW_TESS_PROGRAMS */
4042 const struct brw_program
*tep
=
4043 brw_program_const(brw
->programs
[MESA_SHADER_TESS_EVAL
]);
4046 /* BRW_NEW_TES_PROG_DATA */
4047 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4048 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
4049 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
4053 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4055 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4056 .brw
= BRW_NEW_BATCH
|
4058 BRW_NEW_TESS_PROGRAMS
|
4059 BRW_NEW_TES_PROG_DATA
,
4061 .emit
= genX(upload_tes_push_constants
),
4065 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4067 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4068 /* BRW_NEW_TESS_PROGRAMS */
4069 const struct brw_program
*tcp
=
4070 brw_program_const(brw
->programs
[MESA_SHADER_TESS_CTRL
]);
4071 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4074 /* BRW_NEW_TCS_PROG_DATA */
4075 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4077 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
4078 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
4082 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4084 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4085 .brw
= BRW_NEW_BATCH
|
4087 BRW_NEW_DEFAULT_TESS_LEVELS
|
4088 BRW_NEW_TESS_PROGRAMS
|
4089 BRW_NEW_TCS_PROG_DATA
,
4091 .emit
= genX(upload_tcs_push_constants
),
4096 /* ---------------------------------------------------------------------- */
4100 genX(upload_cs_state
)(struct brw_context
*brw
)
4102 if (!brw
->cs
.base
.prog_data
)
4106 uint32_t *desc
= (uint32_t*) brw_state_batch(
4107 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4110 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4111 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4112 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4113 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4115 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4116 brw_emit_buffer_surface_state(
4117 brw
, &stage_state
->surf_offset
[
4118 prog_data
->binding_table
.shader_time_start
],
4119 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4120 brw
->shader_time
.bo
->size
, 1,
4124 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4125 32, &stage_state
->bind_bo_offset
);
4127 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4128 if (prog_data
->total_scratch
) {
4132 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4133 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4135 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 11;
4136 } else if (GEN_IS_HASWELL
) {
4137 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4138 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4140 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 12;
4142 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4143 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4145 bo_offset
= stage_state
->per_thread_scratch
/ 1024 - 1;
4147 vfe
.ScratchSpaceBasePointer
=
4148 rw_bo(stage_state
->scratch_bo
, bo_offset
);
4151 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4152 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4153 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4154 vfe
.ResetGatewayTimer
=
4155 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4157 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4163 /* We are uploading duplicated copies of push constant uniforms for each
4164 * thread. Although the local id data needs to vary per thread, it won't
4165 * change for other uniform data. Unfortunately this duplication is
4166 * required for gen7. As of Haswell, this duplication can be avoided,
4167 * but this older mechanism with duplicated data continues to work.
4169 * FINISHME: As of Haswell, we could make use of the
4170 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4171 * field to only store one copy of uniform data.
4173 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4174 * which is described in the GPGPU_WALKER command and in the Broadwell
4175 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4176 * Operations => GPGPU Mode => Indirect Payload Storage.
4178 * Note: The constant data is built in brw_upload_cs_push_constants
4181 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4183 const uint32_t vfe_curbe_allocation
=
4184 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4185 cs_prog_data
->push
.cross_thread
.regs
, 2);
4186 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4189 if (cs_prog_data
->push
.total
.size
> 0) {
4190 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4191 curbe
.CURBETotalDataLength
=
4192 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4193 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4197 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4198 memcpy(bind
, stage_state
->surf_offset
,
4199 prog_data
->binding_table
.size_bytes
);
4200 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4201 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4202 .SamplerStatePointer
= stage_state
->sampler_offset
,
4203 .SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4) >> 2,
4204 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4205 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4206 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4207 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4208 prog_data
->total_shared
),
4209 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4210 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4211 .CrossThreadConstantDataReadLength
=
4212 cs_prog_data
->push
.cross_thread
.regs
,
4216 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4218 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4219 load
.InterfaceDescriptorTotalLength
=
4220 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4221 load
.InterfaceDescriptorDataStartAddress
= offset
;
4225 static const struct brw_tracked_state
genX(cs_state
) = {
4227 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4228 .brw
= BRW_NEW_BATCH
|
4230 BRW_NEW_CS_PROG_DATA
|
4231 BRW_NEW_SAMPLER_STATE_TABLE
|
4234 .emit
= genX(upload_cs_state
)
4239 /* ---------------------------------------------------------------------- */
4243 genX(upload_raster
)(struct brw_context
*brw
)
4245 struct gl_context
*ctx
= &brw
->ctx
;
4248 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4251 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4254 struct gl_point_attrib
*point
= &ctx
->Point
;
4256 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4257 if (brw
->polygon_front_bit
== render_to_fbo
)
4258 raster
.FrontWinding
= CounterClockwise
;
4260 if (polygon
->CullFlag
) {
4261 switch (polygon
->CullFaceMode
) {
4263 raster
.CullMode
= CULLMODE_FRONT
;
4266 raster
.CullMode
= CULLMODE_BACK
;
4268 case GL_FRONT_AND_BACK
:
4269 raster
.CullMode
= CULLMODE_BOTH
;
4272 unreachable("not reached");
4275 raster
.CullMode
= CULLMODE_NONE
;
4278 point
->SmoothFlag
= raster
.SmoothPointEnable
;
4280 raster
.DXMultisampleRasterizationEnable
=
4281 _mesa_is_multisample_enabled(ctx
);
4283 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4284 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4285 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4287 switch (polygon
->FrontMode
) {
4289 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4292 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4295 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4298 unreachable("not reached");
4301 switch (polygon
->BackMode
) {
4303 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4306 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4309 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4312 unreachable("not reached");
4316 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4319 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4321 /* _NEW_TRANSFORM */
4322 if (!ctx
->Transform
.DepthClamp
) {
4324 raster
.ViewportZFarClipTestEnable
= true;
4325 raster
.ViewportZNearClipTestEnable
= true;
4327 raster
.ViewportZClipTestEnable
= true;
4331 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4333 raster
.ConservativeRasterizationEnable
=
4334 ctx
->IntelConservativeRasterization
;
4337 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4338 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4340 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4344 static const struct brw_tracked_state
genX(raster_state
) = {
4346 .mesa
= _NEW_BUFFERS
|
4353 .brw
= BRW_NEW_BLORP
|
4355 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4357 .emit
= genX(upload_raster
),
4361 /* ---------------------------------------------------------------------- */
4365 genX(upload_ps_extra
)(struct brw_context
*brw
)
4367 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4369 const struct brw_wm_prog_data
*prog_data
=
4370 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4372 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4373 psx
.PixelShaderValid
= true;
4374 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4375 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4376 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4377 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4378 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4379 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4381 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4382 if (prog_data
->uses_sample_mask
) {
4384 if (prog_data
->post_depth_coverage
)
4385 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4386 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4387 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4389 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4391 psx
.PixelShaderUsesInputCoverageMask
= true;
4395 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4397 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4398 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4401 /* The stricter cross-primitive coherency guarantees that the hardware
4402 * gives us with the "Accesses UAV" bit set for at least one shader stage
4403 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4404 * are redundant within the current image, atomic counter and SSBO GL
4405 * APIs, which all have very loose ordering and coherency requirements
4406 * and generally rely on the application to insert explicit barriers when
4407 * a shader invocation is expected to see the memory writes performed by
4408 * the invocations of some previous primitive. Regardless of the value
4409 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4410 * cause an in most cases useless DC flush when the lowermost stage with
4411 * the bit set finishes execution.
4413 * It would be nice to disable it, but in some cases we can't because on
4414 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4415 * signal (which could be set independently from the coherency mechanism
4416 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4417 * determine whether the hardware skips execution of the fragment shader
4418 * or not via the ThreadDispatchEnable signal. However if we know that
4419 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4420 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4421 * difference so we may just disable it here.
4423 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4424 * take into account KillPixels when no depth or stencil writes are
4425 * enabled. In order for occlusion queries to work correctly with no
4426 * attachments, we need to force-enable here.
4428 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4431 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4432 !brw_color_buffer_write_enabled(brw
))
4433 psx
.PixelShaderHasUAV
= true;
4437 const struct brw_tracked_state
genX(ps_extra
) = {
4439 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4440 .brw
= BRW_NEW_BLORP
|
4442 BRW_NEW_FRAGMENT_PROGRAM
|
4443 BRW_NEW_FS_PROG_DATA
|
4444 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4446 .emit
= genX(upload_ps_extra
),
4450 /* ---------------------------------------------------------------------- */
4454 genX(upload_ps_blend
)(struct brw_context
*brw
)
4456 struct gl_context
*ctx
= &brw
->ctx
;
4459 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4460 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4463 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4465 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4466 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4467 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4469 bool alpha_to_one
= false;
4471 if (!buffer0_is_integer
) {
4472 /* _NEW_MULTISAMPLE */
4474 if (_mesa_is_multisample_enabled(ctx
)) {
4475 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4476 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4479 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4482 /* Used for implementing the following bit of GL_EXT_texture_integer:
4483 * "Per-fragment operations that require floating-point color
4484 * components, including multisample alpha operations, alpha test,
4485 * blending, and dithering, have no effect when the corresponding
4486 * colors are written to an integer color buffer."
4488 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4489 * "If drawbuffer zero is not NONE and the buffer it references has an
4490 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4491 * operations are skipped."
4493 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4494 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4495 GLenum eqA
= color
->Blend
[0].EquationA
;
4496 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4497 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4498 GLenum srcA
= color
->Blend
[0].SrcA
;
4499 GLenum dstA
= color
->Blend
[0].DstA
;
4501 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4502 srcRGB
= dstRGB
= GL_ONE
;
4504 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4505 srcA
= dstA
= GL_ONE
;
4507 /* Due to hardware limitations, the destination may have information
4508 * in an alpha channel even when the format specifies no alpha
4509 * channel. In order to avoid getting any incorrect blending due to
4510 * that alpha channel, coerce the blend factors to values that will
4511 * not read the alpha channel, but will instead use the correct
4512 * implicit value for alpha.
4514 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4515 GL_TEXTURE_ALPHA_TYPE
)) {
4516 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4517 srcA
= brw_fix_xRGB_alpha(srcA
);
4518 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4519 dstA
= brw_fix_xRGB_alpha(dstA
);
4522 /* Alpha to One doesn't work with Dual Color Blending. Override
4523 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4525 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4526 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4527 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4528 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4529 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4532 pb
.ColorBufferBlendEnable
= true;
4533 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4534 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4535 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4536 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4538 pb
.IndependentAlphaBlendEnable
=
4539 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4544 static const struct brw_tracked_state
genX(ps_blend
) = {
4546 .mesa
= _NEW_BUFFERS
|
4549 .brw
= BRW_NEW_BLORP
|
4551 BRW_NEW_FRAGMENT_PROGRAM
,
4553 .emit
= genX(upload_ps_blend
)
4557 /* ---------------------------------------------------------------------- */
4561 genX(emit_vf_topology
)(struct brw_context
*brw
)
4563 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4564 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4568 static const struct brw_tracked_state
genX(vf_topology
) = {
4571 .brw
= BRW_NEW_BLORP
|
4574 .emit
= genX(emit_vf_topology
),
4578 /* ---------------------------------------------------------------------- */
4582 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4584 uint32_t offset_in_bytes
,
4587 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4588 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4589 mi_rpc
.ReportID
= report_id
;
4594 /* ---------------------------------------------------------------------- */
4597 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4600 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4601 struct brw_stage_state
*stage_state
)
4604 static const uint16_t packet_headers
[] = {
4605 [MESA_SHADER_VERTEX
] = 43,
4606 [MESA_SHADER_TESS_CTRL
] = 44,
4607 [MESA_SHADER_TESS_EVAL
] = 45,
4608 [MESA_SHADER_GEOMETRY
] = 46,
4609 [MESA_SHADER_FRAGMENT
] = 47,
4612 /* Ivybridge requires a workaround flush before VS packets. */
4613 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4614 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4615 gen7_emit_vs_workaround_flush(brw
);
4618 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4619 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4620 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4626 has_component(mesa_format format
, int i
)
4628 if (_mesa_is_format_color_format(format
))
4629 return _mesa_format_has_color_component(format
, i
);
4631 /* depth and stencil have only one component */
4636 * Upload SAMPLER_BORDER_COLOR_STATE.
4639 genX(upload_default_color
)(struct brw_context
*brw
,
4640 const struct gl_sampler_object
*sampler
,
4641 mesa_format format
, GLenum base_format
,
4642 bool is_integer_format
, bool is_stencil_sampling
,
4643 uint32_t *sdc_offset
)
4645 union gl_color_union color
;
4647 switch (base_format
) {
4648 case GL_DEPTH_COMPONENT
:
4649 /* GL specs that border color for depth textures is taken from the
4650 * R channel, while the hardware uses A. Spam R into all the
4651 * channels for safety.
4653 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4654 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4655 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4656 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4662 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4665 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4666 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4667 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4668 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4671 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4672 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4673 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4674 color
.ui
[3] = float_as_int(1.0);
4676 case GL_LUMINANCE_ALPHA
:
4677 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4678 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4679 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4680 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4683 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4684 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4685 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4686 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4690 /* In some cases we use an RGBA surface format for GL RGB textures,
4691 * where we've initialized the A channel to 1.0. We also have to set
4692 * the border color alpha to 1.0 in that case.
4694 if (base_format
== GL_RGB
)
4695 color
.ui
[3] = float_as_int(1.0);
4700 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4704 uint32_t *sdc
= brw_state_batch(
4705 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4706 alignment
, sdc_offset
);
4708 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4710 #define ASSIGN(dst, src) \
4715 #define ASSIGNu16(dst, src) \
4717 dst = (uint16_t)src; \
4720 #define ASSIGNu8(dst, src) \
4722 dst = (uint8_t)src; \
4725 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4726 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4727 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4728 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4729 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4732 /* On Broadwell, the border color is represented as four 32-bit floats,
4733 * integers, or unsigned values, interpreted according to the surface
4734 * format. This matches the sampler->BorderColor union exactly; just
4735 * memcpy the values.
4737 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4738 #elif GEN_IS_HASWELL
4739 if (is_integer_format
|| is_stencil_sampling
) {
4740 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4741 const int bits_per_channel
=
4742 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4744 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4745 * "If any color channel is missing from the surface format,
4746 * corresponding border color should be programmed as zero and if
4747 * alpha channel is missing, corresponding Alpha border color should
4748 * be programmed as 1."
4750 unsigned c
[4] = { 0, 0, 0, 1 };
4751 for (int i
= 0; i
< 4; i
++) {
4752 if (has_component(format
, i
))
4756 switch (bits_per_channel
) {
4758 /* Copy RGBA in order. */
4759 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4762 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4764 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4767 if (base_format
== GL_RG
) {
4768 /* Careful inspection of the tables reveals that for RG32 formats,
4769 * the green channel needs to go where blue normally belongs.
4771 state
.BorderColor32bitRed
= c
[0];
4772 state
.BorderColor32bitBlue
= c
[1];
4773 state
.BorderColor32bitAlpha
= 1;
4775 /* Copy RGBA in order. */
4776 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4780 assert(!"Invalid number of bits per channel in integer format.");
4784 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4786 #elif GEN_GEN == 5 || GEN_GEN == 6
4787 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4788 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4789 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4791 #define MESA_FLOAT_TO_HALF(dst, src) \
4792 dst = _mesa_float_to_half(src);
4794 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4796 #undef MESA_FLOAT_TO_HALF
4798 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4799 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4800 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4801 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4803 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4805 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4807 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4811 #undef BORDER_COLOR_ATTR
4813 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4817 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4824 /* GL_CLAMP is the weird mode where coordinates are clamped to
4825 * [0.0, 1.0], so linear filtering of coordinates outside of
4826 * [0.0, 1.0] give you half edge texel value and half border
4829 * Gen8+ supports this natively.
4831 return TCM_HALF_BORDER
;
4833 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4834 * and set clamp_border here, which gets the result desired.
4835 * We just use clamp(_to_edge) for nearest, because for nearest
4836 * clamping to 1.0 gives border color instead of the desired
4842 return TCM_CLAMP_BORDER
;
4844 case GL_CLAMP_TO_EDGE
:
4846 case GL_CLAMP_TO_BORDER
:
4847 return TCM_CLAMP_BORDER
;
4848 case GL_MIRRORED_REPEAT
:
4850 case GL_MIRROR_CLAMP_TO_EDGE
:
4851 return TCM_MIRROR_ONCE
;
4858 * Return true if the given wrap mode requires the border color to exist.
4861 wrap_mode_needs_border_color(unsigned wrap_mode
)
4864 return wrap_mode
== TCM_CLAMP_BORDER
||
4865 wrap_mode
== TCM_HALF_BORDER
;
4867 return wrap_mode
== TCM_CLAMP_BORDER
;
4872 * Sets the sampler state for a single unit based off of the sampler key
4876 genX(update_sampler_state
)(struct brw_context
*brw
,
4877 GLenum target
, bool tex_cube_map_seamless
,
4878 GLfloat tex_unit_lod_bias
,
4879 mesa_format format
, GLenum base_format
,
4880 const struct gl_texture_object
*texObj
,
4881 const struct gl_sampler_object
*sampler
,
4882 uint32_t *sampler_state
,
4883 uint32_t batch_offset_for_sampler_state
)
4885 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
4887 /* Select min and mip filters. */
4888 switch (sampler
->MinFilter
) {
4890 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4891 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4894 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4895 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4897 case GL_NEAREST_MIPMAP_NEAREST
:
4898 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4899 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4901 case GL_LINEAR_MIPMAP_NEAREST
:
4902 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4903 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4905 case GL_NEAREST_MIPMAP_LINEAR
:
4906 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4907 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4909 case GL_LINEAR_MIPMAP_LINEAR
:
4910 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4911 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4914 unreachable("not reached");
4917 /* Select mag filter. */
4918 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
4919 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
4921 /* Enable anisotropic filtering if desired. */
4922 samp_st
.MaximumAnisotropy
= RATIO21
;
4924 if (sampler
->MaxAnisotropy
> 1.0f
) {
4925 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
4926 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
4927 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
4928 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
4930 if (sampler
->MaxAnisotropy
> 2.0f
) {
4931 samp_st
.MaximumAnisotropy
=
4932 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
4936 /* Set address rounding bits if not using nearest filtering. */
4937 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
4938 samp_st
.UAddressMinFilterRoundingEnable
= true;
4939 samp_st
.VAddressMinFilterRoundingEnable
= true;
4940 samp_st
.RAddressMinFilterRoundingEnable
= true;
4943 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
4944 samp_st
.UAddressMagFilterRoundingEnable
= true;
4945 samp_st
.VAddressMagFilterRoundingEnable
= true;
4946 samp_st
.RAddressMagFilterRoundingEnable
= true;
4949 bool either_nearest
=
4950 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
4951 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
4952 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
4953 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
4955 if (target
== GL_TEXTURE_CUBE_MAP
||
4956 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
4957 /* Cube maps must use the same wrap mode for all three coordinate
4958 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
4960 * Ivybridge and Baytrail seem to have problems with CUBE mode and
4961 * integer formats. Fall back to CLAMP for now.
4963 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
4964 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
4973 } else if (target
== GL_TEXTURE_1D
) {
4974 /* There's a bug in 1D texture sampling - it actually pays
4975 * attention to the wrap_t value, though it should not.
4976 * Override the wrap_t value here to GL_REPEAT to keep
4977 * any nonexistent border pixels from floating in.
4982 samp_st
.TCXAddressControlMode
= wrap_s
;
4983 samp_st
.TCYAddressControlMode
= wrap_t
;
4984 samp_st
.TCZAddressControlMode
= wrap_r
;
4986 samp_st
.ShadowFunction
=
4987 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
4988 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
4991 /* Set shadow function. */
4992 samp_st
.AnisotropicAlgorithm
=
4993 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
4994 EWAApproximation
: LEGACY
;
4998 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5001 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5002 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5003 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5004 samp_st
.TextureLODBias
=
5005 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5008 samp_st
.BaseMipLevel
=
5009 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5010 samp_st
.MinandMagStateNotEqual
=
5011 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5014 /* Upload the border color if necessary. If not, just point it at
5015 * offset 0 (the start of the batch) - the color should be ignored,
5016 * but that address won't fault in case something reads it anyway.
5018 uint32_t border_color_offset
= 0;
5019 if (wrap_mode_needs_border_color(wrap_s
) ||
5020 wrap_mode_needs_border_color(wrap_t
) ||
5021 wrap_mode_needs_border_color(wrap_r
)) {
5022 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5023 texObj
->_IsIntegerFormat
,
5024 texObj
->StencilSampling
,
5025 &border_color_offset
);
5028 samp_st
.BorderColorPointer
=
5029 ro_bo(brw
->batch
.state_bo
, border_color_offset
);
5031 samp_st
.BorderColorPointer
= border_color_offset
;
5035 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5037 samp_st
.LODPreClampEnable
= true;
5040 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5044 update_sampler_state(struct brw_context
*brw
,
5046 uint32_t *sampler_state
,
5047 uint32_t batch_offset_for_sampler_state
)
5049 struct gl_context
*ctx
= &brw
->ctx
;
5050 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5051 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5052 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5054 /* These don't use samplers at all. */
5055 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5058 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5059 genX(update_sampler_state
)(brw
, texObj
->Target
,
5060 ctx
->Texture
.CubeMapSeamless
,
5062 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5064 sampler_state
, batch_offset_for_sampler_state
);
5068 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5069 struct gl_program
*prog
,
5070 struct brw_stage_state
*stage_state
)
5072 struct gl_context
*ctx
= &brw
->ctx
;
5073 uint32_t sampler_count
= stage_state
->sampler_count
;
5075 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5077 if (sampler_count
== 0)
5080 /* SAMPLER_STATE is 4 DWords on all platforms. */
5081 const int dwords
= GENX(SAMPLER_STATE_length
);
5082 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5084 uint32_t *sampler_state
= brw_state_batch(brw
,
5085 sampler_count
* size_in_bytes
,
5086 32, &stage_state
->sampler_offset
);
5087 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5089 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
5091 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5092 if (SamplersUsed
& (1 << s
)) {
5093 const unsigned unit
= prog
->SamplerUnits
[s
];
5094 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5095 update_sampler_state(brw
, unit
, sampler_state
,
5096 batch_offset_for_sampler_state
);
5100 sampler_state
+= dwords
;
5101 batch_offset_for_sampler_state
+= size_in_bytes
;
5104 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5105 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5106 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5108 /* Flag that the sampler state table pointer has changed; later atoms
5111 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5116 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5118 /* BRW_NEW_FRAGMENT_PROGRAM */
5119 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5120 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5123 static const struct brw_tracked_state
genX(fs_samplers
) = {
5125 .mesa
= _NEW_TEXTURE
,
5126 .brw
= BRW_NEW_BATCH
|
5128 BRW_NEW_FRAGMENT_PROGRAM
,
5130 .emit
= genX(upload_fs_samplers
),
5134 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5136 /* BRW_NEW_VERTEX_PROGRAM */
5137 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5138 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5141 static const struct brw_tracked_state
genX(vs_samplers
) = {
5143 .mesa
= _NEW_TEXTURE
,
5144 .brw
= BRW_NEW_BATCH
|
5146 BRW_NEW_VERTEX_PROGRAM
,
5148 .emit
= genX(upload_vs_samplers
),
5153 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5155 /* BRW_NEW_GEOMETRY_PROGRAM */
5156 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5160 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5164 static const struct brw_tracked_state
genX(gs_samplers
) = {
5166 .mesa
= _NEW_TEXTURE
,
5167 .brw
= BRW_NEW_BATCH
|
5169 BRW_NEW_GEOMETRY_PROGRAM
,
5171 .emit
= genX(upload_gs_samplers
),
5177 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5179 /* BRW_NEW_TESS_PROGRAMS */
5180 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5184 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5187 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5189 .mesa
= _NEW_TEXTURE
,
5190 .brw
= BRW_NEW_BATCH
|
5192 BRW_NEW_TESS_PROGRAMS
,
5194 .emit
= genX(upload_tcs_samplers
),
5200 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5202 /* BRW_NEW_TESS_PROGRAMS */
5203 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5207 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5210 static const struct brw_tracked_state
genX(tes_samplers
) = {
5212 .mesa
= _NEW_TEXTURE
,
5213 .brw
= BRW_NEW_BATCH
|
5215 BRW_NEW_TESS_PROGRAMS
,
5217 .emit
= genX(upload_tes_samplers
),
5223 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5225 /* BRW_NEW_COMPUTE_PROGRAM */
5226 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5230 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5233 const struct brw_tracked_state
genX(cs_samplers
) = {
5235 .mesa
= _NEW_TEXTURE
,
5236 .brw
= BRW_NEW_BATCH
|
5238 BRW_NEW_COMPUTE_PROGRAM
,
5240 .emit
= genX(upload_cs_samplers
),
5244 /* ---------------------------------------------------------------------- */
5248 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5250 struct gl_context
*ctx
= &brw
->ctx
;
5252 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5253 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5254 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5255 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5256 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5260 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5263 .brw
= BRW_NEW_CONTEXT
|
5266 .emit
= genX(upload_blend_constant_color
)
5270 /* ---------------------------------------------------------------------- */
5273 genX(init_atoms
)(struct brw_context
*brw
)
5276 static const struct brw_tracked_state
*render_atoms
[] =
5278 /* Once all the programs are done, we know how large urb entry
5279 * sizes need to be and can decide if we need to change the urb
5283 &brw_recalculate_urb_fence
,
5286 &genX(color_calc_state
),
5288 /* Surface state setup. Must come before the VS/WM unit. The binding
5289 * table upload must be last.
5291 &brw_vs_pull_constants
,
5292 &brw_wm_pull_constants
,
5293 &brw_renderbuffer_surfaces
,
5294 &brw_renderbuffer_read_surfaces
,
5295 &brw_texture_surfaces
,
5296 &brw_vs_binding_table
,
5297 &brw_wm_binding_table
,
5302 /* These set up state for brw_psp_urb_cbs */
5304 &genX(sf_clip_viewport
),
5306 &genX(vs_state
), /* always required, enabled or not */
5312 &brw_invariant_state
,
5314 &brw_binding_table_pointers
,
5315 &genX(blend_constant_color
),
5319 &genX(polygon_stipple
),
5320 &genX(polygon_stipple_offset
),
5322 &genX(line_stipple
),
5326 &genX(drawing_rect
),
5327 &brw_indices
, /* must come before brw_vertices */
5328 &genX(index_buffer
),
5331 &brw_constant_buffer
5334 static const struct brw_tracked_state
*render_atoms
[] =
5336 &genX(sf_clip_viewport
),
5338 /* Command packets: */
5343 &genX(blend_state
), /* must do before cc unit */
5344 &genX(color_calc_state
), /* must do before cc unit */
5345 &genX(depth_stencil_state
), /* must do before cc unit */
5347 &genX(vs_push_constants
), /* Before vs_state */
5348 &genX(gs_push_constants
), /* Before gs_state */
5349 &genX(wm_push_constants
), /* Before wm_state */
5351 /* Surface state setup. Must come before the VS/WM unit. The binding
5352 * table upload must be last.
5354 &brw_vs_pull_constants
,
5355 &brw_vs_ubo_surfaces
,
5356 &brw_gs_pull_constants
,
5357 &brw_gs_ubo_surfaces
,
5358 &brw_wm_pull_constants
,
5359 &brw_wm_ubo_surfaces
,
5360 &gen6_renderbuffer_surfaces
,
5361 &brw_renderbuffer_read_surfaces
,
5362 &brw_texture_surfaces
,
5364 &brw_vs_binding_table
,
5365 &gen6_gs_binding_table
,
5366 &brw_wm_binding_table
,
5371 &gen6_sampler_state
,
5372 &genX(multisample_state
),
5380 &genX(scissor_state
),
5382 &gen6_binding_table_pointers
,
5386 &genX(polygon_stipple
),
5387 &genX(polygon_stipple_offset
),
5389 &genX(line_stipple
),
5391 &genX(drawing_rect
),
5393 &brw_indices
, /* must come before brw_vertices */
5394 &genX(index_buffer
),
5398 static const struct brw_tracked_state
*render_atoms
[] =
5400 /* Command packets: */
5403 &genX(sf_clip_viewport
),
5406 &gen7_push_constant_space
,
5408 &genX(blend_state
), /* must do before cc unit */
5409 &genX(color_calc_state
), /* must do before cc unit */
5410 &genX(depth_stencil_state
), /* must do before cc unit */
5412 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5413 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5414 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5415 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5416 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5418 &genX(vs_push_constants
), /* Before vs_state */
5419 &genX(tcs_push_constants
),
5420 &genX(tes_push_constants
),
5421 &genX(gs_push_constants
), /* Before gs_state */
5422 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5424 /* Surface state setup. Must come before the VS/WM unit. The binding
5425 * table upload must be last.
5427 &brw_vs_pull_constants
,
5428 &brw_vs_ubo_surfaces
,
5429 &brw_vs_abo_surfaces
,
5430 &brw_tcs_pull_constants
,
5431 &brw_tcs_ubo_surfaces
,
5432 &brw_tcs_abo_surfaces
,
5433 &brw_tes_pull_constants
,
5434 &brw_tes_ubo_surfaces
,
5435 &brw_tes_abo_surfaces
,
5436 &brw_gs_pull_constants
,
5437 &brw_gs_ubo_surfaces
,
5438 &brw_gs_abo_surfaces
,
5439 &brw_wm_pull_constants
,
5440 &brw_wm_ubo_surfaces
,
5441 &brw_wm_abo_surfaces
,
5442 &gen6_renderbuffer_surfaces
,
5443 &brw_renderbuffer_read_surfaces
,
5444 &brw_texture_surfaces
,
5446 &genX(push_constant_packets
),
5448 &brw_vs_binding_table
,
5449 &brw_tcs_binding_table
,
5450 &brw_tes_binding_table
,
5451 &brw_gs_binding_table
,
5452 &brw_wm_binding_table
,
5456 &genX(tcs_samplers
),
5457 &genX(tes_samplers
),
5459 &genX(multisample_state
),
5473 &genX(scissor_state
),
5477 &genX(polygon_stipple
),
5478 &genX(polygon_stipple_offset
),
5480 &genX(line_stipple
),
5482 &genX(drawing_rect
),
5484 &brw_indices
, /* must come before brw_vertices */
5485 &genX(index_buffer
),
5493 static const struct brw_tracked_state
*render_atoms
[] =
5496 &genX(sf_clip_viewport
),
5499 &gen7_push_constant_space
,
5502 &genX(color_calc_state
),
5504 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5505 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5506 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5507 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5508 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5510 &genX(vs_push_constants
), /* Before vs_state */
5511 &genX(tcs_push_constants
),
5512 &genX(tes_push_constants
),
5513 &genX(gs_push_constants
), /* Before gs_state */
5514 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5516 /* Surface state setup. Must come before the VS/WM unit. The binding
5517 * table upload must be last.
5519 &brw_vs_pull_constants
,
5520 &brw_vs_ubo_surfaces
,
5521 &brw_vs_abo_surfaces
,
5522 &brw_tcs_pull_constants
,
5523 &brw_tcs_ubo_surfaces
,
5524 &brw_tcs_abo_surfaces
,
5525 &brw_tes_pull_constants
,
5526 &brw_tes_ubo_surfaces
,
5527 &brw_tes_abo_surfaces
,
5528 &brw_gs_pull_constants
,
5529 &brw_gs_ubo_surfaces
,
5530 &brw_gs_abo_surfaces
,
5531 &brw_wm_pull_constants
,
5532 &brw_wm_ubo_surfaces
,
5533 &brw_wm_abo_surfaces
,
5534 &gen6_renderbuffer_surfaces
,
5535 &brw_renderbuffer_read_surfaces
,
5536 &brw_texture_surfaces
,
5538 &genX(push_constant_packets
),
5540 &brw_vs_binding_table
,
5541 &brw_tcs_binding_table
,
5542 &brw_tes_binding_table
,
5543 &brw_gs_binding_table
,
5544 &brw_wm_binding_table
,
5548 &genX(tcs_samplers
),
5549 &genX(tes_samplers
),
5551 &genX(multisample_state
),
5560 &genX(raster_state
),
5566 &genX(depth_stencil_state
),
5569 &genX(scissor_state
),
5573 &genX(polygon_stipple
),
5574 &genX(polygon_stipple_offset
),
5576 &genX(line_stipple
),
5578 &genX(drawing_rect
),
5583 &genX(index_buffer
),
5591 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5592 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5593 render_atoms
, ARRAY_SIZE(render_atoms
));
5596 static const struct brw_tracked_state
*compute_atoms
[] =
5599 &brw_cs_image_surfaces
,
5600 &gen7_cs_push_constants
,
5601 &brw_cs_pull_constants
,
5602 &brw_cs_ubo_surfaces
,
5603 &brw_cs_abo_surfaces
,
5604 &brw_cs_texture_surfaces
,
5605 &brw_cs_work_groups_surface
,
5610 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5611 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5612 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5614 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);