2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
35 #include "brw_context.h"
37 #include "brw_defines.h"
40 #include "brw_multisample_state.h"
41 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
46 #include "intel_buffer_objects.h"
47 #include "intel_fbo.h"
49 #include "main/enums.h"
50 #include "main/fbobject.h"
51 #include "main/framebuffer.h"
52 #include "main/glformats.h"
53 #include "main/shaderapi.h"
54 #include "main/stencil.h"
55 #include "main/transformfeedback.h"
56 #include "main/varray.h"
57 #include "main/viewport.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
71 uint32_t read_domains
;
72 uint32_t write_domain
;
77 emit_reloc(struct brw_context
*brw
,
78 void *location
, struct brw_address address
, uint32_t delta
)
80 uint32_t offset
= (char *) location
- (char *) brw
->batch
.map
;
82 return brw_emit_reloc(&brw
->batch
, offset
, address
.bo
,
83 address
.offset
+ delta
,
85 address
.write_domain
);
88 #define __gen_address_type struct brw_address
89 #define __gen_user_data struct brw_context
92 __gen_combine_address(struct brw_context
*brw
, void *location
,
93 struct brw_address address
, uint32_t delta
)
95 if (address
.bo
== NULL
) {
96 return address
.offset
+ delta
;
98 return emit_reloc(brw
, location
, address
, delta
);
102 static inline struct brw_address
103 render_bo(struct brw_bo
*bo
, uint32_t offset
)
105 return (struct brw_address
) {
108 .read_domains
= I915_GEM_DOMAIN_RENDER
,
109 .write_domain
= I915_GEM_DOMAIN_RENDER
,
113 static inline struct brw_address
114 render_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
116 return (struct brw_address
) {
119 .read_domains
= I915_GEM_DOMAIN_RENDER
,
124 static inline struct brw_address
125 instruction_bo(struct brw_bo
*bo
, uint32_t offset
)
127 return (struct brw_address
) {
130 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
131 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
135 static inline struct brw_address
136 instruction_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
138 return (struct brw_address
) {
141 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
146 static inline struct brw_address
147 vertex_bo(struct brw_bo
*bo
, uint32_t offset
)
149 return (struct brw_address
) {
152 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
157 #include "genxml/genX_pack.h"
159 #define _brw_cmd_length(cmd) cmd ## _length
160 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
161 #define _brw_cmd_header(cmd) cmd ## _header
162 #define _brw_cmd_pack(cmd) cmd ## _pack
164 #define brw_batch_emit(brw, cmd, name) \
165 for (struct cmd name = { _brw_cmd_header(cmd) }, \
166 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
167 __builtin_expect(_dst != NULL, 1); \
168 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
171 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
172 uint32_t *_dw = emit_dwords(brw, n); \
173 struct cmd template = { \
174 _brw_cmd_header(cmd), \
175 .DWordLength = n - _brw_cmd_length_bias(cmd), \
178 _brw_cmd_pack(cmd)(brw, _dw, &template); \
179 _dw + 1; /* Array starts at dw[1] */ \
182 #define brw_state_emit(brw, cmd, align, offset, name) \
183 for (struct cmd name = { 0, }, \
184 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
186 __builtin_expect(_dst != NULL, 1); \
187 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
191 * Polygon stipple packet
194 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
196 struct gl_context
*ctx
= &brw
->ctx
;
199 if (!ctx
->Polygon
.StippleFlag
)
202 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
203 /* Polygon stipple is provided in OpenGL order, i.e. bottom
204 * row first. If we're rendering to a window (i.e. the
205 * default frame buffer object, 0), then we need to invert
206 * it to match our pixel layout. But if we're rendering
207 * to a FBO (i.e. any named frame buffer object), we *don't*
208 * need to invert - we already match the layout.
210 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
211 for (unsigned i
= 0; i
< 32; i
++)
212 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
214 for (unsigned i
= 0; i
< 32; i
++)
215 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
220 static const struct brw_tracked_state
genX(polygon_stipple
) = {
222 .mesa
= _NEW_POLYGON
|
224 .brw
= BRW_NEW_CONTEXT
,
226 .emit
= genX(upload_polygon_stipple
),
230 * Polygon stipple offset packet
233 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
235 struct gl_context
*ctx
= &brw
->ctx
;
238 if (!ctx
->Polygon
.StippleFlag
)
241 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
244 * If we're drawing to a system window we have to invert the Y axis
245 * in order to match the OpenGL pixel coordinate system, and our
246 * offset must be matched to the window position. If we're drawing
247 * to a user-created FBO then our native pixel coordinate system
248 * works just fine, and there's no window system to worry about.
250 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
251 poly
.PolygonStippleYOffset
=
252 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
257 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
259 .mesa
= _NEW_BUFFERS
|
261 .brw
= BRW_NEW_CONTEXT
,
263 .emit
= genX(upload_polygon_stipple_offset
),
267 * Line stipple packet
270 genX(upload_line_stipple
)(struct brw_context
*brw
)
272 struct gl_context
*ctx
= &brw
->ctx
;
274 if (!ctx
->Line
.StippleFlag
)
277 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
278 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
280 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
281 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
285 static const struct brw_tracked_state
genX(line_stipple
) = {
288 .brw
= BRW_NEW_CONTEXT
,
290 .emit
= genX(upload_line_stipple
),
293 /* Constant single cliprect for framebuffer object or DRI2 drawing */
295 genX(upload_drawing_rect
)(struct brw_context
*brw
)
297 struct gl_context
*ctx
= &brw
->ctx
;
298 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
299 const unsigned int fb_width
= _mesa_geometric_width(fb
);
300 const unsigned int fb_height
= _mesa_geometric_height(fb
);
302 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
303 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
304 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
308 static const struct brw_tracked_state
genX(drawing_rect
) = {
310 .mesa
= _NEW_BUFFERS
,
311 .brw
= BRW_NEW_BLORP
|
314 .emit
= genX(upload_drawing_rect
),
318 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
322 unsigned start_offset
,
327 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
328 .VertexBufferIndex
= buffer_nr
,
329 .BufferPitch
= stride
,
330 .BufferStartingAddress
= vertex_bo(bo
, start_offset
),
332 .BufferSize
= end_offset
- start_offset
,
336 .AddressModifyEnable
= true,
340 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
341 .InstanceDataStepRate
= step_rate
,
343 .EndAddress
= vertex_bo(bo
, end_offset
- 1),
348 .VertexBufferMOCS
= SKL_MOCS_WB
,
350 .VertexBufferMOCS
= BDW_MOCS_WB
,
352 .VertexBufferMOCS
= GEN7_MOCS_L3
,
356 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
357 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
361 is_passthru_format(uint32_t format
)
364 case ISL_FORMAT_R64_PASSTHRU
:
365 case ISL_FORMAT_R64G64_PASSTHRU
:
366 case ISL_FORMAT_R64G64B64_PASSTHRU
:
367 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
375 uploads_needed(uint32_t format
)
377 if (!is_passthru_format(format
))
381 case ISL_FORMAT_R64_PASSTHRU
:
382 case ISL_FORMAT_R64G64_PASSTHRU
:
384 case ISL_FORMAT_R64G64B64_PASSTHRU
:
385 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
388 unreachable("not reached");
393 * Returns the format that we are finally going to use when upload a vertex
394 * element. It will only change if we are using *64*PASSTHRU formats, as for
395 * gen < 8 they need to be splitted on two *32*FLOAT formats.
397 * @upload points in which upload we are. Valid values are [0,1]
400 downsize_format_if_needed(uint32_t format
,
403 assert(upload
== 0 || upload
== 1);
405 if (!is_passthru_format(format
))
409 case ISL_FORMAT_R64_PASSTHRU
:
410 return ISL_FORMAT_R32G32_FLOAT
;
411 case ISL_FORMAT_R64G64_PASSTHRU
:
412 return ISL_FORMAT_R32G32B32A32_FLOAT
;
413 case ISL_FORMAT_R64G64B64_PASSTHRU
:
414 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
415 : ISL_FORMAT_R32G32_FLOAT
;
416 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
417 return ISL_FORMAT_R32G32B32A32_FLOAT
;
419 unreachable("not reached");
424 * Returns the number of componentes associated with a format that is used on
425 * a 64 to 32 format split. See downsize_format()
428 upload_format_size(uint32_t upload_format
)
430 switch (upload_format
) {
431 case ISL_FORMAT_R32G32_FLOAT
:
433 case ISL_FORMAT_R32G32B32A32_FLOAT
:
436 unreachable("not reached");
441 genX(emit_vertices
)(struct brw_context
*brw
)
445 brw_prepare_vertices(brw
);
446 brw_prepare_shader_draw_parameters(brw
);
449 brw_emit_query_begin(brw
);
452 const struct brw_vs_prog_data
*vs_prog_data
=
453 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
456 struct gl_context
*ctx
= &brw
->ctx
;
457 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
458 ctx
->Polygon
.BackMode
!= GL_FILL
);
460 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
461 unsigned vue
= brw
->vb
.nr_enabled
;
463 /* The element for the edge flags must always be last, so we have to
464 * insert the SGVS before it in that case.
466 if (uses_edge_flag
) {
472 "Trying to insert VID/IID past 33rd vertex element, "
473 "need to reorder the vertex attrbutes.");
475 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
476 if (vs_prog_data
->uses_vertexid
) {
477 vfs
.VertexIDEnable
= true;
478 vfs
.VertexIDComponentNumber
= 2;
479 vfs
.VertexIDElementOffset
= vue
;
482 if (vs_prog_data
->uses_instanceid
) {
483 vfs
.InstanceIDEnable
= true;
484 vfs
.InstanceIDComponentNumber
= 3;
485 vfs
.InstanceIDElementOffset
= vue
;
489 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
490 vfi
.InstancingEnable
= true;
491 vfi
.VertexElementIndex
= vue
;
494 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
497 /* Normally we don't need an element for the SGVS attribute because the
498 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
499 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
500 * we're using draw parameters then we need an element for the those
501 * values. Additionally if there is an edge flag element then the SGVS
502 * can't be inserted past that so we need a dummy element to ensure that
503 * the edge flag is the last one.
505 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
506 vs_prog_data
->uses_baseinstance
||
507 ((vs_prog_data
->uses_instanceid
||
508 vs_prog_data
->uses_vertexid
)
511 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
512 vs_prog_data
->uses_baseinstance
||
513 vs_prog_data
->uses_instanceid
||
514 vs_prog_data
->uses_vertexid
);
516 unsigned nr_elements
=
517 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
520 /* If any of the formats of vb.enabled needs more that one upload, we need
521 * to add it to nr_elements
523 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
524 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
525 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
527 if (uploads_needed(format
) > 1)
532 /* If the VS doesn't read any inputs (calculating vertex position from
533 * a state variable for some reason, for example), emit a single pad
534 * VERTEX_ELEMENT struct and bail.
536 * The stale VB state stays in place, but they don't do anything unless
537 * a VE loads from them.
539 if (nr_elements
== 0) {
540 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
541 1 + GENX(VERTEX_ELEMENT_STATE_length
));
542 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
544 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
545 .Component0Control
= VFCOMP_STORE_0
,
546 .Component1Control
= VFCOMP_STORE_0
,
547 .Component2Control
= VFCOMP_STORE_0
,
548 .Component3Control
= VFCOMP_STORE_1_FP
,
550 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
554 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
555 const bool uses_draw_params
=
556 vs_prog_data
->uses_basevertex
||
557 vs_prog_data
->uses_baseinstance
;
558 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
559 uses_draw_params
+ vs_prog_data
->uses_drawid
;
562 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
564 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
565 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
567 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
568 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
569 /* Prior to Haswell and Bay Trail we have to use 4-component formats
570 * to fake 3-component ones. In particular, we do this for
571 * half-float and 8 and 16-bit integer formats. This means that the
572 * vertex element may poke over the end of the buffer by 2 bytes.
574 const unsigned padding
=
575 (GEN_GEN
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
576 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
577 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
584 if (uses_draw_params
) {
585 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
586 brw
->draw
.draw_params_bo
,
587 brw
->draw
.draw_params_offset
,
588 brw
->draw
.draw_params_bo
->size
,
593 if (vs_prog_data
->uses_drawid
) {
594 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
595 brw
->draw
.draw_id_bo
,
596 brw
->draw
.draw_id_offset
,
597 brw
->draw
.draw_id_bo
->size
,
603 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
604 * presumably for VertexID/InstanceID.
607 assert(nr_elements
<= 34);
608 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
610 assert(nr_elements
<= 18);
613 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
614 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
616 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
617 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
618 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
619 uint32_t comp0
= VFCOMP_STORE_SRC
;
620 uint32_t comp1
= VFCOMP_STORE_SRC
;
621 uint32_t comp2
= VFCOMP_STORE_SRC
;
622 uint32_t comp3
= VFCOMP_STORE_SRC
;
623 const unsigned num_uploads
= GEN_GEN
< 8 ? uploads_needed(format
) : 1;
626 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
627 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
628 * element which has edge flag enabled."
630 assert(!(is_passthru_format(format
) && uses_edge_flag
));
633 /* The gen4 driver expects edgeflag to come in as a float, and passes
634 * that float on to the tests in the clipper. Mesa's current vertex
635 * attribute value for EdgeFlag is stored as a float, which works out.
636 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
637 * integer ubyte. Just rewrite that to convert to a float.
639 * Gen6+ passes edgeflag as sideband along with the vertex, instead
640 * of in the VUE. We have to upload it sideband as the last vertex
641 * element according to the B-Spec.
644 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
645 gen6_edgeflag_input
= input
;
650 for (unsigned c
= 0; c
< num_uploads
; c
++) {
651 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
652 downsize_format_if_needed(format
, c
);
653 /* If we need more that one upload, the offset stride would be 128
654 * bits (16 bytes), as for previous uploads we are using the full
656 const unsigned offset
= input
->offset
+ c
* 16;
658 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
659 upload_format_size(upload_format
) : input
->glarray
->Size
;
662 case 0: comp0
= VFCOMP_STORE_0
;
663 case 1: comp1
= VFCOMP_STORE_0
;
664 case 2: comp2
= VFCOMP_STORE_0
;
666 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
667 comp3
= VFCOMP_STORE_0
;
668 } else if (input
->glarray
->Integer
) {
669 comp3
= VFCOMP_STORE_1_INT
;
671 comp3
= VFCOMP_STORE_1_FP
;
678 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
680 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
681 * formats, 64-bit components are stored in the URB without any
682 * conversion. In this case, vertex elements must be written as 128
683 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
684 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
685 * component into the URB, Component 1 must be specified as
686 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
687 * order to output a 128-bit vertex element, or Components 1-3 must
688 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
689 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
690 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
693 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
694 /* Store vertex elements which correspond to double and dvec2 vertex
695 * shader inputs as 128-bit vertex elements, instead of 256-bits.
697 comp2
= VFCOMP_NOSTORE
;
698 comp3
= VFCOMP_NOSTORE
;
702 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
703 .VertexBufferIndex
= input
->buffer
,
705 .SourceElementFormat
= upload_format
,
706 .SourceElementOffset
= offset
,
707 .Component0Control
= comp0
,
708 .Component1Control
= comp1
,
709 .Component2Control
= comp2
,
710 .Component3Control
= comp3
,
712 .DestinationElementOffset
= i
* 4,
716 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
717 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
721 if (needs_sgvs_element
) {
722 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
724 .Component0Control
= VFCOMP_STORE_0
,
725 .Component1Control
= VFCOMP_STORE_0
,
726 .Component2Control
= VFCOMP_STORE_0
,
727 .Component3Control
= VFCOMP_STORE_0
,
729 .DestinationElementOffset
= i
* 4,
734 if (vs_prog_data
->uses_basevertex
||
735 vs_prog_data
->uses_baseinstance
) {
736 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
737 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
738 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
739 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
742 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
743 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
744 if (vs_prog_data
->uses_basevertex
)
745 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
747 if (vs_prog_data
->uses_baseinstance
)
748 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
750 if (vs_prog_data
->uses_vertexid
)
751 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
753 if (vs_prog_data
->uses_instanceid
)
754 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
757 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
758 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
761 if (vs_prog_data
->uses_drawid
) {
762 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
764 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
765 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
766 .Component0Control
= VFCOMP_STORE_SRC
,
767 .Component1Control
= VFCOMP_STORE_0
,
768 .Component2Control
= VFCOMP_STORE_0
,
769 .Component3Control
= VFCOMP_STORE_0
,
771 .DestinationElementOffset
= i
* 4,
775 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
776 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
780 if (gen6_edgeflag_input
) {
781 const uint32_t format
=
782 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
784 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
786 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
787 .EdgeFlagEnable
= true,
788 .SourceElementFormat
= format
,
789 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
790 .Component0Control
= VFCOMP_STORE_SRC
,
791 .Component1Control
= VFCOMP_STORE_0
,
792 .Component2Control
= VFCOMP_STORE_0
,
793 .Component3Control
= VFCOMP_STORE_0
,
796 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
797 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
802 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
803 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
804 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
805 unsigned element_index
;
807 /* The edge flag element is reordered to be the last one in the code
808 * above so we need to compensate for that in the element indices used
811 if (input
== gen6_edgeflag_input
)
812 element_index
= nr_elements
- 1;
816 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
817 vfi
.VertexElementIndex
= element_index
;
818 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
819 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
823 if (vs_prog_data
->uses_drawid
) {
824 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
826 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
827 vfi
.VertexElementIndex
= element
;
833 static const struct brw_tracked_state
genX(vertices
) = {
835 .mesa
= _NEW_POLYGON
,
836 .brw
= BRW_NEW_BATCH
|
839 BRW_NEW_VS_PROG_DATA
,
841 .emit
= genX(emit_vertices
),
845 genX(emit_index_buffer
)(struct brw_context
*brw
)
847 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
849 if (index_buffer
== NULL
)
852 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
853 #if GEN_GEN < 8 && !GEN_IS_HASWELL
854 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
856 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
857 ib
.BufferStartingAddress
= vertex_bo(brw
->ib
.bo
, 0);
859 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
860 ib
.BufferSize
= brw
->ib
.size
;
862 ib
.BufferEndingAddress
= vertex_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
867 static const struct brw_tracked_state
genX(index_buffer
) = {
870 .brw
= BRW_NEW_BATCH
|
872 BRW_NEW_INDEX_BUFFER
,
874 .emit
= genX(emit_index_buffer
),
877 #if GEN_IS_HASWELL || GEN_GEN >= 8
879 genX(upload_cut_index
)(struct brw_context
*brw
)
881 const struct gl_context
*ctx
= &brw
->ctx
;
883 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
884 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
885 vf
.IndexedDrawCutIndexEnable
= true;
886 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
891 const struct brw_tracked_state
genX(cut_index
) = {
893 .mesa
= _NEW_TRANSFORM
,
894 .brw
= BRW_NEW_INDEX_BUFFER
,
896 .emit
= genX(upload_cut_index
),
902 * Determine the appropriate attribute override value to store into the
903 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
904 * override value contains two pieces of information: the location of the
905 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
906 * flag indicating whether to "swizzle" the attribute based on the direction
907 * the triangle is facing.
909 * If an attribute is "swizzled", then the given VUE location is used for
910 * front-facing triangles, and the VUE location that immediately follows is
911 * used for back-facing triangles. We use this to implement the mapping from
912 * gl_FrontColor/gl_BackColor to gl_Color.
914 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
915 * being instructed to begin reading attribute data. It can be set to a
916 * nonzero value to prevent the SF unit from wasting time reading elements of
917 * the VUE that are not needed by the fragment shader. It is measured in
918 * 256-bit increments.
921 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
922 const struct brw_vue_map
*vue_map
,
923 int urb_entry_read_offset
, int fs_attr
,
924 bool two_side_color
, uint32_t *max_source_attr
)
926 /* Find the VUE slot for this attribute. */
927 int slot
= vue_map
->varying_to_slot
[fs_attr
];
929 /* Viewport and Layer are stored in the VUE header. We need to override
930 * them to zero if earlier stages didn't write them, as GL requires that
931 * they read back as zero when not explicitly set.
933 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
934 attr
->ComponentOverrideX
= true;
935 attr
->ComponentOverrideW
= true;
936 attr
->ConstantSource
= CONST_0000
;
938 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
939 attr
->ComponentOverrideY
= true;
940 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
941 attr
->ComponentOverrideZ
= true;
946 /* If there was only a back color written but not front, use back
947 * as the color instead of undefined
949 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
950 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
951 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
952 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
955 /* This attribute does not exist in the VUE--that means that the vertex
956 * shader did not write to it. This means that either:
958 * (a) This attribute is a texture coordinate, and it is going to be
959 * replaced with point coordinates (as a consequence of a call to
960 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
961 * hardware will ignore whatever attribute override we supply.
963 * (b) This attribute is read by the fragment shader but not written by
964 * the vertex shader, so its value is undefined. Therefore the
965 * attribute override we supply doesn't matter.
967 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
968 * previous shader stage.
970 * Note that we don't have to worry about the cases where the attribute
971 * is gl_PointCoord or is undergoing point sprite coordinate
972 * replacement, because in those cases, this function isn't called.
974 * In case (c), we need to program the attribute overrides so that the
975 * primitive ID will be stored in this slot. In every other case, the
976 * attribute override we supply doesn't matter. So just go ahead and
977 * program primitive ID in every case.
979 attr
->ComponentOverrideW
= true;
980 attr
->ComponentOverrideX
= true;
981 attr
->ComponentOverrideY
= true;
982 attr
->ComponentOverrideZ
= true;
983 attr
->ConstantSource
= PRIM_ID
;
987 /* Compute the location of the attribute relative to urb_entry_read_offset.
988 * Each increment of urb_entry_read_offset represents a 256-bit value, so
989 * it counts for two 128-bit VUE slots.
991 int source_attr
= slot
- 2 * urb_entry_read_offset
;
992 assert(source_attr
>= 0 && source_attr
< 32);
994 /* If we are doing two-sided color, and the VUE slot following this one
995 * represents a back-facing color, then we need to instruct the SF unit to
996 * do back-facing swizzling.
998 bool swizzling
= two_side_color
&&
999 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1000 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1001 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1002 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1004 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1005 if (*max_source_attr
< source_attr
+ swizzling
)
1006 *max_source_attr
= source_attr
+ swizzling
;
1008 attr
->SourceAttribute
= source_attr
;
1010 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1015 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1016 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1017 uint32_t *point_sprite_enables
,
1018 uint32_t *urb_entry_read_length
,
1019 uint32_t *urb_entry_read_offset
)
1021 const struct gl_context
*ctx
= &brw
->ctx
;
1024 const struct gl_point_attrib
*point
= &ctx
->Point
;
1026 /* BRW_NEW_FS_PROG_DATA */
1027 const struct brw_wm_prog_data
*wm_prog_data
=
1028 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1029 uint32_t max_source_attr
= 0;
1031 *point_sprite_enables
= 0;
1033 /* BRW_NEW_FRAGMENT_PROGRAM
1035 * If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
1036 * the full vertex header. Otherwise, we can program the SF to start
1037 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
1038 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1039 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
1042 bool fs_needs_vue_header
= brw
->fragment_program
->info
.inputs_read
&
1043 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1045 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
1047 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1048 * description of dw10 Point Sprite Texture Coordinate Enable:
1050 * "This field must be programmed to zero when non-point primitives
1053 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1054 * must be programmed to zero when rendering non-point primitives, but
1055 * the IvyBridge PRM does, and if we don't, we get garbage.
1057 * This is not required on Haswell, as the hardware ignores this state
1058 * when drawing non-points -- although we do still need to be careful to
1059 * correctly set the attr overrides.
1062 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1064 bool drawing_points
= brw_is_drawing_points(brw
);
1066 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1067 int input_index
= wm_prog_data
->urb_setup
[attr
];
1069 if (input_index
< 0)
1073 bool point_sprite
= false;
1074 if (drawing_points
) {
1075 if (point
->PointSprite
&&
1076 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1077 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1078 point_sprite
= true;
1081 if (attr
== VARYING_SLOT_PNTC
)
1082 point_sprite
= true;
1085 *point_sprite_enables
|= (1 << input_index
);
1088 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1089 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1091 if (!point_sprite
) {
1092 genX(get_attr_override
)(&attribute
,
1093 &brw
->vue_map_geom_out
,
1094 *urb_entry_read_offset
, attr
,
1095 brw
->ctx
.VertexProgram
._TwoSideEnabled
,
1099 /* The hardware can only do the overrides on 16 overrides at a
1100 * time, and the other up to 16 have to be lined up so that the
1101 * input index = the output index. We'll need to do some
1102 * tweaking to make sure that's the case.
1104 if (input_index
< 16)
1105 attr_overrides
[input_index
] = attribute
;
1107 assert(attribute
.SourceAttribute
== input_index
);
1110 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1111 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1113 * "This field should be set to the minimum length required to read the
1114 * maximum source attribute. The maximum source attribute is indicated
1115 * by the maximum value of the enabled Attribute # Source Attribute if
1116 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1117 * enable is not set.
1118 * read_length = ceiling((max_source_attr + 1) / 2)
1120 * [errata] Corruption/Hang possible if length programmed larger than
1123 * Similar text exists for Ivy Bridge.
1125 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1129 /* ---------------------------------------------------------------------- */
1133 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1135 struct gl_context
*ctx
= &brw
->ctx
;
1138 struct intel_renderbuffer
*depth_irb
=
1139 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1142 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1145 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1146 const int b
= stencil
->_BackFace
;
1149 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1152 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, wmds
) {
1154 if (depth
->Test
&& depth_irb
) {
1155 wmds
.DepthTestEnable
= true;
1156 wmds
.DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1157 wmds
.DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1160 if (stencil
->_Enabled
) {
1161 wmds
.StencilTestEnable
= true;
1162 wmds
.StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1163 wmds
.StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1165 wmds
.StencilTestFunction
=
1166 intel_translate_compare_func(stencil
->Function
[0]);
1167 wmds
.StencilFailOp
=
1168 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1169 wmds
.StencilPassDepthPassOp
=
1170 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1171 wmds
.StencilPassDepthFailOp
=
1172 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1174 wmds
.StencilBufferWriteEnable
= stencil
->_WriteEnabled
;
1176 if (stencil
->_TestTwoSide
) {
1177 wmds
.DoubleSidedStencilEnable
= true;
1178 wmds
.BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1179 wmds
.BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1181 wmds
.BackfaceStencilTestFunction
=
1182 intel_translate_compare_func(stencil
->Function
[b
]);
1183 wmds
.BackfaceStencilFailOp
=
1184 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1185 wmds
.BackfaceStencilPassDepthPassOp
=
1186 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1187 wmds
.BackfaceStencilPassDepthFailOp
=
1188 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1192 wmds
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1193 wmds
.BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1199 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1200 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1201 ptr
.DEPTH_STENCIL_STATEChange
= true;
1204 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1205 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1210 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1212 .mesa
= _NEW_BUFFERS
|
1215 .brw
= BRW_NEW_BLORP
|
1216 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1218 BRW_NEW_STATE_BASE_ADDRESS
),
1220 .emit
= genX(upload_depth_stencil_state
),
1224 /* ---------------------------------------------------------------------- */
1228 genX(upload_clip_state
)(struct brw_context
*brw
)
1230 struct gl_context
*ctx
= &brw
->ctx
;
1233 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1235 /* BRW_NEW_FS_PROG_DATA */
1236 struct brw_wm_prog_data
*wm_prog_data
=
1237 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1239 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1240 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1242 if (wm_prog_data
->barycentric_interp_modes
&
1243 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1244 clip
.NonPerspectiveBarycentricEnable
= true;
1247 clip
.EarlyCullEnable
= true;
1251 clip
.FrontWinding
= ctx
->Polygon
._FrontBit
== _mesa_is_user_fbo(fb
);
1253 if (ctx
->Polygon
.CullFlag
) {
1254 switch (ctx
->Polygon
.CullFaceMode
) {
1256 clip
.CullMode
= CULLMODE_FRONT
;
1259 clip
.CullMode
= CULLMODE_BACK
;
1261 case GL_FRONT_AND_BACK
:
1262 clip
.CullMode
= CULLMODE_BOTH
;
1265 unreachable("Should not get here: invalid CullFlag");
1268 clip
.CullMode
= CULLMODE_NONE
;
1273 clip
.UserClipDistanceCullTestEnableBitmask
=
1274 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1276 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1280 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1281 clip
.TriangleStripListProvokingVertexSelect
= 0;
1282 clip
.TriangleFanProvokingVertexSelect
= 1;
1283 clip
.LineStripListProvokingVertexSelect
= 0;
1285 clip
.TriangleStripListProvokingVertexSelect
= 2;
1286 clip
.TriangleFanProvokingVertexSelect
= 2;
1287 clip
.LineStripListProvokingVertexSelect
= 1;
1290 /* _NEW_TRANSFORM */
1291 clip
.UserClipDistanceClipTestEnableBitmask
=
1292 ctx
->Transform
.ClipPlanesEnabled
;
1295 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1298 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1299 clip
.APIMode
= APIMODE_D3D
;
1301 clip
.APIMode
= APIMODE_OGL
;
1303 clip
.GuardbandClipTestEnable
= true;
1305 /* BRW_NEW_VIEWPORT_COUNT */
1306 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1308 if (ctx
->RasterDiscard
) {
1309 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1311 perf_debug("Rasterizer discard is currently implemented via the "
1312 "clipper; having the GS not write primitives would "
1313 "likely be faster.\n");
1316 clip
.ClipMode
= CLIPMODE_NORMAL
;
1319 clip
.ClipEnable
= brw
->primitive
!= _3DPRIM_RECTLIST
;
1322 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1324 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1325 clip
.ViewportXYClipTestEnable
= true;
1327 clip
.MinimumPointWidth
= 0.125;
1328 clip
.MaximumPointWidth
= 255.875;
1329 clip
.MaximumVPIndex
= viewport_count
- 1;
1330 if (_mesa_geometric_layers(fb
) == 0)
1331 clip
.ForceZeroRTAIndexEnable
= true;
1335 static const struct brw_tracked_state
genX(clip_state
) = {
1337 .mesa
= _NEW_BUFFERS
|
1341 .brw
= BRW_NEW_BLORP
|
1343 BRW_NEW_FS_PROG_DATA
|
1344 BRW_NEW_GS_PROG_DATA
|
1345 BRW_NEW_VS_PROG_DATA
|
1346 BRW_NEW_META_IN_PROGRESS
|
1348 BRW_NEW_RASTERIZER_DISCARD
|
1349 BRW_NEW_TES_PROG_DATA
|
1350 BRW_NEW_VIEWPORT_COUNT
,
1352 .emit
= genX(upload_clip_state
),
1356 /* ---------------------------------------------------------------------- */
1360 genX(upload_sf
)(struct brw_context
*brw
)
1362 struct gl_context
*ctx
= &brw
->ctx
;
1367 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1368 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1371 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1372 sf
.StatisticsEnable
= true;
1373 sf
.ViewportTransformEnable
= true;
1377 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1382 sf
.FrontWinding
= ctx
->Polygon
._FrontBit
== render_to_fbo
;
1383 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1384 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1385 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1387 switch (ctx
->Polygon
.FrontMode
) {
1389 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1392 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1395 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1398 unreachable("not reached");
1401 switch (ctx
->Polygon
.BackMode
) {
1403 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1406 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1409 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1412 unreachable("not reached");
1415 sf
.ScissorRectangleEnable
= true;
1417 if (ctx
->Polygon
.CullFlag
) {
1418 switch (ctx
->Polygon
.CullFaceMode
) {
1420 sf
.CullMode
= CULLMODE_FRONT
;
1423 sf
.CullMode
= CULLMODE_BACK
;
1425 case GL_FRONT_AND_BACK
:
1426 sf
.CullMode
= CULLMODE_BOTH
;
1429 unreachable("not reached");
1432 sf
.CullMode
= CULLMODE_NONE
;
1436 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1439 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1440 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1442 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1443 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1444 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1449 if (brw
->is_cherryview
)
1450 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1452 sf
.LineWidth
= brw_get_line_width(brw
);
1454 sf
.LineWidth
= brw_get_line_width(brw
);
1457 if (ctx
->Line
.SmoothFlag
) {
1458 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1460 sf
.AntiAliasingEnable
= true;
1464 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1465 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1466 /* Clamp to the hardware limits */
1467 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1469 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1470 if (use_state_point_size(brw
))
1471 sf
.PointWidthSource
= State
;
1474 /* _NEW_POINT | _NEW_MULTISAMPLE */
1475 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1476 !ctx
->Point
.PointSprite
)
1477 sf
.SmoothPointEnable
= true;
1480 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1483 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1484 sf
.TriangleStripListProvokingVertexSelect
= 2;
1485 sf
.TriangleFanProvokingVertexSelect
= 2;
1486 sf
.LineStripListProvokingVertexSelect
= 1;
1488 sf
.TriangleFanProvokingVertexSelect
= 1;
1492 /* BRW_NEW_FS_PROG_DATA */
1493 const struct brw_wm_prog_data
*wm_prog_data
=
1494 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1496 sf
.AttributeSwizzleEnable
= true;
1497 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1500 * Window coordinates in an FBO are inverted, which means point
1501 * sprite origin must be inverted, too.
1503 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1504 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1506 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1509 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1510 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1512 uint32_t urb_entry_read_length
;
1513 uint32_t urb_entry_read_offset
;
1514 uint32_t point_sprite_enables
;
1515 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1516 &urb_entry_read_length
,
1517 &urb_entry_read_offset
);
1518 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1519 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1520 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1521 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1526 static const struct brw_tracked_state
genX(sf_state
) = {
1528 .mesa
= _NEW_LIGHT
|
1533 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1534 .brw
= BRW_NEW_BLORP
|
1536 BRW_NEW_VUE_MAP_GEOM_OUT
|
1537 (GEN_GEN
<= 7 ? BRW_NEW_GS_PROG_DATA
|
1539 BRW_NEW_TES_PROG_DATA
1541 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1542 BRW_NEW_FRAGMENT_PROGRAM
1545 .emit
= genX(upload_sf
),
1549 /* ---------------------------------------------------------------------- */
1553 genX(upload_wm
)(struct brw_context
*brw
)
1555 struct gl_context
*ctx
= &brw
->ctx
;
1557 /* BRW_NEW_FS_PROG_DATA */
1558 const struct brw_wm_prog_data
*wm_prog_data
=
1559 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1561 UNUSED
bool writes_depth
=
1562 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1565 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1566 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1568 /* We can't fold this into gen6_upload_wm_push_constants(), because
1569 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1570 * (3DSTATE_CONSTANT_PS [DevSNB]):
1572 * "[DevSNB]: This packet must be followed by WM_STATE."
1574 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1575 if (wm_prog_data
->base
.nr_params
!= 0) {
1576 wmcp
.Buffer0Valid
= true;
1577 /* Pointer to the WM constant buffer. Covered by the set of
1578 * state flags from gen6_upload_wm_push_constants.
1580 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1581 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1586 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1587 wm
.StatisticsEnable
= true;
1588 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1589 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1592 if (wm_prog_data
->base
.use_alt_mode
)
1593 wm
.FloatingPointMode
= Alternate
;
1595 wm
.SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1596 wm
.BindingTableEntryCount
= wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1597 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1598 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1599 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1600 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1601 wm_prog_data
->base
.dispatch_grf_start_reg
;
1602 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1603 wm_prog_data
->dispatch_grf_start_reg_2
;
1604 wm
.KernelStartPointer0
= stage_state
->prog_offset
;
1605 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1606 wm_prog_data
->prog_offset_2
;
1607 wm
.DualSourceBlendEnable
=
1608 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1609 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1610 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1611 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1613 /* From the SNB PRM, volume 2 part 1, page 281:
1614 * "If the PS kernel does not need the Position XY Offsets
1615 * to compute a Position XY value, then this field should be
1616 * programmed to POSOFFSET_NONE."
1618 * "SW Recommendation: If the PS kernel needs the Position Offsets
1619 * to compute a Position XY value, this field should match Position
1620 * ZW Interpolation Mode to ensure a consistent position.xyzw
1622 * We only require XY sample offsets. So, this recommendation doesn't
1623 * look useful at the moment. We might need this in future.
1625 if (wm_prog_data
->uses_pos_offset
)
1626 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1628 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1630 if (wm_prog_data
->base
.total_scratch
) {
1631 wm
.ScratchSpaceBasePointer
=
1632 render_bo(stage_state
->scratch_bo
,
1633 ffs(stage_state
->per_thread_scratch
) - 11);
1636 wm
.PixelShaderComputedDepth
= writes_depth
;
1639 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1642 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1645 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1646 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1650 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1652 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1653 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1654 if (wm_prog_data
->uses_kill
||
1655 _mesa_is_alpha_test_enabled(ctx
) ||
1656 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1657 wm_prog_data
->uses_omask
) {
1658 wm
.PixelShaderKillsPixel
= true;
1661 /* _NEW_BUFFERS | _NEW_COLOR */
1662 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1663 wm_prog_data
->has_side_effects
|| wm
.PixelShaderKillsPixel
) {
1664 wm
.ThreadDispatchEnable
= true;
1666 if (multisampled_fbo
) {
1667 /* _NEW_MULTISAMPLE */
1668 if (ctx
->Multisample
.Enabled
)
1669 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1671 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1673 if (wm_prog_data
->persample_dispatch
)
1674 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1676 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1678 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1679 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1683 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1684 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1687 /* The "UAV access enable" bits are unnecessary on HSW because they only
1688 * seem to have an effect on the HW-assisted coherency mechanism which we
1689 * don't need, and the rasterization-related UAV_ONLY flag and the
1690 * DISPATCH_ENABLE bit can be set independently from it.
1691 * C.f. gen8_upload_ps_extra().
1693 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1697 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1698 wm_prog_data
->has_side_effects
)
1704 /* BRW_NEW_FS_PROG_DATA */
1705 if (wm_prog_data
->early_fragment_tests
)
1706 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1707 else if (wm_prog_data
->has_side_effects
)
1708 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1713 static const struct brw_tracked_state
genX(wm_state
) = {
1717 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1721 (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
1722 .brw
= BRW_NEW_BLORP
|
1723 BRW_NEW_FS_PROG_DATA
|
1724 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
1726 .emit
= genX(upload_wm
),
1730 /* ---------------------------------------------------------------------- */
1733 static inline struct brw_address
1734 KSP(struct brw_context
*brw
, uint32_t offset
)
1736 return instruction_bo(brw
->cache
.bo
, offset
);
1739 static inline uint32_t
1740 KSP(struct brw_context
*brw
, uint32_t offset
)
1746 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1747 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
1748 pkt.SamplerCount = \
1749 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1750 pkt.BindingTableEntryCount = \
1751 stage_prog_data->binding_table.size_bytes / 4; \
1752 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
1754 if (stage_prog_data->total_scratch) { \
1755 pkt.ScratchSpaceBasePointer = \
1756 render_bo(stage_state->scratch_bo, 0); \
1757 pkt.PerThreadScratchSpace = \
1758 ffs(stage_state->per_thread_scratch) - 11; \
1761 pkt.DispatchGRFStartRegisterForURBData = \
1762 stage_prog_data->dispatch_grf_start_reg; \
1763 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1764 pkt.prefix##URBEntryReadOffset = 0; \
1766 pkt.StatisticsEnable = true; \
1770 genX(upload_vs_state
)(struct brw_context
*brw
)
1772 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
1773 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1774 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
1776 /* BRW_NEW_VS_PROG_DATA */
1777 const struct brw_vue_prog_data
*vue_prog_data
=
1778 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
1779 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
1781 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
1782 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
1785 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1786 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1788 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
1789 * command that causes the VS Function Enable to toggle. Pipeline
1790 * flush can be executed by sending a PIPE_CONTROL command with CS
1791 * stall bit set and a post sync operation.
1793 * We've already done such a flush at the start of state upload, so we
1794 * don't need to do another one here.
1796 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
1797 if (stage_state
->push_const_size
!= 0) {
1798 cvs
.Buffer0Valid
= true;
1799 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
1800 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1805 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
1806 gen7_emit_vs_workaround_flush(brw
);
1809 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
1811 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1812 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
1814 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1816 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1819 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
1820 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
1821 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
1823 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
1824 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1826 vs
.MaximumNumberofThreads
=
1827 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
1829 vs
.StatisticsEnable
= false;
1830 vs
.SamplerStatePointer
=
1831 instruction_ro_bo(brw
->batch
.bo
, stage_state
->sampler_offset
);
1835 /* Force single program flow on Ironlake. We cannot reliably get
1836 * all applications working without it. See:
1837 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
1839 * The most notable and reliably failing application is the Humus
1842 vs
.SingleProgramFlow
= true;
1843 vs
.SamplerCount
= 0; /* hardware requirement */
1847 vs
.SIMD8DispatchEnable
=
1848 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
1850 vs
.UserClipDistanceCullTestEnableBitmask
=
1851 vue_prog_data
->cull_distance_mask
;
1856 /* Based on my reading of the simulator, the VS constants don't get
1857 * pulled into the VS FF unit until an appropriate pipeline flush
1858 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
1859 * references to them into a little FIFO. The flushes are common,
1860 * but don't reliably happen between this and a 3DPRIMITIVE, causing
1861 * the primitive to use the wrong constants. Then the FIFO
1862 * containing the constant setup gets added to again on the next
1863 * constants change, and eventually when a flush does happen the
1864 * unit is overwhelmed by constant changes and dies.
1866 * To avoid this, send a PIPE_CONTROL down the line that will
1867 * update the unit immediately loading the constants. The flush
1868 * type bits here were those set by the STATE_BASE_ADDRESS whose
1869 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
1870 * bug reports that led to this workaround, and may be more than
1871 * what is strictly required to avoid the issue.
1873 brw_emit_pipe_control_flush(brw
,
1874 PIPE_CONTROL_DEPTH_STALL
|
1875 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1876 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
1880 static const struct brw_tracked_state
genX(vs_state
) = {
1882 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
1883 .brw
= BRW_NEW_BATCH
|
1886 BRW_NEW_VS_PROG_DATA
|
1887 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
1888 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1889 BRW_NEW_PROGRAM_CACHE
|
1890 BRW_NEW_SAMPLER_STATE_TABLE
|
1894 .emit
= genX(upload_vs_state
),
1897 /* ---------------------------------------------------------------------- */
1900 genX(upload_cc_viewport
)(struct brw_context
*brw
)
1902 struct gl_context
*ctx
= &brw
->ctx
;
1904 /* BRW_NEW_VIEWPORT_COUNT */
1905 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1907 struct GENX(CC_VIEWPORT
) ccv
;
1908 uint32_t cc_vp_offset
;
1910 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
1913 for (unsigned i
= 0; i
< viewport_count
; i
++) {
1914 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
1915 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
1916 if (ctx
->Transform
.DepthClamp
) {
1917 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
1918 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
1920 ccv
.MinimumDepth
= 0.0;
1921 ccv
.MaximumDepth
= 1.0;
1923 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
1924 cc_map
+= GENX(CC_VIEWPORT_length
);
1928 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1929 ptr
.CCViewportPointer
= cc_vp_offset
;
1932 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
1933 vp
.CCViewportStateChange
= 1;
1934 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1937 brw
->cc
.vp_offset
= cc_vp_offset
;
1938 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
1942 const struct brw_tracked_state
genX(cc_vp
) = {
1944 .mesa
= _NEW_TRANSFORM
|
1946 .brw
= BRW_NEW_BATCH
|
1948 BRW_NEW_VIEWPORT_COUNT
,
1950 .emit
= genX(upload_cc_viewport
)
1953 /* ---------------------------------------------------------------------- */
1956 set_scissor_bits(const struct gl_context
*ctx
, int i
,
1957 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
1958 struct GENX(SCISSOR_RECT
) *sc
)
1962 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
1963 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
1964 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
1965 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
1966 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
1968 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
1969 /* If the scissor was out of bounds and got clamped to 0 width/height
1970 * at the bounds, the subtraction of 1 from maximums could produce a
1971 * negative number and thus not clip anything. Instead, just provide
1972 * a min > max scissor inside the bounds, which produces the expected
1975 sc
->ScissorRectangleXMin
= 1;
1976 sc
->ScissorRectangleXMax
= 0;
1977 sc
->ScissorRectangleYMin
= 1;
1978 sc
->ScissorRectangleYMax
= 0;
1979 } else if (render_to_fbo
) {
1980 /* texmemory: Y=0=bottom */
1981 sc
->ScissorRectangleXMin
= bbox
[0];
1982 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
1983 sc
->ScissorRectangleYMin
= bbox
[2];
1984 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
1986 /* memory: Y=0=top */
1987 sc
->ScissorRectangleXMin
= bbox
[0];
1988 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
1989 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
1990 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
1996 genX(upload_scissor_state
)(struct brw_context
*brw
)
1998 struct gl_context
*ctx
= &brw
->ctx
;
1999 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2000 struct GENX(SCISSOR_RECT
) scissor
;
2001 uint32_t scissor_state_offset
;
2002 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2003 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2004 uint32_t *scissor_map
;
2006 /* BRW_NEW_VIEWPORT_COUNT */
2007 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2009 scissor_map
= brw_state_batch(
2010 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2011 32, &scissor_state_offset
);
2013 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2015 /* The scissor only needs to handle the intersection of drawable and
2016 * scissor rect. Clipping to the boundaries of static shared buffers
2017 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2019 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2020 * inclusive but max is exclusive.
2022 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2023 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2024 GENX(SCISSOR_RECT_pack
)(
2025 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2028 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2029 ptr
.ScissorRectPointer
= scissor_state_offset
;
2033 static const struct brw_tracked_state
genX(scissor_state
) = {
2035 .mesa
= _NEW_BUFFERS
|
2038 .brw
= BRW_NEW_BATCH
|
2040 BRW_NEW_VIEWPORT_COUNT
,
2042 .emit
= genX(upload_scissor_state
),
2046 /* ---------------------------------------------------------------------- */
2049 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2050 float m00
, float m11
, float m30
, float m31
,
2051 float *xmin
, float *xmax
,
2052 float *ymin
, float *ymax
)
2054 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2055 * Strips and Fans documentation:
2057 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2058 * fixed-point "guardband" range supported by the rasterization hardware"
2062 * "In almost all circumstances, if an object’s vertices are actually
2063 * modified by this clamping (i.e., had X or Y coordinates outside of
2064 * the guardband extent the rendered object will not match the intended
2065 * result. Therefore software should take steps to ensure that this does
2066 * not happen - e.g., by clipping objects such that they do not exceed
2067 * these limits after the Drawing Rectangle is applied."
2069 * I believe the fundamental restriction is that the rasterizer (in
2070 * the SF/WM stages) have a limit on the number of pixels that can be
2071 * rasterized. We need to ensure any coordinates beyond the rasterizer
2072 * limit are handled by the clipper. So effectively that limit becomes
2073 * the clipper's guardband size.
2075 * It goes on to say:
2077 * "In addition, in order to be correctly rendered, objects must have a
2078 * screenspace bounding box not exceeding 8K in the X or Y direction.
2079 * This additional restriction must also be comprehended by software,
2080 * i.e., enforced by use of clipping."
2082 * This makes no sense. Gen7+ hardware supports 16K render targets,
2083 * and you definitely need to be able to draw polygons that fill the
2084 * surface. Our assumption is that the rasterizer was limited to 8K
2085 * on Sandybridge, which only supports 8K surfaces, and it was actually
2086 * increased to 16K on Ivybridge and later.
2088 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2090 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2092 if (m00
!= 0 && m11
!= 0) {
2093 /* First, we compute the screen-space render area */
2094 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2095 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2096 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2097 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2099 /* We want the guardband to be centered on that */
2100 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2101 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2102 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2103 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2105 /* Now we need it in native device coordinates */
2106 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2107 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2108 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2109 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2111 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2112 * flipped upside-down. X should be fine though.
2114 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2115 *xmin
= ndc_gb_xmin
;
2116 *xmax
= ndc_gb_xmax
;
2117 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2118 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2120 /* The viewport scales to 0, so nothing will be rendered. */
2129 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2131 struct gl_context
*ctx
= &brw
->ctx
;
2132 float y_scale
, y_bias
;
2134 /* BRW_NEW_VIEWPORT_COUNT */
2135 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2138 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2139 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2140 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2144 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2145 uint32_t sf_clip_vp_offset
;
2146 uint32_t *sf_clip_map
=
2147 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2148 64, &sf_clip_vp_offset
);
2150 struct GENX(SF_VIEWPORT
) sfv
;
2151 struct GENX(CLIP_VIEWPORT
) clv
;
2152 uint32_t sf_vp_offset
, clip_vp_offset
;
2154 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2156 uint32_t *clip_map
=
2157 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2158 32, &clip_vp_offset
);
2162 if (render_to_fbo
) {
2167 y_bias
= (float)fb_height
;
2170 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2171 /* _NEW_VIEWPORT: Guardband Clipping */
2172 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2173 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2175 sfv
.ViewportMatrixElementm00
= scale
[0];
2176 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2177 sfv
.ViewportMatrixElementm22
= scale
[2],
2178 sfv
.ViewportMatrixElementm30
= translate
[0],
2179 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2180 sfv
.ViewportMatrixElementm32
= translate
[2],
2181 brw_calculate_guardband_size(fb_width
, fb_height
,
2182 sfv
.ViewportMatrixElementm00
,
2183 sfv
.ViewportMatrixElementm11
,
2184 sfv
.ViewportMatrixElementm30
,
2185 sfv
.ViewportMatrixElementm31
,
2186 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2189 clv
.XMinClipGuardband
= gb_xmin
;
2190 clv
.XMaxClipGuardband
= gb_xmax
;
2191 clv
.YMinClipGuardband
= gb_ymin
;
2192 clv
.YMaxClipGuardband
= gb_ymax
;
2195 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2196 &sfv
.ScissorRectangle
);
2198 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2199 * The hardware will take the intersection of the drawing rectangle,
2200 * scissor rectangle, and the viewport extents. We don't need to be
2201 * smart, and can therefore just program the viewport extents.
2203 const float viewport_Xmax
=
2204 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2205 const float viewport_Ymax
=
2206 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2208 if (render_to_fbo
) {
2209 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2210 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2211 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2212 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2214 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2215 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2216 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2217 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2222 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2223 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2225 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2226 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2227 sf_map
+= GENX(SF_VIEWPORT_length
);
2228 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2233 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2234 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2237 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2238 vp
.SFViewportStateChange
= 1;
2239 vp
.CLIPViewportStateChange
= 1;
2240 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2241 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2244 brw
->sf
.vp_offset
= sf_vp_offset
;
2245 brw
->clip
.vp_offset
= clip_vp_offset
;
2246 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2250 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2252 .mesa
= _NEW_BUFFERS
|
2254 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2255 .brw
= BRW_NEW_BATCH
|
2257 BRW_NEW_VIEWPORT_COUNT
,
2259 .emit
= genX(upload_sf_clip_viewport
),
2262 /* ---------------------------------------------------------------------- */
2266 genX(upload_gs_state
)(struct brw_context
*brw
)
2268 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2269 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2270 /* BRW_NEW_GEOMETRY_PROGRAM */
2271 bool active
= brw
->geometry_program
;
2273 /* BRW_NEW_GS_PROG_DATA */
2274 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2275 const struct brw_vue_prog_data
*vue_prog_data
=
2276 brw_vue_prog_data(stage_prog_data
);
2278 const struct brw_gs_prog_data
*gs_prog_data
=
2279 brw_gs_prog_data(stage_prog_data
);
2283 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2284 if (active
&& stage_state
->push_const_size
!= 0) {
2285 cgs
.Buffer0Valid
= true;
2286 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2287 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2292 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2294 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2295 * Geometry > Geometry Shader > State:
2297 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2298 * whole fixed function pipeline when the GS enable changes value in
2301 * The hardware architects have clarified that in this context "flush the
2302 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2305 if (brw
->gt
== 2 && brw
->gs
.enabled
!= active
)
2306 gen7_emit_cs_stall_flush(brw
);
2310 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2311 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2314 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2315 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2316 gs
.ControlDataHeaderSize
=
2317 gs_prog_data
->control_data_header_size_hwords
;
2319 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2320 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2322 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2324 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2327 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2328 * Ivy Bridge and Haswell.
2330 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2331 * strip to be delivered to the geometry shader in an order that does
2332 * not strictly follow the OpenGL spec, but preserves triangle
2333 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2334 * the geometry shader sees triangles:
2336 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2338 * (Clearing the bit is even worse, because it fails to preserve
2341 * Triangle strips with adjacency always ordered in a way that preserves
2342 * triangle orientation but does not strictly follow the OpenGL spec,
2343 * regardless of the setting of this bit.
2345 * On Haswell, both triangle strips and triangle strips with adjacency
2346 * are always ordered in a way that preserves triangle orientation.
2347 * Setting this bit causes the ordering to strictly follow the OpenGL
2350 * So in either case we want to set the bit. Unfortunately on Ivy
2351 * Bridge this will get the order close to correct but not perfect.
2353 gs
.ReorderMode
= TRAILING
;
2354 gs
.MaximumNumberofThreads
=
2355 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2356 : (devinfo
->max_gs_threads
- 1);
2359 gs
.SOStatisticsEnable
= true;
2360 gs
.RenderingEnabled
= 1;
2361 if (brw
->geometry_program
->info
.has_transform_feedback_varyings
)
2362 gs
.SVBIPayloadEnable
= true;
2364 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2365 * was previously done for gen6.
2367 * TODO: test with both disabled to see if the HW is behaving
2368 * as expected, like in gen7.
2370 gs
.SingleProgramFlow
= true;
2371 gs
.VectorMaskEnable
= true;
2375 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2377 if (gs_prog_data
->static_vertex_count
!= -1) {
2378 gs
.StaticOutput
= true;
2379 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2381 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2383 gs
.UserClipDistanceCullTestEnableBitmask
=
2384 vue_prog_data
->cull_distance_mask
;
2386 const int urb_entry_write_offset
= 1;
2387 const uint32_t urb_entry_output_length
=
2388 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2389 urb_entry_write_offset
;
2391 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2392 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2396 } else if (brw
->ff_gs
.prog_active
) {
2397 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
2398 * program. This function provides the needed 3DSTATE_GS for this.
2400 upload_gs_state_for_tf(brw
);
2403 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2404 gs
.StatisticsEnable
= true;
2406 gs
.RenderingEnabled
= true;
2410 gs
.DispatchGRFStartRegisterForURBData
= 1;
2412 gs
.IncludeVertexHandles
= true;
2418 brw
->gs
.enabled
= active
;
2422 static const struct brw_tracked_state
genX(gs_state
) = {
2424 .mesa
= (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
2425 .brw
= BRW_NEW_BATCH
|
2428 BRW_NEW_GEOMETRY_PROGRAM
|
2429 BRW_NEW_GS_PROG_DATA
|
2430 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2432 .emit
= genX(upload_gs_state
),
2436 /* ---------------------------------------------------------------------- */
2438 UNUSED
static GLenum
2439 fix_dual_blend_alpha_to_one(GLenum function
)
2445 case GL_ONE_MINUS_SRC1_ALPHA
:
2452 #define blend_factor(x) brw_translate_blend_factor(x)
2453 #define blend_eqn(x) brw_translate_blend_equation(x)
2457 genX(upload_blend_state
)(struct brw_context
*brw
)
2459 struct gl_context
*ctx
= &brw
->ctx
;
2462 /* We need at least one BLEND_STATE written, because we might do
2463 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2464 * for computed depth or alpha test), which will do an FB write
2465 * with render target 0, which will reference BLEND_STATE[0] for
2466 * alpha test enable.
2468 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2469 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2470 nr_draw_buffers
= 1;
2472 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2474 size
+= GENX(BLEND_STATE_length
) * 4;
2477 uint32_t *blend_map
;
2478 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2481 struct GENX(BLEND_STATE
) blend
= { 0 };
2484 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2485 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2488 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2489 * "If drawbuffer zero is not NONE and the buffer it references has an
2490 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2491 * operations are skipped."
2493 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2494 /* _NEW_MULTISAMPLE */
2495 if (_mesa_is_multisample_enabled(ctx
)) {
2496 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2497 blend
.AlphaToCoverageEnable
= true;
2498 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2500 if (ctx
->Multisample
.SampleAlphaToOne
)
2501 blend
.AlphaToOneEnable
= true;
2505 if (ctx
->Color
.AlphaEnabled
) {
2506 blend
.AlphaTestEnable
= true;
2507 blend
.AlphaTestFunction
=
2508 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2511 if (ctx
->Color
.DitherFlag
) {
2512 blend
.ColorDitherEnable
= true;
2517 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2518 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2524 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2526 /* Used for implementing the following bit of GL_EXT_texture_integer:
2527 * "Per-fragment operations that require floating-point color
2528 * components, including multisample alpha operations, alpha test,
2529 * blending, and dithering, have no effect when the corresponding
2530 * colors are written to an integer color buffer."
2532 bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2535 if (ctx
->Color
.ColorLogicOpEnabled
) {
2536 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2537 : GL_UNSIGNED_NORMALIZED
;
2538 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2539 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2540 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2542 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2543 _mesa_enum_to_string(rb_type
));
2544 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2545 entry
.LogicOpEnable
= true;
2546 entry
.LogicOpFunction
=
2547 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2549 } else if (ctx
->Color
.BlendEnabled
& (1 << i
) && !integer
&&
2550 !ctx
->Color
._AdvancedBlendMode
) {
2551 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2552 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2553 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2554 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2555 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2556 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2558 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2559 srcRGB
= dstRGB
= GL_ONE
;
2561 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2562 srcA
= dstA
= GL_ONE
;
2564 /* Due to hardware limitations, the destination may have information
2565 * in an alpha channel even when the format specifies no alpha
2566 * channel. In order to avoid getting any incorrect blending due to
2567 * that alpha channel, coerce the blend factors to values that will
2568 * not read the alpha channel, but will instead use the correct
2569 * implicit value for alpha.
2571 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2572 GL_TEXTURE_ALPHA_TYPE
)) {
2573 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2574 srcA
= brw_fix_xRGB_alpha(srcA
);
2575 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2576 dstA
= brw_fix_xRGB_alpha(dstA
);
2579 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2580 * "If Dual Source Blending is enabled, this bit must be disabled."
2582 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2583 * and leave it enabled anyway.
2585 if (ctx
->Color
.Blend
[i
]._UsesDualSrc
&& blend
.AlphaToOneEnable
) {
2586 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2587 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2588 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2589 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2592 entry
.ColorBufferBlendEnable
= true;
2593 entry
.DestinationBlendFactor
= blend_factor(dstRGB
);
2594 entry
.SourceBlendFactor
= blend_factor(srcRGB
);
2595 entry
.DestinationAlphaBlendFactor
= blend_factor(dstA
);
2596 entry
.SourceAlphaBlendFactor
= blend_factor(srcA
);
2597 entry
.ColorBlendFunction
= blend_eqn(eqRGB
);
2598 entry
.AlphaBlendFunction
= blend_eqn(eqA
);
2600 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2601 blend
.IndependentAlphaBlendEnable
= true;
2604 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2605 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2607 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2608 * clamping in the fragment shader. For its clamping of
2609 * blending, the spec says:
2611 * "RESOLVED: For fixed-point color buffers, the inputs and
2612 * the result of the blending equation are clamped. For
2613 * floating-point color buffers, no clamping occurs."
2615 * So, generally, we want clamping to the render target's range.
2616 * And, good news, the hardware tables for both pre- and
2617 * post-blend color clamping are either ignored, or any are
2618 * allowed, or clamping is required but RT range clamping is a
2621 entry
.PreBlendColorClampEnable
= true;
2622 entry
.PostBlendColorClampEnable
= true;
2623 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2625 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2626 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2627 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2628 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2631 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2633 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2639 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2643 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2644 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2645 ptr
.BLEND_STATEChange
= true;
2648 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2649 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2651 ptr
.BlendStatePointerValid
= true;
2657 static const struct brw_tracked_state
genX(blend_state
) = {
2659 .mesa
= _NEW_BUFFERS
|
2662 .brw
= BRW_NEW_BATCH
|
2664 BRW_NEW_STATE_BASE_ADDRESS
,
2666 .emit
= genX(upload_blend_state
),
2670 /* ---------------------------------------------------------------------- */
2673 UNUSED
static const uint32_t push_constant_opcodes
[] = {
2674 [MESA_SHADER_VERTEX
] = 21,
2675 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2676 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2677 [MESA_SHADER_GEOMETRY
] = 22,
2678 [MESA_SHADER_FRAGMENT
] = 23,
2679 [MESA_SHADER_COMPUTE
] = 0,
2683 upload_constant_state(struct brw_context
*brw
,
2684 struct brw_stage_state
*stage_state
,
2685 bool active
, uint32_t stage
)
2687 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
2688 active
= active
&& stage_state
->push_const_size
!= 0;
2690 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2691 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2693 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2694 pkt
.ConstantBody
.ReadLength
[2] = stage_state
->push_const_size
;
2695 pkt
.ConstantBody
.Buffer
[2] =
2696 render_ro_bo(brw
->curbe
.curbe_bo
, stage_state
->push_const_offset
);
2698 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
2699 pkt
.ConstantBody
.Buffer
[0].offset
=
2700 stage_state
->push_const_offset
| mocs
;
2705 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
2711 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
2713 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2715 /* _BRW_NEW_VERTEX_PROGRAM */
2716 const struct brw_program
*vp
= brw_program_const(brw
->vertex_program
);
2717 /* BRW_NEW_VS_PROG_DATA */
2718 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
2720 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
2721 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
2724 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !brw
->is_baytrail
)
2725 gen7_emit_vs_workaround_flush(brw
);
2727 upload_constant_state(brw
, stage_state
, true /* active */,
2728 MESA_SHADER_VERTEX
);
2732 static const struct brw_tracked_state
genX(vs_push_constants
) = {
2734 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2736 .brw
= BRW_NEW_BATCH
|
2738 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2739 BRW_NEW_VERTEX_PROGRAM
|
2740 BRW_NEW_VS_PROG_DATA
,
2742 .emit
= genX(upload_vs_push_constants
),
2746 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
2748 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2750 /* BRW_NEW_GEOMETRY_PROGRAM */
2751 const struct brw_program
*gp
= brw_program_const(brw
->geometry_program
);
2754 /* BRW_NEW_GS_PROG_DATA */
2755 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
2757 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
2758 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
2762 upload_constant_state(brw
, stage_state
, gp
, MESA_SHADER_GEOMETRY
);
2766 static const struct brw_tracked_state
genX(gs_push_constants
) = {
2768 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2770 .brw
= BRW_NEW_BATCH
|
2772 BRW_NEW_GEOMETRY_PROGRAM
|
2773 BRW_NEW_GS_PROG_DATA
|
2774 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2776 .emit
= genX(upload_gs_push_constants
),
2780 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
2782 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
2783 /* BRW_NEW_FRAGMENT_PROGRAM */
2784 const struct brw_program
*fp
= brw_program_const(brw
->fragment_program
);
2785 /* BRW_NEW_FS_PROG_DATA */
2786 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
2788 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
2790 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
2793 upload_constant_state(brw
, stage_state
, true, MESA_SHADER_FRAGMENT
);
2797 static const struct brw_tracked_state
genX(wm_push_constants
) = {
2799 .mesa
= _NEW_PROGRAM_CONSTANTS
,
2800 .brw
= BRW_NEW_BATCH
|
2802 BRW_NEW_FRAGMENT_PROGRAM
|
2803 BRW_NEW_FS_PROG_DATA
|
2804 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2806 .emit
= genX(upload_wm_push_constants
),
2810 /* ---------------------------------------------------------------------- */
2814 genX(determine_sample_mask
)(struct brw_context
*brw
)
2816 struct gl_context
*ctx
= &brw
->ctx
;
2817 float coverage
= 1.0f
;
2818 float coverage_invert
= false;
2819 unsigned sample_mask
= ~0u;
2821 /* BRW_NEW_NUM_SAMPLES */
2822 unsigned num_samples
= brw
->num_samples
;
2824 if (_mesa_is_multisample_enabled(ctx
)) {
2825 if (ctx
->Multisample
.SampleCoverage
) {
2826 coverage
= ctx
->Multisample
.SampleCoverageValue
;
2827 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
2829 if (ctx
->Multisample
.SampleMask
) {
2830 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
2834 if (num_samples
> 1) {
2835 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
2836 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
2837 if (coverage_invert
)
2838 coverage_bits
^= (1 << num_samples
) - 1;
2839 return coverage_bits
& sample_mask
;
2846 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
2847 unsigned num_samples
)
2849 assert(brw
->num_samples
<= 16);
2851 unsigned log2_samples
= ffs(MAX2(num_samples
, 1)) - 1;
2853 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
2854 multi
.PixelLocation
= CENTER
;
2855 multi
.NumberofMultisamples
= log2_samples
;
2857 GEN_SAMPLE_POS_4X(multi
.Sample
);
2859 switch (num_samples
) {
2861 GEN_SAMPLE_POS_1X(multi
.Sample
);
2864 GEN_SAMPLE_POS_2X(multi
.Sample
);
2867 GEN_SAMPLE_POS_4X(multi
.Sample
);
2870 GEN_SAMPLE_POS_8X(multi
.Sample
);
2880 genX(upload_multisample_state
)(struct brw_context
*brw
)
2882 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
2884 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
2885 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
2889 static const struct brw_tracked_state
genX(multisample_state
) = {
2891 .mesa
= _NEW_MULTISAMPLE
,
2892 .brw
= BRW_NEW_BLORP
|
2894 BRW_NEW_NUM_SAMPLES
,
2896 .emit
= genX(upload_multisample_state
)
2900 /* ---------------------------------------------------------------------- */
2904 genX(upload_color_calc_state
)(struct brw_context
*brw
)
2906 struct gl_context
*ctx
= &brw
->ctx
;
2908 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
2910 cc
.AlphaTestFormat
= ALPHATEST_UNORM8
;
2911 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
2912 ctx
->Color
.AlphaRef
);
2916 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
2917 cc
.BackfaceStencilReferenceValue
=
2918 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
2922 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
2923 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
2924 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
2925 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
2928 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2929 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
2931 ptr
.ColorCalcStatePointerValid
= true;
2936 static const struct brw_tracked_state
genX(color_calc_state
) = {
2938 .mesa
= _NEW_COLOR
|
2940 .brw
= BRW_NEW_BATCH
|
2943 BRW_NEW_STATE_BASE_ADDRESS
,
2945 .emit
= genX(upload_color_calc_state
),
2950 /* ---------------------------------------------------------------------- */
2954 genX(upload_sbe
)(struct brw_context
*brw
)
2956 struct gl_context
*ctx
= &brw
->ctx
;
2957 /* BRW_NEW_FS_PROG_DATA */
2958 const struct brw_wm_prog_data
*wm_prog_data
=
2959 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
2961 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
2963 #define attr_overrides sbe.Attribute
2965 uint32_t urb_entry_read_length
;
2966 uint32_t urb_entry_read_offset
;
2967 uint32_t point_sprite_enables
;
2969 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
2970 sbe
.AttributeSwizzleEnable
= true;
2971 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2974 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2978 * Window coordinates in an FBO are inverted, which means point
2979 * sprite origin must be inverted.
2981 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
2982 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
2984 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
2986 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
2987 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
2988 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
2989 * BRW_NEW_VUE_MAP_GEOM_OUT
2991 genX(calculate_attr_overrides
)(brw
,
2993 &point_sprite_enables
,
2994 &urb_entry_read_length
,
2995 &urb_entry_read_offset
);
2997 /* Typically, the URB entry read length and offset should be programmed
2998 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
2999 * stage which produces geometry. However, we don't know the proper
3000 * value until we call calculate_attr_overrides().
3002 * To fit with our existing code, we override the inherited values and
3003 * specify it here directly, as we did on previous generations.
3005 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3006 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3007 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3008 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3011 sbe
.ForceVertexURBEntryReadLength
= true;
3012 sbe
.ForceVertexURBEntryReadOffset
= true;
3016 /* prepare the active component dwords */
3017 int input_index
= 0;
3018 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
3019 if (!(brw
->fragment_program
->info
.inputs_read
&
3020 BITFIELD64_BIT(attr
))) {
3024 assert(input_index
< 32);
3026 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3033 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3034 for (int i
= 0; i
< 16; i
++)
3035 sbes
.Attribute
[i
] = attr_overrides
[i
];
3039 #undef attr_overrides
3042 static const struct brw_tracked_state
genX(sbe_state
) = {
3044 .mesa
= _NEW_BUFFERS
|
3049 .brw
= BRW_NEW_BLORP
|
3051 BRW_NEW_FRAGMENT_PROGRAM
|
3052 BRW_NEW_FS_PROG_DATA
|
3053 BRW_NEW_GS_PROG_DATA
|
3054 BRW_NEW_TES_PROG_DATA
|
3055 BRW_NEW_VUE_MAP_GEOM_OUT
|
3056 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3059 .emit
= genX(upload_sbe
),
3063 /* ---------------------------------------------------------------------- */
3067 * Outputs the 3DSTATE_SO_DECL_LIST command.
3069 * The data output is a series of 64-bit entries containing a SO_DECL per
3070 * stream. We only have one stream of rendering coming out of the GS unit, so
3071 * we only emit stream 0 (low 16 bits) SO_DECLs.
3074 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3075 const struct brw_vue_map
*vue_map
)
3077 struct gl_context
*ctx
= &brw
->ctx
;
3078 /* BRW_NEW_TRANSFORM_FEEDBACK */
3079 struct gl_transform_feedback_object
*xfb_obj
=
3080 ctx
->TransformFeedback
.CurrentObject
;
3081 const struct gl_transform_feedback_info
*linked_xfb_info
=
3082 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3083 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3084 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3085 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3086 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3088 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3090 memset(so_decl
, 0, sizeof(so_decl
));
3092 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3093 * command feels strange -- each dword pair contains a SO_DECL per stream.
3095 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3096 const struct gl_transform_feedback_output
*output
=
3097 &linked_xfb_info
->Outputs
[i
];
3098 const int buffer
= output
->OutputBuffer
;
3099 const int varying
= output
->OutputRegister
;
3100 const unsigned stream_id
= output
->StreamId
;
3101 assert(stream_id
< MAX_VERTEX_STREAMS
);
3103 buffer_mask
[stream_id
] |= 1 << buffer
;
3105 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3107 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3108 * array. Instead, it simply increments DstOffset for the following
3109 * input by the number of components that should be skipped.
3111 * Our hardware is unusual in that it requires us to program SO_DECLs
3112 * for fake "hole" components, rather than simply taking the offset
3113 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3114 * program as many size = 4 holes as we can, then a final hole to
3115 * accommodate the final 1, 2, or 3 remaining.
3117 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3119 while (skip_components
> 0) {
3120 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3122 .OutputBufferSlot
= output
->OutputBuffer
,
3123 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3125 skip_components
-= 4;
3128 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3130 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3131 .OutputBufferSlot
= output
->OutputBuffer
,
3132 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3134 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3137 if (decls
[stream_id
] > max_decls
)
3138 max_decls
= decls
[stream_id
];
3142 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3143 .StreamtoBufferSelects0
= buffer_mask
[0],
3144 .StreamtoBufferSelects1
= buffer_mask
[1],
3145 .StreamtoBufferSelects2
= buffer_mask
[2],
3146 .StreamtoBufferSelects3
= buffer_mask
[3],
3147 .NumEntries0
= decls
[0],
3148 .NumEntries1
= decls
[1],
3149 .NumEntries2
= decls
[2],
3150 .NumEntries3
= decls
[3]);
3152 for (int i
= 0; i
< max_decls
; i
++) {
3153 GENX(SO_DECL_ENTRY_pack
)(
3154 brw
, dw
+ 2 + i
* 2,
3155 &(struct GENX(SO_DECL_ENTRY
)) {
3156 .Stream0Decl
= so_decl
[0][i
],
3157 .Stream1Decl
= so_decl
[1][i
],
3158 .Stream2Decl
= so_decl
[2][i
],
3159 .Stream3Decl
= so_decl
[3][i
],
3165 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3167 struct gl_context
*ctx
= &brw
->ctx
;
3168 /* BRW_NEW_TRANSFORM_FEEDBACK */
3169 struct gl_transform_feedback_object
*xfb_obj
=
3170 ctx
->TransformFeedback
.CurrentObject
;
3172 const struct gl_transform_feedback_info
*linked_xfb_info
=
3173 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3175 struct brw_transform_feedback_object
*brw_obj
=
3176 (struct brw_transform_feedback_object
*) xfb_obj
;
3177 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3180 /* Set up the up to 4 output buffers. These are the ranges defined in the
3181 * gl_transform_feedback_object.
3183 for (int i
= 0; i
< 4; i
++) {
3184 struct intel_buffer_object
*bufferobj
=
3185 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3188 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3189 sob
.SOBufferIndex
= i
;
3194 uint32_t start
= xfb_obj
->Offset
[i
];
3195 assert(start
% 4 == 0);
3196 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3198 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
);
3199 assert(end
<= bo
->size
);
3201 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3202 sob
.SOBufferIndex
= i
;
3204 sob
.SurfaceBaseAddress
= render_bo(bo
, start
);
3206 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3207 sob
.SurfaceEndAddress
= render_bo(bo
, end
);
3209 sob
.SOBufferEnable
= true;
3210 sob
.StreamOffsetWriteEnable
= true;
3211 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3212 sob
.SOBufferMOCS
= mocs_wb
;
3214 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3215 sob
.StreamOutputBufferOffsetAddress
=
3216 instruction_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3218 if (brw_obj
->zero_offsets
) {
3219 /* Zero out the offset and write that to offset_bo */
3220 sob
.StreamOffset
= 0;
3222 /* Use offset_bo as the "Stream Offset." */
3223 sob
.StreamOffset
= 0xFFFFFFFF;
3230 brw_obj
->zero_offsets
= false;
3235 query_active(struct gl_query_object
*q
)
3237 return q
&& q
->Active
;
3241 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3242 const struct brw_vue_map
*vue_map
)
3244 struct gl_context
*ctx
= &brw
->ctx
;
3245 /* BRW_NEW_TRANSFORM_FEEDBACK */
3246 struct gl_transform_feedback_object
*xfb_obj
=
3247 ctx
->TransformFeedback
.CurrentObject
;
3249 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3251 int urb_entry_read_offset
= 0;
3252 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3253 urb_entry_read_offset
;
3255 sos
.SOFunctionEnable
= true;
3256 sos
.SOStatisticsEnable
= true;
3258 /* BRW_NEW_RASTERIZER_DISCARD */
3259 if (ctx
->RasterDiscard
) {
3260 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3261 sos
.RenderingDisable
= true;
3263 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3264 "query active relies on the clipper.");
3269 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3270 sos
.ReorderMode
= TRAILING
;
3273 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3274 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3275 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3276 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3278 const struct gl_transform_feedback_info
*linked_xfb_info
=
3279 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3280 /* Set buffer pitches; 0 means unbound. */
3281 if (xfb_obj
->Buffers
[0])
3282 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3283 if (xfb_obj
->Buffers
[1])
3284 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3285 if (xfb_obj
->Buffers
[2])
3286 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3287 if (xfb_obj
->Buffers
[3])
3288 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3291 /* We always read the whole vertex. This could be reduced at some
3292 * point by reading less and offsetting the register index in the
3295 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3296 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3297 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3298 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3299 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3300 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3301 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3302 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3308 genX(upload_sol
)(struct brw_context
*brw
)
3310 struct gl_context
*ctx
= &brw
->ctx
;
3311 /* BRW_NEW_TRANSFORM_FEEDBACK */
3312 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3315 genX(upload_3dstate_so_buffers
)(brw
);
3317 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3318 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3321 /* Finally, set up the SOL stage. This command must always follow updates to
3322 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3323 * MMIO register updates (current performed by the kernel at each batch
3326 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3329 static const struct brw_tracked_state
genX(sol_state
) = {
3332 .brw
= BRW_NEW_BATCH
|
3334 BRW_NEW_RASTERIZER_DISCARD
|
3335 BRW_NEW_VUE_MAP_GEOM_OUT
|
3336 BRW_NEW_TRANSFORM_FEEDBACK
,
3338 .emit
= genX(upload_sol
),
3342 /* ---------------------------------------------------------------------- */
3346 genX(upload_ps
)(struct brw_context
*brw
)
3348 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3349 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3351 /* BRW_NEW_FS_PROG_DATA */
3352 const struct brw_wm_prog_data
*prog_data
=
3353 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3354 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3359 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3360 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3361 * incorrect for subspans where some of the pixels are unlit. We believe
3362 * the bit just didn't take effect in previous generations.
3364 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3367 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3369 /* BRW_NEW_FS_PROG_DATA */
3370 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3372 if (prog_data
->base
.use_alt_mode
)
3373 ps
.FloatingPointMode
= Alternate
;
3375 /* Haswell requires the sample mask to be set in this packet as well as
3376 * in 3DSTATE_SAMPLE_MASK; the values should match.
3379 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3381 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3384 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3385 * it implicitly scales for different GT levels (which have some # of
3388 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3391 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3393 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3395 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3398 if (prog_data
->base
.nr_params
> 0)
3399 ps
.PushConstantEnable
= true;
3402 /* From the IVB PRM, volume 2 part 1, page 287:
3403 * "This bit is inserted in the PS payload header and made available to
3404 * the DataPort (either via the message header or via header bypass) to
3405 * indicate that oMask data (one or two phases) is included in Render
3406 * Target Write messages. If present, the oMask data is used to mask off
3409 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3411 /* The hardware wedges if you have this bit set but don't turn on any
3412 * dual source blend factors.
3414 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3416 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3417 (ctx
->Color
.BlendEnabled
& 1) &&
3418 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3420 /* BRW_NEW_FS_PROG_DATA */
3421 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3424 /* From the documentation for this packet:
3425 * "If the PS kernel does not need the Position XY Offsets to
3426 * compute a Position Value, then this field should be programmed
3427 * to POSOFFSET_NONE."
3429 * "SW Recommendation: If the PS kernel needs the Position Offsets
3430 * to compute a Position XY value, this field should match Position
3431 * ZW Interpolation Mode to ensure a consistent position.xyzw
3434 * We only require XY sample offsets. So, this recommendation doesn't
3435 * look useful at the moment. We might need this in future.
3437 if (prog_data
->uses_pos_offset
)
3438 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3440 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3442 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3443 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3444 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3445 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3446 prog_data
->base
.dispatch_grf_start_reg
;
3447 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3448 prog_data
->dispatch_grf_start_reg_2
;
3450 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3451 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3452 prog_data
->prog_offset_2
;
3454 if (prog_data
->base
.total_scratch
) {
3455 ps
.ScratchSpaceBasePointer
=
3456 render_bo(stage_state
->scratch_bo
,
3457 ffs(stage_state
->per_thread_scratch
) - 11);
3462 static const struct brw_tracked_state
genX(ps_state
) = {
3464 .mesa
= _NEW_MULTISAMPLE
|
3465 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3468 .brw
= BRW_NEW_BATCH
|
3470 BRW_NEW_FS_PROG_DATA
,
3472 .emit
= genX(upload_ps
),
3476 /* ---------------------------------------------------------------------- */
3480 genX(upload_hs_state
)(struct brw_context
*brw
)
3482 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3483 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3484 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3485 const struct brw_vue_prog_data
*vue_prog_data
=
3486 brw_vue_prog_data(stage_prog_data
);
3488 /* BRW_NEW_TES_PROG_DATA */
3489 struct brw_tcs_prog_data
*tcs_prog_data
=
3490 brw_tcs_prog_data(stage_prog_data
);
3492 if (!tcs_prog_data
) {
3493 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3495 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3496 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3498 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3499 hs
.IncludeVertexHandles
= true;
3501 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3506 static const struct brw_tracked_state
genX(hs_state
) = {
3509 .brw
= BRW_NEW_BATCH
|
3511 BRW_NEW_TCS_PROG_DATA
|
3512 BRW_NEW_TESS_PROGRAMS
,
3514 .emit
= genX(upload_hs_state
),
3518 genX(upload_ds_state
)(struct brw_context
*brw
)
3520 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3521 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3522 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3524 /* BRW_NEW_TES_PROG_DATA */
3525 const struct brw_tes_prog_data
*tes_prog_data
=
3526 brw_tes_prog_data(stage_prog_data
);
3527 const struct brw_vue_prog_data
*vue_prog_data
=
3528 brw_vue_prog_data(stage_prog_data
);
3530 if (!tes_prog_data
) {
3531 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3533 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3534 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3536 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3537 ds
.ComputeWCoordinateEnable
=
3538 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3541 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3542 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3543 ds
.UserClipDistanceCullTestEnableBitmask
=
3544 vue_prog_data
->cull_distance_mask
;
3550 static const struct brw_tracked_state
genX(ds_state
) = {
3553 .brw
= BRW_NEW_BATCH
|
3555 BRW_NEW_TESS_PROGRAMS
|
3556 BRW_NEW_TES_PROG_DATA
,
3558 .emit
= genX(upload_ds_state
),
3561 /* ---------------------------------------------------------------------- */
3564 upload_te_state(struct brw_context
*brw
)
3566 /* BRW_NEW_TESS_PROGRAMS */
3567 bool active
= brw
->tess_eval_program
;
3569 /* BRW_NEW_TES_PROG_DATA */
3570 const struct brw_tes_prog_data
*tes_prog_data
=
3571 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
3574 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
3575 te
.Partitioning
= tes_prog_data
->partitioning
;
3576 te
.OutputTopology
= tes_prog_data
->output_topology
;
3577 te
.TEDomain
= tes_prog_data
->domain
;
3579 te
.MaximumTessellationFactorOdd
= 63.0;
3580 te
.MaximumTessellationFactorNotOdd
= 64.0;
3583 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
3587 static const struct brw_tracked_state
genX(te_state
) = {
3590 .brw
= BRW_NEW_BLORP
|
3592 BRW_NEW_TES_PROG_DATA
|
3593 BRW_NEW_TESS_PROGRAMS
,
3595 .emit
= upload_te_state
,
3598 /* ---------------------------------------------------------------------- */
3601 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
3603 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3604 /* BRW_NEW_TESS_PROGRAMS */
3605 const struct brw_program
*tep
= brw_program_const(brw
->tess_eval_program
);
3608 /* BRW_NEW_TES_PROG_DATA */
3609 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
3610 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
3611 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
3614 upload_constant_state(brw
, stage_state
, tep
, MESA_SHADER_TESS_EVAL
);
3617 static const struct brw_tracked_state
genX(tes_push_constants
) = {
3619 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3620 .brw
= BRW_NEW_BATCH
|
3622 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3623 BRW_NEW_TESS_PROGRAMS
|
3624 BRW_NEW_TES_PROG_DATA
,
3626 .emit
= genX(upload_tes_push_constants
),
3630 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
3632 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3633 /* BRW_NEW_TESS_PROGRAMS */
3634 const struct brw_program
*tcp
= brw_program_const(brw
->tess_ctrl_program
);
3635 bool active
= brw
->tess_eval_program
;
3638 /* BRW_NEW_TCS_PROG_DATA */
3639 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
3641 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
3642 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
3645 upload_constant_state(brw
, stage_state
, active
, MESA_SHADER_TESS_CTRL
);
3648 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
3650 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3651 .brw
= BRW_NEW_BATCH
|
3653 BRW_NEW_DEFAULT_TESS_LEVELS
|
3654 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3655 BRW_NEW_TESS_PROGRAMS
|
3656 BRW_NEW_TCS_PROG_DATA
,
3658 .emit
= genX(upload_tcs_push_constants
),
3663 /* ---------------------------------------------------------------------- */
3667 genX(upload_cs_state
)(struct brw_context
*brw
)
3669 if (!brw
->cs
.base
.prog_data
)
3673 uint32_t *desc
= (uint32_t*) brw_state_batch(
3674 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
3677 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
3678 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
3679 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3680 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3682 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
3683 brw_emit_buffer_surface_state(
3684 brw
, &stage_state
->surf_offset
[
3685 prog_data
->binding_table
.shader_time_start
],
3686 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
3687 brw
->shader_time
.bo
->size
, 1, true);
3690 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
3691 32, &stage_state
->bind_bo_offset
);
3693 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
3694 if (prog_data
->total_scratch
) {
3698 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
3699 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
3701 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 11;
3702 } else if (GEN_IS_HASWELL
) {
3703 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
3704 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
3706 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 12;
3708 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
3709 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
3711 bo_offset
= stage_state
->per_thread_scratch
/ 1024 - 1;
3713 vfe
.ScratchSpaceBasePointer
=
3714 render_bo(stage_state
->scratch_bo
, bo_offset
);
3717 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
3718 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
3719 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
3720 vfe
.ResetGatewayTimer
=
3721 Resettingrelativetimerandlatchingtheglobaltimestamp
;
3723 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
3729 /* We are uploading duplicated copies of push constant uniforms for each
3730 * thread. Although the local id data needs to vary per thread, it won't
3731 * change for other uniform data. Unfortunately this duplication is
3732 * required for gen7. As of Haswell, this duplication can be avoided,
3733 * but this older mechanism with duplicated data continues to work.
3735 * FINISHME: As of Haswell, we could make use of the
3736 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
3737 * field to only store one copy of uniform data.
3739 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
3740 * which is described in the GPGPU_WALKER command and in the Broadwell
3741 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
3742 * Operations => GPGPU Mode => Indirect Payload Storage.
3744 * Note: The constant data is built in brw_upload_cs_push_constants
3747 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
3749 const uint32_t vfe_curbe_allocation
=
3750 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
3751 cs_prog_data
->push
.cross_thread
.regs
, 2);
3752 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
3755 if (cs_prog_data
->push
.total
.size
> 0) {
3756 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3757 curbe
.CURBETotalDataLength
=
3758 ALIGN(cs_prog_data
->push
.total
.size
, 64);
3759 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
3763 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
3764 memcpy(bind
, stage_state
->surf_offset
,
3765 prog_data
->binding_table
.size_bytes
);
3766 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
3767 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
3768 .SamplerStatePointer
= stage_state
->sampler_offset
,
3769 .SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4) >> 2,
3770 .BindingTablePointer
= stage_state
->bind_bo_offset
,
3771 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
3772 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
3773 .SharedLocalMemorySize
= encode_slm_size(devinfo
->gen
,
3774 prog_data
->total_shared
),
3775 .BarrierEnable
= cs_prog_data
->uses_barrier
,
3776 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3777 .CrossThreadConstantDataReadLength
=
3778 cs_prog_data
->push
.cross_thread
.regs
,
3782 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
3784 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
3785 load
.InterfaceDescriptorTotalLength
=
3786 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3787 load
.InterfaceDescriptorDataStartAddress
= offset
;
3791 static const struct brw_tracked_state
genX(cs_state
) = {
3793 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3794 .brw
= BRW_NEW_BATCH
|
3796 BRW_NEW_CS_PROG_DATA
|
3797 BRW_NEW_SAMPLER_STATE_TABLE
|
3800 .emit
= genX(upload_cs_state
)
3805 /* ---------------------------------------------------------------------- */
3809 genX(upload_raster
)(struct brw_context
*brw
)
3811 struct gl_context
*ctx
= &brw
->ctx
;
3814 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3817 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
3820 struct gl_point_attrib
*point
= &ctx
->Point
;
3822 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
3823 if (polygon
->_FrontBit
== render_to_fbo
)
3824 raster
.FrontWinding
= CounterClockwise
;
3826 if (polygon
->CullFlag
) {
3827 switch (polygon
->CullFaceMode
) {
3829 raster
.CullMode
= CULLMODE_FRONT
;
3832 raster
.CullMode
= CULLMODE_BACK
;
3834 case GL_FRONT_AND_BACK
:
3835 raster
.CullMode
= CULLMODE_BOTH
;
3838 unreachable("not reached");
3841 raster
.CullMode
= CULLMODE_NONE
;
3844 point
->SmoothFlag
= raster
.SmoothPointEnable
;
3846 raster
.DXMultisampleRasterizationEnable
=
3847 _mesa_is_multisample_enabled(ctx
);
3849 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
3850 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
3851 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
3853 switch (polygon
->FrontMode
) {
3855 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
3858 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
3861 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
3864 unreachable("not reached");
3867 switch (polygon
->BackMode
) {
3869 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
3872 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
3875 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
3878 unreachable("not reached");
3882 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
3885 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
3887 /* _NEW_TRANSFORM */
3888 if (!ctx
->Transform
.DepthClamp
) {
3890 raster
.ViewportZFarClipTestEnable
= true;
3891 raster
.ViewportZNearClipTestEnable
= true;
3893 raster
.ViewportZClipTestEnable
= true;
3897 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
3899 raster
.ConservativeRasterizationEnable
=
3900 ctx
->IntelConservativeRasterization
;
3903 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
3904 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
3906 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
3910 static const struct brw_tracked_state
genX(raster_state
) = {
3912 .mesa
= _NEW_BUFFERS
|
3919 .brw
= BRW_NEW_BLORP
|
3921 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3923 .emit
= genX(upload_raster
),
3927 /* ---------------------------------------------------------------------- */
3931 genX(upload_ps_extra
)(struct brw_context
*brw
)
3933 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
3935 const struct brw_wm_prog_data
*prog_data
=
3936 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3938 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
3939 psx
.PixelShaderValid
= true;
3940 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
3941 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
3942 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
3943 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
3944 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
3945 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
3947 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
3948 if (prog_data
->uses_sample_mask
) {
3950 if (prog_data
->post_depth_coverage
)
3951 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3952 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
3953 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
3955 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3957 psx
.PixelShaderUsesInputCoverageMask
= true;
3961 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3963 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
3964 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
3967 /* The stricter cross-primitive coherency guarantees that the hardware
3968 * gives us with the "Accesses UAV" bit set for at least one shader stage
3969 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
3970 * are redundant within the current image, atomic counter and SSBO GL
3971 * APIs, which all have very loose ordering and coherency requirements
3972 * and generally rely on the application to insert explicit barriers when
3973 * a shader invocation is expected to see the memory writes performed by
3974 * the invocations of some previous primitive. Regardless of the value
3975 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
3976 * cause an in most cases useless DC flush when the lowermost stage with
3977 * the bit set finishes execution.
3979 * It would be nice to disable it, but in some cases we can't because on
3980 * Gen8+ it also has an influence on rasterization via the PS UAV-only
3981 * signal (which could be set independently from the coherency mechanism
3982 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
3983 * determine whether the hardware skips execution of the fragment shader
3984 * or not via the ThreadDispatchEnable signal. However if we know that
3985 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
3986 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
3987 * difference so we may just disable it here.
3989 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
3990 * take into account KillPixels when no depth or stencil writes are
3991 * enabled. In order for occlusion queries to work correctly with no
3992 * attachments, we need to force-enable here.
3994 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
3997 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
3998 !brw_color_buffer_write_enabled(brw
))
3999 psx
.PixelShaderHasUAV
= true;
4003 const struct brw_tracked_state
genX(ps_extra
) = {
4005 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4006 .brw
= BRW_NEW_BLORP
|
4008 BRW_NEW_FRAGMENT_PROGRAM
|
4009 BRW_NEW_FS_PROG_DATA
|
4010 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4012 .emit
= genX(upload_ps_extra
),
4016 /* ---------------------------------------------------------------------- */
4020 genX(upload_ps_blend
)(struct brw_context
*brw
)
4022 struct gl_context
*ctx
= &brw
->ctx
;
4025 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4026 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4029 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4031 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4032 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4033 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4035 bool alpha_to_one
= false;
4037 if (!buffer0_is_integer
) {
4038 /* _NEW_MULTISAMPLE */
4040 if (_mesa_is_multisample_enabled(ctx
)) {
4041 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4042 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4045 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4048 /* Used for implementing the following bit of GL_EXT_texture_integer:
4049 * "Per-fragment operations that require floating-point color
4050 * components, including multisample alpha operations, alpha test,
4051 * blending, and dithering, have no effect when the corresponding
4052 * colors are written to an integer color buffer."
4054 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4055 * "If drawbuffer zero is not NONE and the buffer it references has an
4056 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4057 * operations are skipped."
4059 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4060 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4061 GLenum eqA
= color
->Blend
[0].EquationA
;
4062 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4063 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4064 GLenum srcA
= color
->Blend
[0].SrcA
;
4065 GLenum dstA
= color
->Blend
[0].DstA
;
4067 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4068 srcRGB
= dstRGB
= GL_ONE
;
4070 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4071 srcA
= dstA
= GL_ONE
;
4073 /* Due to hardware limitations, the destination may have information
4074 * in an alpha channel even when the format specifies no alpha
4075 * channel. In order to avoid getting any incorrect blending due to
4076 * that alpha channel, coerce the blend factors to values that will
4077 * not read the alpha channel, but will instead use the correct
4078 * implicit value for alpha.
4080 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4081 GL_TEXTURE_ALPHA_TYPE
)) {
4082 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4083 srcA
= brw_fix_xRGB_alpha(srcA
);
4084 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4085 dstA
= brw_fix_xRGB_alpha(dstA
);
4088 /* Alpha to One doesn't work with Dual Color Blending. Override
4089 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4091 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4092 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4093 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4094 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4095 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4098 pb
.ColorBufferBlendEnable
= true;
4099 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4100 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4101 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4102 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4104 pb
.IndependentAlphaBlendEnable
=
4105 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4110 static const struct brw_tracked_state
genX(ps_blend
) = {
4112 .mesa
= _NEW_BUFFERS
|
4115 .brw
= BRW_NEW_BLORP
|
4117 BRW_NEW_FRAGMENT_PROGRAM
,
4119 .emit
= genX(upload_ps_blend
)
4123 /* ---------------------------------------------------------------------- */
4127 genX(emit_vf_topology
)(struct brw_context
*brw
)
4129 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4130 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4134 static const struct brw_tracked_state
genX(vf_topology
) = {
4137 .brw
= BRW_NEW_BLORP
|
4140 .emit
= genX(emit_vf_topology
),
4144 /* ---------------------------------------------------------------------- */
4147 genX(init_atoms
)(struct brw_context
*brw
)
4150 static const struct brw_tracked_state
*render_atoms
[] =
4152 /* Once all the programs are done, we know how large urb entry
4153 * sizes need to be and can decide if we need to change the urb
4157 &brw_recalculate_urb_fence
,
4162 /* Surface state setup. Must come before the VS/WM unit. The binding
4163 * table upload must be last.
4165 &brw_vs_pull_constants
,
4166 &brw_wm_pull_constants
,
4167 &brw_renderbuffer_surfaces
,
4168 &brw_renderbuffer_read_surfaces
,
4169 &brw_texture_surfaces
,
4170 &brw_vs_binding_table
,
4171 &brw_wm_binding_table
,
4176 /* These set up state for brw_psp_urb_cbs */
4178 &genX(sf_clip_viewport
),
4180 &genX(vs_state
), /* always required, enabled or not */
4186 &brw_invariant_state
,
4188 &brw_binding_table_pointers
,
4189 &brw_blend_constant_color
,
4193 &genX(polygon_stipple
),
4194 &genX(polygon_stipple_offset
),
4196 &genX(line_stipple
),
4200 &genX(drawing_rect
),
4201 &brw_indices
, /* must come before brw_vertices */
4202 &genX(index_buffer
),
4205 &brw_constant_buffer
4208 static const struct brw_tracked_state
*render_atoms
[] =
4210 &genX(sf_clip_viewport
),
4212 /* Command packets: */
4217 &genX(blend_state
), /* must do before cc unit */
4218 &genX(color_calc_state
), /* must do before cc unit */
4219 &genX(depth_stencil_state
), /* must do before cc unit */
4221 &genX(vs_push_constants
), /* Before vs_state */
4222 &genX(gs_push_constants
), /* Before gs_state */
4223 &genX(wm_push_constants
), /* Before wm_state */
4225 /* Surface state setup. Must come before the VS/WM unit. The binding
4226 * table upload must be last.
4228 &brw_vs_pull_constants
,
4229 &brw_vs_ubo_surfaces
,
4230 &brw_gs_pull_constants
,
4231 &brw_gs_ubo_surfaces
,
4232 &brw_wm_pull_constants
,
4233 &brw_wm_ubo_surfaces
,
4234 &gen6_renderbuffer_surfaces
,
4235 &brw_renderbuffer_read_surfaces
,
4236 &brw_texture_surfaces
,
4238 &brw_vs_binding_table
,
4239 &gen6_gs_binding_table
,
4240 &brw_wm_binding_table
,
4245 &gen6_sampler_state
,
4246 &genX(multisample_state
),
4254 &genX(scissor_state
),
4256 &gen6_binding_table_pointers
,
4260 &genX(polygon_stipple
),
4261 &genX(polygon_stipple_offset
),
4263 &genX(line_stipple
),
4265 &genX(drawing_rect
),
4267 &brw_indices
, /* must come before brw_vertices */
4268 &genX(index_buffer
),
4272 static const struct brw_tracked_state
*render_atoms
[] =
4274 /* Command packets: */
4277 &genX(sf_clip_viewport
),
4280 &gen7_push_constant_space
,
4282 &genX(blend_state
), /* must do before cc unit */
4283 &genX(color_calc_state
), /* must do before cc unit */
4284 &genX(depth_stencil_state
), /* must do before cc unit */
4286 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4287 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4288 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4289 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4290 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4292 &genX(vs_push_constants
), /* Before vs_state */
4293 &genX(tcs_push_constants
),
4294 &genX(tes_push_constants
),
4295 &genX(gs_push_constants
), /* Before gs_state */
4296 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4298 /* Surface state setup. Must come before the VS/WM unit. The binding
4299 * table upload must be last.
4301 &brw_vs_pull_constants
,
4302 &brw_vs_ubo_surfaces
,
4303 &brw_vs_abo_surfaces
,
4304 &brw_tcs_pull_constants
,
4305 &brw_tcs_ubo_surfaces
,
4306 &brw_tcs_abo_surfaces
,
4307 &brw_tes_pull_constants
,
4308 &brw_tes_ubo_surfaces
,
4309 &brw_tes_abo_surfaces
,
4310 &brw_gs_pull_constants
,
4311 &brw_gs_ubo_surfaces
,
4312 &brw_gs_abo_surfaces
,
4313 &brw_wm_pull_constants
,
4314 &brw_wm_ubo_surfaces
,
4315 &brw_wm_abo_surfaces
,
4316 &gen6_renderbuffer_surfaces
,
4317 &brw_renderbuffer_read_surfaces
,
4318 &brw_texture_surfaces
,
4319 &brw_vs_binding_table
,
4320 &brw_tcs_binding_table
,
4321 &brw_tes_binding_table
,
4322 &brw_gs_binding_table
,
4323 &brw_wm_binding_table
,
4330 &genX(multisample_state
),
4344 &genX(scissor_state
),
4348 &genX(polygon_stipple
),
4349 &genX(polygon_stipple_offset
),
4351 &genX(line_stipple
),
4353 &genX(drawing_rect
),
4355 &brw_indices
, /* must come before brw_vertices */
4356 &genX(index_buffer
),
4364 static const struct brw_tracked_state
*render_atoms
[] =
4367 &genX(sf_clip_viewport
),
4370 &gen7_push_constant_space
,
4373 &genX(color_calc_state
),
4375 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4376 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4377 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4378 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4379 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4381 &genX(vs_push_constants
), /* Before vs_state */
4382 &genX(tcs_push_constants
),
4383 &genX(tes_push_constants
),
4384 &genX(gs_push_constants
), /* Before gs_state */
4385 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4387 /* Surface state setup. Must come before the VS/WM unit. The binding
4388 * table upload must be last.
4390 &brw_vs_pull_constants
,
4391 &brw_vs_ubo_surfaces
,
4392 &brw_vs_abo_surfaces
,
4393 &brw_tcs_pull_constants
,
4394 &brw_tcs_ubo_surfaces
,
4395 &brw_tcs_abo_surfaces
,
4396 &brw_tes_pull_constants
,
4397 &brw_tes_ubo_surfaces
,
4398 &brw_tes_abo_surfaces
,
4399 &brw_gs_pull_constants
,
4400 &brw_gs_ubo_surfaces
,
4401 &brw_gs_abo_surfaces
,
4402 &brw_wm_pull_constants
,
4403 &brw_wm_ubo_surfaces
,
4404 &brw_wm_abo_surfaces
,
4405 &gen6_renderbuffer_surfaces
,
4406 &brw_renderbuffer_read_surfaces
,
4407 &brw_texture_surfaces
,
4408 &brw_vs_binding_table
,
4409 &brw_tcs_binding_table
,
4410 &brw_tes_binding_table
,
4411 &brw_gs_binding_table
,
4412 &brw_wm_binding_table
,
4419 &genX(multisample_state
),
4428 &genX(raster_state
),
4434 &genX(depth_stencil_state
),
4437 &genX(scissor_state
),
4441 &genX(polygon_stipple
),
4442 &genX(polygon_stipple_offset
),
4444 &genX(line_stipple
),
4446 &genX(drawing_rect
),
4451 &genX(index_buffer
),
4459 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
4460 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
4461 render_atoms
, ARRAY_SIZE(render_atoms
));
4464 static const struct brw_tracked_state
*compute_atoms
[] =
4467 &brw_cs_image_surfaces
,
4468 &gen7_cs_push_constants
,
4469 &brw_cs_pull_constants
,
4470 &brw_cs_ubo_surfaces
,
4471 &brw_cs_abo_surfaces
,
4472 &brw_cs_texture_surfaces
,
4473 &brw_cs_work_groups_surface
,
4478 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
4479 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
4480 compute_atoms
, ARRAY_SIZE(compute_atoms
));