2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
35 #include "brw_context.h"
37 #include "brw_defines.h"
40 #include "brw_multisample_state.h"
41 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
46 #include "intel_buffer_objects.h"
47 #include "intel_fbo.h"
49 #include "main/enums.h"
50 #include "main/fbobject.h"
51 #include "main/framebuffer.h"
52 #include "main/glformats.h"
53 #include "main/shaderapi.h"
54 #include "main/stencil.h"
55 #include "main/transformfeedback.h"
56 #include "main/viewport.h"
59 emit_dwords(struct brw_context
*brw
, unsigned n
)
61 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
62 uint32_t *map
= brw
->batch
.map_next
;
63 brw
->batch
.map_next
+= n
;
64 intel_batchbuffer_advance(brw
);
70 uint32_t read_domains
;
71 uint32_t write_domain
;
76 emit_reloc(struct brw_context
*brw
,
77 void *location
, struct brw_address address
, uint32_t delta
)
79 uint32_t offset
= (char *) location
- (char *) brw
->batch
.map
;
81 return brw_emit_reloc(&brw
->batch
, offset
, address
.bo
,
82 address
.offset
+ delta
,
84 address
.write_domain
);
87 #define __gen_address_type struct brw_address
88 #define __gen_user_data struct brw_context
91 __gen_combine_address(struct brw_context
*brw
, void *location
,
92 struct brw_address address
, uint32_t delta
)
94 if (address
.bo
== NULL
) {
95 return address
.offset
+ delta
;
97 return emit_reloc(brw
, location
, address
, delta
);
101 static inline struct brw_address
102 render_bo(struct brw_bo
*bo
, uint32_t offset
)
104 return (struct brw_address
) {
107 .read_domains
= I915_GEM_DOMAIN_RENDER
,
108 .write_domain
= I915_GEM_DOMAIN_RENDER
,
112 static inline struct brw_address
113 render_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
115 return (struct brw_address
) {
118 .read_domains
= I915_GEM_DOMAIN_RENDER
,
123 static inline struct brw_address
124 instruction_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
130 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
134 static inline struct brw_address
135 vertex_bo(struct brw_bo
*bo
, uint32_t offset
)
137 return (struct brw_address
) {
140 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
145 #include "genxml/genX_pack.h"
147 #define _brw_cmd_length(cmd) cmd ## _length
148 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
149 #define _brw_cmd_header(cmd) cmd ## _header
150 #define _brw_cmd_pack(cmd) cmd ## _pack
152 #define brw_batch_emit(brw, cmd, name) \
153 for (struct cmd name = { _brw_cmd_header(cmd) }, \
154 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
155 __builtin_expect(_dst != NULL, 1); \
156 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
159 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
160 uint32_t *_dw = emit_dwords(brw, n); \
161 struct cmd template = { \
162 _brw_cmd_header(cmd), \
163 .DWordLength = n - _brw_cmd_length_bias(cmd), \
166 _brw_cmd_pack(cmd)(brw, _dw, &template); \
167 _dw + 1; /* Array starts at dw[1] */ \
170 #define brw_state_emit(brw, cmd, align, offset, name) \
171 for (struct cmd name = { 0, }, \
172 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
174 __builtin_expect(_dst != NULL, 1); \
175 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
179 * Polygon stipple packet
182 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
184 struct gl_context
*ctx
= &brw
->ctx
;
187 if (!ctx
->Polygon
.StippleFlag
)
190 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
191 /* Polygon stipple is provided in OpenGL order, i.e. bottom
192 * row first. If we're rendering to a window (i.e. the
193 * default frame buffer object, 0), then we need to invert
194 * it to match our pixel layout. But if we're rendering
195 * to a FBO (i.e. any named frame buffer object), we *don't*
196 * need to invert - we already match the layout.
198 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
199 for (unsigned i
= 0; i
< 32; i
++)
200 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
202 for (unsigned i
= 0; i
< 32; i
++)
203 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
208 static const struct brw_tracked_state
genX(polygon_stipple
) = {
210 .mesa
= _NEW_POLYGON
|
212 .brw
= BRW_NEW_CONTEXT
,
214 .emit
= genX(upload_polygon_stipple
),
218 * Polygon stipple offset packet
221 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
223 struct gl_context
*ctx
= &brw
->ctx
;
226 if (!ctx
->Polygon
.StippleFlag
)
229 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
232 * If we're drawing to a system window we have to invert the Y axis
233 * in order to match the OpenGL pixel coordinate system, and our
234 * offset must be matched to the window position. If we're drawing
235 * to a user-created FBO then our native pixel coordinate system
236 * works just fine, and there's no window system to worry about.
238 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
239 poly
.PolygonStippleYOffset
=
240 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
245 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
247 .mesa
= _NEW_BUFFERS
|
249 .brw
= BRW_NEW_CONTEXT
,
251 .emit
= genX(upload_polygon_stipple_offset
),
255 * Line stipple packet
258 genX(upload_line_stipple
)(struct brw_context
*brw
)
260 struct gl_context
*ctx
= &brw
->ctx
;
262 if (!ctx
->Line
.StippleFlag
)
265 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
266 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
268 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
269 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
273 static const struct brw_tracked_state
genX(line_stipple
) = {
276 .brw
= BRW_NEW_CONTEXT
,
278 .emit
= genX(upload_line_stipple
),
281 /* Constant single cliprect for framebuffer object or DRI2 drawing */
283 genX(upload_drawing_rect
)(struct brw_context
*brw
)
285 struct gl_context
*ctx
= &brw
->ctx
;
286 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
287 const unsigned int fb_width
= _mesa_geometric_width(fb
);
288 const unsigned int fb_height
= _mesa_geometric_height(fb
);
290 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
291 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
292 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
296 static const struct brw_tracked_state
genX(drawing_rect
) = {
298 .mesa
= _NEW_BUFFERS
,
299 .brw
= BRW_NEW_BLORP
|
302 .emit
= genX(upload_drawing_rect
),
306 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
310 unsigned start_offset
,
315 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
316 .VertexBufferIndex
= buffer_nr
,
317 .BufferPitch
= stride
,
318 .BufferStartingAddress
= vertex_bo(bo
, start_offset
),
320 .BufferSize
= end_offset
- start_offset
,
324 .AddressModifyEnable
= true,
328 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
329 .InstanceDataStepRate
= step_rate
,
331 .EndAddress
= vertex_bo(bo
, end_offset
- 1),
336 .VertexBufferMOCS
= SKL_MOCS_WB
,
338 .VertexBufferMOCS
= BDW_MOCS_WB
,
340 .VertexBufferMOCS
= GEN7_MOCS_L3
,
344 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
345 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
349 is_passthru_format(uint32_t format
)
352 case ISL_FORMAT_R64_PASSTHRU
:
353 case ISL_FORMAT_R64G64_PASSTHRU
:
354 case ISL_FORMAT_R64G64B64_PASSTHRU
:
355 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
363 genX(uploads_needed
)(uint32_t format
)
365 if (!is_passthru_format(format
))
369 case ISL_FORMAT_R64_PASSTHRU
:
370 case ISL_FORMAT_R64G64_PASSTHRU
:
372 case ISL_FORMAT_R64G64B64_PASSTHRU
:
373 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
376 unreachable("not reached");
381 * Returns the format that we are finally going to use when upload a vertex
382 * element. It will only change if we are using *64*PASSTHRU formats, as for
383 * gen < 8 they need to be splitted on two *32*FLOAT formats.
385 * @upload points in which upload we are. Valid values are [0,1]
388 downsize_format_if_needed(uint32_t format
,
391 assert(upload
== 0 || upload
== 1);
393 if (!is_passthru_format(format
))
397 case ISL_FORMAT_R64_PASSTHRU
:
398 return ISL_FORMAT_R32G32_FLOAT
;
399 case ISL_FORMAT_R64G64_PASSTHRU
:
400 return ISL_FORMAT_R32G32B32A32_FLOAT
;
401 case ISL_FORMAT_R64G64B64_PASSTHRU
:
402 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
403 : ISL_FORMAT_R32G32_FLOAT
;
404 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
405 return ISL_FORMAT_R32G32B32A32_FLOAT
;
407 unreachable("not reached");
412 * Returns the number of componentes associated with a format that is used on
413 * a 64 to 32 format split. See downsize_format()
416 upload_format_size(uint32_t upload_format
)
418 switch (upload_format
) {
419 case ISL_FORMAT_R32G32_FLOAT
:
421 case ISL_FORMAT_R32G32B32A32_FLOAT
:
424 unreachable("not reached");
429 genX(emit_vertices
)(struct brw_context
*brw
)
433 brw_prepare_vertices(brw
);
434 brw_prepare_shader_draw_parameters(brw
);
437 brw_emit_query_begin(brw
);
440 const struct brw_vs_prog_data
*vs_prog_data
=
441 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
444 struct gl_context
*ctx
= &brw
->ctx
;
445 bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
446 ctx
->Polygon
.BackMode
!= GL_FILL
);
448 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
449 unsigned vue
= brw
->vb
.nr_enabled
;
451 /* The element for the edge flags must always be last, so we have to
452 * insert the SGVS before it in that case.
454 if (uses_edge_flag
) {
460 "Trying to insert VID/IID past 33rd vertex element, "
461 "need to reorder the vertex attrbutes.");
463 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
464 if (vs_prog_data
->uses_vertexid
) {
465 vfs
.VertexIDEnable
= true;
466 vfs
.VertexIDComponentNumber
= 2;
467 vfs
.VertexIDElementOffset
= vue
;
470 if (vs_prog_data
->uses_instanceid
) {
471 vfs
.InstanceIDEnable
= true;
472 vfs
.InstanceIDComponentNumber
= 3;
473 vfs
.InstanceIDElementOffset
= vue
;
477 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
478 vfi
.InstancingEnable
= true;
479 vfi
.VertexElementIndex
= vue
;
482 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
485 /* Normally we don't need an element for the SGVS attribute because the
486 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
487 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
488 * we're using draw parameters then we need an element for the those
489 * values. Additionally if there is an edge flag element then the SGVS
490 * can't be inserted past that so we need a dummy element to ensure that
491 * the edge flag is the last one.
493 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
494 vs_prog_data
->uses_baseinstance
||
495 ((vs_prog_data
->uses_instanceid
||
496 vs_prog_data
->uses_vertexid
)
499 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
500 vs_prog_data
->uses_baseinstance
||
501 vs_prog_data
->uses_instanceid
||
502 vs_prog_data
->uses_vertexid
);
504 unsigned nr_elements
=
505 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
508 /* If any of the formats of vb.enabled needs more that one upload, we need
509 * to add it to nr_elements
511 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
512 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
513 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
515 if (genX(uploads_needed(format
)) > 1)
520 /* If the VS doesn't read any inputs (calculating vertex position from
521 * a state variable for some reason, for example), emit a single pad
522 * VERTEX_ELEMENT struct and bail.
524 * The stale VB state stays in place, but they don't do anything unless
525 * a VE loads from them.
527 if (nr_elements
== 0) {
528 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
), 1 + GENX(VERTEX_ELEMENT_STATE_length
));
529 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
531 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
532 .Component0Control
= VFCOMP_STORE_0
,
533 .Component1Control
= VFCOMP_STORE_0
,
534 .Component2Control
= VFCOMP_STORE_0
,
535 .Component3Control
= VFCOMP_STORE_1_FP
,
537 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
541 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
542 const bool uses_draw_params
=
543 vs_prog_data
->uses_basevertex
||
544 vs_prog_data
->uses_baseinstance
;
545 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
546 uses_draw_params
+ vs_prog_data
->uses_drawid
;
550 assert(nr_buffers
<= 33);
552 assert(nr_buffers
<= 17);
554 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
556 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
557 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
559 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
560 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
561 /* Prior to Haswell and Bay Trail we have to use 4-component formats
562 * to fake 3-component ones. In particular, we do this for
563 * half-float and 8 and 16-bit integer formats. This means that the
564 * vertex element may poke over the end of the buffer by 2 bytes.
567 (GEN_GEN
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
568 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
570 buffer
->offset
+ buffer
->size
+ padding
,
575 if (uses_draw_params
) {
576 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
577 brw
->draw
.draw_params_bo
,
578 brw
->draw
.draw_params_offset
,
579 brw
->draw
.draw_params_bo
->size
,
584 if (vs_prog_data
->uses_drawid
) {
585 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
586 brw
->draw
.draw_id_bo
,
587 brw
->draw
.draw_id_offset
,
588 brw
->draw
.draw_id_bo
->size
,
594 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
595 * presumably for VertexID/InstanceID.
598 assert(nr_elements
<= 34);
599 struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
601 assert(nr_elements
<= 18);
604 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
605 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
607 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
608 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
609 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
610 uint32_t comp0
= VFCOMP_STORE_SRC
;
611 uint32_t comp1
= VFCOMP_STORE_SRC
;
612 uint32_t comp2
= VFCOMP_STORE_SRC
;
613 uint32_t comp3
= VFCOMP_STORE_SRC
;
614 unsigned num_uploads
= 1;
617 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
618 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
619 * element which has edge flag enabled."
621 assert(!(is_passthru_format(format
) && uses_edge_flag
));
624 /* The gen4 driver expects edgeflag to come in as a float, and passes
625 * that float on to the tests in the clipper. Mesa's current vertex
626 * attribute value for EdgeFlag is stored as a float, which works out.
627 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
628 * integer ubyte. Just rewrite that to convert to a float.
630 * Gen6+ passes edgeflag as sideband along with the vertex, instead
631 * of in the VUE. We have to upload it sideband as the last vertex
632 * element according to the B-Spec.
635 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
636 gen6_edgeflag_input
= input
;
642 num_uploads
= genX(uploads_needed(format
));
645 for (unsigned c
= 0; c
< num_uploads
; c
++) {
646 uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
647 downsize_format_if_needed(format
, c
);
648 /* If we need more that one upload, the offset stride would be 128
649 * bits (16 bytes), as for previous uploads we are using the full
651 unsigned int offset
= input
->offset
+ c
* 16;
652 int size
= input
->glarray
->Size
;
654 if (GEN_GEN
< 8 && is_passthru_format(format
))
655 size
= upload_format_size(upload_format
);
658 case 0: comp0
= VFCOMP_STORE_0
;
659 case 1: comp1
= VFCOMP_STORE_0
;
660 case 2: comp2
= VFCOMP_STORE_0
;
662 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
663 comp3
= VFCOMP_STORE_0
;
664 } else if (input
->glarray
->Integer
) {
665 comp3
= VFCOMP_STORE_1_INT
;
667 comp3
= VFCOMP_STORE_1_FP
;
674 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
676 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
677 * formats, 64-bit components are stored in the URB without any
678 * conversion. In this case, vertex elements must be written as 128
679 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
680 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
681 * component into the URB, Component 1 must be specified as
682 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
683 * order to output a 128-bit vertex element, or Components 1-3 must
684 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
685 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
686 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
689 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
690 /* Store vertex elements which correspond to double and dvec2 vertex
691 * shader inputs as 128-bit vertex elements, instead of 256-bits.
693 comp2
= VFCOMP_NOSTORE
;
694 comp3
= VFCOMP_NOSTORE
;
698 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
699 .VertexBufferIndex
= input
->buffer
,
701 .SourceElementFormat
= upload_format
,
702 .SourceElementOffset
= offset
,
703 .Component0Control
= comp0
,
704 .Component1Control
= comp1
,
705 .Component2Control
= comp2
,
706 .Component3Control
= comp3
,
708 .DestinationElementOffset
= i
* 4,
712 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
713 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
717 if (needs_sgvs_element
) {
718 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
720 .Component0Control
= VFCOMP_STORE_0
,
721 .Component1Control
= VFCOMP_STORE_0
,
722 .Component2Control
= VFCOMP_STORE_0
,
723 .Component3Control
= VFCOMP_STORE_0
,
725 .DestinationElementOffset
= i
* 4,
730 if (vs_prog_data
->uses_basevertex
||
731 vs_prog_data
->uses_baseinstance
) {
732 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
733 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
734 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
735 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
738 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
739 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
740 if (vs_prog_data
->uses_basevertex
)
741 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
743 if (vs_prog_data
->uses_baseinstance
)
744 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
746 if (vs_prog_data
->uses_vertexid
)
747 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
749 if (vs_prog_data
->uses_instanceid
)
750 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
753 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
754 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
757 if (vs_prog_data
->uses_drawid
) {
758 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
760 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
761 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
762 .Component0Control
= VFCOMP_STORE_SRC
,
763 .Component1Control
= VFCOMP_STORE_0
,
764 .Component2Control
= VFCOMP_STORE_0
,
765 .Component3Control
= VFCOMP_STORE_0
,
767 .DestinationElementOffset
= i
* 4,
771 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
772 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
776 if (gen6_edgeflag_input
) {
778 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
780 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
782 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
783 .EdgeFlagEnable
= true,
784 .SourceElementFormat
= format
,
785 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
786 .Component0Control
= VFCOMP_STORE_SRC
,
787 .Component1Control
= VFCOMP_STORE_0
,
788 .Component2Control
= VFCOMP_STORE_0
,
789 .Component3Control
= VFCOMP_STORE_0
,
792 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
793 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
798 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
799 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
800 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
801 unsigned element_index
;
803 /* The edge flag element is reordered to be the last one in the code
804 * above so we need to compensate for that in the element indices used
807 if (input
== gen6_edgeflag_input
)
808 element_index
= nr_elements
- 1;
812 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
813 vfi
.VertexElementIndex
= element_index
;
814 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
815 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
819 if (vs_prog_data
->uses_drawid
) {
820 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
822 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
823 vfi
.VertexElementIndex
= element
;
829 static const struct brw_tracked_state
genX(vertices
) = {
831 .mesa
= _NEW_POLYGON
,
832 .brw
= BRW_NEW_BATCH
|
835 BRW_NEW_VS_PROG_DATA
,
837 .emit
= genX(emit_vertices
),
842 * Determine the appropriate attribute override value to store into the
843 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
844 * override value contains two pieces of information: the location of the
845 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
846 * flag indicating whether to "swizzle" the attribute based on the direction
847 * the triangle is facing.
849 * If an attribute is "swizzled", then the given VUE location is used for
850 * front-facing triangles, and the VUE location that immediately follows is
851 * used for back-facing triangles. We use this to implement the mapping from
852 * gl_FrontColor/gl_BackColor to gl_Color.
854 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
855 * being instructed to begin reading attribute data. It can be set to a
856 * nonzero value to prevent the SF unit from wasting time reading elements of
857 * the VUE that are not needed by the fragment shader. It is measured in
858 * 256-bit increments.
861 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
862 const struct brw_vue_map
*vue_map
,
863 int urb_entry_read_offset
, int fs_attr
,
864 bool two_side_color
, uint32_t *max_source_attr
)
866 /* Find the VUE slot for this attribute. */
867 int slot
= vue_map
->varying_to_slot
[fs_attr
];
869 /* Viewport and Layer are stored in the VUE header. We need to override
870 * them to zero if earlier stages didn't write them, as GL requires that
871 * they read back as zero when not explicitly set.
873 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
874 attr
->ComponentOverrideX
= true;
875 attr
->ComponentOverrideW
= true;
876 attr
->ConstantSource
= CONST_0000
;
878 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
879 attr
->ComponentOverrideY
= true;
880 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
881 attr
->ComponentOverrideZ
= true;
886 /* If there was only a back color written but not front, use back
887 * as the color instead of undefined
889 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
890 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
891 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
892 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
895 /* This attribute does not exist in the VUE--that means that the vertex
896 * shader did not write to it. This means that either:
898 * (a) This attribute is a texture coordinate, and it is going to be
899 * replaced with point coordinates (as a consequence of a call to
900 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
901 * hardware will ignore whatever attribute override we supply.
903 * (b) This attribute is read by the fragment shader but not written by
904 * the vertex shader, so its value is undefined. Therefore the
905 * attribute override we supply doesn't matter.
907 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
908 * previous shader stage.
910 * Note that we don't have to worry about the cases where the attribute
911 * is gl_PointCoord or is undergoing point sprite coordinate
912 * replacement, because in those cases, this function isn't called.
914 * In case (c), we need to program the attribute overrides so that the
915 * primitive ID will be stored in this slot. In every other case, the
916 * attribute override we supply doesn't matter. So just go ahead and
917 * program primitive ID in every case.
919 attr
->ComponentOverrideW
= true;
920 attr
->ComponentOverrideX
= true;
921 attr
->ComponentOverrideY
= true;
922 attr
->ComponentOverrideZ
= true;
923 attr
->ConstantSource
= PRIM_ID
;
927 /* Compute the location of the attribute relative to urb_entry_read_offset.
928 * Each increment of urb_entry_read_offset represents a 256-bit value, so
929 * it counts for two 128-bit VUE slots.
931 int source_attr
= slot
- 2 * urb_entry_read_offset
;
932 assert(source_attr
>= 0 && source_attr
< 32);
934 /* If we are doing two-sided color, and the VUE slot following this one
935 * represents a back-facing color, then we need to instruct the SF unit to
936 * do back-facing swizzling.
938 bool swizzling
= two_side_color
&&
939 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
940 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
941 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
942 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
944 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
945 if (*max_source_attr
< source_attr
+ swizzling
)
946 *max_source_attr
= source_attr
+ swizzling
;
948 attr
->SourceAttribute
= source_attr
;
950 attr
->SwizzleSelect
= INPUTATTR_FACING
;
955 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
956 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
957 uint32_t *point_sprite_enables
,
958 uint32_t *urb_entry_read_length
,
959 uint32_t *urb_entry_read_offset
)
961 const struct gl_context
*ctx
= &brw
->ctx
;
964 const struct gl_point_attrib
*point
= &ctx
->Point
;
966 /* BRW_NEW_FS_PROG_DATA */
967 const struct brw_wm_prog_data
*wm_prog_data
=
968 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
969 uint32_t max_source_attr
= 0;
971 *point_sprite_enables
= 0;
973 /* BRW_NEW_FRAGMENT_PROGRAM
975 * If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
976 * the full vertex header. Otherwise, we can program the SF to start
977 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
978 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
979 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
982 bool fs_needs_vue_header
= brw
->fragment_program
->info
.inputs_read
&
983 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
985 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
987 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
988 * description of dw10 Point Sprite Texture Coordinate Enable:
990 * "This field must be programmed to zero when non-point primitives
993 * The SandyBridge PRM doesn't explicitly say that point sprite enables
994 * must be programmed to zero when rendering non-point primitives, but
995 * the IvyBridge PRM does, and if we don't, we get garbage.
997 * This is not required on Haswell, as the hardware ignores this state
998 * when drawing non-points -- although we do still need to be careful to
999 * correctly set the attr overrides.
1002 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1004 bool drawing_points
= brw_is_drawing_points(brw
);
1006 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1007 int input_index
= wm_prog_data
->urb_setup
[attr
];
1009 if (input_index
< 0)
1013 bool point_sprite
= false;
1014 if (drawing_points
) {
1015 if (point
->PointSprite
&&
1016 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1017 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1018 point_sprite
= true;
1021 if (attr
== VARYING_SLOT_PNTC
)
1022 point_sprite
= true;
1025 *point_sprite_enables
|= (1 << input_index
);
1028 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1029 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1031 if (!point_sprite
) {
1032 genX(get_attr_override
)(&attribute
,
1033 &brw
->vue_map_geom_out
,
1034 *urb_entry_read_offset
, attr
,
1035 brw
->ctx
.VertexProgram
._TwoSideEnabled
,
1039 /* The hardware can only do the overrides on 16 overrides at a
1040 * time, and the other up to 16 have to be lined up so that the
1041 * input index = the output index. We'll need to do some
1042 * tweaking to make sure that's the case.
1044 if (input_index
< 16)
1045 attr_overrides
[input_index
] = attribute
;
1047 assert(attribute
.SourceAttribute
== input_index
);
1050 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1051 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1053 * "This field should be set to the minimum length required to read the
1054 * maximum source attribute. The maximum source attribute is indicated
1055 * by the maximum value of the enabled Attribute # Source Attribute if
1056 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1057 * enable is not set.
1058 * read_length = ceiling((max_source_attr + 1) / 2)
1060 * [errata] Corruption/Hang possible if length programmed larger than
1063 * Similar text exists for Ivy Bridge.
1065 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1068 /* ---------------------------------------------------------------------- */
1071 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1073 struct gl_context
*ctx
= &brw
->ctx
;
1076 struct intel_renderbuffer
*depth_irb
=
1077 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1080 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1083 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1084 const int b
= stencil
->_BackFace
;
1087 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1090 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, wmds
) {
1092 if (depth
->Test
&& depth_irb
) {
1093 wmds
.DepthTestEnable
= true;
1094 wmds
.DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1095 wmds
.DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1098 if (stencil
->_Enabled
) {
1099 wmds
.StencilTestEnable
= true;
1100 wmds
.StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1101 wmds
.StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1103 wmds
.StencilTestFunction
=
1104 intel_translate_compare_func(stencil
->Function
[0]);
1105 wmds
.StencilFailOp
=
1106 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1107 wmds
.StencilPassDepthPassOp
=
1108 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1109 wmds
.StencilPassDepthFailOp
=
1110 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1112 wmds
.StencilBufferWriteEnable
= stencil
->_WriteEnabled
;
1114 if (stencil
->_TestTwoSide
) {
1115 wmds
.DoubleSidedStencilEnable
= true;
1116 wmds
.BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1117 wmds
.BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1119 wmds
.BackfaceStencilTestFunction
=
1120 intel_translate_compare_func(stencil
->Function
[b
]);
1121 wmds
.BackfaceStencilFailOp
=
1122 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1123 wmds
.BackfaceStencilPassDepthPassOp
=
1124 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1125 wmds
.BackfaceStencilPassDepthFailOp
=
1126 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1130 wmds
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1131 wmds
.BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1137 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1138 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1139 ptr
.DEPTH_STENCIL_STATEChange
= true;
1142 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1143 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1148 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1150 .mesa
= _NEW_BUFFERS
|
1153 .brw
= BRW_NEW_BLORP
|
1154 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1156 BRW_NEW_STATE_BASE_ADDRESS
),
1158 .emit
= genX(upload_depth_stencil_state
),
1161 /* ---------------------------------------------------------------------- */
1164 genX(upload_clip_state
)(struct brw_context
*brw
)
1166 struct gl_context
*ctx
= &brw
->ctx
;
1169 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1171 /* BRW_NEW_FS_PROG_DATA */
1172 struct brw_wm_prog_data
*wm_prog_data
=
1173 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1175 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1176 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1178 if (wm_prog_data
->barycentric_interp_modes
&
1179 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1180 clip
.NonPerspectiveBarycentricEnable
= true;
1183 clip
.EarlyCullEnable
= true;
1187 clip
.FrontWinding
= ctx
->Polygon
._FrontBit
== _mesa_is_user_fbo(fb
);
1189 if (ctx
->Polygon
.CullFlag
) {
1190 switch (ctx
->Polygon
.CullFaceMode
) {
1192 clip
.CullMode
= CULLMODE_FRONT
;
1195 clip
.CullMode
= CULLMODE_BACK
;
1197 case GL_FRONT_AND_BACK
:
1198 clip
.CullMode
= CULLMODE_BOTH
;
1201 unreachable("Should not get here: invalid CullFlag");
1204 clip
.CullMode
= CULLMODE_NONE
;
1209 clip
.UserClipDistanceCullTestEnableBitmask
=
1210 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1212 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1216 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1217 clip
.TriangleStripListProvokingVertexSelect
= 0;
1218 clip
.TriangleFanProvokingVertexSelect
= 1;
1219 clip
.LineStripListProvokingVertexSelect
= 0;
1221 clip
.TriangleStripListProvokingVertexSelect
= 2;
1222 clip
.TriangleFanProvokingVertexSelect
= 2;
1223 clip
.LineStripListProvokingVertexSelect
= 1;
1226 /* _NEW_TRANSFORM */
1227 clip
.UserClipDistanceClipTestEnableBitmask
=
1228 ctx
->Transform
.ClipPlanesEnabled
;
1231 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1234 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1235 clip
.APIMode
= APIMODE_D3D
;
1237 clip
.APIMode
= APIMODE_OGL
;
1239 clip
.GuardbandClipTestEnable
= true;
1241 /* BRW_NEW_VIEWPORT_COUNT */
1242 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1244 if (ctx
->RasterDiscard
) {
1245 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1247 perf_debug("Rasterizer discard is currently implemented via the "
1248 "clipper; having the GS not write primitives would "
1249 "likely be faster.\n");
1252 clip
.ClipMode
= CLIPMODE_NORMAL
;
1255 clip
.ClipEnable
= brw
->primitive
!= _3DPRIM_RECTLIST
;
1258 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1260 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1261 clip
.ViewportXYClipTestEnable
= true;
1263 clip
.MinimumPointWidth
= 0.125;
1264 clip
.MaximumPointWidth
= 255.875;
1265 clip
.MaximumVPIndex
= viewport_count
- 1;
1266 if (_mesa_geometric_layers(fb
) == 0)
1267 clip
.ForceZeroRTAIndexEnable
= true;
1271 static const struct brw_tracked_state
genX(clip_state
) = {
1273 .mesa
= _NEW_BUFFERS
|
1277 .brw
= BRW_NEW_BLORP
|
1279 BRW_NEW_FS_PROG_DATA
|
1280 BRW_NEW_GS_PROG_DATA
|
1281 BRW_NEW_VS_PROG_DATA
|
1282 BRW_NEW_META_IN_PROGRESS
|
1284 BRW_NEW_RASTERIZER_DISCARD
|
1285 BRW_NEW_TES_PROG_DATA
|
1286 BRW_NEW_VIEWPORT_COUNT
,
1288 .emit
= genX(upload_clip_state
),
1291 /* ---------------------------------------------------------------------- */
1294 genX(upload_sf
)(struct brw_context
*brw
)
1296 struct gl_context
*ctx
= &brw
->ctx
;
1301 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1302 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1305 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1306 sf
.StatisticsEnable
= true;
1307 sf
.ViewportTransformEnable
= brw
->sf
.viewport_transform_enable
;
1311 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1316 sf
.FrontWinding
= ctx
->Polygon
._FrontBit
== render_to_fbo
;
1317 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1318 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1319 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1321 switch (ctx
->Polygon
.FrontMode
) {
1323 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1326 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1329 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1332 unreachable("not reached");
1335 switch (ctx
->Polygon
.BackMode
) {
1337 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1340 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1343 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1346 unreachable("not reached");
1349 sf
.ScissorRectangleEnable
= true;
1351 if (ctx
->Polygon
.CullFlag
) {
1352 switch (ctx
->Polygon
.CullFaceMode
) {
1354 sf
.CullMode
= CULLMODE_FRONT
;
1357 sf
.CullMode
= CULLMODE_BACK
;
1359 case GL_FRONT_AND_BACK
:
1360 sf
.CullMode
= CULLMODE_BOTH
;
1363 unreachable("not reached");
1366 sf
.CullMode
= CULLMODE_NONE
;
1370 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1373 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1374 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1376 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1377 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1378 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1383 if (brw
->is_cherryview
)
1384 sf
.CHVLineWidth
= brw_get_line_width_float(brw
);
1386 sf
.LineWidth
= brw_get_line_width_float(brw
);
1388 sf
.LineWidth
= brw_get_line_width_float(brw
);
1391 if (ctx
->Line
.SmoothFlag
) {
1392 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1394 sf
.AntiAliasingEnable
= true;
1398 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1399 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1400 /* Clamp to the hardware limits */
1401 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1403 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1404 if (use_state_point_size(brw
))
1405 sf
.PointWidthSource
= State
;
1408 /* _NEW_POINT | _NEW_MULTISAMPLE */
1409 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1410 !ctx
->Point
.PointSprite
)
1411 sf
.SmoothPointEnable
= true;
1414 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1417 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1418 sf
.TriangleStripListProvokingVertexSelect
= 2;
1419 sf
.TriangleFanProvokingVertexSelect
= 2;
1420 sf
.LineStripListProvokingVertexSelect
= 1;
1422 sf
.TriangleFanProvokingVertexSelect
= 1;
1426 /* BRW_NEW_FS_PROG_DATA */
1427 const struct brw_wm_prog_data
*wm_prog_data
=
1428 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1430 sf
.AttributeSwizzleEnable
= true;
1431 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1434 * Window coordinates in an FBO are inverted, which means point
1435 * sprite origin must be inverted, too.
1437 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1438 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1440 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1443 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1444 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1446 uint32_t urb_entry_read_length
;
1447 uint32_t urb_entry_read_offset
;
1448 uint32_t point_sprite_enables
;
1449 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1450 &urb_entry_read_length
,
1451 &urb_entry_read_offset
);
1452 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1453 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1454 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1455 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1460 static const struct brw_tracked_state
genX(sf_state
) = {
1462 .mesa
= _NEW_LIGHT
|
1467 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1468 .brw
= BRW_NEW_BLORP
|
1470 BRW_NEW_VUE_MAP_GEOM_OUT
|
1471 (GEN_GEN
<= 7 ? BRW_NEW_GS_PROG_DATA
|
1473 BRW_NEW_TES_PROG_DATA
1475 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1476 BRW_NEW_FRAGMENT_PROGRAM
1479 .emit
= genX(upload_sf
),
1482 /* ---------------------------------------------------------------------- */
1485 genX(upload_wm
)(struct brw_context
*brw
)
1487 struct gl_context
*ctx
= &brw
->ctx
;
1489 /* BRW_NEW_FS_PROG_DATA */
1490 const struct brw_wm_prog_data
*wm_prog_data
=
1491 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1493 UNUSED
bool writes_depth
=
1494 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1497 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1498 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1500 /* We can't fold this into gen6_upload_wm_push_constants(), because
1501 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1502 * (3DSTATE_CONSTANT_PS [DevSNB]):
1504 * "[DevSNB]: This packet must be followed by WM_STATE."
1506 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1507 if (wm_prog_data
->base
.nr_params
!= 0) {
1508 wmcp
.Buffer0Valid
= true;
1509 /* Pointer to the WM constant buffer. Covered by the set of
1510 * state flags from gen6_upload_wm_push_constants.
1512 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1513 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1518 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1519 wm
.StatisticsEnable
= true;
1520 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1521 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1524 if (wm_prog_data
->base
.use_alt_mode
)
1525 wm
.FloatingPointMode
= Alternate
;
1527 wm
.SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1528 wm
.BindingTableEntryCount
= wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1529 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1530 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1531 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1532 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1533 wm_prog_data
->base
.dispatch_grf_start_reg
;
1534 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1535 wm_prog_data
->dispatch_grf_start_reg_2
;
1536 wm
.KernelStartPointer0
= stage_state
->prog_offset
;
1537 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1538 wm_prog_data
->prog_offset_2
;
1539 wm
.DualSourceBlendEnable
=
1540 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1541 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1542 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1543 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1545 /* From the SNB PRM, volume 2 part 1, page 281:
1546 * "If the PS kernel does not need the Position XY Offsets
1547 * to compute a Position XY value, then this field should be
1548 * programmed to POSOFFSET_NONE."
1550 * "SW Recommendation: If the PS kernel needs the Position Offsets
1551 * to compute a Position XY value, this field should match Position
1552 * ZW Interpolation Mode to ensure a consistent position.xyzw
1554 * We only require XY sample offsets. So, this recommendation doesn't
1555 * look useful at the moment. We might need this in future.
1557 if (wm_prog_data
->uses_pos_offset
)
1558 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1560 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1562 if (wm_prog_data
->base
.total_scratch
) {
1563 wm
.ScratchSpaceBasePointer
=
1564 render_bo(stage_state
->scratch_bo
,
1565 ffs(stage_state
->per_thread_scratch
) - 11);
1568 wm
.PixelShaderComputedDepth
= writes_depth
;
1571 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1574 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1577 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1578 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1582 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1584 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1585 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1586 if (wm_prog_data
->uses_kill
||
1587 _mesa_is_alpha_test_enabled(ctx
) ||
1588 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1589 wm_prog_data
->uses_omask
) {
1590 wm
.PixelShaderKillsPixel
= true;
1593 /* _NEW_BUFFERS | _NEW_COLOR */
1594 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1595 wm_prog_data
->has_side_effects
|| wm
.PixelShaderKillsPixel
) {
1596 wm
.ThreadDispatchEnable
= true;
1598 if (multisampled_fbo
) {
1599 /* _NEW_MULTISAMPLE */
1600 if (ctx
->Multisample
.Enabled
)
1601 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1603 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1605 if (wm_prog_data
->persample_dispatch
)
1606 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1608 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1610 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1611 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1615 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1616 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1619 /* The "UAV access enable" bits are unnecessary on HSW because they only
1620 * seem to have an effect on the HW-assisted coherency mechanism which we
1621 * don't need, and the rasterization-related UAV_ONLY flag and the
1622 * DISPATCH_ENABLE bit can be set independently from it.
1623 * C.f. gen8_upload_ps_extra().
1625 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1629 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1630 wm_prog_data
->has_side_effects
)
1636 /* BRW_NEW_FS_PROG_DATA */
1637 if (wm_prog_data
->early_fragment_tests
)
1638 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1639 else if (wm_prog_data
->has_side_effects
)
1640 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1645 static const struct brw_tracked_state
genX(wm_state
) = {
1649 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1653 (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
1654 .brw
= BRW_NEW_BLORP
|
1655 BRW_NEW_FS_PROG_DATA
|
1656 (GEN_GEN
< 7 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1660 .emit
= genX(upload_wm
),
1663 /* ---------------------------------------------------------------------- */
1665 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1666 pkt.KernelStartPointer = stage_state->prog_offset; \
1667 pkt.SamplerCount = \
1668 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1669 pkt.BindingTableEntryCount = \
1670 stage_prog_data->binding_table.size_bytes / 4; \
1671 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
1673 if (stage_prog_data->total_scratch) { \
1674 pkt.ScratchSpaceBasePointer = \
1675 render_bo(stage_state->scratch_bo, 0); \
1676 pkt.PerThreadScratchSpace = \
1677 ffs(stage_state->per_thread_scratch) - 11; \
1680 pkt.DispatchGRFStartRegisterForURBData = \
1681 stage_prog_data->dispatch_grf_start_reg; \
1682 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1683 pkt.prefix##URBEntryReadOffset = 0; \
1685 pkt.StatisticsEnable = true; \
1690 genX(upload_vs_state
)(struct brw_context
*brw
)
1692 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1693 const struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
1695 /* BRW_NEW_VS_PROG_DATA */
1696 const struct brw_vue_prog_data
*vue_prog_data
=
1697 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
1698 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
1700 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
1701 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
1703 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1704 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1706 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
1707 * command that causes the VS Function Enable to toggle. Pipeline
1708 * flush can be executed by sending a PIPE_CONTROL command with CS
1709 * stall bit set and a post sync operation.
1711 * We've already done such a flush at the start of state upload, so we
1712 * don't need to do another one here.
1716 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
1717 if (stage_state
->push_const_size
!= 0) {
1718 cvs
.Buffer0Valid
= true;
1719 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
1720 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1725 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
1726 gen7_emit_vs_workaround_flush(brw
);
1728 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
1729 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1731 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1734 vs
.SIMD8DispatchEnable
=
1735 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
1737 vs
.UserClipDistanceCullTestEnableBitmask
=
1738 vue_prog_data
->cull_distance_mask
;
1743 /* Based on my reading of the simulator, the VS constants don't get
1744 * pulled into the VS FF unit until an appropriate pipeline flush
1745 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
1746 * references to them into a little FIFO. The flushes are common,
1747 * but don't reliably happen between this and a 3DPRIMITIVE, causing
1748 * the primitive to use the wrong constants. Then the FIFO
1749 * containing the constant setup gets added to again on the next
1750 * constants change, and eventually when a flush does happen the
1751 * unit is overwhelmed by constant changes and dies.
1753 * To avoid this, send a PIPE_CONTROL down the line that will
1754 * update the unit immediately loading the constants. The flush
1755 * type bits here were those set by the STATE_BASE_ADDRESS whose
1756 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
1757 * bug reports that led to this workaround, and may be more than
1758 * what is strictly required to avoid the issue.
1760 brw_emit_pipe_control_flush(brw
,
1761 PIPE_CONTROL_DEPTH_STALL
|
1762 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1763 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
1767 static const struct brw_tracked_state
genX(vs_state
) = {
1769 .mesa
= (GEN_GEN
< 7 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
1770 .brw
= BRW_NEW_BATCH
|
1773 BRW_NEW_VS_PROG_DATA
|
1774 (GEN_GEN
< 7 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1775 BRW_NEW_VERTEX_PROGRAM
1778 .emit
= genX(upload_vs_state
),
1781 /* ---------------------------------------------------------------------- */
1784 brw_calculate_guardband_size(const struct gen_device_info
*devinfo
,
1785 uint32_t fb_width
, uint32_t fb_height
,
1786 float m00
, float m11
, float m30
, float m31
,
1787 float *xmin
, float *xmax
,
1788 float *ymin
, float *ymax
)
1790 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1791 * Strips and Fans documentation:
1793 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1794 * fixed-point "guardband" range supported by the rasterization hardware"
1798 * "In almost all circumstances, if an object’s vertices are actually
1799 * modified by this clamping (i.e., had X or Y coordinates outside of
1800 * the guardband extent the rendered object will not match the intended
1801 * result. Therefore software should take steps to ensure that this does
1802 * not happen - e.g., by clipping objects such that they do not exceed
1803 * these limits after the Drawing Rectangle is applied."
1805 * I believe the fundamental restriction is that the rasterizer (in
1806 * the SF/WM stages) have a limit on the number of pixels that can be
1807 * rasterized. We need to ensure any coordinates beyond the rasterizer
1808 * limit are handled by the clipper. So effectively that limit becomes
1809 * the clipper's guardband size.
1811 * It goes on to say:
1813 * "In addition, in order to be correctly rendered, objects must have a
1814 * screenspace bounding box not exceeding 8K in the X or Y direction.
1815 * This additional restriction must also be comprehended by software,
1816 * i.e., enforced by use of clipping."
1818 * This makes no sense. Gen7+ hardware supports 16K render targets,
1819 * and you definitely need to be able to draw polygons that fill the
1820 * surface. Our assumption is that the rasterizer was limited to 8K
1821 * on Sandybridge, which only supports 8K surfaces, and it was actually
1822 * increased to 16K on Ivybridge and later.
1824 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1826 const float gb_size
= devinfo
->gen
>= 7 ? 16384.0f
: 8192.0f
;
1828 if (m00
!= 0 && m11
!= 0) {
1829 /* First, we compute the screen-space render area */
1830 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1831 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1832 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1833 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1835 /* We want the guardband to be centered on that */
1836 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1837 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1838 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1839 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1841 /* Now we need it in native device coordinates */
1842 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1843 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1844 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1845 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1847 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1848 * flipped upside-down. X should be fine though.
1850 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1851 *xmin
= ndc_gb_xmin
;
1852 *xmax
= ndc_gb_xmax
;
1853 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1854 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1856 /* The viewport scales to 0, so nothing will be rendered. */
1865 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
1867 struct gl_context
*ctx
= &brw
->ctx
;
1868 float y_scale
, y_bias
;
1869 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1871 /* BRW_NEW_VIEWPORT_COUNT */
1872 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1875 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1876 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
1877 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
1881 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
1882 uint32_t sf_clip_vp_offset
;
1883 uint32_t *sf_clip_map
= brw_state_batch(brw
, 16 * 4 * viewport_count
,
1884 64, &sf_clip_vp_offset
);
1886 struct GENX(SF_VIEWPORT
) sfv
;
1887 struct GENX(CLIP_VIEWPORT
) clv
;
1888 uint32_t *sf_map
= brw_state_batch(brw
, 8 * 4 * viewport_count
,
1889 32, &brw
->sf
.vp_offset
);
1890 uint32_t *clip_map
= brw_state_batch(brw
, 4 * 4 * viewport_count
,
1891 32, &brw
->clip
.vp_offset
);
1895 if (render_to_fbo
) {
1900 y_bias
= (float)fb_height
;
1903 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
1904 /* _NEW_VIEWPORT: Guardband Clipping */
1905 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
1906 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
1908 sfv
.ViewportMatrixElementm00
= scale
[0];
1909 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
1910 sfv
.ViewportMatrixElementm22
= scale
[2],
1911 sfv
.ViewportMatrixElementm30
= translate
[0],
1912 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
1913 sfv
.ViewportMatrixElementm32
= translate
[2],
1914 brw_calculate_guardband_size(devinfo
, fb_width
, fb_height
,
1915 sfv
.ViewportMatrixElementm00
,
1916 sfv
.ViewportMatrixElementm11
,
1917 sfv
.ViewportMatrixElementm30
,
1918 sfv
.ViewportMatrixElementm31
,
1919 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
1922 clv
.XMinClipGuardband
= gb_xmin
;
1923 clv
.XMaxClipGuardband
= gb_xmax
;
1924 clv
.YMinClipGuardband
= gb_ymin
;
1925 clv
.YMaxClipGuardband
= gb_ymax
;
1928 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
1929 * The hardware will take the intersection of the drawing rectangle,
1930 * scissor rectangle, and the viewport extents. We don't need to be
1931 * smart, and can therefore just program the viewport extents.
1933 const float viewport_Xmax
=
1934 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
1935 const float viewport_Ymax
=
1936 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
1938 if (render_to_fbo
) {
1939 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
1940 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
1941 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
1942 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
1944 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
1945 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
1946 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
1947 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
1952 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
1955 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
1956 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
1963 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
1964 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
1967 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
1971 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
1973 .mesa
= _NEW_BUFFERS
|
1975 .brw
= BRW_NEW_BATCH
|
1977 BRW_NEW_VIEWPORT_COUNT
,
1979 .emit
= genX(upload_sf_clip_viewport
),
1983 genX(upload_gs_state
)(struct brw_context
*brw
)
1985 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1986 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
1987 /* BRW_NEW_GEOMETRY_PROGRAM */
1988 bool active
= brw
->geometry_program
;
1990 /* BRW_NEW_GS_PROG_DATA */
1991 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
1992 const struct brw_vue_prog_data
*vue_prog_data
=
1993 brw_vue_prog_data(stage_prog_data
);
1995 const struct brw_gs_prog_data
*gs_prog_data
=
1996 brw_gs_prog_data(stage_prog_data
);
2000 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2001 if (active
&& stage_state
->push_const_size
!= 0) {
2002 cgs
.Buffer0Valid
= true;
2003 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2004 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2009 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2011 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2012 * Geometry > Geometry Shader > State:
2014 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2015 * whole fixed function pipeline when the GS enable changes value in
2018 * The hardware architects have clarified that in this context "flush the
2019 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2022 if (brw
->gt
== 2 && brw
->gs
.enabled
!= active
)
2023 gen7_emit_cs_stall_flush(brw
);
2027 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2028 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2031 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2032 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2033 gs
.ControlDataHeaderSize
=
2034 gs_prog_data
->control_data_header_size_hwords
;
2036 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2037 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2039 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2041 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2044 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2045 * Ivy Bridge and Haswell.
2047 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2048 * strip to be delivered to the geometry shader in an order that does
2049 * not strictly follow the OpenGL spec, but preserves triangle
2050 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2051 * the geometry shader sees triangles:
2053 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2055 * (Clearing the bit is even worse, because it fails to preserve
2058 * Triangle strips with adjacency always ordered in a way that preserves
2059 * triangle orientation but does not strictly follow the OpenGL spec,
2060 * regardless of the setting of this bit.
2062 * On Haswell, both triangle strips and triangle strips with adjacency
2063 * are always ordered in a way that preserves triangle orientation.
2064 * Setting this bit causes the ordering to strictly follow the OpenGL
2067 * So in either case we want to set the bit. Unfortunately on Ivy
2068 * Bridge this will get the order close to correct but not perfect.
2070 gs
.ReorderMode
= TRAILING
;
2071 gs
.MaximumNumberofThreads
=
2072 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2073 : (devinfo
->max_gs_threads
- 1);
2076 gs
.SOStatisticsEnable
= true;
2077 gs
.RenderingEnabled
= 1;
2078 if (brw
->geometry_program
->info
.has_transform_feedback_varyings
)
2079 gs
.SVBIPayloadEnable
= true;
2081 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2082 * was previously done for gen6.
2084 * TODO: test with both disabled to see if the HW is behaving
2085 * as expected, like in gen7.
2087 gs
.SingleProgramFlow
= true;
2088 gs
.VectorMaskEnable
= true;
2092 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2094 if (gs_prog_data
->static_vertex_count
!= -1) {
2095 gs
.StaticOutput
= true;
2096 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2098 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2100 gs
.UserClipDistanceCullTestEnableBitmask
=
2101 vue_prog_data
->cull_distance_mask
;
2103 const int urb_entry_write_offset
= 1;
2104 const uint32_t urb_entry_output_length
=
2105 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2106 urb_entry_write_offset
;
2108 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2109 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2113 } else if (brw
->ff_gs
.prog_active
) {
2114 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
2115 * program. This function provides the needed 3DSTATE_GS for this.
2117 upload_gs_state_for_tf(brw
);
2120 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2121 gs
.StatisticsEnable
= true;
2123 gs
.RenderingEnabled
= true;
2127 gs
.DispatchGRFStartRegisterForURBData
= 1;
2129 gs
.IncludeVertexHandles
= true;
2135 brw
->gs
.enabled
= active
;
2139 static const struct brw_tracked_state
genX(gs_state
) = {
2141 .mesa
= (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
2142 .brw
= BRW_NEW_BATCH
|
2145 BRW_NEW_GEOMETRY_PROGRAM
|
2146 BRW_NEW_GS_PROG_DATA
|
2147 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
|
2148 BRW_NEW_PUSH_CONSTANT_ALLOCATION
2151 .emit
= genX(upload_gs_state
),
2154 /* ---------------------------------------------------------------------- */
2156 #define blend_factor(x) brw_translate_blend_factor(x)
2157 #define blend_eqn(x) brw_translate_blend_equation(x)
2160 genX(upload_blend_state
)(struct brw_context
*brw
)
2162 struct gl_context
*ctx
= &brw
->ctx
;
2165 /* We need at least one BLEND_STATE written, because we might do
2166 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2167 * for computed depth or alpha test), which will do an FB write
2168 * with render target 0, which will reference BLEND_STATE[0] for
2169 * alpha test enable.
2171 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2172 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2173 nr_draw_buffers
= 1;
2175 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2177 size
+= GENX(BLEND_STATE_length
) * 4;
2180 uint32_t *blend_map
;
2181 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2184 struct GENX(BLEND_STATE
) blend
= { 0 };
2187 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2188 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2191 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2192 * "If drawbuffer zero is not NONE and the buffer it references has an
2193 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2194 * operations are skipped."
2196 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2197 /* _NEW_MULTISAMPLE */
2198 if (_mesa_is_multisample_enabled(ctx
)) {
2199 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2200 blend
.AlphaToCoverageEnable
= true;
2201 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2203 if (ctx
->Multisample
.SampleAlphaToOne
)
2204 blend
.AlphaToOneEnable
= true;
2208 if (ctx
->Color
.AlphaEnabled
) {
2209 blend
.AlphaTestEnable
= true;
2210 blend
.AlphaTestFunction
=
2211 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2214 if (ctx
->Color
.DitherFlag
) {
2215 blend
.ColorDitherEnable
= true;
2220 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2221 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2227 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2229 /* Used for implementing the following bit of GL_EXT_texture_integer:
2230 * "Per-fragment operations that require floating-point color
2231 * components, including multisample alpha operations, alpha test,
2232 * blending, and dithering, have no effect when the corresponding
2233 * colors are written to an integer color buffer."
2235 bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2238 if (ctx
->Color
.ColorLogicOpEnabled
) {
2239 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2240 : GL_UNSIGNED_NORMALIZED
;
2241 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2242 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2243 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2245 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2246 _mesa_enum_to_string(rb_type
));
2247 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2248 entry
.LogicOpEnable
= true;
2249 entry
.LogicOpFunction
=
2250 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2252 } else if (ctx
->Color
.BlendEnabled
& (1 << i
) && !integer
&&
2253 !ctx
->Color
._AdvancedBlendMode
) {
2254 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2255 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2256 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2257 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2258 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2259 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2261 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2262 srcRGB
= dstRGB
= GL_ONE
;
2264 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2265 srcA
= dstA
= GL_ONE
;
2267 /* Due to hardware limitations, the destination may have information
2268 * in an alpha channel even when the format specifies no alpha
2269 * channel. In order to avoid getting any incorrect blending due to
2270 * that alpha channel, coerce the blend factors to values that will
2271 * not read the alpha channel, but will instead use the correct
2272 * implicit value for alpha.
2274 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2275 GL_TEXTURE_ALPHA_TYPE
)) {
2276 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2277 srcA
= brw_fix_xRGB_alpha(srcA
);
2278 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2279 dstA
= brw_fix_xRGB_alpha(dstA
);
2282 entry
.ColorBufferBlendEnable
= true;
2283 entry
.DestinationBlendFactor
= blend_factor(dstRGB
);
2284 entry
.SourceBlendFactor
= blend_factor(srcRGB
);
2285 entry
.DestinationAlphaBlendFactor
= blend_factor(dstA
);
2286 entry
.SourceAlphaBlendFactor
= blend_factor(srcA
);
2287 entry
.ColorBlendFunction
= blend_eqn(eqRGB
);
2288 entry
.AlphaBlendFunction
= blend_eqn(eqA
);
2290 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2291 blend
.IndependentAlphaBlendEnable
= true;
2294 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2295 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2297 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2298 * clamping in the fragment shader. For its clamping of
2299 * blending, the spec says:
2301 * "RESOLVED: For fixed-point color buffers, the inputs and
2302 * the result of the blending equation are clamped. For
2303 * floating-point color buffers, no clamping occurs."
2305 * So, generally, we want clamping to the render target's range.
2306 * And, good news, the hardware tables for both pre- and
2307 * post-blend color clamping are either ignored, or any are
2308 * allowed, or clamping is required but RT range clamping is a
2311 entry
.PreBlendColorClampEnable
= true;
2312 entry
.PostBlendColorClampEnable
= true;
2313 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2315 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2316 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2317 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2318 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2320 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2321 * "If Dual Source Blending is enabled, this bit must be disabled."
2323 WARN_ONCE(ctx
->Color
.Blend
[i
]._UsesDualSrc
&&
2324 _mesa_is_multisample_enabled(ctx
) &&
2325 ctx
->Multisample
.SampleAlphaToOne
,
2326 "HW workaround: disabling alpha to one with dual src "
2328 if (ctx
->Color
.Blend
[i
]._UsesDualSrc
)
2329 blend
.AlphaToOneEnable
= false;
2331 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2333 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2339 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2343 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2344 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2345 ptr
.BLEND_STATEChange
= true;
2348 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2349 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2351 ptr
.BlendStatePointerValid
= true;
2357 static const struct brw_tracked_state
genX(blend_state
) = {
2359 .mesa
= _NEW_BUFFERS
|
2362 .brw
= BRW_NEW_BATCH
|
2364 BRW_NEW_STATE_BASE_ADDRESS
,
2366 .emit
= genX(upload_blend_state
),
2369 /* ---------------------------------------------------------------------- */
2372 genX(upload_scissor_state
)(struct brw_context
*brw
)
2374 struct gl_context
*ctx
= &brw
->ctx
;
2375 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2376 struct GENX(SCISSOR_RECT
) scissor
;
2377 uint32_t scissor_state_offset
;
2378 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2379 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2380 uint32_t *scissor_map
;
2382 /* BRW_NEW_VIEWPORT_COUNT */
2383 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2385 scissor_map
= brw_state_batch(
2386 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2387 32, &scissor_state_offset
);
2389 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2391 /* The scissor only needs to handle the intersection of drawable and
2392 * scissor rect. Clipping to the boundaries of static shared buffers
2393 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2395 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2396 * inclusive but max is exclusive.
2398 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2401 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2402 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2403 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2404 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2405 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2407 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2408 /* If the scissor was out of bounds and got clamped to 0 width/height
2409 * at the bounds, the subtraction of 1 from maximums could produce a
2410 * negative number and thus not clip anything. Instead, just provide
2411 * a min > max scissor inside the bounds, which produces the expected
2414 scissor
.ScissorRectangleXMin
= 1;
2415 scissor
.ScissorRectangleXMax
= 0;
2416 scissor
.ScissorRectangleYMin
= 1;
2417 scissor
.ScissorRectangleYMax
= 0;
2418 } else if (render_to_fbo
) {
2419 /* texmemory: Y=0=bottom */
2420 scissor
.ScissorRectangleXMin
= bbox
[0];
2421 scissor
.ScissorRectangleXMax
= bbox
[1] - 1;
2422 scissor
.ScissorRectangleYMin
= bbox
[2];
2423 scissor
.ScissorRectangleYMax
= bbox
[3] - 1;
2425 /* memory: Y=0=top */
2426 scissor
.ScissorRectangleXMin
= bbox
[0];
2427 scissor
.ScissorRectangleXMax
= bbox
[1] - 1;
2428 scissor
.ScissorRectangleYMin
= fb_height
- bbox
[3];
2429 scissor
.ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2432 GENX(SCISSOR_RECT_pack
)(
2433 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2436 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2437 ptr
.ScissorRectPointer
= scissor_state_offset
;
2441 static const struct brw_tracked_state
genX(scissor_state
) = {
2443 .mesa
= _NEW_BUFFERS
|
2446 .brw
= BRW_NEW_BATCH
|
2448 BRW_NEW_VIEWPORT_COUNT
,
2450 .emit
= genX(upload_scissor_state
),
2454 UNUSED
static const uint32_t push_constant_opcodes
[] = {
2455 [MESA_SHADER_VERTEX
] = 21,
2456 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2457 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2458 [MESA_SHADER_GEOMETRY
] = 22,
2459 [MESA_SHADER_FRAGMENT
] = 23,
2460 [MESA_SHADER_COMPUTE
] = 0,
2464 upload_constant_state(struct brw_context
*brw
,
2465 struct brw_stage_state
*stage_state
,
2466 bool active
, uint32_t stage
)
2468 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
2469 active
= active
&& stage_state
->push_const_size
!= 0;
2471 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2472 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2475 pkt
.ConstantBody
.ConstantBuffer2ReadLength
=
2476 stage_state
->push_const_size
;
2477 pkt
.ConstantBody
.PointerToConstantBuffer2
=
2478 render_ro_bo(brw
->batch
.bo
, stage_state
->push_const_offset
);
2480 pkt
.ConstantBody
.ConstantBuffer0ReadLength
=
2481 stage_state
->push_const_size
;
2482 pkt
.ConstantBody
.PointerToConstantBuffer0
.offset
=
2483 stage_state
->push_const_offset
| mocs
;
2488 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
2493 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
2495 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2497 /* _BRW_NEW_VERTEX_PROGRAM */
2498 const struct brw_program
*vp
= brw_program_const(brw
->vertex_program
);
2499 /* BRW_NEW_VS_PROG_DATA */
2500 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
2502 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
2503 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
2506 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !brw
->is_baytrail
)
2507 gen7_emit_vs_workaround_flush(brw
);
2509 upload_constant_state(brw
, stage_state
, true /* active */,
2510 MESA_SHADER_VERTEX
);
2514 static const struct brw_tracked_state
genX(vs_push_constants
) = {
2516 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2518 .brw
= BRW_NEW_BATCH
|
2520 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2521 BRW_NEW_VERTEX_PROGRAM
|
2522 BRW_NEW_VS_PROG_DATA
,
2524 .emit
= genX(upload_vs_push_constants
),
2528 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
2530 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2532 /* BRW_NEW_GEOMETRY_PROGRAM */
2533 const struct brw_program
*gp
= brw_program_const(brw
->geometry_program
);
2536 /* BRW_NEW_GS_PROG_DATA */
2537 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
2539 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
2540 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
2544 upload_constant_state(brw
, stage_state
, gp
, MESA_SHADER_GEOMETRY
);
2548 static const struct brw_tracked_state
genX(gs_push_constants
) = {
2550 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2552 .brw
= BRW_NEW_BATCH
|
2554 BRW_NEW_GEOMETRY_PROGRAM
|
2555 BRW_NEW_GS_PROG_DATA
|
2556 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2558 .emit
= genX(upload_gs_push_constants
),
2562 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
2564 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
2565 /* BRW_NEW_FRAGMENT_PROGRAM */
2566 const struct brw_program
*fp
= brw_program_const(brw
->fragment_program
);
2567 /* BRW_NEW_FS_PROG_DATA */
2568 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
2570 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
2572 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
2575 upload_constant_state(brw
, stage_state
, true, MESA_SHADER_FRAGMENT
);
2579 static const struct brw_tracked_state
genX(wm_push_constants
) = {
2581 .mesa
= _NEW_PROGRAM_CONSTANTS
,
2582 .brw
= BRW_NEW_BATCH
|
2584 BRW_NEW_FRAGMENT_PROGRAM
|
2585 BRW_NEW_FS_PROG_DATA
|
2586 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2588 .emit
= genX(upload_wm_push_constants
),
2591 /* ---------------------------------------------------------------------- */
2594 genX(determine_sample_mask
)(struct brw_context
*brw
)
2596 struct gl_context
*ctx
= &brw
->ctx
;
2597 float coverage
= 1.0f
;
2598 float coverage_invert
= false;
2599 unsigned sample_mask
= ~0u;
2601 /* BRW_NEW_NUM_SAMPLES */
2602 unsigned num_samples
= brw
->num_samples
;
2604 if (_mesa_is_multisample_enabled(ctx
)) {
2605 if (ctx
->Multisample
.SampleCoverage
) {
2606 coverage
= ctx
->Multisample
.SampleCoverageValue
;
2607 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
2609 if (ctx
->Multisample
.SampleMask
) {
2610 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
2614 if (num_samples
> 1) {
2615 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
2616 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
2617 if (coverage_invert
)
2618 coverage_bits
^= (1 << num_samples
) - 1;
2619 return coverage_bits
& sample_mask
;
2625 /* ---------------------------------------------------------------------- */
2628 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
2629 unsigned num_samples
)
2631 assert(brw
->num_samples
<= 16);
2633 unsigned log2_samples
= ffs(MAX2(num_samples
, 1)) - 1;
2635 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
2636 multi
.PixelLocation
= CENTER
;
2637 multi
.NumberofMultisamples
= log2_samples
;
2639 GEN_SAMPLE_POS_4X(multi
.Sample
);
2641 switch (num_samples
) {
2643 GEN_SAMPLE_POS_1X(multi
.Sample
);
2646 GEN_SAMPLE_POS_2X(multi
.Sample
);
2649 GEN_SAMPLE_POS_4X(multi
.Sample
);
2652 GEN_SAMPLE_POS_8X(multi
.Sample
);
2662 genX(upload_multisample_state
)(struct brw_context
*brw
)
2664 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
2666 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
2667 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
2671 static const struct brw_tracked_state
genX(multisample_state
) = {
2673 .mesa
= _NEW_MULTISAMPLE
,
2674 .brw
= BRW_NEW_BLORP
|
2676 BRW_NEW_NUM_SAMPLES
,
2678 .emit
= genX(upload_multisample_state
)
2681 /* ---------------------------------------------------------------------- */
2684 genX(upload_color_calc_state
)(struct brw_context
*brw
)
2686 struct gl_context
*ctx
= &brw
->ctx
;
2688 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
2690 cc
.AlphaTestFormat
= ALPHATEST_UNORM8
;
2691 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
2692 ctx
->Color
.AlphaRef
);
2696 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
2697 cc
.BackfaceStencilReferenceValue
=
2698 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
2702 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
2703 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
2704 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
2705 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
2708 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2709 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
2711 ptr
.ColorCalcStatePointerValid
= true;
2716 static const struct brw_tracked_state
genX(color_calc_state
) = {
2718 .mesa
= _NEW_COLOR
|
2720 .brw
= BRW_NEW_BATCH
|
2723 BRW_NEW_STATE_BASE_ADDRESS
,
2725 .emit
= genX(upload_color_calc_state
),
2730 /* ---------------------------------------------------------------------- */
2734 genX(upload_sbe
)(struct brw_context
*brw
)
2736 struct gl_context
*ctx
= &brw
->ctx
;
2737 /* BRW_NEW_FS_PROG_DATA */
2738 const struct brw_wm_prog_data
*wm_prog_data
=
2739 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
2741 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
2743 #define attr_overrides sbe.Attribute
2745 uint32_t urb_entry_read_length
;
2746 uint32_t urb_entry_read_offset
;
2747 uint32_t point_sprite_enables
;
2749 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
2750 sbe
.AttributeSwizzleEnable
= true;
2751 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2754 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2758 * Window coordinates in an FBO are inverted, which means point
2759 * sprite origin must be inverted.
2761 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
2762 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
2764 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
2766 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
2767 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
2768 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
2769 * BRW_NEW_VUE_MAP_GEOM_OUT
2771 genX(calculate_attr_overrides
)(brw
,
2773 &point_sprite_enables
,
2774 &urb_entry_read_length
,
2775 &urb_entry_read_offset
);
2777 /* Typically, the URB entry read length and offset should be programmed
2778 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
2779 * stage which produces geometry. However, we don't know the proper
2780 * value until we call calculate_attr_overrides().
2782 * To fit with our existing code, we override the inherited values and
2783 * specify it here directly, as we did on previous generations.
2785 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
2786 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
2787 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
2788 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2791 sbe
.ForceVertexURBEntryReadLength
= true;
2792 sbe
.ForceVertexURBEntryReadOffset
= true;
2796 /* prepare the active component dwords */
2797 int input_index
= 0;
2798 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
2799 if (!(brw
->fragment_program
->info
.inputs_read
&
2800 BITFIELD64_BIT(attr
))) {
2804 assert(input_index
< 32);
2806 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
2813 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2814 for (int i
= 0; i
< 16; i
++)
2815 sbes
.Attribute
[i
] = attr_overrides
[i
];
2819 #undef attr_overrides
2822 static const struct brw_tracked_state
genX(sbe_state
) = {
2824 .mesa
= _NEW_BUFFERS
|
2829 .brw
= BRW_NEW_BLORP
|
2831 BRW_NEW_FRAGMENT_PROGRAM
|
2832 BRW_NEW_FS_PROG_DATA
|
2833 BRW_NEW_GS_PROG_DATA
|
2834 BRW_NEW_TES_PROG_DATA
|
2835 BRW_NEW_VUE_MAP_GEOM_OUT
|
2836 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
2839 .emit
= genX(upload_sbe
),
2842 /* ---------------------------------------------------------------------- */
2845 * Outputs the 3DSTATE_SO_DECL_LIST command.
2847 * The data output is a series of 64-bit entries containing a SO_DECL per
2848 * stream. We only have one stream of rendering coming out of the GS unit, so
2849 * we only emit stream 0 (low 16 bits) SO_DECLs.
2852 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
2853 const struct brw_vue_map
*vue_map
)
2855 struct gl_context
*ctx
= &brw
->ctx
;
2856 /* BRW_NEW_TRANSFORM_FEEDBACK */
2857 struct gl_transform_feedback_object
*xfb_obj
=
2858 ctx
->TransformFeedback
.CurrentObject
;
2859 const struct gl_transform_feedback_info
*linked_xfb_info
=
2860 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
2861 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2862 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2863 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2864 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2866 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2868 memset(so_decl
, 0, sizeof(so_decl
));
2870 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2871 * command feels strange -- each dword pair contains a SO_DECL per stream.
2873 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
2874 int buffer
= linked_xfb_info
->Outputs
[i
].OutputBuffer
;
2875 struct GENX(SO_DECL
) decl
= {0};
2876 int varying
= linked_xfb_info
->Outputs
[i
].OutputRegister
;
2877 const unsigned components
= linked_xfb_info
->Outputs
[i
].NumComponents
;
2878 unsigned component_mask
= (1 << components
) - 1;
2879 unsigned stream_id
= linked_xfb_info
->Outputs
[i
].StreamId
;
2880 unsigned decl_buffer_slot
= buffer
;
2881 assert(stream_id
< MAX_VERTEX_STREAMS
);
2883 /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w
2884 * gl_Layer is stored in VARYING_SLOT_PSIZ.y
2885 * gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
2887 if (varying
== VARYING_SLOT_PSIZ
) {
2888 assert(components
== 1);
2889 component_mask
<<= 3;
2890 } else if (varying
== VARYING_SLOT_LAYER
) {
2891 assert(components
== 1);
2892 component_mask
<<= 1;
2893 } else if (varying
== VARYING_SLOT_VIEWPORT
) {
2894 assert(components
== 1);
2895 component_mask
<<= 2;
2897 component_mask
<<= linked_xfb_info
->Outputs
[i
].ComponentOffset
;
2900 buffer_mask
[stream_id
] |= 1 << buffer
;
2902 decl
.OutputBufferSlot
= decl_buffer_slot
;
2903 if (varying
== VARYING_SLOT_LAYER
|| varying
== VARYING_SLOT_VIEWPORT
) {
2904 decl
.RegisterIndex
= vue_map
->varying_to_slot
[VARYING_SLOT_PSIZ
];
2906 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2907 decl
.RegisterIndex
= vue_map
->varying_to_slot
[varying
];
2909 decl
.ComponentMask
= component_mask
;
2911 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2912 * array. Instead, it simply increments DstOffset for the following
2913 * input by the number of components that should be skipped.
2915 * Our hardware is unusual in that it requires us to program SO_DECLs
2916 * for fake "hole" components, rather than simply taking the offset
2917 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2918 * program as many size = 4 holes as we can, then a final hole to
2919 * accommodate the final 1, 2, or 3 remaining.
2921 int skip_components
=
2922 linked_xfb_info
->Outputs
[i
].DstOffset
- next_offset
[buffer
];
2924 next_offset
[buffer
] += skip_components
;
2926 while (skip_components
>= 4) {
2927 struct GENX(SO_DECL
) *d
= &so_decl
[stream_id
][decls
[stream_id
]++];
2929 d
->OutputBufferSlot
= decl_buffer_slot
;
2930 d
->ComponentMask
= 0xf;
2931 skip_components
-= 4;
2934 if (skip_components
> 0) {
2935 struct GENX(SO_DECL
) *d
= &so_decl
[stream_id
][decls
[stream_id
]++];
2937 d
->OutputBufferSlot
= decl_buffer_slot
;
2938 d
->ComponentMask
= (1 << skip_components
) - 1;
2941 assert(linked_xfb_info
->Outputs
[i
].DstOffset
== next_offset
[buffer
]);
2943 next_offset
[buffer
] += components
;
2945 so_decl
[stream_id
][decls
[stream_id
]++] = decl
;
2947 if (decls
[stream_id
] > max_decls
)
2948 max_decls
= decls
[stream_id
];
2952 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
2953 .StreamtoBufferSelects0
= buffer_mask
[0],
2954 .StreamtoBufferSelects1
= buffer_mask
[1],
2955 .StreamtoBufferSelects2
= buffer_mask
[2],
2956 .StreamtoBufferSelects3
= buffer_mask
[3],
2957 .NumEntries0
= decls
[0],
2958 .NumEntries1
= decls
[1],
2959 .NumEntries2
= decls
[2],
2960 .NumEntries3
= decls
[3]);
2962 for (int i
= 0; i
< max_decls
; i
++) {
2963 GENX(SO_DECL_ENTRY_pack
)(
2964 brw
, dw
+ 2 + i
* 2,
2965 &(struct GENX(SO_DECL_ENTRY
)) {
2966 .Stream0Decl
= so_decl
[0][i
],
2967 .Stream1Decl
= so_decl
[1][i
],
2968 .Stream2Decl
= so_decl
[2][i
],
2969 .Stream3Decl
= so_decl
[3][i
],
2975 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
2977 struct gl_context
*ctx
= &brw
->ctx
;
2978 /* BRW_NEW_TRANSFORM_FEEDBACK */
2979 struct gl_transform_feedback_object
*xfb_obj
=
2980 ctx
->TransformFeedback
.CurrentObject
;
2982 const struct gl_transform_feedback_info
*linked_xfb_info
=
2983 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
2985 struct brw_transform_feedback_object
*brw_obj
=
2986 (struct brw_transform_feedback_object
*) xfb_obj
;
2987 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
2990 /* Set up the up to 4 output buffers. These are the ranges defined in the
2991 * gl_transform_feedback_object.
2993 for (int i
= 0; i
< 4; i
++) {
2994 struct intel_buffer_object
*bufferobj
=
2995 intel_buffer_object(xfb_obj
->Buffers
[i
]);
2998 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2999 sob
.SOBufferIndex
= i
;
3004 uint32_t start
= xfb_obj
->Offset
[i
];
3005 assert(start
% 4 == 0);
3006 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3008 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
);
3009 assert(end
<= bo
->size
);
3011 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3012 sob
.SOBufferIndex
= i
;
3014 sob
.SurfaceBaseAddress
= render_bo(bo
, start
);
3016 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3017 sob
.SurfaceEndAddress
= render_bo(bo
, end
);
3019 sob
.SOBufferEnable
= true;
3020 sob
.StreamOffsetWriteEnable
= true;
3021 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3022 sob
.SOBufferMOCS
= mocs_wb
;
3024 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3025 sob
.StreamOutputBufferOffsetAddress
=
3026 instruction_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3028 if (brw_obj
->zero_offsets
) {
3029 /* Zero out the offset and write that to offset_bo */
3030 sob
.StreamOffset
= 0;
3032 /* Use offset_bo as the "Stream Offset." */
3033 sob
.StreamOffset
= 0xFFFFFFFF;
3040 brw_obj
->zero_offsets
= false;
3045 query_active(struct gl_query_object
*q
)
3047 return q
&& q
->Active
;
3051 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3052 const struct brw_vue_map
*vue_map
)
3054 struct gl_context
*ctx
= &brw
->ctx
;
3055 /* BRW_NEW_TRANSFORM_FEEDBACK */
3056 struct gl_transform_feedback_object
*xfb_obj
=
3057 ctx
->TransformFeedback
.CurrentObject
;
3059 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3061 int urb_entry_read_offset
= 0;
3062 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3063 urb_entry_read_offset
;
3065 sos
.SOFunctionEnable
= true;
3066 sos
.SOStatisticsEnable
= true;
3068 /* BRW_NEW_RASTERIZER_DISCARD */
3069 if (ctx
->RasterDiscard
) {
3070 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3071 sos
.RenderingDisable
= true;
3073 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3074 "query active relies on the clipper.");
3079 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3080 sos
.ReorderMode
= TRAILING
;
3083 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3084 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3085 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3086 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3088 const struct gl_transform_feedback_info
*linked_xfb_info
=
3089 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3090 /* Set buffer pitches; 0 means unbound. */
3091 if (xfb_obj
->Buffers
[0])
3092 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3093 if (xfb_obj
->Buffers
[1])
3094 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3095 if (xfb_obj
->Buffers
[2])
3096 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3097 if (xfb_obj
->Buffers
[3])
3098 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3101 /* We always read the whole vertex. This could be reduced at some
3102 * point by reading less and offsetting the register index in the
3105 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3106 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3107 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3108 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3109 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3110 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3111 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3112 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3118 genX(upload_sol
)(struct brw_context
*brw
)
3120 struct gl_context
*ctx
= &brw
->ctx
;
3121 /* BRW_NEW_TRANSFORM_FEEDBACK */
3122 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3125 genX(upload_3dstate_so_buffers
)(brw
);
3127 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3128 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3131 /* Finally, set up the SOL stage. This command must always follow updates to
3132 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3133 * MMIO register updates (current performed by the kernel at each batch
3136 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3139 static const struct brw_tracked_state
genX(sol_state
) = {
3142 .brw
= BRW_NEW_BATCH
|
3144 BRW_NEW_RASTERIZER_DISCARD
|
3145 BRW_NEW_VUE_MAP_GEOM_OUT
|
3146 BRW_NEW_TRANSFORM_FEEDBACK
,
3148 .emit
= genX(upload_sol
),
3151 /* ---------------------------------------------------------------------- */
3154 genX(upload_ps
)(struct brw_context
*brw
)
3156 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3157 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3159 /* BRW_NEW_FS_PROG_DATA */
3160 const struct brw_wm_prog_data
*prog_data
=
3161 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3162 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3167 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3168 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3169 * incorrect for subspans where some of the pixels are unlit. We believe
3170 * the bit just didn't take effect in previous generations.
3172 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3175 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3177 /* BRW_NEW_FS_PROG_DATA */
3178 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3180 if (prog_data
->base
.use_alt_mode
)
3181 ps
.FloatingPointMode
= Alternate
;
3183 /* Haswell requires the sample mask to be set in this packet as well as
3184 * in 3DSTATE_SAMPLE_MASK; the values should match.
3187 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3189 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3192 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3193 * it implicitly scales for different GT levels (which have some # of
3196 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3199 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3201 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3203 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3206 if (prog_data
->base
.nr_params
> 0)
3207 ps
.PushConstantEnable
= true;
3210 /* From the IVB PRM, volume 2 part 1, page 287:
3211 * "This bit is inserted in the PS payload header and made available to
3212 * the DataPort (either via the message header or via header bypass) to
3213 * indicate that oMask data (one or two phases) is included in Render
3214 * Target Write messages. If present, the oMask data is used to mask off
3217 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3219 /* The hardware wedges if you have this bit set but don't turn on any
3220 * dual source blend factors.
3222 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3224 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3225 (ctx
->Color
.BlendEnabled
& 1) &&
3226 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3228 /* BRW_NEW_FS_PROG_DATA */
3229 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3232 /* From the documentation for this packet:
3233 * "If the PS kernel does not need the Position XY Offsets to
3234 * compute a Position Value, then this field should be programmed
3235 * to POSOFFSET_NONE."
3237 * "SW Recommendation: If the PS kernel needs the Position Offsets
3238 * to compute a Position XY value, this field should match Position
3239 * ZW Interpolation Mode to ensure a consistent position.xyzw
3242 * We only require XY sample offsets. So, this recommendation doesn't
3243 * look useful at the moment. We might need this in future.
3245 if (prog_data
->uses_pos_offset
)
3246 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3248 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3250 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3251 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3252 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3253 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3254 prog_data
->base
.dispatch_grf_start_reg
;
3255 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3256 prog_data
->dispatch_grf_start_reg_2
;
3258 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3259 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3260 prog_data
->prog_offset_2
;
3262 if (prog_data
->base
.total_scratch
) {
3263 ps
.ScratchSpaceBasePointer
=
3264 render_bo(stage_state
->scratch_bo
,
3265 ffs(stage_state
->per_thread_scratch
) - 11);
3270 static const struct brw_tracked_state
genX(ps_state
) = {
3272 .mesa
= _NEW_MULTISAMPLE
|
3273 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3276 .brw
= BRW_NEW_BATCH
|
3278 BRW_NEW_FS_PROG_DATA
,
3280 .emit
= genX(upload_ps
),
3283 /* ---------------------------------------------------------------------- */
3286 genX(upload_hs_state
)(struct brw_context
*brw
)
3288 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3289 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3290 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3291 const struct brw_vue_prog_data
*vue_prog_data
=
3292 brw_vue_prog_data(stage_prog_data
);
3294 /* BRW_NEW_TES_PROG_DATA */
3295 struct brw_tcs_prog_data
*tcs_prog_data
=
3296 brw_tcs_prog_data(stage_prog_data
);
3298 if (!tcs_prog_data
) {
3299 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3301 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3302 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3304 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3305 hs
.IncludeVertexHandles
= true;
3307 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3312 static const struct brw_tracked_state
genX(hs_state
) = {
3315 .brw
= BRW_NEW_BATCH
|
3317 BRW_NEW_TCS_PROG_DATA
|
3318 BRW_NEW_TESS_PROGRAMS
,
3320 .emit
= genX(upload_hs_state
),
3324 genX(upload_ds_state
)(struct brw_context
*brw
)
3326 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3327 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3328 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3330 /* BRW_NEW_TES_PROG_DATA */
3331 const struct brw_tes_prog_data
*tes_prog_data
=
3332 brw_tes_prog_data(stage_prog_data
);
3333 const struct brw_vue_prog_data
*vue_prog_data
=
3334 brw_vue_prog_data(stage_prog_data
);
3336 if (!tes_prog_data
) {
3337 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3339 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3340 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3342 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3343 ds
.ComputeWCoordinateEnable
=
3344 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3347 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3348 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3349 ds
.UserClipDistanceCullTestEnableBitmask
=
3350 vue_prog_data
->cull_distance_mask
;
3356 static const struct brw_tracked_state
genX(ds_state
) = {
3359 .brw
= BRW_NEW_BATCH
|
3361 BRW_NEW_TESS_PROGRAMS
|
3362 BRW_NEW_TES_PROG_DATA
,
3364 .emit
= genX(upload_ds_state
),
3367 /* ---------------------------------------------------------------------- */
3370 upload_te_state(struct brw_context
*brw
)
3372 /* BRW_NEW_TESS_PROGRAMS */
3373 bool active
= brw
->tess_eval_program
;
3375 /* BRW_NEW_TES_PROG_DATA */
3376 const struct brw_tes_prog_data
*tes_prog_data
=
3377 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
3380 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
3381 te
.Partitioning
= tes_prog_data
->partitioning
;
3382 te
.OutputTopology
= tes_prog_data
->output_topology
;
3383 te
.TEDomain
= tes_prog_data
->domain
;
3385 te
.MaximumTessellationFactorOdd
= 63.0;
3386 te
.MaximumTessellationFactorNotOdd
= 64.0;
3389 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
3393 static const struct brw_tracked_state
genX(te_state
) = {
3396 .brw
= BRW_NEW_BLORP
|
3398 BRW_NEW_TES_PROG_DATA
|
3399 BRW_NEW_TESS_PROGRAMS
,
3401 .emit
= upload_te_state
,
3404 /* ---------------------------------------------------------------------- */
3407 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
3409 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3410 /* BRW_NEW_TESS_PROGRAMS */
3411 const struct brw_program
*tep
= brw_program_const(brw
->tess_eval_program
);
3414 /* BRW_NEW_TES_PROG_DATA */
3415 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
3416 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
3417 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
3420 upload_constant_state(brw
, stage_state
, tep
, MESA_SHADER_TESS_EVAL
);
3423 static const struct brw_tracked_state
genX(tes_push_constants
) = {
3425 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3426 .brw
= BRW_NEW_BATCH
|
3428 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3429 BRW_NEW_TESS_PROGRAMS
|
3430 BRW_NEW_TES_PROG_DATA
,
3432 .emit
= genX(upload_tes_push_constants
),
3436 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
3438 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3439 /* BRW_NEW_TESS_PROGRAMS */
3440 const struct brw_program
*tcp
= brw_program_const(brw
->tess_ctrl_program
);
3441 bool active
= brw
->tess_eval_program
;
3444 /* BRW_NEW_TCS_PROG_DATA */
3445 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
3447 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
3448 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
3451 upload_constant_state(brw
, stage_state
, active
, MESA_SHADER_TESS_CTRL
);
3454 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
3456 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3457 .brw
= BRW_NEW_BATCH
|
3459 BRW_NEW_DEFAULT_TESS_LEVELS
|
3460 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3461 BRW_NEW_TESS_PROGRAMS
|
3462 BRW_NEW_TCS_PROG_DATA
,
3464 .emit
= genX(upload_tcs_push_constants
),
3468 /* ---------------------------------------------------------------------- */
3472 genX(upload_raster
)(struct brw_context
*brw
)
3474 struct gl_context
*ctx
= &brw
->ctx
;
3477 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3480 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
3483 struct gl_point_attrib
*point
= &ctx
->Point
;
3485 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
3486 if (polygon
->_FrontBit
== render_to_fbo
)
3487 raster
.FrontWinding
= CounterClockwise
;
3489 if (polygon
->CullFlag
) {
3490 switch (polygon
->CullFaceMode
) {
3492 raster
.CullMode
= CULLMODE_FRONT
;
3495 raster
.CullMode
= CULLMODE_BACK
;
3497 case GL_FRONT_AND_BACK
:
3498 raster
.CullMode
= CULLMODE_BOTH
;
3501 unreachable("not reached");
3504 raster
.CullMode
= CULLMODE_NONE
;
3507 point
->SmoothFlag
= raster
.SmoothPointEnable
;
3509 raster
.DXMultisampleRasterizationEnable
=
3510 _mesa_is_multisample_enabled(ctx
);
3512 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
3513 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
3514 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
3516 switch (polygon
->FrontMode
) {
3518 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
3521 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
3524 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
3527 unreachable("not reached");
3530 switch (polygon
->BackMode
) {
3532 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
3535 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
3538 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
3541 unreachable("not reached");
3545 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
3548 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
3550 /* _NEW_TRANSFORM */
3551 if (!ctx
->Transform
.DepthClamp
) {
3553 raster
.ViewportZFarClipTestEnable
= true;
3554 raster
.ViewportZNearClipTestEnable
= true;
3556 raster
.ViewportZClipTestEnable
= true;
3560 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
3562 raster
.ConservativeRasterizationEnable
=
3563 ctx
->IntelConservativeRasterization
;
3566 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
3567 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
3569 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
3573 static const struct brw_tracked_state
genX(raster_state
) = {
3575 .mesa
= _NEW_BUFFERS
|
3582 .brw
= BRW_NEW_BLORP
|
3584 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3586 .emit
= genX(upload_raster
),
3589 /* ---------------------------------------------------------------------- */
3592 genX(upload_ps_extra
)(struct brw_context
*brw
)
3594 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
3596 const struct brw_wm_prog_data
*prog_data
=
3597 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3599 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
3600 psx
.PixelShaderValid
= true;
3601 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
3602 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
3603 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
3604 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
3605 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
3606 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
3608 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
3609 if (prog_data
->uses_sample_mask
) {
3611 if (prog_data
->post_depth_coverage
)
3612 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3613 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
3614 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
3616 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3618 psx
.PixelShaderUsesInputCoverageMask
= true;
3622 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3624 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
3625 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
3628 /* The stricter cross-primitive coherency guarantees that the hardware
3629 * gives us with the "Accesses UAV" bit set for at least one shader stage
3630 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
3631 * are redundant within the current image, atomic counter and SSBO GL
3632 * APIs, which all have very loose ordering and coherency requirements
3633 * and generally rely on the application to insert explicit barriers when
3634 * a shader invocation is expected to see the memory writes performed by
3635 * the invocations of some previous primitive. Regardless of the value
3636 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
3637 * cause an in most cases useless DC flush when the lowermost stage with
3638 * the bit set finishes execution.
3640 * It would be nice to disable it, but in some cases we can't because on
3641 * Gen8+ it also has an influence on rasterization via the PS UAV-only
3642 * signal (which could be set independently from the coherency mechanism
3643 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
3644 * determine whether the hardware skips execution of the fragment shader
3645 * or not via the ThreadDispatchEnable signal. However if we know that
3646 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
3647 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
3648 * difference so we may just disable it here.
3650 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
3651 * take into account KillPixels when no depth or stencil writes are
3652 * enabled. In order for occlusion queries to work correctly with no
3653 * attachments, we need to force-enable here.
3655 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
3658 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
3659 !brw_color_buffer_write_enabled(brw
))
3660 psx
.PixelShaderHasUAV
= true;
3664 const struct brw_tracked_state
genX(ps_extra
) = {
3666 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
3667 .brw
= BRW_NEW_BLORP
|
3669 BRW_NEW_FRAGMENT_PROGRAM
|
3670 BRW_NEW_FS_PROG_DATA
|
3671 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3673 .emit
= genX(upload_ps_extra
),
3676 /* ---------------------------------------------------------------------- */
3679 genX(upload_ps_blend
)(struct brw_context
*brw
)
3681 struct gl_context
*ctx
= &brw
->ctx
;
3684 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
3685 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
3688 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
3690 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
3691 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
3692 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
3694 if (!buffer0_is_integer
) {
3695 /* _NEW_MULTISAMPLE */
3696 pb
.AlphaToCoverageEnable
=
3697 _mesa_is_multisample_enabled(ctx
) &&
3698 ctx
->Multisample
.SampleAlphaToCoverage
;
3700 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
3703 /* Used for implementing the following bit of GL_EXT_texture_integer:
3704 * "Per-fragment operations that require floating-point color
3705 * components, including multisample alpha operations, alpha test,
3706 * blending, and dithering, have no effect when the corresponding
3707 * colors are written to an integer color buffer."
3709 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
3710 * "If drawbuffer zero is not NONE and the buffer it references has an
3711 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
3712 * operations are skipped."
3714 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
3715 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
3716 GLenum eqA
= color
->Blend
[0].EquationA
;
3717 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
3718 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
3719 GLenum srcA
= color
->Blend
[0].SrcA
;
3720 GLenum dstA
= color
->Blend
[0].DstA
;
3722 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
3723 srcRGB
= dstRGB
= GL_ONE
;
3725 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
3726 srcA
= dstA
= GL_ONE
;
3728 /* Due to hardware limitations, the destination may have information
3729 * in an alpha channel even when the format specifies no alpha
3730 * channel. In order to avoid getting any incorrect blending due to
3731 * that alpha channel, coerce the blend factors to values that will
3732 * not read the alpha channel, but will instead use the correct
3733 * implicit value for alpha.
3735 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
3736 GL_TEXTURE_ALPHA_TYPE
)) {
3737 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
3738 srcA
= brw_fix_xRGB_alpha(srcA
);
3739 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
3740 dstA
= brw_fix_xRGB_alpha(dstA
);
3743 pb
.ColorBufferBlendEnable
= true;
3744 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
3745 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
3746 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
3747 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
3749 pb
.IndependentAlphaBlendEnable
=
3750 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
3755 static const struct brw_tracked_state
genX(ps_blend
) = {
3757 .mesa
= _NEW_BUFFERS
|
3760 .brw
= BRW_NEW_BLORP
|
3762 BRW_NEW_FRAGMENT_PROGRAM
,
3764 .emit
= genX(upload_ps_blend
)
3769 /* ---------------------------------------------------------------------- */
3773 genX(upload_viewport_state_pointers
)(struct brw_context
*brw
)
3775 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
3776 vp
.CCViewportStateChange
= 1;
3777 vp
.SFViewportStateChange
= 1;
3778 vp
.CLIPViewportStateChange
= 1;
3779 vp
.PointertoCLIP_VIEWPORT
= brw
->clip
.vp_offset
;
3780 vp
.PointertoSF_VIEWPORT
= brw
->sf
.vp_offset
;
3781 vp
.PointertoCC_VIEWPORT
= brw
->cc
.vp_offset
;
3785 static const struct brw_tracked_state
genX(viewport_state
) = {
3788 .brw
= BRW_NEW_BATCH
|
3793 BRW_NEW_STATE_BASE_ADDRESS
,
3795 .emit
= genX(upload_viewport_state_pointers
),
3799 /* ---------------------------------------------------------------------- */
3802 genX(init_atoms
)(struct brw_context
*brw
)
3805 static const struct brw_tracked_state
*render_atoms
[] =
3807 /* Once all the programs are done, we know how large urb entry
3808 * sizes need to be and can decide if we need to change the urb
3812 &brw_recalculate_urb_fence
,
3817 /* Surface state setup. Must come before the VS/WM unit. The binding
3818 * table upload must be last.
3820 &brw_vs_pull_constants
,
3821 &brw_wm_pull_constants
,
3822 &brw_renderbuffer_surfaces
,
3823 &brw_renderbuffer_read_surfaces
,
3824 &brw_texture_surfaces
,
3825 &brw_vs_binding_table
,
3826 &brw_wm_binding_table
,
3831 /* These set up state for brw_psp_urb_cbs */
3835 &brw_vs_unit
, /* always required, enabled or not */
3841 &brw_invariant_state
,
3843 &brw_binding_table_pointers
,
3844 &brw_blend_constant_color
,
3848 &genX(polygon_stipple
),
3849 &genX(polygon_stipple_offset
),
3851 &genX(line_stipple
),
3855 &genX(drawing_rect
),
3856 &brw_indices
, /* must come before brw_vertices */
3860 &brw_constant_buffer
3863 static const struct brw_tracked_state
*render_atoms
[] =
3865 &genX(sf_clip_viewport
),
3867 /* Command packets: */
3870 &genX(viewport_state
), /* must do after *_vp stages */
3873 &genX(blend_state
), /* must do before cc unit */
3874 &genX(color_calc_state
), /* must do before cc unit */
3875 &gen6_depth_stencil_state
, /* must do before cc unit */
3877 &genX(vs_push_constants
), /* Before vs_state */
3878 &genX(gs_push_constants
), /* Before gs_state */
3879 &genX(wm_push_constants
), /* Before wm_state */
3881 /* Surface state setup. Must come before the VS/WM unit. The binding
3882 * table upload must be last.
3884 &brw_vs_pull_constants
,
3885 &brw_vs_ubo_surfaces
,
3886 &brw_gs_pull_constants
,
3887 &brw_gs_ubo_surfaces
,
3888 &brw_wm_pull_constants
,
3889 &brw_wm_ubo_surfaces
,
3890 &gen6_renderbuffer_surfaces
,
3891 &brw_renderbuffer_read_surfaces
,
3892 &brw_texture_surfaces
,
3894 &brw_vs_binding_table
,
3895 &gen6_gs_binding_table
,
3896 &brw_wm_binding_table
,
3901 &gen6_sampler_state
,
3902 &genX(multisample_state
),
3910 &genX(scissor_state
),
3912 &gen6_binding_table_pointers
,
3916 &genX(polygon_stipple
),
3917 &genX(polygon_stipple_offset
),
3919 &genX(line_stipple
),
3921 &genX(drawing_rect
),
3923 &brw_indices
, /* must come before brw_vertices */
3928 static const struct brw_tracked_state
*render_atoms
[] =
3930 /* Command packets: */
3933 &genX(sf_clip_viewport
),
3936 &gen7_push_constant_space
,
3938 &genX(blend_state
), /* must do before cc unit */
3939 &genX(color_calc_state
), /* must do before cc unit */
3940 &genX(depth_stencil_state
), /* must do before cc unit */
3942 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
3943 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
3944 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
3945 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
3946 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
3948 &genX(vs_push_constants
), /* Before vs_state */
3949 &genX(tcs_push_constants
),
3950 &genX(tes_push_constants
),
3951 &genX(gs_push_constants
), /* Before gs_state */
3952 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
3954 /* Surface state setup. Must come before the VS/WM unit. The binding
3955 * table upload must be last.
3957 &brw_vs_pull_constants
,
3958 &brw_vs_ubo_surfaces
,
3959 &brw_vs_abo_surfaces
,
3960 &brw_tcs_pull_constants
,
3961 &brw_tcs_ubo_surfaces
,
3962 &brw_tcs_abo_surfaces
,
3963 &brw_tes_pull_constants
,
3964 &brw_tes_ubo_surfaces
,
3965 &brw_tes_abo_surfaces
,
3966 &brw_gs_pull_constants
,
3967 &brw_gs_ubo_surfaces
,
3968 &brw_gs_abo_surfaces
,
3969 &brw_wm_pull_constants
,
3970 &brw_wm_ubo_surfaces
,
3971 &brw_wm_abo_surfaces
,
3972 &gen6_renderbuffer_surfaces
,
3973 &brw_renderbuffer_read_surfaces
,
3974 &brw_texture_surfaces
,
3975 &brw_vs_binding_table
,
3976 &brw_tcs_binding_table
,
3977 &brw_tes_binding_table
,
3978 &brw_gs_binding_table
,
3979 &brw_wm_binding_table
,
3986 &genX(multisample_state
),
4000 &genX(scissor_state
),
4004 &genX(polygon_stipple
),
4005 &genX(polygon_stipple_offset
),
4007 &genX(line_stipple
),
4009 &genX(drawing_rect
),
4011 &brw_indices
, /* must come before brw_vertices */
4018 static const struct brw_tracked_state
*render_atoms
[] =
4021 &genX(sf_clip_viewport
),
4024 &gen7_push_constant_space
,
4027 &genX(color_calc_state
),
4029 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4030 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4031 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4032 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4033 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4035 &genX(vs_push_constants
), /* Before vs_state */
4036 &genX(tcs_push_constants
),
4037 &genX(tes_push_constants
),
4038 &genX(gs_push_constants
), /* Before gs_state */
4039 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4041 /* Surface state setup. Must come before the VS/WM unit. The binding
4042 * table upload must be last.
4044 &brw_vs_pull_constants
,
4045 &brw_vs_ubo_surfaces
,
4046 &brw_vs_abo_surfaces
,
4047 &brw_tcs_pull_constants
,
4048 &brw_tcs_ubo_surfaces
,
4049 &brw_tcs_abo_surfaces
,
4050 &brw_tes_pull_constants
,
4051 &brw_tes_ubo_surfaces
,
4052 &brw_tes_abo_surfaces
,
4053 &brw_gs_pull_constants
,
4054 &brw_gs_ubo_surfaces
,
4055 &brw_gs_abo_surfaces
,
4056 &brw_wm_pull_constants
,
4057 &brw_wm_ubo_surfaces
,
4058 &brw_wm_abo_surfaces
,
4059 &gen6_renderbuffer_surfaces
,
4060 &brw_renderbuffer_read_surfaces
,
4061 &brw_texture_surfaces
,
4062 &brw_vs_binding_table
,
4063 &brw_tcs_binding_table
,
4064 &brw_tes_binding_table
,
4065 &brw_gs_binding_table
,
4066 &brw_wm_binding_table
,
4073 &genX(multisample_state
),
4082 &genX(raster_state
),
4088 &genX(depth_stencil_state
),
4091 &genX(scissor_state
),
4095 &genX(polygon_stipple
),
4096 &genX(polygon_stipple_offset
),
4098 &genX(line_stipple
),
4100 &genX(drawing_rect
),
4113 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
4114 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
4115 render_atoms
, ARRAY_SIZE(render_atoms
));
4118 static const struct brw_tracked_state
*compute_atoms
[] =
4121 &brw_cs_image_surfaces
,
4122 &gen7_cs_push_constants
,
4123 &brw_cs_pull_constants
,
4124 &brw_cs_ubo_surfaces
,
4125 &brw_cs_abo_surfaces
,
4126 &brw_cs_texture_surfaces
,
4127 &brw_cs_work_groups_surface
,
4132 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
4133 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
4134 compute_atoms
, ARRAY_SIZE(compute_atoms
));