src/mesa/drivers/dri/i965/genX_state_upload.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "common/gen_device_info.h"
  27 #include "genxml/gen_macros.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31
  32 #include "intel_batchbuffer.h"
  33 #include "intel_fbo.h"
  34
  35 #include "main/fbobject.h"
  36 #include "main/framebuffer.h"
  37 #include "main/stencil.h"
  38
  39 UNUSED static void *
  40 emit_dwords(struct brw_context *brw, unsigned n)
  41 {
  42    intel_batchbuffer_begin(brw, n, RENDER_RING);
  43    uint32_t *map = brw->batch.map_next;
  44    brw->batch.map_next += n;
  45    intel_batchbuffer_advance(brw);
  46    return map;
  47 }
  48
  49 struct brw_address {
  50    struct brw_bo *bo;
  51    uint32_t read_domains;
  52    uint32_t write_domain;
  53    uint32_t offset;
  54 };
  55
  56 static uint64_t
  57 emit_reloc(struct brw_context *brw,
  58            void *location, struct brw_address address, uint32_t delta)
  59 {
  60    uint32_t offset = (char *) location - (char *) brw->batch.map;
  61
  62    return brw_emit_reloc(&brw->batch, offset, address.bo,
  63                          address.offset + delta,
  64                          address.read_domains,
  65                          address.write_domain);
  66 }
  67
  68 #define __gen_address_type struct brw_address
  69 #define __gen_user_data struct brw_context
  70
  71 static uint64_t
  72 __gen_combine_address(struct brw_context *brw, void *location,
  73                       struct brw_address address, uint32_t delta)
  74 {
  75    if (address.bo == NULL) {
  76       return address.offset + delta;
  77    } else {
  78       return emit_reloc(brw, location, address, delta);
  79    }
  80 }
  81
  82 #include "genxml/genX_pack.h"
  83
  84 #define _brw_cmd_length(cmd) cmd ## _length
  85 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
  86 #define _brw_cmd_header(cmd) cmd ## _header
  87 #define _brw_cmd_pack(cmd) cmd ## _pack
  88
  89 #define brw_batch_emit(brw, cmd, name)                  \
  90    for (struct cmd name = { _brw_cmd_header(cmd) },     \
  91         *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
  92         __builtin_expect(_dst != NULL, 1);              \
  93         _brw_cmd_pack(cmd)(brw, (void *)_dst, &name),   \
  94         _dst = NULL)
  95
  96 #define brw_batch_emitn(brw, cmd, n) ({                \
  97       uint32_t *_dw = emit_dwords(brw, n);             \
  98       struct cmd template = {                          \
  99          _brw_cmd_header(cmd),                         \
 100          .DWordLength = n - _brw_cmd_length_bias(cmd), \
 101       };                                               \
 102       _brw_cmd_pack(cmd)(brw, _dw, &template);         \
 103       _dw + 1; /* Array starts at dw[1] */             \
 104    })
 105
 106 #define brw_state_emit(brw, cmd, align, offset, name)              \
 107    for (struct cmd name = { 0, },                                  \
 108         *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4,     \
 109                                 align, offset);                    \
 110         __builtin_expect(_dst != NULL, 1);                         \
 111         _brw_cmd_pack(cmd)(brw, (void *)_dst, &name),              \
 112         _dst = NULL)
 113
 114 /* ---------------------------------------------------------------------- */
 115
 116 #if GEN_GEN >= 6
 117
 118 /* ---------------------------------------------------------------------- */
 119
 120 static void
 121 genX(upload_depth_stencil_state)(struct brw_context *brw)
 122 {
 123    struct gl_context *ctx = &brw->ctx;
 124
 125    /* _NEW_BUFFERS */
 126    struct intel_renderbuffer *depth_irb =
 127       intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 128
 129    /* _NEW_DEPTH */
 130    struct gl_depthbuffer_attrib *depth = &ctx->Depth;
 131
 132    /* _NEW_STENCIL */
 133    struct gl_stencil_attrib *stencil = &ctx->Stencil;
 134    const int b = stencil->_BackFace;
 135
 136 #if GEN_GEN >= 8
 137    brw_batch_emit(brw, GENX(3DSTATE_WM_DEPTH_STENCIL), wmds) {
 138 #else
 139    uint32_t ds_offset;
 140    brw_state_emit(brw, GENX(DEPTH_STENCIL_STATE), 64, &ds_offset, wmds) {
 141 #endif
 142       if (depth->Test && depth_irb) {
 143          wmds.DepthTestEnable = true;
 144          wmds.DepthBufferWriteEnable = brw_depth_writes_enabled(brw);
 145          wmds.DepthTestFunction = intel_translate_compare_func(depth->Func);
 146       }
 147
 148       if (stencil->_Enabled) {
 149          wmds.StencilTestEnable = true;
 150          wmds.StencilWriteMask = stencil->WriteMask[0] & 0xff;
 151          wmds.StencilTestMask = stencil->ValueMask[0] & 0xff;
 152
 153          wmds.StencilTestFunction =
 154             intel_translate_compare_func(stencil->Function[0]);
 155          wmds.StencilFailOp =
 156             intel_translate_stencil_op(stencil->FailFunc[0]);
 157          wmds.StencilPassDepthPassOp =
 158             intel_translate_stencil_op(stencil->ZPassFunc[0]);
 159          wmds.StencilPassDepthFailOp =
 160             intel_translate_stencil_op(stencil->ZFailFunc[0]);
 161
 162          wmds.StencilBufferWriteEnable = stencil->_WriteEnabled;
 163
 164          if (stencil->_TestTwoSide) {
 165             wmds.DoubleSidedStencilEnable = true;
 166             wmds.BackfaceStencilWriteMask = stencil->WriteMask[b] & 0xff;
 167             wmds.BackfaceStencilTestMask = stencil->ValueMask[b] & 0xff;
 168
 169             wmds.BackfaceStencilTestFunction =
 170                intel_translate_compare_func(stencil->Function[b]);
 171             wmds.BackfaceStencilFailOp =
 172                intel_translate_stencil_op(stencil->FailFunc[b]);
 173             wmds.BackfaceStencilPassDepthPassOp =
 174                intel_translate_stencil_op(stencil->ZPassFunc[b]);
 175             wmds.BackfaceStencilPassDepthFailOp =
 176                intel_translate_stencil_op(stencil->ZFailFunc[b]);
 177          }
 178
 179 #if GEN_GEN >= 9
 180          wmds.StencilReferenceValue = _mesa_get_stencil_ref(ctx, 0);
 181          wmds.BackfaceStencilReferenceValue = _mesa_get_stencil_ref(ctx, b);
 182 #endif
 183       }
 184    }
 185
 186 #if GEN_GEN == 6
 187    brw_batch_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
 188       ptr.PointertoDEPTH_STENCIL_STATE = ds_offset;
 189       ptr.DEPTH_STENCIL_STATEChange = true;
 190    }
 191 #elif GEN_GEN == 7
 192    brw_batch_emit(brw, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), ptr) {
 193       ptr.PointertoDEPTH_STENCIL_STATE = ds_offset;
 194    }
 195 #endif
 196 }
 197
 198 static const struct brw_tracked_state genX(depth_stencil_state) = {
 199    .dirty = {
 200       .mesa = _NEW_BUFFERS |
 201               _NEW_DEPTH |
 202               _NEW_STENCIL,
 203       .brw  = BRW_NEW_BLORP |
 204               (GEN_GEN >= 8 ? BRW_NEW_CONTEXT
 205                             : BRW_NEW_BATCH |
 206                               BRW_NEW_STATE_BASE_ADDRESS),
 207    },
 208    .emit = genX(upload_depth_stencil_state),
 209 };
 210
 211 /* ---------------------------------------------------------------------- */
 212
 213 static void
 214 genX(upload_clip_state)(struct brw_context *brw)
 215 {
 216    struct gl_context *ctx = &brw->ctx;
 217
 218    /* _NEW_BUFFERS */
 219    struct gl_framebuffer *fb = ctx->DrawBuffer;
 220
 221    /* BRW_NEW_FS_PROG_DATA */
 222    struct brw_wm_prog_data *wm_prog_data =
 223       brw_wm_prog_data(brw->wm.base.prog_data);
 224
 225    brw_batch_emit(brw, GENX(3DSTATE_CLIP), clip) {
 226       clip.StatisticsEnable = !brw->meta_in_progress;
 227
 228       if (wm_prog_data->barycentric_interp_modes &
 229           BRW_BARYCENTRIC_NONPERSPECTIVE_BITS)
 230          clip.NonPerspectiveBarycentricEnable = true;
 231
 232 #if GEN_GEN >= 7
 233       clip.EarlyCullEnable = true;
 234 #endif
 235
 236 #if GEN_GEN == 7
 237       clip.FrontWinding = ctx->Polygon._FrontBit == _mesa_is_user_fbo(fb);
 238
 239       if (ctx->Polygon.CullFlag) {
 240          switch (ctx->Polygon.CullFaceMode) {
 241          case GL_FRONT:
 242             clip.CullMode = CULLMODE_FRONT;
 243             break;
 244          case GL_BACK:
 245             clip.CullMode = CULLMODE_BACK;
 246             break;
 247          case GL_FRONT_AND_BACK:
 248             clip.CullMode = CULLMODE_BOTH;
 249             break;
 250          default:
 251             unreachable("Should not get here: invalid CullFlag");
 252          }
 253       } else {
 254          clip.CullMode = CULLMODE_NONE;
 255       }
 256 #endif
 257
 258 #if GEN_GEN < 8
 259       clip.UserClipDistanceCullTestEnableBitmask =
 260          brw_vue_prog_data(brw->vs.base.prog_data)->cull_distance_mask;
 261
 262       clip.ViewportZClipTestEnable = !ctx->Transform.DepthClamp;
 263 #endif
 264
 265       /* _NEW_LIGHT */
 266       if (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
 267          clip.TriangleStripListProvokingVertexSelect = 0;
 268          clip.TriangleFanProvokingVertexSelect = 1;
 269          clip.LineStripListProvokingVertexSelect = 0;
 270       } else {
 271          clip.TriangleStripListProvokingVertexSelect = 2;
 272          clip.TriangleFanProvokingVertexSelect = 2;
 273          clip.LineStripListProvokingVertexSelect = 1;
 274       }
 275
 276       /* _NEW_TRANSFORM */
 277       clip.UserClipDistanceClipTestEnableBitmask =
 278          ctx->Transform.ClipPlanesEnabled;
 279
 280 #if GEN_GEN >= 8
 281       clip.ForceUserClipDistanceClipTestEnableBitmask = true;
 282 #endif
 283
 284       if (ctx->Transform.ClipDepthMode == GL_ZERO_TO_ONE)
 285          clip.APIMode = APIMODE_D3D;
 286       else
 287          clip.APIMode = APIMODE_OGL;
 288
 289       clip.GuardbandClipTestEnable = true;
 290
 291       /* BRW_NEW_VIEWPORT_COUNT */
 292       const unsigned viewport_count = brw->clip.viewport_count;
 293
 294       if (ctx->RasterDiscard) {
 295          clip.ClipMode = CLIPMODE_REJECT_ALL;
 296 #if GEN_GEN == 6
 297          perf_debug("Rasterizer discard is currently implemented via the "
 298                     "clipper; having the GS not write primitives would "
 299                     "likely be faster.\n");
 300 #endif
 301       } else {
 302          clip.ClipMode = CLIPMODE_NORMAL;
 303       }
 304
 305       clip.ClipEnable = brw->primitive != _3DPRIM_RECTLIST;
 306
 307       /* _NEW_POLYGON,
 308        * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
 309        */
 310       if (!brw_is_drawing_points(brw) && !brw_is_drawing_lines(brw))
 311          clip.ViewportXYClipTestEnable = true;
 312
 313       clip.MinimumPointWidth = 0.125;
 314       clip.MaximumPointWidth = 255.875;
 315       clip.MaximumVPIndex = viewport_count - 1;
 316       if (_mesa_geometric_layers(fb) == 0)
 317          clip.ForceZeroRTAIndexEnable = true;
 318    }
 319 }
 320
 321 static const struct brw_tracked_state genX(clip_state) = {
 322    .dirty = {
 323       .mesa  = _NEW_BUFFERS |
 324                _NEW_LIGHT |
 325                _NEW_POLYGON |
 326                _NEW_TRANSFORM,
 327       .brw   = BRW_NEW_BLORP |
 328                BRW_NEW_CONTEXT |
 329                BRW_NEW_FS_PROG_DATA |
 330                BRW_NEW_GS_PROG_DATA |
 331                BRW_NEW_VS_PROG_DATA |
 332                BRW_NEW_META_IN_PROGRESS |
 333                BRW_NEW_PRIMITIVE |
 334                BRW_NEW_RASTERIZER_DISCARD |
 335                BRW_NEW_TES_PROG_DATA |
 336                BRW_NEW_VIEWPORT_COUNT,
 337    },
 338    .emit = genX(upload_clip_state),
 339 };
 340
 341 /* ---------------------------------------------------------------------- */
 342
 343 #endif
 344
 345 void
 346 genX(init_atoms)(struct brw_context *brw)
 347 {
 348 #if GEN_GEN < 6
 349    static const struct brw_tracked_state *render_atoms[] =
 350    {
 351       /* Once all the programs are done, we know how large urb entry
 352        * sizes need to be and can decide if we need to change the urb
 353        * layout.
 354        */
 355       &brw_curbe_offsets,
 356       &brw_recalculate_urb_fence,
 357
 358       &brw_cc_vp,
 359       &brw_cc_unit,
 360
 361       /* Surface state setup.  Must come before the VS/WM unit.  The binding
 362        * table upload must be last.
 363        */
 364       &brw_vs_pull_constants,
 365       &brw_wm_pull_constants,
 366       &brw_renderbuffer_surfaces,
 367       &brw_renderbuffer_read_surfaces,
 368       &brw_texture_surfaces,
 369       &brw_vs_binding_table,
 370       &brw_wm_binding_table,
 371
 372       &brw_fs_samplers,
 373       &brw_vs_samplers,
 374
 375       /* These set up state for brw_psp_urb_cbs */
 376       &brw_wm_unit,
 377       &brw_sf_vp,
 378       &brw_sf_unit,
 379       &brw_vs_unit,             /* always required, enabled or not */
 380       &brw_clip_unit,
 381       &brw_gs_unit,
 382
 383       /* Command packets:
 384        */
 385       &brw_invariant_state,
 386
 387       &brw_binding_table_pointers,
 388       &brw_blend_constant_color,
 389
 390       &brw_depthbuffer,
 391
 392       &brw_polygon_stipple,
 393       &brw_polygon_stipple_offset,
 394
 395       &brw_line_stipple,
 396
 397       &brw_psp_urb_cbs,
 398
 399       &brw_drawing_rect,
 400       &brw_indices, /* must come before brw_vertices */
 401       &brw_index_buffer,
 402       &brw_vertices,
 403
 404       &brw_constant_buffer
 405    };
 406 #elif GEN_GEN == 6
 407    static const struct brw_tracked_state *render_atoms[] =
 408    {
 409       &gen6_sf_and_clip_viewports,
 410
 411       /* Command packets: */
 412
 413       &brw_cc_vp,
 414       &gen6_viewport_state,     /* must do after *_vp stages */
 415
 416       &gen6_urb,
 417       &gen6_blend_state,                /* must do before cc unit */
 418       &gen6_color_calc_state,   /* must do before cc unit */
 419       &gen6_depth_stencil_state,        /* must do before cc unit */
 420
 421       &gen6_vs_push_constants, /* Before vs_state */
 422       &gen6_gs_push_constants, /* Before gs_state */
 423       &gen6_wm_push_constants, /* Before wm_state */
 424
 425       /* Surface state setup.  Must come before the VS/WM unit.  The binding
 426        * table upload must be last.
 427        */
 428       &brw_vs_pull_constants,
 429       &brw_vs_ubo_surfaces,
 430       &brw_gs_pull_constants,
 431       &brw_gs_ubo_surfaces,
 432       &brw_wm_pull_constants,
 433       &brw_wm_ubo_surfaces,
 434       &gen6_renderbuffer_surfaces,
 435       &brw_renderbuffer_read_surfaces,
 436       &brw_texture_surfaces,
 437       &gen6_sol_surface,
 438       &brw_vs_binding_table,
 439       &gen6_gs_binding_table,
 440       &brw_wm_binding_table,
 441
 442       &brw_fs_samplers,
 443       &brw_vs_samplers,
 444       &brw_gs_samplers,
 445       &gen6_sampler_state,
 446       &gen6_multisample_state,
 447
 448       &gen6_vs_state,
 449       &gen6_gs_state,
 450       &genX(clip_state),
 451       &gen6_sf_state,
 452       &gen6_wm_state,
 453
 454       &gen6_scissor_state,
 455
 456       &gen6_binding_table_pointers,
 457
 458       &brw_depthbuffer,
 459
 460       &brw_polygon_stipple,
 461       &brw_polygon_stipple_offset,
 462
 463       &brw_line_stipple,
 464
 465       &brw_drawing_rect,
 466
 467       &brw_indices, /* must come before brw_vertices */
 468       &brw_index_buffer,
 469       &brw_vertices,
 470    };
 471 #elif GEN_GEN == 7
 472    static const struct brw_tracked_state *render_atoms[] =
 473    {
 474       /* Command packets: */
 475
 476       &brw_cc_vp,
 477       &gen7_sf_clip_viewport,
 478
 479       &gen7_l3_state,
 480       &gen7_push_constant_space,
 481       &gen7_urb,
 482       &gen6_blend_state,                /* must do before cc unit */
 483       &gen6_color_calc_state,   /* must do before cc unit */
 484       &genX(depth_stencil_state),       /* must do before cc unit */
 485
 486       &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
 487       &brw_tcs_image_surfaces, /* Before tcs push/pull constants and binding table */
 488       &brw_tes_image_surfaces, /* Before tes push/pull constants and binding table */
 489       &brw_gs_image_surfaces, /* Before gs push/pull constants and binding table */
 490       &brw_wm_image_surfaces, /* Before wm push/pull constants and binding table */
 491
 492       &gen6_vs_push_constants, /* Before vs_state */
 493       &gen7_tcs_push_constants,
 494       &gen7_tes_push_constants,
 495       &gen6_gs_push_constants, /* Before gs_state */
 496       &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 497
 498       /* Surface state setup.  Must come before the VS/WM unit.  The binding
 499        * table upload must be last.
 500        */
 501       &brw_vs_pull_constants,
 502       &brw_vs_ubo_surfaces,
 503       &brw_vs_abo_surfaces,
 504       &brw_tcs_pull_constants,
 505       &brw_tcs_ubo_surfaces,
 506       &brw_tcs_abo_surfaces,
 507       &brw_tes_pull_constants,
 508       &brw_tes_ubo_surfaces,
 509       &brw_tes_abo_surfaces,
 510       &brw_gs_pull_constants,
 511       &brw_gs_ubo_surfaces,
 512       &brw_gs_abo_surfaces,
 513       &brw_wm_pull_constants,
 514       &brw_wm_ubo_surfaces,
 515       &brw_wm_abo_surfaces,
 516       &gen6_renderbuffer_surfaces,
 517       &brw_renderbuffer_read_surfaces,
 518       &brw_texture_surfaces,
 519       &brw_vs_binding_table,
 520       &brw_tcs_binding_table,
 521       &brw_tes_binding_table,
 522       &brw_gs_binding_table,
 523       &brw_wm_binding_table,
 524
 525       &brw_fs_samplers,
 526       &brw_vs_samplers,
 527       &brw_tcs_samplers,
 528       &brw_tes_samplers,
 529       &brw_gs_samplers,
 530       &gen6_multisample_state,
 531
 532       &gen7_vs_state,
 533       &gen7_hs_state,
 534       &gen7_te_state,
 535       &gen7_ds_state,
 536       &gen7_gs_state,
 537       &gen7_sol_state,
 538       &genX(clip_state),
 539       &gen7_sbe_state,
 540       &gen7_sf_state,
 541       &gen7_wm_state,
 542       &gen7_ps_state,
 543
 544       &gen6_scissor_state,
 545
 546       &gen7_depthbuffer,
 547
 548       &brw_polygon_stipple,
 549       &brw_polygon_stipple_offset,
 550
 551       &brw_line_stipple,
 552
 553       &brw_drawing_rect,
 554
 555       &brw_indices, /* must come before brw_vertices */
 556       &brw_index_buffer,
 557       &brw_vertices,
 558
 559       &haswell_cut_index,
 560    };
 561 #elif GEN_GEN >= 8
 562    static const struct brw_tracked_state *render_atoms[] =
 563    {
 564       &brw_cc_vp,
 565       &gen8_sf_clip_viewport,
 566
 567       &gen7_l3_state,
 568       &gen7_push_constant_space,
 569       &gen7_urb,
 570       &gen8_blend_state,
 571       &gen6_color_calc_state,
 572
 573       &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
 574       &brw_tcs_image_surfaces, /* Before tcs push/pull constants and binding table */
 575       &brw_tes_image_surfaces, /* Before tes push/pull constants and binding table */
 576       &brw_gs_image_surfaces, /* Before gs push/pull constants and binding table */
 577       &brw_wm_image_surfaces, /* Before wm push/pull constants and binding table */
 578
 579       &gen6_vs_push_constants, /* Before vs_state */
 580       &gen7_tcs_push_constants,
 581       &gen7_tes_push_constants,
 582       &gen6_gs_push_constants, /* Before gs_state */
 583       &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 584
 585       /* Surface state setup.  Must come before the VS/WM unit.  The binding
 586        * table upload must be last.
 587        */
 588       &brw_vs_pull_constants,
 589       &brw_vs_ubo_surfaces,
 590       &brw_vs_abo_surfaces,
 591       &brw_tcs_pull_constants,
 592       &brw_tcs_ubo_surfaces,
 593       &brw_tcs_abo_surfaces,
 594       &brw_tes_pull_constants,
 595       &brw_tes_ubo_surfaces,
 596       &brw_tes_abo_surfaces,
 597       &brw_gs_pull_constants,
 598       &brw_gs_ubo_surfaces,
 599       &brw_gs_abo_surfaces,
 600       &brw_wm_pull_constants,
 601       &brw_wm_ubo_surfaces,
 602       &brw_wm_abo_surfaces,
 603       &gen6_renderbuffer_surfaces,
 604       &brw_renderbuffer_read_surfaces,
 605       &brw_texture_surfaces,
 606       &brw_vs_binding_table,
 607       &brw_tcs_binding_table,
 608       &brw_tes_binding_table,
 609       &brw_gs_binding_table,
 610       &brw_wm_binding_table,
 611
 612       &brw_fs_samplers,
 613       &brw_vs_samplers,
 614       &brw_tcs_samplers,
 615       &brw_tes_samplers,
 616       &brw_gs_samplers,
 617       &gen8_multisample_state,
 618
 619       &gen8_vs_state,
 620       &gen8_hs_state,
 621       &gen7_te_state,
 622       &gen8_ds_state,
 623       &gen8_gs_state,
 624       &gen7_sol_state,
 625       &genX(clip_state),
 626       &gen8_raster_state,
 627       &gen8_sbe_state,
 628       &gen8_sf_state,
 629       &gen8_ps_blend,
 630       &gen8_ps_extra,
 631       &gen8_ps_state,
 632       &genX(depth_stencil_state),
 633       &gen8_wm_state,
 634
 635       &gen6_scissor_state,
 636
 637       &gen7_depthbuffer,
 638
 639       &brw_polygon_stipple,
 640       &brw_polygon_stipple_offset,
 641
 642       &brw_line_stipple,
 643
 644       &brw_drawing_rect,
 645
 646       &gen8_vf_topology,
 647
 648       &brw_indices,
 649       &gen8_index_buffer,
 650       &gen8_vertices,
 651
 652       &haswell_cut_index,
 653       &gen8_pma_fix,
 654    };
 655 #endif
 656
 657    STATIC_ASSERT(ARRAY_SIZE(render_atoms) <= ARRAY_SIZE(brw->render_atoms));
 658    brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
 659                            render_atoms, ARRAY_SIZE(render_atoms));
 660
 661 #if GEN_GEN >= 7
 662    static const struct brw_tracked_state *compute_atoms[] =
 663    {
 664       &gen7_l3_state,
 665       &brw_cs_image_surfaces,
 666       &gen7_cs_push_constants,
 667       &brw_cs_pull_constants,
 668       &brw_cs_ubo_surfaces,
 669       &brw_cs_abo_surfaces,
 670       &brw_cs_texture_surfaces,
 671       &brw_cs_work_groups_surface,
 672       &brw_cs_samplers,
 673       &brw_cs_state,
 674    };
 675
 676    STATIC_ASSERT(ARRAY_SIZE(compute_atoms) <= ARRAY_SIZE(brw->compute_atoms));
 677    brw_copy_pipeline_atoms(brw, BRW_COMPUTE_PIPELINE,
 678                            compute_atoms, ARRAY_SIZE(compute_atoms));
 679 #endif
 680 }