2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "dev/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 UNUSED
static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 static struct brw_address
124 rw_32_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_32BIT
,
133 static struct brw_address
134 ro_32_bo(struct brw_bo
*bo
, uint32_t offset
)
136 return (struct brw_address
) {
139 .reloc_flags
= RELOC_32BIT
,
143 UNUSED
static struct brw_address
144 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
146 return (struct brw_address
) {
149 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
154 static struct brw_address
155 KSP(struct brw_context
*brw
, uint32_t offset
)
157 return ro_bo(brw
->cache
.bo
, offset
);
161 KSP(UNUSED
struct brw_context
*brw
, uint32_t offset
)
167 #include "genxml/genX_pack.h"
169 #define _brw_cmd_length(cmd) cmd ## _length
170 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
171 #define _brw_cmd_header(cmd) cmd ## _header
172 #define _brw_cmd_pack(cmd) cmd ## _pack
174 #define brw_batch_emit(brw, cmd, name) \
175 for (struct cmd name = { _brw_cmd_header(cmd) }, \
176 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
177 __builtin_expect(_dst != NULL, 1); \
178 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
182 uint32_t *_dw = emit_dwords(brw, n); \
183 struct cmd template = { \
184 _brw_cmd_header(cmd), \
185 .DWordLength = n - _brw_cmd_length_bias(cmd), \
188 _brw_cmd_pack(cmd)(brw, _dw, &template); \
189 _dw + 1; /* Array starts at dw[1] */ \
192 #define brw_state_emit(brw, cmd, align, offset, name) \
193 for (struct cmd name = {}, \
194 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
196 __builtin_expect(_dst != NULL, 1); \
197 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
201 * Polygon stipple packet
204 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
206 struct gl_context
*ctx
= &brw
->ctx
;
209 if (!ctx
->Polygon
.StippleFlag
)
212 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
213 /* Polygon stipple is provided in OpenGL order, i.e. bottom
214 * row first. If we're rendering to a window (i.e. the
215 * default frame buffer object, 0), then we need to invert
216 * it to match our pixel layout. But if we're rendering
217 * to a FBO (i.e. any named frame buffer object), we *don't*
218 * need to invert - we already match the layout.
220 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
221 for (unsigned i
= 0; i
< 32; i
++)
222 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
224 for (unsigned i
= 0; i
< 32; i
++)
225 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
230 static const struct brw_tracked_state
genX(polygon_stipple
) = {
232 .mesa
= _NEW_POLYGON
|
234 .brw
= BRW_NEW_CONTEXT
,
236 .emit
= genX(upload_polygon_stipple
),
240 * Polygon stipple offset packet
243 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
245 struct gl_context
*ctx
= &brw
->ctx
;
248 if (!ctx
->Polygon
.StippleFlag
)
251 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
254 * If we're drawing to a system window we have to invert the Y axis
255 * in order to match the OpenGL pixel coordinate system, and our
256 * offset must be matched to the window position. If we're drawing
257 * to a user-created FBO then our native pixel coordinate system
258 * works just fine, and there's no window system to worry about.
260 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
261 poly
.PolygonStippleYOffset
=
262 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
267 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
269 .mesa
= _NEW_BUFFERS
|
271 .brw
= BRW_NEW_CONTEXT
,
273 .emit
= genX(upload_polygon_stipple_offset
),
277 * Line stipple packet
280 genX(upload_line_stipple
)(struct brw_context
*brw
)
282 struct gl_context
*ctx
= &brw
->ctx
;
284 if (!ctx
->Line
.StippleFlag
)
287 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
288 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
290 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
291 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
295 static const struct brw_tracked_state
genX(line_stipple
) = {
298 .brw
= BRW_NEW_CONTEXT
,
300 .emit
= genX(upload_line_stipple
),
303 /* Constant single cliprect for framebuffer object or DRI2 drawing */
305 genX(upload_drawing_rect
)(struct brw_context
*brw
)
307 struct gl_context
*ctx
= &brw
->ctx
;
308 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
309 const unsigned int fb_width
= _mesa_geometric_width(fb
);
310 const unsigned int fb_height
= _mesa_geometric_height(fb
);
312 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
313 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
314 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
318 static const struct brw_tracked_state
genX(drawing_rect
) = {
320 .mesa
= _NEW_BUFFERS
,
321 .brw
= BRW_NEW_BLORP
|
324 .emit
= genX(upload_drawing_rect
),
328 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
332 unsigned start_offset
,
333 MAYBE_UNUSED
unsigned end_offset
,
335 MAYBE_UNUSED
unsigned step_rate
)
337 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
338 .VertexBufferIndex
= buffer_nr
,
339 .BufferPitch
= stride
,
341 /* The VF cache designers apparently cut corners, and made the cache
342 * only consider the bottom 32 bits of memory addresses. If you happen
343 * to have two vertex buffers which get placed exactly 4 GiB apart and
344 * use them in back-to-back draw calls, you can get collisions. To work
345 * around this problem, we restrict vertex buffers to the low 32 bits of
348 .BufferStartingAddress
= ro_32_bo(bo
, start_offset
),
350 .BufferSize
= end_offset
- start_offset
,
354 .AddressModifyEnable
= true,
358 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
359 .InstanceDataStepRate
= step_rate
,
361 .EndAddress
= ro_bo(bo
, end_offset
- 1),
366 .VertexBufferMOCS
= ICL_MOCS_WB
,
368 .VertexBufferMOCS
= CNL_MOCS_WB
,
370 .VertexBufferMOCS
= SKL_MOCS_WB
,
372 .VertexBufferMOCS
= BDW_MOCS_WB
,
374 .VertexBufferMOCS
= GEN7_MOCS_L3
,
378 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
379 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
383 is_passthru_format(uint32_t format
)
386 case ISL_FORMAT_R64_PASSTHRU
:
387 case ISL_FORMAT_R64G64_PASSTHRU
:
388 case ISL_FORMAT_R64G64B64_PASSTHRU
:
389 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
397 uploads_needed(uint32_t format
,
400 if (!is_passthru_format(format
))
407 case ISL_FORMAT_R64_PASSTHRU
:
408 case ISL_FORMAT_R64G64_PASSTHRU
:
410 case ISL_FORMAT_R64G64B64_PASSTHRU
:
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
414 unreachable("not reached");
419 * Returns the format that we are finally going to use when upload a vertex
420 * element. It will only change if we are using *64*PASSTHRU formats, as for
421 * gen < 8 they need to be splitted on two *32*FLOAT formats.
423 * @upload points in which upload we are. Valid values are [0,1]
426 downsize_format_if_needed(uint32_t format
,
429 assert(upload
== 0 || upload
== 1);
431 if (!is_passthru_format(format
))
434 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
435 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
436 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
437 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
438 * flagging that we want to fill with zeroes this second forced upload.
441 case ISL_FORMAT_R64_PASSTHRU
:
442 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
443 : ISL_FORMAT_R32_FLOAT
;
444 case ISL_FORMAT_R64G64_PASSTHRU
:
445 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
446 : ISL_FORMAT_R32_FLOAT
;
447 case ISL_FORMAT_R64G64B64_PASSTHRU
:
448 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
449 : ISL_FORMAT_R32G32_FLOAT
;
450 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
451 return ISL_FORMAT_R32G32B32A32_FLOAT
;
453 unreachable("not reached");
458 * Returns the number of componentes associated with a format that is used on
459 * a 64 to 32 format split. See downsize_format()
462 upload_format_size(uint32_t upload_format
)
464 switch (upload_format
) {
465 case ISL_FORMAT_R32_FLOAT
:
467 /* downsized_format has returned this one in order to flag that we are
468 * performing a second upload which we want to have filled with
469 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
470 * vertex shader input variables.
474 case ISL_FORMAT_R32G32_FLOAT
:
476 case ISL_FORMAT_R32G32B32A32_FLOAT
:
479 unreachable("not reached");
483 static UNUSED
uint16_t
484 pinned_bo_high_bits(struct brw_bo
*bo
)
486 return (bo
->kflags
& EXEC_OBJECT_PINNED
) ? bo
->gtt_offset
>> 32ull : 0;
489 /* The VF cache designers apparently cut corners, and made the cache key's
490 * <VertexBufferIndex, Memory Address> tuple only consider the bottom 32 bits
491 * of the address. If you happen to have two vertex buffers which get placed
492 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
493 * collisions. (These collisions can happen within a single batch.)
495 * In the soft-pin world, we'd like to assign addresses up front, and never
496 * move buffers. So, we need to do a VF cache invalidate if the buffer for
497 * a particular VB slot has different [48:32] address bits than the last one.
499 * In the relocation world, we have no idea what the addresses will be, so
500 * we can't apply this workaround. Instead, we tell the kernel to move it
501 * to the low 4GB regardless.
504 vf_invalidate_for_vb_48bit_transitions(struct brw_context
*brw
)
507 bool need_invalidate
= false;
510 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
511 uint16_t high_bits
= pinned_bo_high_bits(brw
->vb
.buffers
[i
].bo
);
513 if (high_bits
!= brw
->vb
.last_bo_high_bits
[i
]) {
514 need_invalidate
= true;
515 brw
->vb
.last_bo_high_bits
[i
] = high_bits
;
519 /* Don't bother with draw parameter buffers - those are generated by
520 * the driver so we can select a consistent memory zone.
523 if (need_invalidate
) {
524 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
530 vf_invalidate_for_ib_48bit_transition(struct brw_context
*brw
)
533 uint16_t high_bits
= pinned_bo_high_bits(brw
->ib
.bo
);
535 if (high_bits
!= brw
->ib
.last_bo_high_bits
) {
536 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
537 brw
->ib
.last_bo_high_bits
= high_bits
;
543 genX(emit_vertices
)(struct brw_context
*brw
)
545 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
548 brw_prepare_vertices(brw
);
549 brw_prepare_shader_draw_parameters(brw
);
552 brw_emit_query_begin(brw
);
555 const struct brw_vs_prog_data
*vs_prog_data
=
556 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
559 struct gl_context
*ctx
= &brw
->ctx
;
560 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
561 ctx
->Polygon
.BackMode
!= GL_FILL
);
563 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
564 unsigned vue
= brw
->vb
.nr_enabled
;
566 /* The element for the edge flags must always be last, so we have to
567 * insert the SGVS before it in that case.
569 if (uses_edge_flag
) {
575 "Trying to insert VID/IID past 33rd vertex element, "
576 "need to reorder the vertex attrbutes.");
578 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
579 if (vs_prog_data
->uses_vertexid
) {
580 vfs
.VertexIDEnable
= true;
581 vfs
.VertexIDComponentNumber
= 2;
582 vfs
.VertexIDElementOffset
= vue
;
585 if (vs_prog_data
->uses_instanceid
) {
586 vfs
.InstanceIDEnable
= true;
587 vfs
.InstanceIDComponentNumber
= 3;
588 vfs
.InstanceIDElementOffset
= vue
;
592 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
593 vfi
.InstancingEnable
= true;
594 vfi
.VertexElementIndex
= vue
;
597 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
601 const bool uses_draw_params
=
602 vs_prog_data
->uses_firstvertex
||
603 vs_prog_data
->uses_baseinstance
;
605 const bool uses_derived_draw_params
=
606 vs_prog_data
->uses_drawid
||
607 vs_prog_data
->uses_is_indexed_draw
;
609 const bool needs_sgvs_element
= (uses_draw_params
||
610 vs_prog_data
->uses_instanceid
||
611 vs_prog_data
->uses_vertexid
);
613 unsigned nr_elements
=
614 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ uses_derived_draw_params
;
617 /* If any of the formats of vb.enabled needs more that one upload, we need
618 * to add it to nr_elements
620 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
621 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
622 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
623 uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
625 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
630 /* If the VS doesn't read any inputs (calculating vertex position from
631 * a state variable for some reason, for example), emit a single pad
632 * VERTEX_ELEMENT struct and bail.
634 * The stale VB state stays in place, but they don't do anything unless
635 * a VE loads from them.
637 if (nr_elements
== 0) {
638 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
639 1 + GENX(VERTEX_ELEMENT_STATE_length
));
640 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
642 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
643 .Component0Control
= VFCOMP_STORE_0
,
644 .Component1Control
= VFCOMP_STORE_0
,
645 .Component2Control
= VFCOMP_STORE_0
,
646 .Component3Control
= VFCOMP_STORE_1_FP
,
648 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
652 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
653 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
654 uses_draw_params
+ uses_derived_draw_params
;
656 vf_invalidate_for_vb_48bit_transitions(brw
);
659 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
661 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
662 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
664 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
665 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
666 /* Prior to Haswell and Bay Trail we have to use 4-component formats
667 * to fake 3-component ones. In particular, we do this for
668 * half-float and 8 and 16-bit integer formats. This means that the
669 * vertex element may poke over the end of the buffer by 2 bytes.
671 const unsigned padding
=
672 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
673 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
674 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
681 if (uses_draw_params
) {
682 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
683 brw
->draw
.draw_params_bo
,
684 brw
->draw
.draw_params_offset
,
685 brw
->draw
.draw_params_bo
->size
,
690 if (uses_derived_draw_params
) {
691 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
692 brw
->draw
.derived_draw_params_bo
,
693 brw
->draw
.derived_draw_params_offset
,
694 brw
->draw
.derived_draw_params_bo
->size
,
700 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
701 * presumably for VertexID/InstanceID.
704 assert(nr_elements
<= 34);
705 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
707 assert(nr_elements
<= 18);
710 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
711 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
713 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
714 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
715 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
716 uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
717 uint32_t comp0
= VFCOMP_STORE_SRC
;
718 uint32_t comp1
= VFCOMP_STORE_SRC
;
719 uint32_t comp2
= VFCOMP_STORE_SRC
;
720 uint32_t comp3
= VFCOMP_STORE_SRC
;
721 const unsigned num_uploads
= GEN_GEN
< 8 ?
722 uploads_needed(format
, input
->is_dual_slot
) : 1;
725 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
726 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
727 * element which has edge flag enabled."
729 assert(!(is_passthru_format(format
) && uses_edge_flag
));
732 /* The gen4 driver expects edgeflag to come in as a float, and passes
733 * that float on to the tests in the clipper. Mesa's current vertex
734 * attribute value for EdgeFlag is stored as a float, which works out.
735 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
736 * integer ubyte. Just rewrite that to convert to a float.
738 * Gen6+ passes edgeflag as sideband along with the vertex, instead
739 * of in the VUE. We have to upload it sideband as the last vertex
740 * element according to the B-Spec.
743 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
744 gen6_edgeflag_input
= input
;
749 for (unsigned c
= 0; c
< num_uploads
; c
++) {
750 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
751 downsize_format_if_needed(format
, c
);
752 /* If we need more that one upload, the offset stride would be 128
753 * bits (16 bytes), as for previous uploads we are using the full
755 const unsigned offset
= input
->offset
+ c
* 16;
757 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
758 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
759 upload_format_size(upload_format
) : glattrib
->Size
;
762 case 0: comp0
= VFCOMP_STORE_0
;
763 case 1: comp1
= VFCOMP_STORE_0
;
764 case 2: comp2
= VFCOMP_STORE_0
;
766 if (GEN_GEN
>= 8 && glattrib
->Doubles
) {
767 comp3
= VFCOMP_STORE_0
;
768 } else if (glattrib
->Integer
) {
769 comp3
= VFCOMP_STORE_1_INT
;
771 comp3
= VFCOMP_STORE_1_FP
;
778 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
780 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
781 * formats, 64-bit components are stored in the URB without any
782 * conversion. In this case, vertex elements must be written as 128
783 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
784 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
785 * component into the URB, Component 1 must be specified as
786 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
787 * order to output a 128-bit vertex element, or Components 1-3 must
788 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
789 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
790 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
793 if (glattrib
->Doubles
&& !input
->is_dual_slot
) {
794 /* Store vertex elements which correspond to double and dvec2 vertex
795 * shader inputs as 128-bit vertex elements, instead of 256-bits.
797 comp2
= VFCOMP_NOSTORE
;
798 comp3
= VFCOMP_NOSTORE
;
802 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
803 .VertexBufferIndex
= input
->buffer
,
805 .SourceElementFormat
= upload_format
,
806 .SourceElementOffset
= offset
,
807 .Component0Control
= comp0
,
808 .Component1Control
= comp1
,
809 .Component2Control
= comp2
,
810 .Component3Control
= comp3
,
812 .DestinationElementOffset
= i
* 4,
816 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
817 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
821 if (needs_sgvs_element
) {
822 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
824 .Component0Control
= VFCOMP_STORE_0
,
825 .Component1Control
= VFCOMP_STORE_0
,
826 .Component2Control
= VFCOMP_STORE_0
,
827 .Component3Control
= VFCOMP_STORE_0
,
829 .DestinationElementOffset
= i
* 4,
834 if (uses_draw_params
) {
835 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
836 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
837 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
838 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
841 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
842 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
843 if (uses_draw_params
) {
844 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
845 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
848 if (vs_prog_data
->uses_vertexid
)
849 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
851 if (vs_prog_data
->uses_instanceid
)
852 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
855 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
856 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
859 if (uses_derived_draw_params
) {
860 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
862 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
863 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
864 .Component0Control
= VFCOMP_STORE_SRC
,
865 .Component1Control
= VFCOMP_STORE_SRC
,
866 .Component2Control
= VFCOMP_STORE_0
,
867 .Component3Control
= VFCOMP_STORE_0
,
869 .DestinationElementOffset
= i
* 4,
873 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
874 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
878 if (gen6_edgeflag_input
) {
879 const struct gl_array_attributes
*glattrib
= gen6_edgeflag_input
->glattrib
;
880 const uint32_t format
= brw_get_vertex_surface_type(brw
, glattrib
);
882 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
884 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
885 .EdgeFlagEnable
= true,
886 .SourceElementFormat
= format
,
887 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
888 .Component0Control
= VFCOMP_STORE_SRC
,
889 .Component1Control
= VFCOMP_STORE_0
,
890 .Component2Control
= VFCOMP_STORE_0
,
891 .Component3Control
= VFCOMP_STORE_0
,
894 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
895 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
900 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
901 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
902 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
903 unsigned element_index
;
905 /* The edge flag element is reordered to be the last one in the code
906 * above so we need to compensate for that in the element indices used
909 if (input
== gen6_edgeflag_input
)
910 element_index
= nr_elements
- 1;
914 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
915 vfi
.VertexElementIndex
= element_index
;
916 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
917 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
921 if (vs_prog_data
->uses_drawid
) {
922 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
924 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
925 vfi
.VertexElementIndex
= element
;
931 static const struct brw_tracked_state
genX(vertices
) = {
933 .mesa
= _NEW_POLYGON
,
934 .brw
= BRW_NEW_BATCH
|
937 BRW_NEW_VS_PROG_DATA
,
939 .emit
= genX(emit_vertices
),
943 genX(emit_index_buffer
)(struct brw_context
*brw
)
945 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
947 if (index_buffer
== NULL
)
950 vf_invalidate_for_ib_48bit_transition(brw
);
952 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
953 #if GEN_GEN < 8 && !GEN_IS_HASWELL
954 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
956 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
958 /* The VF cache designers apparently cut corners, and made the cache
959 * only consider the bottom 32 bits of memory addresses. If you happen
960 * to have two index buffers which get placed exactly 4 GiB apart and
961 * use them in back-to-back draw calls, you can get collisions. To work
962 * around this problem, we restrict index buffers to the low 32 bits of
965 ib
.BufferStartingAddress
= ro_32_bo(brw
->ib
.bo
, 0);
967 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
968 ib
.BufferSize
= brw
->ib
.size
;
970 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
975 static const struct brw_tracked_state
genX(index_buffer
) = {
978 .brw
= BRW_NEW_BATCH
|
980 BRW_NEW_INDEX_BUFFER
,
982 .emit
= genX(emit_index_buffer
),
985 #if GEN_IS_HASWELL || GEN_GEN >= 8
987 genX(upload_cut_index
)(struct brw_context
*brw
)
989 const struct gl_context
*ctx
= &brw
->ctx
;
991 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
992 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
993 vf
.IndexedDrawCutIndexEnable
= true;
994 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
999 const struct brw_tracked_state
genX(cut_index
) = {
1001 .mesa
= _NEW_TRANSFORM
,
1002 .brw
= BRW_NEW_INDEX_BUFFER
,
1004 .emit
= genX(upload_cut_index
),
1010 * Determine the appropriate attribute override value to store into the
1011 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
1012 * override value contains two pieces of information: the location of the
1013 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
1014 * flag indicating whether to "swizzle" the attribute based on the direction
1015 * the triangle is facing.
1017 * If an attribute is "swizzled", then the given VUE location is used for
1018 * front-facing triangles, and the VUE location that immediately follows is
1019 * used for back-facing triangles. We use this to implement the mapping from
1020 * gl_FrontColor/gl_BackColor to gl_Color.
1022 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
1023 * being instructed to begin reading attribute data. It can be set to a
1024 * nonzero value to prevent the SF unit from wasting time reading elements of
1025 * the VUE that are not needed by the fragment shader. It is measured in
1026 * 256-bit increments.
1029 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
1030 const struct brw_vue_map
*vue_map
,
1031 int urb_entry_read_offset
, int fs_attr
,
1032 bool two_side_color
, uint32_t *max_source_attr
)
1034 /* Find the VUE slot for this attribute. */
1035 int slot
= vue_map
->varying_to_slot
[fs_attr
];
1037 /* Viewport and Layer are stored in the VUE header. We need to override
1038 * them to zero if earlier stages didn't write them, as GL requires that
1039 * they read back as zero when not explicitly set.
1041 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
1042 attr
->ComponentOverrideX
= true;
1043 attr
->ComponentOverrideW
= true;
1044 attr
->ConstantSource
= CONST_0000
;
1046 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
1047 attr
->ComponentOverrideY
= true;
1048 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
1049 attr
->ComponentOverrideZ
= true;
1054 /* If there was only a back color written but not front, use back
1055 * as the color instead of undefined
1057 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
1058 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
1059 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
1060 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
1063 /* This attribute does not exist in the VUE--that means that the vertex
1064 * shader did not write to it. This means that either:
1066 * (a) This attribute is a texture coordinate, and it is going to be
1067 * replaced with point coordinates (as a consequence of a call to
1068 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
1069 * hardware will ignore whatever attribute override we supply.
1071 * (b) This attribute is read by the fragment shader but not written by
1072 * the vertex shader, so its value is undefined. Therefore the
1073 * attribute override we supply doesn't matter.
1075 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
1076 * previous shader stage.
1078 * Note that we don't have to worry about the cases where the attribute
1079 * is gl_PointCoord or is undergoing point sprite coordinate
1080 * replacement, because in those cases, this function isn't called.
1082 * In case (c), we need to program the attribute overrides so that the
1083 * primitive ID will be stored in this slot. In every other case, the
1084 * attribute override we supply doesn't matter. So just go ahead and
1085 * program primitive ID in every case.
1087 attr
->ComponentOverrideW
= true;
1088 attr
->ComponentOverrideX
= true;
1089 attr
->ComponentOverrideY
= true;
1090 attr
->ComponentOverrideZ
= true;
1091 attr
->ConstantSource
= PRIM_ID
;
1095 /* Compute the location of the attribute relative to urb_entry_read_offset.
1096 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1097 * it counts for two 128-bit VUE slots.
1099 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1100 assert(source_attr
>= 0 && source_attr
< 32);
1102 /* If we are doing two-sided color, and the VUE slot following this one
1103 * represents a back-facing color, then we need to instruct the SF unit to
1104 * do back-facing swizzling.
1106 bool swizzling
= two_side_color
&&
1107 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1108 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1109 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1110 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1112 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1113 if (*max_source_attr
< source_attr
+ swizzling
)
1114 *max_source_attr
= source_attr
+ swizzling
;
1116 attr
->SourceAttribute
= source_attr
;
1118 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1123 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1124 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1125 uint32_t *point_sprite_enables
,
1126 uint32_t *urb_entry_read_length
,
1127 uint32_t *urb_entry_read_offset
)
1129 const struct gl_context
*ctx
= &brw
->ctx
;
1132 const struct gl_point_attrib
*point
= &ctx
->Point
;
1134 /* BRW_NEW_FRAGMENT_PROGRAM */
1135 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1137 /* BRW_NEW_FS_PROG_DATA */
1138 const struct brw_wm_prog_data
*wm_prog_data
=
1139 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1140 uint32_t max_source_attr
= 0;
1142 *point_sprite_enables
= 0;
1145 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1146 &brw
->vue_map_geom_out
);
1148 /* Each URB offset packs two varying slots */
1149 assert(first_slot
% 2 == 0);
1150 *urb_entry_read_offset
= first_slot
/ 2;
1152 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1153 * description of dw10 Point Sprite Texture Coordinate Enable:
1155 * "This field must be programmed to zero when non-point primitives
1158 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1159 * must be programmed to zero when rendering non-point primitives, but
1160 * the IvyBridge PRM does, and if we don't, we get garbage.
1162 * This is not required on Haswell, as the hardware ignores this state
1163 * when drawing non-points -- although we do still need to be careful to
1164 * correctly set the attr overrides.
1167 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1169 bool drawing_points
= brw_is_drawing_points(brw
);
1171 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1172 int input_index
= wm_prog_data
->urb_setup
[attr
];
1174 if (input_index
< 0)
1178 bool point_sprite
= false;
1179 if (drawing_points
) {
1180 if (point
->PointSprite
&&
1181 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1182 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1183 point_sprite
= true;
1186 if (attr
== VARYING_SLOT_PNTC
)
1187 point_sprite
= true;
1190 *point_sprite_enables
|= (1 << input_index
);
1193 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1194 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1196 if (!point_sprite
) {
1197 genX(get_attr_override
)(&attribute
,
1198 &brw
->vue_map_geom_out
,
1199 *urb_entry_read_offset
, attr
,
1200 _mesa_vertex_program_two_side_enabled(ctx
),
1204 /* The hardware can only do the overrides on 16 overrides at a
1205 * time, and the other up to 16 have to be lined up so that the
1206 * input index = the output index. We'll need to do some
1207 * tweaking to make sure that's the case.
1209 if (input_index
< 16)
1210 attr_overrides
[input_index
] = attribute
;
1212 assert(attribute
.SourceAttribute
== input_index
);
1215 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1216 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1218 * "This field should be set to the minimum length required to read the
1219 * maximum source attribute. The maximum source attribute is indicated
1220 * by the maximum value of the enabled Attribute # Source Attribute if
1221 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1222 * enable is not set.
1223 * read_length = ceiling((max_source_attr + 1) / 2)
1225 * [errata] Corruption/Hang possible if length programmed larger than
1228 * Similar text exists for Ivy Bridge.
1230 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1234 /* ---------------------------------------------------------------------- */
1237 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1239 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1241 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1245 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1247 struct gl_context
*ctx
= &brw
->ctx
;
1250 struct intel_renderbuffer
*depth_irb
=
1251 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1254 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1257 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1258 const int b
= stencil
->_BackFace
;
1260 if (depth
->Test
&& depth_irb
) {
1261 ds
->DepthTestEnable
= true;
1262 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1263 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1266 if (brw
->stencil_enabled
) {
1267 ds
->StencilTestEnable
= true;
1268 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1269 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1271 ds
->StencilTestFunction
=
1272 intel_translate_compare_func(stencil
->Function
[0]);
1274 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1275 ds
->StencilPassDepthPassOp
=
1276 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1277 ds
->StencilPassDepthFailOp
=
1278 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1280 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1282 if (brw
->stencil_two_sided
) {
1283 ds
->DoubleSidedStencilEnable
= true;
1284 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1285 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1287 ds
->BackfaceStencilTestFunction
=
1288 intel_translate_compare_func(stencil
->Function
[b
]);
1289 ds
->BackfaceStencilFailOp
=
1290 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1291 ds
->BackfaceStencilPassDepthPassOp
=
1292 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1293 ds
->BackfaceStencilPassDepthFailOp
=
1294 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1297 #if GEN_GEN <= 5 || GEN_GEN >= 9
1298 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1299 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1306 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1309 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1310 set_depth_stencil_bits(brw
, &wmds
);
1314 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1315 set_depth_stencil_bits(brw
, &ds
);
1318 /* Now upload a pointer to the indirect state */
1320 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1321 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1322 ptr
.DEPTH_STENCIL_STATEChange
= true;
1325 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1326 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1332 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1334 .mesa
= _NEW_BUFFERS
|
1337 .brw
= BRW_NEW_BLORP
|
1338 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1340 BRW_NEW_STATE_BASE_ADDRESS
),
1342 .emit
= genX(upload_depth_stencil_state
),
1346 /* ---------------------------------------------------------------------- */
1351 genX(upload_clip_state
)(struct brw_context
*brw
)
1353 struct gl_context
*ctx
= &brw
->ctx
;
1355 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1356 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1357 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1358 clip
.GRFRegisterCount
=
1359 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1360 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1361 clip
.SingleProgramFlow
= true;
1362 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1363 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1365 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1366 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1367 clip
.DispatchGRFStartRegisterForURBData
= 1;
1368 clip
.VertexURBEntryReadOffset
= 0;
1370 /* BRW_NEW_URB_FENCE */
1371 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1372 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1374 if (brw
->urb
.nr_clip_entries
>= 10) {
1375 /* Half of the URB entries go to each thread, and it has to be an
1378 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1380 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1381 * only 2 threads can output VUEs at a time.
1383 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1385 assert(brw
->urb
.nr_clip_entries
>= 5);
1386 clip
.MaximumNumberofThreads
= 1 - 1;
1389 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1390 clip
.UserClipFlagsMustClipEnable
= true;
1391 clip
.GuardbandClipTestEnable
= true;
1393 clip
.ClipperViewportStatePointer
=
1394 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1396 clip
.ScreenSpaceViewportXMin
= -1;
1397 clip
.ScreenSpaceViewportXMax
= 1;
1398 clip
.ScreenSpaceViewportYMin
= -1;
1399 clip
.ScreenSpaceViewportYMax
= 1;
1401 clip
.ViewportXYClipTestEnable
= true;
1402 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1404 /* _NEW_TRANSFORM */
1405 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1406 clip
.UserClipDistanceClipTestEnableBitmask
=
1407 ctx
->Transform
.ClipPlanesEnabled
;
1409 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1412 clip
.UserClipDistanceClipTestEnableBitmask
=
1413 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1416 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1417 clip
.APIMode
= APIMODE_D3D
;
1419 clip
.APIMode
= APIMODE_OGL
;
1421 clip
.GuardbandClipTestEnable
= true;
1423 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1426 clip
.NegativeWClipTestEnable
= true;
1431 const struct brw_tracked_state
genX(clip_state
) = {
1433 .mesa
= _NEW_TRANSFORM
|
1435 .brw
= BRW_NEW_BATCH
|
1437 BRW_NEW_CLIP_PROG_DATA
|
1438 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1439 BRW_NEW_PROGRAM_CACHE
|
1442 .emit
= genX(upload_clip_state
),
1448 genX(upload_clip_state
)(struct brw_context
*brw
)
1450 struct gl_context
*ctx
= &brw
->ctx
;
1453 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1455 /* BRW_NEW_FS_PROG_DATA */
1456 struct brw_wm_prog_data
*wm_prog_data
=
1457 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1459 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1460 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1462 if (wm_prog_data
->barycentric_interp_modes
&
1463 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1464 clip
.NonPerspectiveBarycentricEnable
= true;
1467 clip
.EarlyCullEnable
= true;
1471 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1473 if (ctx
->Polygon
.CullFlag
) {
1474 switch (ctx
->Polygon
.CullFaceMode
) {
1476 clip
.CullMode
= CULLMODE_FRONT
;
1479 clip
.CullMode
= CULLMODE_BACK
;
1481 case GL_FRONT_AND_BACK
:
1482 clip
.CullMode
= CULLMODE_BOTH
;
1485 unreachable("Should not get here: invalid CullFlag");
1488 clip
.CullMode
= CULLMODE_NONE
;
1493 clip
.UserClipDistanceCullTestEnableBitmask
=
1494 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1496 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1500 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1501 clip
.TriangleStripListProvokingVertexSelect
= 0;
1502 clip
.TriangleFanProvokingVertexSelect
= 1;
1503 clip
.LineStripListProvokingVertexSelect
= 0;
1505 clip
.TriangleStripListProvokingVertexSelect
= 2;
1506 clip
.TriangleFanProvokingVertexSelect
= 2;
1507 clip
.LineStripListProvokingVertexSelect
= 1;
1510 /* _NEW_TRANSFORM */
1511 clip
.UserClipDistanceClipTestEnableBitmask
=
1512 ctx
->Transform
.ClipPlanesEnabled
;
1515 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1518 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1519 clip
.APIMode
= APIMODE_D3D
;
1521 clip
.APIMode
= APIMODE_OGL
;
1523 clip
.GuardbandClipTestEnable
= true;
1525 /* BRW_NEW_VIEWPORT_COUNT */
1526 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1528 if (ctx
->RasterDiscard
) {
1529 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1531 perf_debug("Rasterizer discard is currently implemented via the "
1532 "clipper; having the GS not write primitives would "
1533 "likely be faster.\n");
1536 clip
.ClipMode
= CLIPMODE_NORMAL
;
1539 clip
.ClipEnable
= true;
1542 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1544 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1545 clip
.ViewportXYClipTestEnable
= true;
1547 clip
.MinimumPointWidth
= 0.125;
1548 clip
.MaximumPointWidth
= 255.875;
1549 clip
.MaximumVPIndex
= viewport_count
- 1;
1550 if (_mesa_geometric_layers(fb
) == 0)
1551 clip
.ForceZeroRTAIndexEnable
= true;
1555 static const struct brw_tracked_state
genX(clip_state
) = {
1557 .mesa
= _NEW_BUFFERS
|
1561 .brw
= BRW_NEW_BLORP
|
1563 BRW_NEW_FS_PROG_DATA
|
1564 BRW_NEW_GS_PROG_DATA
|
1565 BRW_NEW_VS_PROG_DATA
|
1566 BRW_NEW_META_IN_PROGRESS
|
1568 BRW_NEW_RASTERIZER_DISCARD
|
1569 BRW_NEW_TES_PROG_DATA
|
1570 BRW_NEW_VIEWPORT_COUNT
,
1572 .emit
= genX(upload_clip_state
),
1576 /* ---------------------------------------------------------------------- */
1579 genX(upload_sf
)(struct brw_context
*brw
)
1581 struct gl_context
*ctx
= &brw
->ctx
;
1586 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1587 UNUSED
const bool multisampled_fbo
=
1588 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1592 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1594 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1596 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1597 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1598 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1599 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1600 sf
.DispatchGRFStartRegisterForURBData
= 3;
1601 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1602 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1603 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1604 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1606 /* STATE_PREFETCH command description describes this state as being
1607 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1610 sf
.SetupViewportStateOffset
=
1611 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1613 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1615 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1616 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1618 sf
.MaximumNumberofThreads
=
1619 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1621 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1623 sf
.DestinationOriginHorizontalBias
= 0.5;
1624 sf
.DestinationOriginVerticalBias
= 0.5;
1626 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1627 sf
.StatisticsEnable
= true;
1629 sf
.ViewportTransformEnable
= true;
1633 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1638 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1640 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1641 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1642 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1644 switch (ctx
->Polygon
.FrontMode
) {
1646 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1649 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1652 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1655 unreachable("not reached");
1658 switch (ctx
->Polygon
.BackMode
) {
1660 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1663 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1666 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1669 unreachable("not reached");
1672 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1673 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1675 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1676 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1677 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1680 sf
.ScissorRectangleEnable
= true;
1682 if (ctx
->Polygon
.CullFlag
) {
1683 switch (ctx
->Polygon
.CullFaceMode
) {
1685 sf
.CullMode
= CULLMODE_FRONT
;
1688 sf
.CullMode
= CULLMODE_BACK
;
1690 case GL_FRONT_AND_BACK
:
1691 sf
.CullMode
= CULLMODE_BOTH
;
1694 unreachable("not reached");
1697 sf
.CullMode
= CULLMODE_NONE
;
1701 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1708 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1710 if (devinfo
->is_cherryview
)
1711 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1713 sf
.LineWidth
= brw_get_line_width(brw
);
1715 sf
.LineWidth
= brw_get_line_width(brw
);
1718 if (ctx
->Line
.SmoothFlag
) {
1719 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1721 sf
.AntiAliasingEnable
= true;
1725 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1726 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1727 /* Clamp to the hardware limits */
1728 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1730 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1731 if (use_state_point_size(brw
))
1732 sf
.PointWidthSource
= State
;
1735 /* _NEW_POINT | _NEW_MULTISAMPLE */
1736 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1737 !ctx
->Point
.PointSprite
)
1738 sf
.SmoothPointEnable
= true;
1743 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1745 const bool multisampled_fbo
=
1746 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1747 if (multisampled_fbo
)
1748 sf
.SmoothPointEnable
= false;
1751 #if GEN_IS_G4X || GEN_GEN >= 5
1752 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1756 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1757 sf
.TriangleStripListProvokingVertexSelect
= 2;
1758 sf
.TriangleFanProvokingVertexSelect
= 2;
1759 sf
.LineStripListProvokingVertexSelect
= 1;
1761 sf
.TriangleFanProvokingVertexSelect
= 1;
1765 /* BRW_NEW_FS_PROG_DATA */
1766 const struct brw_wm_prog_data
*wm_prog_data
=
1767 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1769 sf
.AttributeSwizzleEnable
= true;
1770 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1773 * Window coordinates in an FBO are inverted, which means point
1774 * sprite origin must be inverted, too.
1776 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1777 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1779 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1782 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1783 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1785 uint32_t urb_entry_read_length
;
1786 uint32_t urb_entry_read_offset
;
1787 uint32_t point_sprite_enables
;
1788 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1789 &urb_entry_read_length
,
1790 &urb_entry_read_offset
);
1791 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1792 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1793 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1794 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1799 static const struct brw_tracked_state
genX(sf_state
) = {
1801 .mesa
= _NEW_LIGHT
|
1805 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1806 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1807 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1808 .brw
= BRW_NEW_BLORP
|
1809 BRW_NEW_VUE_MAP_GEOM_OUT
|
1810 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1811 BRW_NEW_PROGRAM_CACHE
|
1812 BRW_NEW_SF_PROG_DATA
|
1816 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1817 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1818 BRW_NEW_GS_PROG_DATA
|
1820 BRW_NEW_TES_PROG_DATA
1822 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1823 BRW_NEW_FRAGMENT_PROGRAM
1826 .emit
= genX(upload_sf
),
1829 /* ---------------------------------------------------------------------- */
1832 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1834 struct gl_context
*ctx
= &brw
->ctx
;
1835 /* BRW_NEW_FRAGMENT_PROGRAM */
1836 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1840 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1841 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1842 uint64_t outputs_written
= fp
->info
.outputs_written
;
1845 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1846 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1847 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1856 genX(upload_wm
)(struct brw_context
*brw
)
1858 struct gl_context
*ctx
= &brw
->ctx
;
1860 /* BRW_NEW_FS_PROG_DATA */
1861 const struct brw_wm_prog_data
*wm_prog_data
=
1862 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1864 UNUSED
bool writes_depth
=
1865 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1866 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1867 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1870 /* We can't fold this into gen6_upload_wm_push_constants(), because
1871 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1872 * (3DSTATE_CONSTANT_PS [DevSNB]):
1874 * "[DevSNB]: This packet must be followed by WM_STATE."
1876 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1877 if (wm_prog_data
->base
.nr_params
!= 0) {
1878 wmcp
.Buffer0Valid
= true;
1879 /* Pointer to the WM constant buffer. Covered by the set of
1880 * state flags from gen6_upload_wm_push_constants.
1882 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1883 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1889 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1890 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1891 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1893 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1894 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1896 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1897 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1898 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1899 /* These two fields should be the same pre-gen6, which is why we
1900 * only have one hardware field to program for both dispatch
1903 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1904 wm_prog_data
->dispatch_grf_start_reg_2
);
1907 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1908 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1910 if (stage_state
->sampler_count
)
1911 wm
.SamplerStatePointer
=
1912 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1914 if (wm_prog_data
->prog_offset_2
)
1915 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1918 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1919 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1920 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1921 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1922 wm
.EarlyDepthTestEnable
= true;
1923 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1924 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1927 if (ctx
->Polygon
.OffsetFill
) {
1928 wm
.GlobalDepthOffsetEnable
= true;
1929 /* Something weird going on with legacy_global_depth_bias,
1930 * offset_constant, scaling and MRD. This value passes glean
1931 * but gives some odd results elsewere (eg. the
1932 * quad-offset-units test).
1934 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1936 /* This is the only value that passes glean:
1938 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1941 wm
.DepthCoefficientURBReadOffset
= 1;
1944 /* BRW_NEW_STATS_WM */
1945 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1948 if (wm_prog_data
->base
.use_alt_mode
)
1949 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1951 wm
.SamplerCount
= GEN_GEN
== 5 ?
1952 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1954 wm
.BindingTableEntryCount
=
1955 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1956 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1957 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1958 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1959 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1960 wm_prog_data
->base
.dispatch_grf_start_reg
;
1962 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1963 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1967 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1968 wm
.KernelStartPointer2
=
1969 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1974 wm
.DualSourceBlendEnable
=
1975 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1976 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1977 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1978 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1980 /* From the SNB PRM, volume 2 part 1, page 281:
1981 * "If the PS kernel does not need the Position XY Offsets
1982 * to compute a Position XY value, then this field should be
1983 * programmed to POSOFFSET_NONE."
1985 * "SW Recommendation: If the PS kernel needs the Position Offsets
1986 * to compute a Position XY value, this field should match Position
1987 * ZW Interpolation Mode to ensure a consistent position.xyzw
1989 * We only require XY sample offsets. So, this recommendation doesn't
1990 * look useful at the moment. We might need this in future.
1992 if (wm_prog_data
->uses_pos_offset
)
1993 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1995 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1997 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1998 wm_prog_data
->dispatch_grf_start_reg_2
;
2001 if (wm_prog_data
->base
.total_scratch
) {
2002 wm
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
2003 wm
.PerThreadScratchSpace
=
2004 ffs(stage_state
->per_thread_scratch
) - 11;
2007 wm
.PixelShaderComputedDepth
= writes_depth
;
2011 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
2014 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
2019 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2022 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
2024 if (multisampled_fbo
) {
2025 /* _NEW_MULTISAMPLE */
2026 if (ctx
->Multisample
.Enabled
)
2027 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
2029 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
2031 if (wm_prog_data
->persample_dispatch
)
2032 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
2034 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
2036 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
2037 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
2040 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2041 if (wm_prog_data
->uses_kill
||
2042 _mesa_is_alpha_test_enabled(ctx
) ||
2043 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
2044 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
2045 wm
.PixelShaderKillsPixel
= true;
2048 /* _NEW_BUFFERS | _NEW_COLOR */
2049 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
2050 wm
.PixelShaderKillsPixel
||
2051 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
2052 wm
.ThreadDispatchEnable
= true;
2056 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2057 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
2060 /* The "UAV access enable" bits are unnecessary on HSW because they only
2061 * seem to have an effect on the HW-assisted coherency mechanism which we
2062 * don't need, and the rasterization-related UAV_ONLY flag and the
2063 * DISPATCH_ENABLE bit can be set independently from it.
2064 * C.f. gen8_upload_ps_extra().
2066 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
2070 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
2071 wm_prog_data
->has_side_effects
)
2077 /* BRW_NEW_FS_PROG_DATA */
2078 if (wm_prog_data
->early_fragment_tests
)
2079 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2080 else if (wm_prog_data
->has_side_effects
)
2081 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2086 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
2087 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
2088 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
2091 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
2096 static const struct brw_tracked_state
genX(wm_state
) = {
2100 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
2103 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2104 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2105 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2106 .brw
= BRW_NEW_BLORP
|
2107 BRW_NEW_FS_PROG_DATA
|
2108 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2109 BRW_NEW_FRAGMENT_PROGRAM
|
2110 BRW_NEW_PROGRAM_CACHE
|
2111 BRW_NEW_SAMPLER_STATE_TABLE
|
2114 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2116 .emit
= genX(upload_wm
),
2119 /* ---------------------------------------------------------------------- */
2121 /* We restrict scratch buffers to the bottom 32 bits of the address space
2122 * by using rw_32_bo().
2124 * General State Base Address is a bit broken. If the address + size as
2125 * seen by STATE_BASE_ADDRESS overflows 48 bits, the GPU appears to treat
2126 * all accesses to the buffer as being out of bounds and returns zero.
2129 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2130 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2131 pkt.SamplerCount = \
2132 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2133 pkt.BindingTableEntryCount = \
2134 stage_prog_data->binding_table.size_bytes / 4; \
2135 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2137 if (stage_prog_data->total_scratch) { \
2138 pkt.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0); \
2139 pkt.PerThreadScratchSpace = \
2140 ffs(stage_state->per_thread_scratch) - 11; \
2143 pkt.DispatchGRFStartRegisterForURBData = \
2144 stage_prog_data->dispatch_grf_start_reg; \
2145 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2146 pkt.prefix##URBEntryReadOffset = 0; \
2148 pkt.StatisticsEnable = true; \
2152 genX(upload_vs_state
)(struct brw_context
*brw
)
2154 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2155 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2156 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2158 /* BRW_NEW_VS_PROG_DATA */
2159 const struct brw_vue_prog_data
*vue_prog_data
=
2160 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2161 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2163 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2164 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2165 assert(GEN_GEN
< 11 ||
2166 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
2169 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2170 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2172 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2173 * command that causes the VS Function Enable to toggle. Pipeline
2174 * flush can be executed by sending a PIPE_CONTROL command with CS
2175 * stall bit set and a post sync operation.
2177 * We've already done such a flush at the start of state upload, so we
2178 * don't need to do another one here.
2180 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2181 if (stage_state
->push_const_size
!= 0) {
2182 cvs
.Buffer0Valid
= true;
2183 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2184 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2189 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2190 gen7_emit_vs_workaround_flush(brw
);
2193 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2195 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2196 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2198 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2200 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2203 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2204 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2205 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2207 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2208 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2210 vs
.MaximumNumberofThreads
=
2211 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2213 vs
.StatisticsEnable
= false;
2214 vs
.SamplerStatePointer
=
2215 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2219 /* Force single program flow on Ironlake. We cannot reliably get
2220 * all applications working without it. See:
2221 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2223 * The most notable and reliably failing application is the Humus
2226 vs
.SingleProgramFlow
= true;
2227 vs
.SamplerCount
= 0; /* hardware requirement */
2231 vs
.SIMD8DispatchEnable
=
2232 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2234 vs
.UserClipDistanceCullTestEnableBitmask
=
2235 vue_prog_data
->cull_distance_mask
;
2240 /* Based on my reading of the simulator, the VS constants don't get
2241 * pulled into the VS FF unit until an appropriate pipeline flush
2242 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2243 * references to them into a little FIFO. The flushes are common,
2244 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2245 * the primitive to use the wrong constants. Then the FIFO
2246 * containing the constant setup gets added to again on the next
2247 * constants change, and eventually when a flush does happen the
2248 * unit is overwhelmed by constant changes and dies.
2250 * To avoid this, send a PIPE_CONTROL down the line that will
2251 * update the unit immediately loading the constants. The flush
2252 * type bits here were those set by the STATE_BASE_ADDRESS whose
2253 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2254 * bug reports that led to this workaround, and may be more than
2255 * what is strictly required to avoid the issue.
2257 brw_emit_pipe_control_flush(brw
,
2258 PIPE_CONTROL_DEPTH_STALL
|
2259 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2260 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2264 static const struct brw_tracked_state
genX(vs_state
) = {
2266 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2267 .brw
= BRW_NEW_BATCH
|
2270 BRW_NEW_VS_PROG_DATA
|
2271 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2272 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2273 BRW_NEW_PROGRAM_CACHE
|
2274 BRW_NEW_SAMPLER_STATE_TABLE
|
2278 .emit
= genX(upload_vs_state
),
2281 /* ---------------------------------------------------------------------- */
2284 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2286 struct gl_context
*ctx
= &brw
->ctx
;
2288 /* BRW_NEW_VIEWPORT_COUNT */
2289 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2291 struct GENX(CC_VIEWPORT
) ccv
;
2292 uint32_t cc_vp_offset
;
2294 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2297 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2298 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2299 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2300 if (ctx
->Transform
.DepthClamp
) {
2301 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2302 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2304 ccv
.MinimumDepth
= 0.0;
2305 ccv
.MaximumDepth
= 1.0;
2307 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2308 cc_map
+= GENX(CC_VIEWPORT_length
);
2312 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2313 ptr
.CCViewportPointer
= cc_vp_offset
;
2316 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2317 vp
.CCViewportStateChange
= 1;
2318 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2321 brw
->cc
.vp_offset
= cc_vp_offset
;
2322 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2326 const struct brw_tracked_state
genX(cc_vp
) = {
2328 .mesa
= _NEW_TRANSFORM
|
2330 .brw
= BRW_NEW_BATCH
|
2332 BRW_NEW_VIEWPORT_COUNT
,
2334 .emit
= genX(upload_cc_viewport
)
2337 /* ---------------------------------------------------------------------- */
2340 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2341 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2342 struct GENX(SCISSOR_RECT
) *sc
)
2346 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2347 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2348 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2349 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2350 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2352 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2353 /* If the scissor was out of bounds and got clamped to 0 width/height
2354 * at the bounds, the subtraction of 1 from maximums could produce a
2355 * negative number and thus not clip anything. Instead, just provide
2356 * a min > max scissor inside the bounds, which produces the expected
2359 sc
->ScissorRectangleXMin
= 1;
2360 sc
->ScissorRectangleXMax
= 0;
2361 sc
->ScissorRectangleYMin
= 1;
2362 sc
->ScissorRectangleYMax
= 0;
2363 } else if (render_to_fbo
) {
2364 /* texmemory: Y=0=bottom */
2365 sc
->ScissorRectangleXMin
= bbox
[0];
2366 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2367 sc
->ScissorRectangleYMin
= bbox
[2];
2368 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2370 /* memory: Y=0=top */
2371 sc
->ScissorRectangleXMin
= bbox
[0];
2372 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2373 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2374 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2380 genX(upload_scissor_state
)(struct brw_context
*brw
)
2382 struct gl_context
*ctx
= &brw
->ctx
;
2383 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2384 struct GENX(SCISSOR_RECT
) scissor
;
2385 uint32_t scissor_state_offset
;
2386 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2387 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2388 uint32_t *scissor_map
;
2390 /* BRW_NEW_VIEWPORT_COUNT */
2391 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2393 scissor_map
= brw_state_batch(
2394 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2395 32, &scissor_state_offset
);
2397 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2399 /* The scissor only needs to handle the intersection of drawable and
2400 * scissor rect. Clipping to the boundaries of static shared buffers
2401 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2403 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2404 * inclusive but max is exclusive.
2406 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2407 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2408 GENX(SCISSOR_RECT_pack
)(
2409 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2412 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2413 ptr
.ScissorRectPointer
= scissor_state_offset
;
2417 static const struct brw_tracked_state
genX(scissor_state
) = {
2419 .mesa
= _NEW_BUFFERS
|
2422 .brw
= BRW_NEW_BATCH
|
2424 BRW_NEW_VIEWPORT_COUNT
,
2426 .emit
= genX(upload_scissor_state
),
2430 /* ---------------------------------------------------------------------- */
2433 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2434 float m00
, float m11
, float m30
, float m31
,
2435 float *xmin
, float *xmax
,
2436 float *ymin
, float *ymax
)
2438 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2439 * Strips and Fans documentation:
2441 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2442 * fixed-point "guardband" range supported by the rasterization hardware"
2446 * "In almost all circumstances, if an object’s vertices are actually
2447 * modified by this clamping (i.e., had X or Y coordinates outside of
2448 * the guardband extent the rendered object will not match the intended
2449 * result. Therefore software should take steps to ensure that this does
2450 * not happen - e.g., by clipping objects such that they do not exceed
2451 * these limits after the Drawing Rectangle is applied."
2453 * I believe the fundamental restriction is that the rasterizer (in
2454 * the SF/WM stages) have a limit on the number of pixels that can be
2455 * rasterized. We need to ensure any coordinates beyond the rasterizer
2456 * limit are handled by the clipper. So effectively that limit becomes
2457 * the clipper's guardband size.
2459 * It goes on to say:
2461 * "In addition, in order to be correctly rendered, objects must have a
2462 * screenspace bounding box not exceeding 8K in the X or Y direction.
2463 * This additional restriction must also be comprehended by software,
2464 * i.e., enforced by use of clipping."
2466 * This makes no sense. Gen7+ hardware supports 16K render targets,
2467 * and you definitely need to be able to draw polygons that fill the
2468 * surface. Our assumption is that the rasterizer was limited to 8K
2469 * on Sandybridge, which only supports 8K surfaces, and it was actually
2470 * increased to 16K on Ivybridge and later.
2472 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2474 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2476 if (m00
!= 0 && m11
!= 0) {
2477 /* First, we compute the screen-space render area */
2478 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2479 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2480 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2481 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2483 /* We want the guardband to be centered on that */
2484 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2485 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2486 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2487 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2489 /* Now we need it in native device coordinates */
2490 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2491 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2492 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2493 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2495 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2496 * flipped upside-down. X should be fine though.
2498 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2499 *xmin
= ndc_gb_xmin
;
2500 *xmax
= ndc_gb_xmax
;
2501 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2502 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2504 /* The viewport scales to 0, so nothing will be rendered. */
2513 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2515 struct gl_context
*ctx
= &brw
->ctx
;
2516 float y_scale
, y_bias
;
2518 /* BRW_NEW_VIEWPORT_COUNT */
2519 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2522 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2523 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2524 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2528 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2529 uint32_t sf_clip_vp_offset
;
2530 uint32_t *sf_clip_map
=
2531 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2532 64, &sf_clip_vp_offset
);
2534 struct GENX(SF_VIEWPORT
) sfv
;
2535 struct GENX(CLIP_VIEWPORT
) clv
;
2536 uint32_t sf_vp_offset
, clip_vp_offset
;
2538 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2540 uint32_t *clip_map
=
2541 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2542 32, &clip_vp_offset
);
2546 if (render_to_fbo
) {
2551 y_bias
= (float)fb_height
;
2554 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2555 /* _NEW_VIEWPORT: Guardband Clipping */
2556 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2557 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2559 sfv
.ViewportMatrixElementm00
= scale
[0];
2560 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2561 sfv
.ViewportMatrixElementm22
= scale
[2],
2562 sfv
.ViewportMatrixElementm30
= translate
[0],
2563 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2564 sfv
.ViewportMatrixElementm32
= translate
[2],
2565 brw_calculate_guardband_size(fb_width
, fb_height
,
2566 sfv
.ViewportMatrixElementm00
,
2567 sfv
.ViewportMatrixElementm11
,
2568 sfv
.ViewportMatrixElementm30
,
2569 sfv
.ViewportMatrixElementm31
,
2570 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2573 clv
.XMinClipGuardband
= gb_xmin
;
2574 clv
.XMaxClipGuardband
= gb_xmax
;
2575 clv
.YMinClipGuardband
= gb_ymin
;
2576 clv
.YMaxClipGuardband
= gb_ymax
;
2579 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2580 &sfv
.ScissorRectangle
);
2582 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2583 * The hardware will take the intersection of the drawing rectangle,
2584 * scissor rectangle, and the viewport extents. However, emitting
2585 * 3DSTATE_DRAWING_RECTANGLE is expensive since it requires a full
2586 * pipeline stall so we're better off just being a little more clever
2587 * with our viewport so we can emit it once at context creation time.
2589 const float viewport_Xmin
= MAX2(ctx
->ViewportArray
[i
].X
, 0);
2590 const float viewport_Ymin
= MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2591 const float viewport_Xmax
=
2592 MIN2(ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
, fb_width
);
2593 const float viewport_Ymax
=
2594 MIN2(ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
, fb_height
);
2596 if (render_to_fbo
) {
2597 sfv
.XMinViewPort
= viewport_Xmin
;
2598 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2599 sfv
.YMinViewPort
= viewport_Ymin
;
2600 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2602 sfv
.XMinViewPort
= viewport_Xmin
;
2603 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2604 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2605 sfv
.YMaxViewPort
= fb_height
- viewport_Ymin
- 1;
2610 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2611 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2613 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2614 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2615 sf_map
+= GENX(SF_VIEWPORT_length
);
2616 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2621 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2622 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2625 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2626 vp
.SFViewportStateChange
= 1;
2627 vp
.CLIPViewportStateChange
= 1;
2628 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2629 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2632 brw
->sf
.vp_offset
= sf_vp_offset
;
2633 brw
->clip
.vp_offset
= clip_vp_offset
;
2634 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2638 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2640 .mesa
= _NEW_BUFFERS
|
2642 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2643 .brw
= BRW_NEW_BATCH
|
2645 BRW_NEW_VIEWPORT_COUNT
,
2647 .emit
= genX(upload_sf_clip_viewport
),
2650 /* ---------------------------------------------------------------------- */
2653 genX(upload_gs_state
)(struct brw_context
*brw
)
2655 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2656 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2657 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2658 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2659 /* BRW_NEW_GEOMETRY_PROGRAM */
2660 bool active
= GEN_GEN
>= 6 && gs_prog
;
2662 /* BRW_NEW_GS_PROG_DATA */
2663 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2664 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2665 brw_vue_prog_data(stage_prog_data
);
2667 const struct brw_gs_prog_data
*gs_prog_data
=
2668 brw_gs_prog_data(stage_prog_data
);
2672 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2673 if (active
&& stage_state
->push_const_size
!= 0) {
2674 cgs
.Buffer0Valid
= true;
2675 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2676 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2681 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2683 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2684 * Geometry > Geometry Shader > State:
2686 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2687 * whole fixed function pipeline when the GS enable changes value in
2690 * The hardware architects have clarified that in this context "flush the
2691 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2694 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2695 gen7_emit_cs_stall_flush(brw
);
2699 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2701 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2702 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2707 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2710 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2711 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2712 gs
.ControlDataHeaderSize
=
2713 gs_prog_data
->control_data_header_size_hwords
;
2715 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2716 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2718 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2720 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2723 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2724 * Ivy Bridge and Haswell.
2726 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2727 * strip to be delivered to the geometry shader in an order that does
2728 * not strictly follow the OpenGL spec, but preserves triangle
2729 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2730 * the geometry shader sees triangles:
2732 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2734 * (Clearing the bit is even worse, because it fails to preserve
2737 * Triangle strips with adjacency always ordered in a way that preserves
2738 * triangle orientation but does not strictly follow the OpenGL spec,
2739 * regardless of the setting of this bit.
2741 * On Haswell, both triangle strips and triangle strips with adjacency
2742 * are always ordered in a way that preserves triangle orientation.
2743 * Setting this bit causes the ordering to strictly follow the OpenGL
2746 * So in either case we want to set the bit. Unfortunately on Ivy
2747 * Bridge this will get the order close to correct but not perfect.
2749 gs
.ReorderMode
= TRAILING
;
2750 gs
.MaximumNumberofThreads
=
2751 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2752 : (devinfo
->max_gs_threads
- 1);
2755 gs
.SOStatisticsEnable
= true;
2756 if (gs_prog
->info
.has_transform_feedback_varyings
)
2757 gs
.SVBIPayloadEnable
= true;
2759 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2760 * was previously done for gen6.
2762 * TODO: test with both disabled to see if the HW is behaving
2763 * as expected, like in gen7.
2765 gs
.SingleProgramFlow
= true;
2766 gs
.VectorMaskEnable
= true;
2770 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2772 if (gs_prog_data
->static_vertex_count
!= -1) {
2773 gs
.StaticOutput
= true;
2774 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2776 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2778 gs
.UserClipDistanceCullTestEnableBitmask
=
2779 vue_prog_data
->cull_distance_mask
;
2781 const int urb_entry_write_offset
= 1;
2782 const uint32_t urb_entry_output_length
=
2783 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2784 urb_entry_write_offset
;
2786 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2787 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2793 if (!active
&& brw
->ff_gs
.prog_active
) {
2794 /* In gen6, transform feedback for the VS stage is done with an
2795 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2798 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2799 gs
.SingleProgramFlow
= true;
2800 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2801 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2804 gs
.GRFRegisterCount
=
2805 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2806 /* BRW_NEW_URB_FENCE */
2807 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2808 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2809 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2810 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2813 gs
.VectorMaskEnable
= true;
2814 gs
.SVBIPayloadEnable
= true;
2815 gs
.SVBIPostIncrementEnable
= true;
2816 gs
.SVBIPostIncrementValue
=
2817 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2818 gs
.SOStatisticsEnable
= true;
2819 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2823 if (!active
&& !brw
->ff_gs
.prog_active
) {
2825 gs
.DispatchGRFStartRegisterForURBData
= 1;
2827 gs
.IncludeVertexHandles
= true;
2833 gs
.StatisticsEnable
= true;
2835 #if GEN_GEN == 5 || GEN_GEN == 6
2836 gs
.RenderingEnabled
= true;
2839 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2844 brw
->gs
.enabled
= active
;
2848 static const struct brw_tracked_state
genX(gs_state
) = {
2850 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2851 .brw
= BRW_NEW_BATCH
|
2853 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2854 BRW_NEW_PROGRAM_CACHE
|
2856 BRW_NEW_VIEWPORT_COUNT
2858 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2859 BRW_NEW_GEOMETRY_PROGRAM
|
2860 BRW_NEW_GS_PROG_DATA
2862 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2864 .emit
= genX(upload_gs_state
),
2867 /* ---------------------------------------------------------------------- */
2869 UNUSED
static GLenum
2870 fix_dual_blend_alpha_to_one(GLenum function
)
2876 case GL_ONE_MINUS_SRC1_ALPHA
:
2883 #define blend_factor(x) brw_translate_blend_factor(x)
2884 #define blend_eqn(x) brw_translate_blend_equation(x)
2887 * Modify blend function to force destination alpha to 1.0
2889 * If \c function specifies a blend function that uses destination alpha,
2890 * replace it with a function that hard-wires destination alpha to 1.0. This
2891 * is used when rendering to xRGB targets.
2894 brw_fix_xRGB_alpha(GLenum function
)
2900 case GL_ONE_MINUS_DST_ALPHA
:
2901 case GL_SRC_ALPHA_SATURATE
:
2909 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2911 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2915 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2918 struct gl_context
*ctx
= &brw
->ctx
;
2921 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2923 bool independent_alpha_blend
= false;
2925 /* Used for implementing the following bit of GL_EXT_texture_integer:
2926 * "Per-fragment operations that require floating-point color
2927 * components, including multisample alpha operations, alpha test,
2928 * blending, and dithering, have no effect when the corresponding
2929 * colors are written to an integer color buffer."
2931 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2933 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2934 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2937 if (ctx
->Color
.ColorLogicOpEnabled
) {
2938 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2939 : GL_UNSIGNED_NORMALIZED
;
2940 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2941 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2942 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2944 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2945 _mesa_enum_to_string(rb_type
));
2946 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2947 entry
->LogicOpEnable
= true;
2948 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2950 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2951 && (GEN_GEN
<= 5 || !integer
)) {
2952 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2953 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2954 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2955 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2956 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2957 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2959 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2960 srcRGB
= dstRGB
= GL_ONE
;
2962 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2963 srcA
= dstA
= GL_ONE
;
2965 /* Due to hardware limitations, the destination may have information
2966 * in an alpha channel even when the format specifies no alpha
2967 * channel. In order to avoid getting any incorrect blending due to
2968 * that alpha channel, coerce the blend factors to values that will
2969 * not read the alpha channel, but will instead use the correct
2970 * implicit value for alpha.
2972 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2973 GL_TEXTURE_ALPHA_TYPE
)) {
2974 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2975 srcA
= brw_fix_xRGB_alpha(srcA
);
2976 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2977 dstA
= brw_fix_xRGB_alpha(dstA
);
2980 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2981 * "If Dual Source Blending is enabled, this bit must be disabled."
2983 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2984 * and leave it enabled anyway.
2986 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2987 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2988 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2989 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2990 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2993 entry
->ColorBufferBlendEnable
= true;
2994 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2995 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2996 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2997 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2998 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2999 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
3001 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
3002 independent_alpha_blend
= true;
3005 return independent_alpha_blend
;
3010 genX(upload_blend_state
)(struct brw_context
*brw
)
3012 struct gl_context
*ctx
= &brw
->ctx
;
3015 /* We need at least one BLEND_STATE written, because we might do
3016 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
3017 * for computed depth or alpha test), which will do an FB write
3018 * with render target 0, which will reference BLEND_STATE[0] for
3019 * alpha test enable.
3021 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
3022 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
3023 nr_draw_buffers
= 1;
3025 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
3027 size
+= GENX(BLEND_STATE_length
) * 4;
3030 uint32_t *blend_map
;
3031 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
3034 struct GENX(BLEND_STATE
) blend
= { 0 };
3037 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3038 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3041 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
3042 * "If drawbuffer zero is not NONE and the buffer it references has an
3043 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
3044 * operations are skipped."
3046 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
3047 /* _NEW_MULTISAMPLE */
3048 if (_mesa_is_multisample_enabled(ctx
)) {
3049 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
3050 blend
.AlphaToCoverageEnable
= true;
3051 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
3053 if (ctx
->Multisample
.SampleAlphaToOne
)
3054 blend
.AlphaToOneEnable
= true;
3058 if (ctx
->Color
.AlphaEnabled
) {
3059 blend
.AlphaTestEnable
= true;
3060 blend
.AlphaTestFunction
=
3061 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3064 if (ctx
->Color
.DitherFlag
) {
3065 blend
.ColorDitherEnable
= true;
3070 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3071 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3075 blend
.IndependentAlphaBlendEnable
=
3076 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
3077 blend
.IndependentAlphaBlendEnable
;
3079 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
3080 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
3082 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
3083 * clamping in the fragment shader. For its clamping of
3084 * blending, the spec says:
3086 * "RESOLVED: For fixed-point color buffers, the inputs and
3087 * the result of the blending equation are clamped. For
3088 * floating-point color buffers, no clamping occurs."
3090 * So, generally, we want clamping to the render target's range.
3091 * And, good news, the hardware tables for both pre- and
3092 * post-blend color clamping are either ignored, or any are
3093 * allowed, or clamping is required but RT range clamping is a
3096 entry
.PreBlendColorClampEnable
= true;
3097 entry
.PostBlendColorClampEnable
= true;
3098 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
3100 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
3101 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
3102 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
3103 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
3106 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
3108 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3114 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3118 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3119 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3120 ptr
.BLEND_STATEChange
= true;
3123 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3124 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3126 ptr
.BlendStatePointerValid
= true;
3132 static const struct brw_tracked_state
genX(blend_state
) = {
3134 .mesa
= _NEW_BUFFERS
|
3137 .brw
= BRW_NEW_BATCH
|
3139 BRW_NEW_STATE_BASE_ADDRESS
,
3141 .emit
= genX(upload_blend_state
),
3145 /* ---------------------------------------------------------------------- */
3148 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3149 [MESA_SHADER_VERTEX
] = 21,
3150 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3151 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3152 [MESA_SHADER_GEOMETRY
] = 22,
3153 [MESA_SHADER_FRAGMENT
] = 23,
3154 [MESA_SHADER_COMPUTE
] = 0,
3158 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3160 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3161 struct gl_context
*ctx
= &brw
->ctx
;
3163 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3165 struct brw_stage_state
*stage_states
[] = {
3173 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3174 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3175 gen7_emit_vs_workaround_flush(brw
);
3177 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3178 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3179 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3181 if (!stage_state
->push_constants_dirty
)
3184 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3185 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3186 if (stage_state
->prog_data
) {
3187 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3188 /* The Skylake PRM contains the following restriction:
3190 * "The driver must ensure The following case does not occur
3191 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3192 * buffer 3 read length equal to zero committed followed by a
3193 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3196 * To avoid this, we program the buffers in the highest slots.
3197 * This way, slot 0 is only used if slot 3 is also used.
3201 for (int i
= 3; i
>= 0; i
--) {
3202 const struct brw_ubo_range
*range
=
3203 &stage_state
->prog_data
->ubo_ranges
[i
];
3205 if (range
->length
== 0)
3208 const struct gl_uniform_block
*block
=
3209 prog
->sh
.UniformBlocks
[range
->block
];
3210 const struct gl_buffer_binding
*binding
=
3211 &ctx
->UniformBufferBindings
[block
->Binding
];
3213 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3214 static unsigned msg_id
= 0;
3215 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3216 MESA_DEBUG_TYPE_UNDEFINED
,
3217 MESA_DEBUG_SEVERITY_HIGH
,
3218 "UBO %d unbound, %s shader uniform data "
3219 "will be undefined.",
3221 _mesa_shader_stage_to_string(stage
));
3225 assert(binding
->Offset
% 32 == 0);
3227 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3228 intel_buffer_object(binding
->BufferObject
),
3229 binding
->Offset
, range
->length
* 32, false);
3231 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3232 pkt
.ConstantBody
.Buffer
[n
] =
3233 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3237 if (stage_state
->push_const_size
> 0) {
3239 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3240 pkt
.ConstantBody
.Buffer
[n
] =
3241 ro_bo(stage_state
->push_const_bo
,
3242 stage_state
->push_const_offset
);
3245 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3246 pkt
.ConstantBody
.Buffer
[0].offset
=
3247 stage_state
->push_const_offset
| mocs
;
3252 stage_state
->push_constants_dirty
= false;
3253 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3257 const struct brw_tracked_state
genX(push_constant_packets
) = {
3260 .brw
= BRW_NEW_DRAW_CALL
,
3262 .emit
= genX(upload_push_constant_packets
),
3268 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3270 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3272 /* BRW_NEW_VERTEX_PROGRAM */
3273 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3274 /* BRW_NEW_VS_PROG_DATA */
3275 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3277 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3280 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3282 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3284 .brw
= BRW_NEW_BATCH
|
3286 BRW_NEW_VERTEX_PROGRAM
|
3287 BRW_NEW_VS_PROG_DATA
,
3289 .emit
= genX(upload_vs_push_constants
),
3293 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3295 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3297 /* BRW_NEW_GEOMETRY_PROGRAM */
3298 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3300 /* BRW_NEW_GS_PROG_DATA */
3301 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3303 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3306 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3308 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3310 .brw
= BRW_NEW_BATCH
|
3312 BRW_NEW_GEOMETRY_PROGRAM
|
3313 BRW_NEW_GS_PROG_DATA
,
3315 .emit
= genX(upload_gs_push_constants
),
3319 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3321 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3322 /* BRW_NEW_FRAGMENT_PROGRAM */
3323 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3324 /* BRW_NEW_FS_PROG_DATA */
3325 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3327 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3330 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3332 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3333 .brw
= BRW_NEW_BATCH
|
3335 BRW_NEW_FRAGMENT_PROGRAM
|
3336 BRW_NEW_FS_PROG_DATA
,
3338 .emit
= genX(upload_wm_push_constants
),
3342 /* ---------------------------------------------------------------------- */
3346 genX(determine_sample_mask
)(struct brw_context
*brw
)
3348 struct gl_context
*ctx
= &brw
->ctx
;
3349 float coverage
= 1.0f
;
3350 float coverage_invert
= false;
3351 unsigned sample_mask
= ~0u;
3353 /* BRW_NEW_NUM_SAMPLES */
3354 unsigned num_samples
= brw
->num_samples
;
3356 if (_mesa_is_multisample_enabled(ctx
)) {
3357 if (ctx
->Multisample
.SampleCoverage
) {
3358 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3359 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3361 if (ctx
->Multisample
.SampleMask
) {
3362 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3366 if (num_samples
> 1) {
3367 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3368 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3369 if (coverage_invert
)
3370 coverage_bits
^= (1 << num_samples
) - 1;
3371 return coverage_bits
& sample_mask
;
3378 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3379 unsigned num_samples
)
3381 unsigned log2_samples
= ffs(num_samples
) - 1;
3383 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3384 multi
.PixelLocation
= CENTER
;
3385 multi
.NumberofMultisamples
= log2_samples
;
3387 GEN_SAMPLE_POS_4X(multi
.Sample
);
3389 switch (num_samples
) {
3391 GEN_SAMPLE_POS_1X(multi
.Sample
);
3394 GEN_SAMPLE_POS_2X(multi
.Sample
);
3397 GEN_SAMPLE_POS_4X(multi
.Sample
);
3400 GEN_SAMPLE_POS_8X(multi
.Sample
);
3410 genX(upload_multisample_state
)(struct brw_context
*brw
)
3412 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3414 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3416 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3417 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3421 static const struct brw_tracked_state
genX(multisample_state
) = {
3423 .mesa
= _NEW_MULTISAMPLE
|
3424 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3425 .brw
= BRW_NEW_BLORP
|
3427 BRW_NEW_NUM_SAMPLES
,
3429 .emit
= genX(upload_multisample_state
)
3433 /* ---------------------------------------------------------------------- */
3436 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3438 struct gl_context
*ctx
= &brw
->ctx
;
3440 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3442 cc
.IndependentAlphaBlendEnable
=
3443 set_blend_entry_bits(brw
, &cc
, 0, false);
3444 set_depth_stencil_bits(brw
, &cc
);
3446 if (ctx
->Color
.AlphaEnabled
&&
3447 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3448 cc
.AlphaTestEnable
= true;
3449 cc
.AlphaTestFunction
=
3450 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3453 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3455 cc
.StatisticsEnable
= brw
->stats_wm
;
3457 cc
.CCViewportStatePointer
=
3458 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3461 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3462 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3463 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3464 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3468 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3469 cc
.BackfaceStencilReferenceValue
=
3470 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3476 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3477 ctx
->Color
.AlphaRef
);
3481 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3482 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3484 ptr
.ColorCalcStatePointerValid
= true;
3488 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3492 static const struct brw_tracked_state
genX(color_calc_state
) = {
3494 .mesa
= _NEW_COLOR
|
3496 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3499 .brw
= BRW_NEW_BATCH
|
3501 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3503 : BRW_NEW_CC_STATE
|
3504 BRW_NEW_STATE_BASE_ADDRESS
),
3506 .emit
= genX(upload_color_calc_state
),
3510 /* ---------------------------------------------------------------------- */
3514 genX(upload_sbe
)(struct brw_context
*brw
)
3516 struct gl_context
*ctx
= &brw
->ctx
;
3517 /* BRW_NEW_FRAGMENT_PROGRAM */
3518 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3519 /* BRW_NEW_FS_PROG_DATA */
3520 const struct brw_wm_prog_data
*wm_prog_data
=
3521 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3523 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3525 #define attr_overrides sbe.Attribute
3527 uint32_t urb_entry_read_length
;
3528 uint32_t urb_entry_read_offset
;
3529 uint32_t point_sprite_enables
;
3531 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3532 sbe
.AttributeSwizzleEnable
= true;
3533 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3536 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3540 * Window coordinates in an FBO are inverted, which means point
3541 * sprite origin must be inverted.
3543 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3544 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3546 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3548 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3549 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3550 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3551 * BRW_NEW_VUE_MAP_GEOM_OUT
3553 genX(calculate_attr_overrides
)(brw
,
3555 &point_sprite_enables
,
3556 &urb_entry_read_length
,
3557 &urb_entry_read_offset
);
3559 /* Typically, the URB entry read length and offset should be programmed
3560 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3561 * stage which produces geometry. However, we don't know the proper
3562 * value until we call calculate_attr_overrides().
3564 * To fit with our existing code, we override the inherited values and
3565 * specify it here directly, as we did on previous generations.
3567 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3568 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3569 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3570 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3573 sbe
.ForceVertexURBEntryReadLength
= true;
3574 sbe
.ForceVertexURBEntryReadOffset
= true;
3578 /* prepare the active component dwords */
3579 for (int i
= 0; i
< 32; i
++)
3580 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3585 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3586 for (int i
= 0; i
< 16; i
++)
3587 sbes
.Attribute
[i
] = attr_overrides
[i
];
3591 #undef attr_overrides
3594 static const struct brw_tracked_state
genX(sbe_state
) = {
3596 .mesa
= _NEW_BUFFERS
|
3601 .brw
= BRW_NEW_BLORP
|
3603 BRW_NEW_FRAGMENT_PROGRAM
|
3604 BRW_NEW_FS_PROG_DATA
|
3605 BRW_NEW_GS_PROG_DATA
|
3606 BRW_NEW_TES_PROG_DATA
|
3607 BRW_NEW_VUE_MAP_GEOM_OUT
|
3608 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3611 .emit
= genX(upload_sbe
),
3615 /* ---------------------------------------------------------------------- */
3619 * Outputs the 3DSTATE_SO_DECL_LIST command.
3621 * The data output is a series of 64-bit entries containing a SO_DECL per
3622 * stream. We only have one stream of rendering coming out of the GS unit, so
3623 * we only emit stream 0 (low 16 bits) SO_DECLs.
3626 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3627 const struct brw_vue_map
*vue_map
)
3629 struct gl_context
*ctx
= &brw
->ctx
;
3630 /* BRW_NEW_TRANSFORM_FEEDBACK */
3631 struct gl_transform_feedback_object
*xfb_obj
=
3632 ctx
->TransformFeedback
.CurrentObject
;
3633 const struct gl_transform_feedback_info
*linked_xfb_info
=
3634 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3635 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3636 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3637 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3638 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3640 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3642 memset(so_decl
, 0, sizeof(so_decl
));
3644 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3645 * command feels strange -- each dword pair contains a SO_DECL per stream.
3647 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3648 const struct gl_transform_feedback_output
*output
=
3649 &linked_xfb_info
->Outputs
[i
];
3650 const int buffer
= output
->OutputBuffer
;
3651 const int varying
= output
->OutputRegister
;
3652 const unsigned stream_id
= output
->StreamId
;
3653 assert(stream_id
< MAX_VERTEX_STREAMS
);
3655 buffer_mask
[stream_id
] |= 1 << buffer
;
3657 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3659 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3660 * array. Instead, it simply increments DstOffset for the following
3661 * input by the number of components that should be skipped.
3663 * Our hardware is unusual in that it requires us to program SO_DECLs
3664 * for fake "hole" components, rather than simply taking the offset
3665 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3666 * program as many size = 4 holes as we can, then a final hole to
3667 * accommodate the final 1, 2, or 3 remaining.
3669 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3671 while (skip_components
> 0) {
3672 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3674 .OutputBufferSlot
= output
->OutputBuffer
,
3675 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3677 skip_components
-= 4;
3680 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3682 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3683 .OutputBufferSlot
= output
->OutputBuffer
,
3684 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3686 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3689 if (decls
[stream_id
] > max_decls
)
3690 max_decls
= decls
[stream_id
];
3694 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3695 .StreamtoBufferSelects0
= buffer_mask
[0],
3696 .StreamtoBufferSelects1
= buffer_mask
[1],
3697 .StreamtoBufferSelects2
= buffer_mask
[2],
3698 .StreamtoBufferSelects3
= buffer_mask
[3],
3699 .NumEntries0
= decls
[0],
3700 .NumEntries1
= decls
[1],
3701 .NumEntries2
= decls
[2],
3702 .NumEntries3
= decls
[3]);
3704 for (int i
= 0; i
< max_decls
; i
++) {
3705 GENX(SO_DECL_ENTRY_pack
)(
3706 brw
, dw
+ 2 + i
* 2,
3707 &(struct GENX(SO_DECL_ENTRY
)) {
3708 .Stream0Decl
= so_decl
[0][i
],
3709 .Stream1Decl
= so_decl
[1][i
],
3710 .Stream2Decl
= so_decl
[2][i
],
3711 .Stream3Decl
= so_decl
[3][i
],
3717 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3719 struct gl_context
*ctx
= &brw
->ctx
;
3720 /* BRW_NEW_TRANSFORM_FEEDBACK */
3721 struct gl_transform_feedback_object
*xfb_obj
=
3722 ctx
->TransformFeedback
.CurrentObject
;
3724 const struct gl_transform_feedback_info
*linked_xfb_info
=
3725 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3727 struct brw_transform_feedback_object
*brw_obj
=
3728 (struct brw_transform_feedback_object
*) xfb_obj
;
3729 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3732 /* Set up the up to 4 output buffers. These are the ranges defined in the
3733 * gl_transform_feedback_object.
3735 for (int i
= 0; i
< 4; i
++) {
3736 struct intel_buffer_object
*bufferobj
=
3737 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3740 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3741 sob
.SOBufferIndex
= i
;
3746 uint32_t start
= xfb_obj
->Offset
[i
];
3747 assert(start
% 4 == 0);
3748 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3750 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3751 assert(end
<= bo
->size
);
3753 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3754 sob
.SOBufferIndex
= i
;
3756 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3758 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3759 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3761 sob
.SOBufferEnable
= true;
3762 sob
.StreamOffsetWriteEnable
= true;
3763 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3764 sob
.SOBufferMOCS
= mocs_wb
;
3766 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3767 sob
.StreamOutputBufferOffsetAddress
=
3768 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3770 if (brw_obj
->zero_offsets
) {
3771 /* Zero out the offset and write that to offset_bo */
3772 sob
.StreamOffset
= 0;
3774 /* Use offset_bo as the "Stream Offset." */
3775 sob
.StreamOffset
= 0xFFFFFFFF;
3782 brw_obj
->zero_offsets
= false;
3787 query_active(struct gl_query_object
*q
)
3789 return q
&& q
->Active
;
3793 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3794 const struct brw_vue_map
*vue_map
)
3796 struct gl_context
*ctx
= &brw
->ctx
;
3797 /* BRW_NEW_TRANSFORM_FEEDBACK */
3798 struct gl_transform_feedback_object
*xfb_obj
=
3799 ctx
->TransformFeedback
.CurrentObject
;
3801 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3803 int urb_entry_read_offset
= 0;
3804 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3805 urb_entry_read_offset
;
3807 sos
.SOFunctionEnable
= true;
3808 sos
.SOStatisticsEnable
= true;
3810 /* BRW_NEW_RASTERIZER_DISCARD */
3811 if (ctx
->RasterDiscard
) {
3812 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3813 sos
.RenderingDisable
= true;
3815 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3816 "query active relies on the clipper.\n");
3821 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3822 sos
.ReorderMode
= TRAILING
;
3825 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3826 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3827 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3828 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3830 const struct gl_transform_feedback_info
*linked_xfb_info
=
3831 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3832 /* Set buffer pitches; 0 means unbound. */
3833 if (xfb_obj
->Buffers
[0])
3834 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3835 if (xfb_obj
->Buffers
[1])
3836 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3837 if (xfb_obj
->Buffers
[2])
3838 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3839 if (xfb_obj
->Buffers
[3])
3840 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3843 /* We always read the whole vertex. This could be reduced at some
3844 * point by reading less and offsetting the register index in the
3847 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3848 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3849 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3850 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3851 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3852 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3853 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3854 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3860 genX(upload_sol
)(struct brw_context
*brw
)
3862 struct gl_context
*ctx
= &brw
->ctx
;
3863 /* BRW_NEW_TRANSFORM_FEEDBACK */
3864 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3867 genX(upload_3dstate_so_buffers
)(brw
);
3869 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3870 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3873 /* Finally, set up the SOL stage. This command must always follow updates to
3874 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3875 * MMIO register updates (current performed by the kernel at each batch
3878 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3881 static const struct brw_tracked_state
genX(sol_state
) = {
3884 .brw
= BRW_NEW_BATCH
|
3886 BRW_NEW_RASTERIZER_DISCARD
|
3887 BRW_NEW_VUE_MAP_GEOM_OUT
|
3888 BRW_NEW_TRANSFORM_FEEDBACK
,
3890 .emit
= genX(upload_sol
),
3894 /* ---------------------------------------------------------------------- */
3898 genX(upload_ps
)(struct brw_context
*brw
)
3900 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3901 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3903 /* BRW_NEW_FS_PROG_DATA */
3904 const struct brw_wm_prog_data
*prog_data
=
3905 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3906 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3911 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3912 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3913 * incorrect for subspans where some of the pixels are unlit. We believe
3914 * the bit just didn't take effect in previous generations.
3916 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3919 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3921 /* BRW_NEW_FS_PROG_DATA */
3922 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3924 if (prog_data
->base
.use_alt_mode
)
3925 ps
.FloatingPointMode
= Alternate
;
3927 /* Haswell requires the sample mask to be set in this packet as well as
3928 * in 3DSTATE_SAMPLE_MASK; the values should match.
3931 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3933 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3936 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
3937 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
3938 * k, it implies 2(k+1) threads. It implicitly scales for different GT
3939 * levels (which have some # of PSDs).
3941 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
3944 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3946 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3948 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3951 if (prog_data
->base
.nr_params
> 0 ||
3952 prog_data
->base
.ubo_ranges
[0].length
> 0)
3953 ps
.PushConstantEnable
= true;
3956 /* From the IVB PRM, volume 2 part 1, page 287:
3957 * "This bit is inserted in the PS payload header and made available to
3958 * the DataPort (either via the message header or via header bypass) to
3959 * indicate that oMask data (one or two phases) is included in Render
3960 * Target Write messages. If present, the oMask data is used to mask off
3963 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3965 /* The hardware wedges if you have this bit set but don't turn on any
3966 * dual source blend factors.
3968 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3970 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3971 (ctx
->Color
.BlendEnabled
& 1) &&
3972 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3974 /* BRW_NEW_FS_PROG_DATA */
3975 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3978 /* From the documentation for this packet:
3979 * "If the PS kernel does not need the Position XY Offsets to
3980 * compute a Position Value, then this field should be programmed
3981 * to POSOFFSET_NONE."
3983 * "SW Recommendation: If the PS kernel needs the Position Offsets
3984 * to compute a Position XY value, this field should match Position
3985 * ZW Interpolation Mode to ensure a consistent position.xyzw
3988 * We only require XY sample offsets. So, this recommendation doesn't
3989 * look useful at the moment. We might need this in future.
3991 if (prog_data
->uses_pos_offset
)
3992 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3994 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3996 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3997 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3998 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3999 prog_data
->base
.dispatch_grf_start_reg
;
4000 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
4001 prog_data
->dispatch_grf_start_reg_2
;
4003 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
4004 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
4005 prog_data
->prog_offset_2
;
4007 if (prog_data
->base
.total_scratch
) {
4008 ps
.ScratchSpaceBasePointer
=
4009 rw_32_bo(stage_state
->scratch_bo
,
4010 ffs(stage_state
->per_thread_scratch
) - 11);
4015 static const struct brw_tracked_state
genX(ps_state
) = {
4017 .mesa
= _NEW_MULTISAMPLE
|
4018 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
4021 .brw
= BRW_NEW_BATCH
|
4023 BRW_NEW_FS_PROG_DATA
,
4025 .emit
= genX(upload_ps
),
4029 /* ---------------------------------------------------------------------- */
4033 genX(upload_hs_state
)(struct brw_context
*brw
)
4035 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4036 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4037 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4038 const struct brw_vue_prog_data
*vue_prog_data
=
4039 brw_vue_prog_data(stage_prog_data
);
4041 /* BRW_NEW_TES_PROG_DATA */
4042 struct brw_tcs_prog_data
*tcs_prog_data
=
4043 brw_tcs_prog_data(stage_prog_data
);
4045 if (!tcs_prog_data
) {
4046 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
4048 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
4049 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
4051 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
4052 hs
.IncludeVertexHandles
= true;
4054 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
4059 static const struct brw_tracked_state
genX(hs_state
) = {
4062 .brw
= BRW_NEW_BATCH
|
4064 BRW_NEW_TCS_PROG_DATA
|
4065 BRW_NEW_TESS_PROGRAMS
,
4067 .emit
= genX(upload_hs_state
),
4071 genX(upload_ds_state
)(struct brw_context
*brw
)
4073 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4074 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4075 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4077 /* BRW_NEW_TES_PROG_DATA */
4078 const struct brw_tes_prog_data
*tes_prog_data
=
4079 brw_tes_prog_data(stage_prog_data
);
4080 const struct brw_vue_prog_data
*vue_prog_data
=
4081 brw_vue_prog_data(stage_prog_data
);
4083 if (!tes_prog_data
) {
4084 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
4086 assert(GEN_GEN
< 11 ||
4087 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
4089 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
4090 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
4092 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4093 ds
.ComputeWCoordinateEnable
=
4094 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4097 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
4098 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4099 ds
.UserClipDistanceCullTestEnableBitmask
=
4100 vue_prog_data
->cull_distance_mask
;
4106 static const struct brw_tracked_state
genX(ds_state
) = {
4109 .brw
= BRW_NEW_BATCH
|
4111 BRW_NEW_TESS_PROGRAMS
|
4112 BRW_NEW_TES_PROG_DATA
,
4114 .emit
= genX(upload_ds_state
),
4117 /* ---------------------------------------------------------------------- */
4120 upload_te_state(struct brw_context
*brw
)
4122 /* BRW_NEW_TESS_PROGRAMS */
4123 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4125 /* BRW_NEW_TES_PROG_DATA */
4126 const struct brw_tes_prog_data
*tes_prog_data
=
4127 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4130 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4131 te
.Partitioning
= tes_prog_data
->partitioning
;
4132 te
.OutputTopology
= tes_prog_data
->output_topology
;
4133 te
.TEDomain
= tes_prog_data
->domain
;
4135 te
.MaximumTessellationFactorOdd
= 63.0;
4136 te
.MaximumTessellationFactorNotOdd
= 64.0;
4139 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4143 static const struct brw_tracked_state
genX(te_state
) = {
4146 .brw
= BRW_NEW_BLORP
|
4148 BRW_NEW_TES_PROG_DATA
|
4149 BRW_NEW_TESS_PROGRAMS
,
4151 .emit
= upload_te_state
,
4154 /* ---------------------------------------------------------------------- */
4157 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4159 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4160 /* BRW_NEW_TESS_PROGRAMS */
4161 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4163 /* BRW_NEW_TES_PROG_DATA */
4164 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4165 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4168 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4170 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4171 .brw
= BRW_NEW_BATCH
|
4173 BRW_NEW_TESS_PROGRAMS
|
4174 BRW_NEW_TES_PROG_DATA
,
4176 .emit
= genX(upload_tes_push_constants
),
4180 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4182 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4183 /* BRW_NEW_TESS_PROGRAMS */
4184 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4186 /* BRW_NEW_TCS_PROG_DATA */
4187 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4189 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4192 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4194 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4195 .brw
= BRW_NEW_BATCH
|
4197 BRW_NEW_DEFAULT_TESS_LEVELS
|
4198 BRW_NEW_TESS_PROGRAMS
|
4199 BRW_NEW_TCS_PROG_DATA
,
4201 .emit
= genX(upload_tcs_push_constants
),
4206 /* ---------------------------------------------------------------------- */
4210 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4212 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4214 /* BRW_NEW_COMPUTE_PROGRAM */
4215 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4218 /* BRW_NEW_CS_PROG_DATA */
4219 struct brw_cs_prog_data
*cs_prog_data
=
4220 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4222 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4223 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4227 const struct brw_tracked_state
genX(cs_push_constants
) = {
4229 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4230 .brw
= BRW_NEW_BATCH
|
4232 BRW_NEW_COMPUTE_PROGRAM
|
4233 BRW_NEW_CS_PROG_DATA
,
4235 .emit
= genX(upload_cs_push_constants
),
4239 * Creates a new CS constant buffer reflecting the current CS program's
4240 * constants, if needed by the CS program.
4243 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4245 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4247 /* BRW_NEW_COMPUTE_PROGRAM */
4248 struct brw_program
*cp
=
4249 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4251 /* BRW_NEW_CS_PROG_DATA */
4252 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4254 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4255 /* _NEW_PROGRAM_CONSTANTS */
4256 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4257 stage_state
, prog_data
);
4260 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4262 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4263 .brw
= BRW_NEW_BATCH
|
4265 BRW_NEW_COMPUTE_PROGRAM
|
4266 BRW_NEW_CS_PROG_DATA
,
4268 .emit
= genX(upload_cs_pull_constants
),
4272 genX(upload_cs_state
)(struct brw_context
*brw
)
4274 if (!brw
->cs
.base
.prog_data
)
4278 uint32_t *desc
= (uint32_t*) brw_state_batch(
4279 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4282 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4283 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4284 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4285 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4287 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4288 brw_emit_buffer_surface_state(
4289 brw
, &stage_state
->surf_offset
[
4290 prog_data
->binding_table
.shader_time_start
],
4291 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4292 brw
->shader_time
.bo
->size
, 1,
4296 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4297 32, &stage_state
->bind_bo_offset
);
4299 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4301 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4302 * the only bits that are changed are scoreboard related: Scoreboard
4303 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4304 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4306 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4307 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4309 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4311 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4312 if (prog_data
->total_scratch
) {
4313 uint32_t per_thread_scratch_value
;
4316 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4317 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4319 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4320 } else if (GEN_IS_HASWELL
) {
4321 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4322 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4324 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4326 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4327 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4329 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4331 vfe
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
4332 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4335 /* If brw->screen->subslice_total is greater than one, then
4336 * devinfo->max_cs_threads stores number of threads per sub-slice;
4337 * thus we need to multiply by that number by subslices to get
4338 * the actual maximum number of threads; the -1 is because the HW
4339 * has a bias of 1 (would not make sense to say the maximum number
4342 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4343 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4344 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4346 vfe
.ResetGatewayTimer
=
4347 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4350 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4356 /* We are uploading duplicated copies of push constant uniforms for each
4357 * thread. Although the local id data needs to vary per thread, it won't
4358 * change for other uniform data. Unfortunately this duplication is
4359 * required for gen7. As of Haswell, this duplication can be avoided,
4360 * but this older mechanism with duplicated data continues to work.
4362 * FINISHME: As of Haswell, we could make use of the
4363 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4364 * field to only store one copy of uniform data.
4366 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4367 * which is described in the GPGPU_WALKER command and in the Broadwell
4368 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4369 * Operations => GPGPU Mode => Indirect Payload Storage.
4371 * Note: The constant data is built in brw_upload_cs_push_constants
4374 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4376 const uint32_t vfe_curbe_allocation
=
4377 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4378 cs_prog_data
->push
.cross_thread
.regs
, 2);
4379 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4382 if (cs_prog_data
->push
.total
.size
> 0) {
4383 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4384 curbe
.CURBETotalDataLength
=
4385 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4386 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4390 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4391 memcpy(bind
, stage_state
->surf_offset
,
4392 prog_data
->binding_table
.size_bytes
);
4393 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4394 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4395 .SamplerStatePointer
= stage_state
->sampler_offset
,
4396 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4397 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4398 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4399 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4400 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4401 prog_data
->total_shared
),
4402 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4403 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4404 .CrossThreadConstantDataReadLength
=
4405 cs_prog_data
->push
.cross_thread
.regs
,
4409 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4411 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4412 load
.InterfaceDescriptorTotalLength
=
4413 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4414 load
.InterfaceDescriptorDataStartAddress
= offset
;
4418 static const struct brw_tracked_state
genX(cs_state
) = {
4420 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4421 .brw
= BRW_NEW_BATCH
|
4423 BRW_NEW_CS_PROG_DATA
|
4424 BRW_NEW_SAMPLER_STATE_TABLE
|
4427 .emit
= genX(upload_cs_state
)
4432 /* ---------------------------------------------------------------------- */
4436 genX(upload_raster
)(struct brw_context
*brw
)
4438 const struct gl_context
*ctx
= &brw
->ctx
;
4441 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4444 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4447 const struct gl_point_attrib
*point
= &ctx
->Point
;
4449 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4450 if (brw
->polygon_front_bit
== render_to_fbo
)
4451 raster
.FrontWinding
= CounterClockwise
;
4453 if (polygon
->CullFlag
) {
4454 switch (polygon
->CullFaceMode
) {
4456 raster
.CullMode
= CULLMODE_FRONT
;
4459 raster
.CullMode
= CULLMODE_BACK
;
4461 case GL_FRONT_AND_BACK
:
4462 raster
.CullMode
= CULLMODE_BOTH
;
4465 unreachable("not reached");
4468 raster
.CullMode
= CULLMODE_NONE
;
4471 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4473 raster
.DXMultisampleRasterizationEnable
=
4474 _mesa_is_multisample_enabled(ctx
);
4476 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4477 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4478 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4480 switch (polygon
->FrontMode
) {
4482 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4485 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4488 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4491 unreachable("not reached");
4494 switch (polygon
->BackMode
) {
4496 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4499 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4502 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4505 unreachable("not reached");
4509 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4513 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4515 const bool multisampled_fbo
=
4516 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4517 if (multisampled_fbo
)
4518 raster
.AntialiasingEnable
= false;
4522 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4524 /* _NEW_TRANSFORM */
4525 if (!ctx
->Transform
.DepthClamp
) {
4527 raster
.ViewportZFarClipTestEnable
= true;
4528 raster
.ViewportZNearClipTestEnable
= true;
4530 raster
.ViewportZClipTestEnable
= true;
4534 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4536 raster
.ConservativeRasterizationEnable
=
4537 ctx
->IntelConservativeRasterization
;
4540 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4541 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4543 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4547 static const struct brw_tracked_state
genX(raster_state
) = {
4549 .mesa
= _NEW_BUFFERS
|
4556 .brw
= BRW_NEW_BLORP
|
4558 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4560 .emit
= genX(upload_raster
),
4564 /* ---------------------------------------------------------------------- */
4568 genX(upload_ps_extra
)(struct brw_context
*brw
)
4570 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4572 const struct brw_wm_prog_data
*prog_data
=
4573 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4575 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4576 psx
.PixelShaderValid
= true;
4577 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4578 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4579 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4580 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4581 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4582 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4584 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4585 if (prog_data
->uses_sample_mask
) {
4587 if (prog_data
->post_depth_coverage
)
4588 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4589 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4590 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4592 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4594 psx
.PixelShaderUsesInputCoverageMask
= true;
4598 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4600 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4601 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4604 /* The stricter cross-primitive coherency guarantees that the hardware
4605 * gives us with the "Accesses UAV" bit set for at least one shader stage
4606 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4607 * are redundant within the current image, atomic counter and SSBO GL
4608 * APIs, which all have very loose ordering and coherency requirements
4609 * and generally rely on the application to insert explicit barriers when
4610 * a shader invocation is expected to see the memory writes performed by
4611 * the invocations of some previous primitive. Regardless of the value
4612 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4613 * cause an in most cases useless DC flush when the lowermost stage with
4614 * the bit set finishes execution.
4616 * It would be nice to disable it, but in some cases we can't because on
4617 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4618 * signal (which could be set independently from the coherency mechanism
4619 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4620 * determine whether the hardware skips execution of the fragment shader
4621 * or not via the ThreadDispatchEnable signal. However if we know that
4622 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4623 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4624 * difference so we may just disable it here.
4626 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4627 * take into account KillPixels when no depth or stencil writes are
4628 * enabled. In order for occlusion queries to work correctly with no
4629 * attachments, we need to force-enable here.
4631 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4634 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4635 !brw_color_buffer_write_enabled(brw
))
4636 psx
.PixelShaderHasUAV
= true;
4640 const struct brw_tracked_state
genX(ps_extra
) = {
4642 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4643 .brw
= BRW_NEW_BLORP
|
4645 BRW_NEW_FRAGMENT_PROGRAM
|
4646 BRW_NEW_FS_PROG_DATA
|
4647 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4649 .emit
= genX(upload_ps_extra
),
4653 /* ---------------------------------------------------------------------- */
4657 genX(upload_ps_blend
)(struct brw_context
*brw
)
4659 struct gl_context
*ctx
= &brw
->ctx
;
4662 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4663 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4666 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4668 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4669 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4670 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4672 bool alpha_to_one
= false;
4674 if (!buffer0_is_integer
) {
4675 /* _NEW_MULTISAMPLE */
4677 if (_mesa_is_multisample_enabled(ctx
)) {
4678 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4679 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4682 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4685 /* Used for implementing the following bit of GL_EXT_texture_integer:
4686 * "Per-fragment operations that require floating-point color
4687 * components, including multisample alpha operations, alpha test,
4688 * blending, and dithering, have no effect when the corresponding
4689 * colors are written to an integer color buffer."
4691 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4692 * "If drawbuffer zero is not NONE and the buffer it references has an
4693 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4694 * operations are skipped."
4696 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4697 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4698 GLenum eqA
= color
->Blend
[0].EquationA
;
4699 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4700 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4701 GLenum srcA
= color
->Blend
[0].SrcA
;
4702 GLenum dstA
= color
->Blend
[0].DstA
;
4704 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4705 srcRGB
= dstRGB
= GL_ONE
;
4707 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4708 srcA
= dstA
= GL_ONE
;
4710 /* Due to hardware limitations, the destination may have information
4711 * in an alpha channel even when the format specifies no alpha
4712 * channel. In order to avoid getting any incorrect blending due to
4713 * that alpha channel, coerce the blend factors to values that will
4714 * not read the alpha channel, but will instead use the correct
4715 * implicit value for alpha.
4717 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4718 GL_TEXTURE_ALPHA_TYPE
)) {
4719 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4720 srcA
= brw_fix_xRGB_alpha(srcA
);
4721 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4722 dstA
= brw_fix_xRGB_alpha(dstA
);
4725 /* Alpha to One doesn't work with Dual Color Blending. Override
4726 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4728 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4729 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4730 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4731 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4732 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4735 pb
.ColorBufferBlendEnable
= true;
4736 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4737 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4738 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4739 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4741 pb
.IndependentAlphaBlendEnable
=
4742 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4747 static const struct brw_tracked_state
genX(ps_blend
) = {
4749 .mesa
= _NEW_BUFFERS
|
4752 .brw
= BRW_NEW_BLORP
|
4754 BRW_NEW_FRAGMENT_PROGRAM
,
4756 .emit
= genX(upload_ps_blend
)
4760 /* ---------------------------------------------------------------------- */
4764 genX(emit_vf_topology
)(struct brw_context
*brw
)
4766 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4767 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4771 static const struct brw_tracked_state
genX(vf_topology
) = {
4774 .brw
= BRW_NEW_BLORP
|
4777 .emit
= genX(emit_vf_topology
),
4781 /* ---------------------------------------------------------------------- */
4785 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4787 uint32_t offset_in_bytes
,
4790 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4791 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4792 mi_rpc
.ReportID
= report_id
;
4797 /* ---------------------------------------------------------------------- */
4800 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4803 genX(emit_sampler_state_pointers_xs
)(MAYBE_UNUSED
struct brw_context
*brw
,
4804 MAYBE_UNUSED
struct brw_stage_state
*stage_state
)
4807 static const uint16_t packet_headers
[] = {
4808 [MESA_SHADER_VERTEX
] = 43,
4809 [MESA_SHADER_TESS_CTRL
] = 44,
4810 [MESA_SHADER_TESS_EVAL
] = 45,
4811 [MESA_SHADER_GEOMETRY
] = 46,
4812 [MESA_SHADER_FRAGMENT
] = 47,
4815 /* Ivybridge requires a workaround flush before VS packets. */
4816 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4817 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4818 gen7_emit_vs_workaround_flush(brw
);
4821 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4822 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4823 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4829 has_component(mesa_format format
, int i
)
4831 if (_mesa_is_format_color_format(format
))
4832 return _mesa_format_has_color_component(format
, i
);
4834 /* depth and stencil have only one component */
4839 * Upload SAMPLER_BORDER_COLOR_STATE.
4842 genX(upload_default_color
)(struct brw_context
*brw
,
4843 const struct gl_sampler_object
*sampler
,
4844 MAYBE_UNUSED mesa_format format
, GLenum base_format
,
4845 bool is_integer_format
, bool is_stencil_sampling
,
4846 uint32_t *sdc_offset
)
4848 union gl_color_union color
;
4850 switch (base_format
) {
4851 case GL_DEPTH_COMPONENT
:
4852 /* GL specs that border color for depth textures is taken from the
4853 * R channel, while the hardware uses A. Spam R into all the
4854 * channels for safety.
4856 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4857 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4858 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4859 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4865 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4868 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4869 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4870 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4871 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4874 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4875 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4876 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4877 color
.ui
[3] = float_as_int(1.0);
4879 case GL_LUMINANCE_ALPHA
:
4880 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4881 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4882 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4883 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4886 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4887 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4888 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4889 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4893 /* In some cases we use an RGBA surface format for GL RGB textures,
4894 * where we've initialized the A channel to 1.0. We also have to set
4895 * the border color alpha to 1.0 in that case.
4897 if (base_format
== GL_RGB
)
4898 color
.ui
[3] = float_as_int(1.0);
4903 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4907 uint32_t *sdc
= brw_state_batch(
4908 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4909 alignment
, sdc_offset
);
4911 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4913 #define ASSIGN(dst, src) \
4918 #define ASSIGNu16(dst, src) \
4920 dst = (uint16_t)src; \
4923 #define ASSIGNu8(dst, src) \
4925 dst = (uint8_t)src; \
4928 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4929 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4930 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4931 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4932 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4935 /* On Broadwell, the border color is represented as four 32-bit floats,
4936 * integers, or unsigned values, interpreted according to the surface
4937 * format. This matches the sampler->BorderColor union exactly; just
4938 * memcpy the values.
4940 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4941 #elif GEN_IS_HASWELL
4942 if (is_integer_format
|| is_stencil_sampling
) {
4943 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4944 const int bits_per_channel
=
4945 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4947 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4948 * "If any color channel is missing from the surface format,
4949 * corresponding border color should be programmed as zero and if
4950 * alpha channel is missing, corresponding Alpha border color should
4951 * be programmed as 1."
4953 unsigned c
[4] = { 0, 0, 0, 1 };
4954 for (int i
= 0; i
< 4; i
++) {
4955 if (has_component(format
, i
))
4959 switch (bits_per_channel
) {
4961 /* Copy RGBA in order. */
4962 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4965 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4967 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4970 if (base_format
== GL_RG
) {
4971 /* Careful inspection of the tables reveals that for RG32 formats,
4972 * the green channel needs to go where blue normally belongs.
4974 state
.BorderColor32bitRed
= c
[0];
4975 state
.BorderColor32bitBlue
= c
[1];
4976 state
.BorderColor32bitAlpha
= 1;
4978 /* Copy RGBA in order. */
4979 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4983 assert(!"Invalid number of bits per channel in integer format.");
4987 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4989 #elif GEN_GEN == 5 || GEN_GEN == 6
4990 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4991 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4992 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4994 #define MESA_FLOAT_TO_HALF(dst, src) \
4995 dst = _mesa_float_to_half(src);
4997 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4999 #undef MESA_FLOAT_TO_HALF
5001 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
5002 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
5003 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
5004 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
5006 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5008 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
5010 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5014 #undef BORDER_COLOR_ATTR
5016 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
5020 translate_wrap_mode(GLenum wrap
, MAYBE_UNUSED
bool using_nearest
)
5027 /* GL_CLAMP is the weird mode where coordinates are clamped to
5028 * [0.0, 1.0], so linear filtering of coordinates outside of
5029 * [0.0, 1.0] give you half edge texel value and half border
5032 * Gen8+ supports this natively.
5034 return TCM_HALF_BORDER
;
5036 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
5037 * and set clamp_border here, which gets the result desired.
5038 * We just use clamp(_to_edge) for nearest, because for nearest
5039 * clamping to 1.0 gives border color instead of the desired
5045 return TCM_CLAMP_BORDER
;
5047 case GL_CLAMP_TO_EDGE
:
5049 case GL_CLAMP_TO_BORDER
:
5050 return TCM_CLAMP_BORDER
;
5051 case GL_MIRRORED_REPEAT
:
5053 case GL_MIRROR_CLAMP_TO_EDGE
:
5054 return TCM_MIRROR_ONCE
;
5061 * Return true if the given wrap mode requires the border color to exist.
5064 wrap_mode_needs_border_color(unsigned wrap_mode
)
5067 return wrap_mode
== TCM_CLAMP_BORDER
||
5068 wrap_mode
== TCM_HALF_BORDER
;
5070 return wrap_mode
== TCM_CLAMP_BORDER
;
5075 * Sets the sampler state for a single unit based off of the sampler key
5079 genX(update_sampler_state
)(struct brw_context
*brw
,
5080 GLenum target
, bool tex_cube_map_seamless
,
5081 GLfloat tex_unit_lod_bias
,
5082 mesa_format format
, GLenum base_format
,
5083 const struct gl_texture_object
*texObj
,
5084 const struct gl_sampler_object
*sampler
,
5085 uint32_t *sampler_state
)
5087 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
5089 /* Select min and mip filters. */
5090 switch (sampler
->MinFilter
) {
5092 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5093 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5096 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5097 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5099 case GL_NEAREST_MIPMAP_NEAREST
:
5100 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5101 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5103 case GL_LINEAR_MIPMAP_NEAREST
:
5104 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5105 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5107 case GL_NEAREST_MIPMAP_LINEAR
:
5108 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5109 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5111 case GL_LINEAR_MIPMAP_LINEAR
:
5112 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5113 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5116 unreachable("not reached");
5119 /* Select mag filter. */
5120 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5121 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5123 /* Enable anisotropic filtering if desired. */
5124 samp_st
.MaximumAnisotropy
= RATIO21
;
5126 if (sampler
->MaxAnisotropy
> 1.0f
) {
5127 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5128 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5129 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5130 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5132 if (sampler
->MaxAnisotropy
> 2.0f
) {
5133 samp_st
.MaximumAnisotropy
=
5134 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5138 /* Set address rounding bits if not using nearest filtering. */
5139 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5140 samp_st
.UAddressMinFilterRoundingEnable
= true;
5141 samp_st
.VAddressMinFilterRoundingEnable
= true;
5142 samp_st
.RAddressMinFilterRoundingEnable
= true;
5145 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5146 samp_st
.UAddressMagFilterRoundingEnable
= true;
5147 samp_st
.VAddressMagFilterRoundingEnable
= true;
5148 samp_st
.RAddressMagFilterRoundingEnable
= true;
5151 bool either_nearest
=
5152 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5153 unsigned wrap_s
= translate_wrap_mode(sampler
->WrapS
, either_nearest
);
5154 unsigned wrap_t
= translate_wrap_mode(sampler
->WrapT
, either_nearest
);
5155 unsigned wrap_r
= translate_wrap_mode(sampler
->WrapR
, either_nearest
);
5157 if (target
== GL_TEXTURE_CUBE_MAP
||
5158 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5159 /* Cube maps must use the same wrap mode for all three coordinate
5160 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5162 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5163 * integer formats. Fall back to CLAMP for now.
5165 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5166 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5175 } else if (target
== GL_TEXTURE_1D
) {
5176 /* There's a bug in 1D texture sampling - it actually pays
5177 * attention to the wrap_t value, though it should not.
5178 * Override the wrap_t value here to GL_REPEAT to keep
5179 * any nonexistent border pixels from floating in.
5184 samp_st
.TCXAddressControlMode
= wrap_s
;
5185 samp_st
.TCYAddressControlMode
= wrap_t
;
5186 samp_st
.TCZAddressControlMode
= wrap_r
;
5188 samp_st
.ShadowFunction
=
5189 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5190 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5193 /* Set shadow function. */
5194 samp_st
.AnisotropicAlgorithm
=
5195 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5196 EWAApproximation
: LEGACY
;
5200 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5203 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5204 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5205 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5206 samp_st
.TextureLODBias
=
5207 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5210 samp_st
.BaseMipLevel
=
5211 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5212 samp_st
.MinandMagStateNotEqual
=
5213 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5216 /* Upload the border color if necessary. If not, just point it at
5217 * offset 0 (the start of the batch) - the color should be ignored,
5218 * but that address won't fault in case something reads it anyway.
5220 uint32_t border_color_offset
= 0;
5221 if (wrap_mode_needs_border_color(wrap_s
) ||
5222 wrap_mode_needs_border_color(wrap_t
) ||
5223 wrap_mode_needs_border_color(wrap_r
)) {
5224 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5225 texObj
->_IsIntegerFormat
,
5226 texObj
->StencilSampling
,
5227 &border_color_offset
);
5230 samp_st
.BorderColorPointer
=
5231 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5233 samp_st
.BorderColorPointer
= border_color_offset
;
5237 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5239 samp_st
.LODPreClampEnable
= true;
5242 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5246 update_sampler_state(struct brw_context
*brw
,
5248 uint32_t *sampler_state
)
5250 struct gl_context
*ctx
= &brw
->ctx
;
5251 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5252 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5253 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5255 /* These don't use samplers at all. */
5256 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5259 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5260 genX(update_sampler_state
)(brw
, texObj
->Target
,
5261 ctx
->Texture
.CubeMapSeamless
,
5263 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5269 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5270 struct gl_program
*prog
,
5271 struct brw_stage_state
*stage_state
)
5273 struct gl_context
*ctx
= &brw
->ctx
;
5274 uint32_t sampler_count
= stage_state
->sampler_count
;
5276 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5278 if (sampler_count
== 0)
5281 /* SAMPLER_STATE is 4 DWords on all platforms. */
5282 const int dwords
= GENX(SAMPLER_STATE_length
);
5283 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5285 uint32_t *sampler_state
= brw_state_batch(brw
,
5286 sampler_count
* size_in_bytes
,
5287 32, &stage_state
->sampler_offset
);
5288 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5290 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5291 if (SamplersUsed
& (1 << s
)) {
5292 const unsigned unit
= prog
->SamplerUnits
[s
];
5293 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5294 update_sampler_state(brw
, unit
, sampler_state
);
5298 sampler_state
+= dwords
;
5301 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5302 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5303 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5305 /* Flag that the sampler state table pointer has changed; later atoms
5308 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5313 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5315 /* BRW_NEW_FRAGMENT_PROGRAM */
5316 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5317 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5320 static const struct brw_tracked_state
genX(fs_samplers
) = {
5322 .mesa
= _NEW_TEXTURE
,
5323 .brw
= BRW_NEW_BATCH
|
5325 BRW_NEW_FRAGMENT_PROGRAM
,
5327 .emit
= genX(upload_fs_samplers
),
5331 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5333 /* BRW_NEW_VERTEX_PROGRAM */
5334 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5335 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5338 static const struct brw_tracked_state
genX(vs_samplers
) = {
5340 .mesa
= _NEW_TEXTURE
,
5341 .brw
= BRW_NEW_BATCH
|
5343 BRW_NEW_VERTEX_PROGRAM
,
5345 .emit
= genX(upload_vs_samplers
),
5350 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5352 /* BRW_NEW_GEOMETRY_PROGRAM */
5353 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5357 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5361 static const struct brw_tracked_state
genX(gs_samplers
) = {
5363 .mesa
= _NEW_TEXTURE
,
5364 .brw
= BRW_NEW_BATCH
|
5366 BRW_NEW_GEOMETRY_PROGRAM
,
5368 .emit
= genX(upload_gs_samplers
),
5374 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5376 /* BRW_NEW_TESS_PROGRAMS */
5377 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5381 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5384 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5386 .mesa
= _NEW_TEXTURE
,
5387 .brw
= BRW_NEW_BATCH
|
5389 BRW_NEW_TESS_PROGRAMS
,
5391 .emit
= genX(upload_tcs_samplers
),
5397 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5399 /* BRW_NEW_TESS_PROGRAMS */
5400 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5404 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5407 static const struct brw_tracked_state
genX(tes_samplers
) = {
5409 .mesa
= _NEW_TEXTURE
,
5410 .brw
= BRW_NEW_BATCH
|
5412 BRW_NEW_TESS_PROGRAMS
,
5414 .emit
= genX(upload_tes_samplers
),
5420 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5422 /* BRW_NEW_COMPUTE_PROGRAM */
5423 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5427 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5430 const struct brw_tracked_state
genX(cs_samplers
) = {
5432 .mesa
= _NEW_TEXTURE
,
5433 .brw
= BRW_NEW_BATCH
|
5435 BRW_NEW_COMPUTE_PROGRAM
,
5437 .emit
= genX(upload_cs_samplers
),
5441 /* ---------------------------------------------------------------------- */
5445 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5447 struct gl_context
*ctx
= &brw
->ctx
;
5449 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5450 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5451 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5452 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5453 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5457 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5460 .brw
= BRW_NEW_CONTEXT
|
5463 .emit
= genX(upload_blend_constant_color
)
5467 /* ---------------------------------------------------------------------- */
5470 genX(init_atoms
)(struct brw_context
*brw
)
5473 static const struct brw_tracked_state
*render_atoms
[] =
5475 /* Once all the programs are done, we know how large urb entry
5476 * sizes need to be and can decide if we need to change the urb
5480 &brw_recalculate_urb_fence
,
5483 &genX(color_calc_state
),
5485 /* Surface state setup. Must come before the VS/WM unit. The binding
5486 * table upload must be last.
5488 &brw_vs_pull_constants
,
5489 &brw_wm_pull_constants
,
5490 &brw_renderbuffer_surfaces
,
5491 &brw_renderbuffer_read_surfaces
,
5492 &brw_texture_surfaces
,
5493 &brw_vs_binding_table
,
5494 &brw_wm_binding_table
,
5499 /* These set up state for brw_psp_urb_cbs */
5501 &genX(sf_clip_viewport
),
5503 &genX(vs_state
), /* always required, enabled or not */
5509 &brw_binding_table_pointers
,
5510 &genX(blend_constant_color
),
5514 &genX(polygon_stipple
),
5515 &genX(polygon_stipple_offset
),
5517 &genX(line_stipple
),
5521 &genX(drawing_rect
),
5522 &brw_indices
, /* must come before brw_vertices */
5523 &genX(index_buffer
),
5526 &brw_constant_buffer
5529 static const struct brw_tracked_state
*render_atoms
[] =
5531 &genX(sf_clip_viewport
),
5533 /* Command packets: */
5538 &genX(blend_state
), /* must do before cc unit */
5539 &genX(color_calc_state
), /* must do before cc unit */
5540 &genX(depth_stencil_state
), /* must do before cc unit */
5542 &genX(vs_push_constants
), /* Before vs_state */
5543 &genX(gs_push_constants
), /* Before gs_state */
5544 &genX(wm_push_constants
), /* Before wm_state */
5546 /* Surface state setup. Must come before the VS/WM unit. The binding
5547 * table upload must be last.
5549 &brw_vs_pull_constants
,
5550 &brw_vs_ubo_surfaces
,
5551 &brw_gs_pull_constants
,
5552 &brw_gs_ubo_surfaces
,
5553 &brw_wm_pull_constants
,
5554 &brw_wm_ubo_surfaces
,
5555 &gen6_renderbuffer_surfaces
,
5556 &brw_renderbuffer_read_surfaces
,
5557 &brw_texture_surfaces
,
5559 &brw_vs_binding_table
,
5560 &gen6_gs_binding_table
,
5561 &brw_wm_binding_table
,
5566 &gen6_sampler_state
,
5567 &genX(multisample_state
),
5575 &genX(scissor_state
),
5577 &gen6_binding_table_pointers
,
5581 &genX(polygon_stipple
),
5582 &genX(polygon_stipple_offset
),
5584 &genX(line_stipple
),
5586 &genX(drawing_rect
),
5588 &brw_indices
, /* must come before brw_vertices */
5589 &genX(index_buffer
),
5593 static const struct brw_tracked_state
*render_atoms
[] =
5595 /* Command packets: */
5598 &genX(sf_clip_viewport
),
5601 &gen7_push_constant_space
,
5603 &genX(blend_state
), /* must do before cc unit */
5604 &genX(color_calc_state
), /* must do before cc unit */
5605 &genX(depth_stencil_state
), /* must do before cc unit */
5607 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5608 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5609 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5610 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5611 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5613 &genX(vs_push_constants
), /* Before vs_state */
5614 &genX(tcs_push_constants
),
5615 &genX(tes_push_constants
),
5616 &genX(gs_push_constants
), /* Before gs_state */
5617 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5619 /* Surface state setup. Must come before the VS/WM unit. The binding
5620 * table upload must be last.
5622 &brw_vs_pull_constants
,
5623 &brw_vs_ubo_surfaces
,
5624 &brw_tcs_pull_constants
,
5625 &brw_tcs_ubo_surfaces
,
5626 &brw_tes_pull_constants
,
5627 &brw_tes_ubo_surfaces
,
5628 &brw_gs_pull_constants
,
5629 &brw_gs_ubo_surfaces
,
5630 &brw_wm_pull_constants
,
5631 &brw_wm_ubo_surfaces
,
5632 &gen6_renderbuffer_surfaces
,
5633 &brw_renderbuffer_read_surfaces
,
5634 &brw_texture_surfaces
,
5636 &genX(push_constant_packets
),
5638 &brw_vs_binding_table
,
5639 &brw_tcs_binding_table
,
5640 &brw_tes_binding_table
,
5641 &brw_gs_binding_table
,
5642 &brw_wm_binding_table
,
5646 &genX(tcs_samplers
),
5647 &genX(tes_samplers
),
5649 &genX(multisample_state
),
5663 &genX(scissor_state
),
5667 &genX(polygon_stipple
),
5668 &genX(polygon_stipple_offset
),
5670 &genX(line_stipple
),
5672 &genX(drawing_rect
),
5674 &brw_indices
, /* must come before brw_vertices */
5675 &genX(index_buffer
),
5683 static const struct brw_tracked_state
*render_atoms
[] =
5686 &genX(sf_clip_viewport
),
5689 &gen7_push_constant_space
,
5692 &genX(color_calc_state
),
5694 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5695 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5696 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5697 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5698 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5700 &genX(vs_push_constants
), /* Before vs_state */
5701 &genX(tcs_push_constants
),
5702 &genX(tes_push_constants
),
5703 &genX(gs_push_constants
), /* Before gs_state */
5704 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5706 /* Surface state setup. Must come before the VS/WM unit. The binding
5707 * table upload must be last.
5709 &brw_vs_pull_constants
,
5710 &brw_vs_ubo_surfaces
,
5711 &brw_tcs_pull_constants
,
5712 &brw_tcs_ubo_surfaces
,
5713 &brw_tes_pull_constants
,
5714 &brw_tes_ubo_surfaces
,
5715 &brw_gs_pull_constants
,
5716 &brw_gs_ubo_surfaces
,
5717 &brw_wm_pull_constants
,
5718 &brw_wm_ubo_surfaces
,
5719 &gen6_renderbuffer_surfaces
,
5720 &brw_renderbuffer_read_surfaces
,
5721 &brw_texture_surfaces
,
5723 &genX(push_constant_packets
),
5725 &brw_vs_binding_table
,
5726 &brw_tcs_binding_table
,
5727 &brw_tes_binding_table
,
5728 &brw_gs_binding_table
,
5729 &brw_wm_binding_table
,
5733 &genX(tcs_samplers
),
5734 &genX(tes_samplers
),
5736 &genX(multisample_state
),
5745 &genX(raster_state
),
5751 &genX(depth_stencil_state
),
5754 &genX(scissor_state
),
5758 &genX(polygon_stipple
),
5759 &genX(polygon_stipple_offset
),
5761 &genX(line_stipple
),
5763 &genX(drawing_rect
),
5768 &genX(index_buffer
),
5776 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5777 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5778 render_atoms
, ARRAY_SIZE(render_atoms
));
5781 static const struct brw_tracked_state
*compute_atoms
[] =
5784 &brw_cs_image_surfaces
,
5785 &genX(cs_push_constants
),
5786 &genX(cs_pull_constants
),
5787 &brw_cs_ubo_surfaces
,
5788 &brw_cs_texture_surfaces
,
5789 &brw_cs_work_groups_surface
,
5794 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5795 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5796 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5798 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);