2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "dev/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "genX_boilerplate.h"
38 #include "brw_context.h"
40 #include "brw_multisample_state.h"
41 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
46 #include "intel_buffer_objects.h"
47 #include "intel_fbo.h"
49 #include "main/enums.h"
50 #include "main/fbobject.h"
51 #include "main/framebuffer.h"
52 #include "main/glformats.h"
53 #include "main/samplerobj.h"
54 #include "main/shaderapi.h"
55 #include "main/stencil.h"
56 #include "main/transformfeedback.h"
57 #include "main/varray.h"
58 #include "main/viewport.h"
59 #include "util/half_float.h"
62 static struct brw_address
63 KSP(struct brw_context
*brw
, uint32_t offset
)
65 return ro_bo(brw
->cache
.bo
, offset
);
69 KSP(UNUSED
struct brw_context
*brw
, uint32_t offset
)
76 MAYBE_UNUSED
static void
77 emit_lrm(struct brw_context
*brw
, uint32_t reg
, struct brw_address addr
)
79 brw_batch_emit(brw
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
80 lrm
.RegisterAddress
= reg
;
81 lrm
.MemoryAddress
= addr
;
86 MAYBE_UNUSED
static void
87 emit_lri(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
89 brw_batch_emit(brw
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
90 lri
.RegisterOffset
= reg
;
95 #if GEN_IS_HASWELL || GEN_GEN >= 8
96 MAYBE_UNUSED
static void
97 emit_lrr(struct brw_context
*brw
, uint32_t dst
, uint32_t src
)
99 brw_batch_emit(brw
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
100 lrr
.SourceRegisterAddress
= src
;
101 lrr
.DestinationRegisterAddress
= dst
;
107 * Polygon stipple packet
110 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
112 struct gl_context
*ctx
= &brw
->ctx
;
115 if (!ctx
->Polygon
.StippleFlag
)
118 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
119 /* Polygon stipple is provided in OpenGL order, i.e. bottom
120 * row first. If we're rendering to a window (i.e. the
121 * default frame buffer object, 0), then we need to invert
122 * it to match our pixel layout. But if we're rendering
123 * to a FBO (i.e. any named frame buffer object), we *don't*
124 * need to invert - we already match the layout.
126 if (ctx
->DrawBuffer
->FlipY
) {
127 for (unsigned i
= 0; i
< 32; i
++)
128 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
130 for (unsigned i
= 0; i
< 32; i
++)
131 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
136 static const struct brw_tracked_state
genX(polygon_stipple
) = {
138 .mesa
= _NEW_POLYGON
|
140 .brw
= BRW_NEW_CONTEXT
,
142 .emit
= genX(upload_polygon_stipple
),
146 * Polygon stipple offset packet
149 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
151 struct gl_context
*ctx
= &brw
->ctx
;
154 if (!ctx
->Polygon
.StippleFlag
)
157 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
160 * If we're drawing to a system window we have to invert the Y axis
161 * in order to match the OpenGL pixel coordinate system, and our
162 * offset must be matched to the window position. If we're drawing
163 * to a user-created FBO then our native pixel coordinate system
164 * works just fine, and there's no window system to worry about.
166 if (ctx
->DrawBuffer
->FlipY
) {
167 poly
.PolygonStippleYOffset
=
168 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
173 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
175 .mesa
= _NEW_BUFFERS
|
177 .brw
= BRW_NEW_CONTEXT
,
179 .emit
= genX(upload_polygon_stipple_offset
),
183 * Line stipple packet
186 genX(upload_line_stipple
)(struct brw_context
*brw
)
188 struct gl_context
*ctx
= &brw
->ctx
;
190 if (!ctx
->Line
.StippleFlag
)
193 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
194 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
196 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
197 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
201 static const struct brw_tracked_state
genX(line_stipple
) = {
204 .brw
= BRW_NEW_CONTEXT
,
206 .emit
= genX(upload_line_stipple
),
209 /* Constant single cliprect for framebuffer object or DRI2 drawing */
211 genX(upload_drawing_rect
)(struct brw_context
*brw
)
213 struct gl_context
*ctx
= &brw
->ctx
;
214 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
215 const unsigned int fb_width
= _mesa_geometric_width(fb
);
216 const unsigned int fb_height
= _mesa_geometric_height(fb
);
218 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
219 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
220 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
224 static const struct brw_tracked_state
genX(drawing_rect
) = {
226 .mesa
= _NEW_BUFFERS
,
227 .brw
= BRW_NEW_BLORP
|
230 .emit
= genX(upload_drawing_rect
),
234 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
238 unsigned start_offset
,
239 MAYBE_UNUSED
unsigned end_offset
,
241 MAYBE_UNUSED
unsigned step_rate
)
243 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
244 .VertexBufferIndex
= buffer_nr
,
245 .BufferPitch
= stride
,
247 /* The VF cache designers apparently cut corners, and made the cache
248 * only consider the bottom 32 bits of memory addresses. If you happen
249 * to have two vertex buffers which get placed exactly 4 GiB apart and
250 * use them in back-to-back draw calls, you can get collisions. To work
251 * around this problem, we restrict vertex buffers to the low 32 bits of
254 .BufferStartingAddress
= ro_32_bo(bo
, start_offset
),
256 .BufferSize
= end_offset
- start_offset
,
260 .AddressModifyEnable
= true,
264 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
265 .InstanceDataStepRate
= step_rate
,
267 .EndAddress
= ro_bo(bo
, end_offset
- 1),
280 .MOCS
= GEN7_MOCS_L3
,
284 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
285 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
289 is_passthru_format(uint32_t format
)
292 case ISL_FORMAT_R64_PASSTHRU
:
293 case ISL_FORMAT_R64G64_PASSTHRU
:
294 case ISL_FORMAT_R64G64B64_PASSTHRU
:
295 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
303 uploads_needed(uint32_t format
,
306 if (!is_passthru_format(format
))
313 case ISL_FORMAT_R64_PASSTHRU
:
314 case ISL_FORMAT_R64G64_PASSTHRU
:
316 case ISL_FORMAT_R64G64B64_PASSTHRU
:
317 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
320 unreachable("not reached");
325 * Returns the format that we are finally going to use when upload a vertex
326 * element. It will only change if we are using *64*PASSTHRU formats, as for
327 * gen < 8 they need to be splitted on two *32*FLOAT formats.
329 * @upload points in which upload we are. Valid values are [0,1]
332 downsize_format_if_needed(uint32_t format
,
335 assert(upload
== 0 || upload
== 1);
337 if (!is_passthru_format(format
))
340 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
341 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
342 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
343 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
344 * flagging that we want to fill with zeroes this second forced upload.
347 case ISL_FORMAT_R64_PASSTHRU
:
348 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
349 : ISL_FORMAT_R32_FLOAT
;
350 case ISL_FORMAT_R64G64_PASSTHRU
:
351 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
352 : ISL_FORMAT_R32_FLOAT
;
353 case ISL_FORMAT_R64G64B64_PASSTHRU
:
354 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
355 : ISL_FORMAT_R32G32_FLOAT
;
356 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
357 return ISL_FORMAT_R32G32B32A32_FLOAT
;
359 unreachable("not reached");
364 * Returns the number of componentes associated with a format that is used on
365 * a 64 to 32 format split. See downsize_format()
368 upload_format_size(uint32_t upload_format
)
370 switch (upload_format
) {
371 case ISL_FORMAT_R32_FLOAT
:
373 /* downsized_format has returned this one in order to flag that we are
374 * performing a second upload which we want to have filled with
375 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
376 * vertex shader input variables.
380 case ISL_FORMAT_R32G32_FLOAT
:
382 case ISL_FORMAT_R32G32B32A32_FLOAT
:
385 unreachable("not reached");
389 static UNUSED
uint16_t
390 pinned_bo_high_bits(struct brw_bo
*bo
)
392 return (bo
->kflags
& EXEC_OBJECT_PINNED
) ? bo
->gtt_offset
>> 32ull : 0;
395 /* The VF cache designers apparently cut corners, and made the cache key's
396 * <VertexBufferIndex, Memory Address> tuple only consider the bottom 32 bits
397 * of the address. If you happen to have two vertex buffers which get placed
398 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
399 * collisions. (These collisions can happen within a single batch.)
401 * In the soft-pin world, we'd like to assign addresses up front, and never
402 * move buffers. So, we need to do a VF cache invalidate if the buffer for
403 * a particular VB slot has different [48:32] address bits than the last one.
405 * In the relocation world, we have no idea what the addresses will be, so
406 * we can't apply this workaround. Instead, we tell the kernel to move it
407 * to the low 4GB regardless.
409 * This HW issue is gone on Gen11+.
412 vf_invalidate_for_vb_48bit_transitions(struct brw_context
*brw
)
414 #if GEN_GEN >= 8 && GEN_GEN < 11
415 bool need_invalidate
= false;
417 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
418 uint16_t high_bits
= pinned_bo_high_bits(brw
->vb
.buffers
[i
].bo
);
420 if (high_bits
!= brw
->vb
.last_bo_high_bits
[i
]) {
421 need_invalidate
= true;
422 brw
->vb
.last_bo_high_bits
[i
] = high_bits
;
426 if (brw
->draw
.draw_params_bo
) {
427 uint16_t high_bits
= pinned_bo_high_bits(brw
->draw
.draw_params_bo
);
429 if (brw
->vb
.last_bo_high_bits
[brw
->vb
.nr_buffers
] != high_bits
) {
430 need_invalidate
= true;
431 brw
->vb
.last_bo_high_bits
[brw
->vb
.nr_buffers
] = high_bits
;
435 if (brw
->draw
.derived_draw_params_bo
) {
436 uint16_t high_bits
= pinned_bo_high_bits(brw
->draw
.derived_draw_params_bo
);
438 if (brw
->vb
.last_bo_high_bits
[brw
->vb
.nr_buffers
+ 1] != high_bits
) {
439 need_invalidate
= true;
440 brw
->vb
.last_bo_high_bits
[brw
->vb
.nr_buffers
+ 1] = high_bits
;
444 if (need_invalidate
) {
445 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_VF_CACHE_INVALIDATE
| PIPE_CONTROL_CS_STALL
);
451 vf_invalidate_for_ib_48bit_transition(struct brw_context
*brw
)
454 uint16_t high_bits
= pinned_bo_high_bits(brw
->ib
.bo
);
456 if (high_bits
!= brw
->ib
.last_bo_high_bits
) {
457 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
458 brw
->ib
.last_bo_high_bits
= high_bits
;
464 genX(emit_vertices
)(struct brw_context
*brw
)
466 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
469 brw_prepare_vertices(brw
);
470 brw_prepare_shader_draw_parameters(brw
);
473 brw_emit_query_begin(brw
);
476 const struct brw_vs_prog_data
*vs_prog_data
=
477 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
480 struct gl_context
*ctx
= &brw
->ctx
;
481 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
482 ctx
->Polygon
.BackMode
!= GL_FILL
);
484 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
485 unsigned vue
= brw
->vb
.nr_enabled
;
487 /* The element for the edge flags must always be last, so we have to
488 * insert the SGVS before it in that case.
490 if (uses_edge_flag
) {
496 "Trying to insert VID/IID past 33rd vertex element, "
497 "need to reorder the vertex attrbutes.");
499 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
500 if (vs_prog_data
->uses_vertexid
) {
501 vfs
.VertexIDEnable
= true;
502 vfs
.VertexIDComponentNumber
= 2;
503 vfs
.VertexIDElementOffset
= vue
;
506 if (vs_prog_data
->uses_instanceid
) {
507 vfs
.InstanceIDEnable
= true;
508 vfs
.InstanceIDComponentNumber
= 3;
509 vfs
.InstanceIDElementOffset
= vue
;
513 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
514 vfi
.InstancingEnable
= true;
515 vfi
.VertexElementIndex
= vue
;
518 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
522 const bool uses_draw_params
=
523 vs_prog_data
->uses_firstvertex
||
524 vs_prog_data
->uses_baseinstance
;
526 const bool uses_derived_draw_params
=
527 vs_prog_data
->uses_drawid
||
528 vs_prog_data
->uses_is_indexed_draw
;
530 const bool needs_sgvs_element
= (uses_draw_params
||
531 vs_prog_data
->uses_instanceid
||
532 vs_prog_data
->uses_vertexid
);
534 unsigned nr_elements
=
535 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ uses_derived_draw_params
;
538 /* If any of the formats of vb.enabled needs more that one upload, we need
539 * to add it to nr_elements
541 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
542 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
543 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
544 uint32_t format
= brw_get_vertex_surface_type(brw
, &glattrib
->Format
);
546 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
551 /* If the VS doesn't read any inputs (calculating vertex position from
552 * a state variable for some reason, for example), emit a single pad
553 * VERTEX_ELEMENT struct and bail.
555 * The stale VB state stays in place, but they don't do anything unless
556 * a VE loads from them.
558 if (nr_elements
== 0) {
559 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
560 1 + GENX(VERTEX_ELEMENT_STATE_length
));
561 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
563 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
564 .Component0Control
= VFCOMP_STORE_0
,
565 .Component1Control
= VFCOMP_STORE_0
,
566 .Component2Control
= VFCOMP_STORE_0
,
567 .Component3Control
= VFCOMP_STORE_1_FP
,
569 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
573 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
574 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
575 uses_draw_params
+ uses_derived_draw_params
;
577 vf_invalidate_for_vb_48bit_transitions(brw
);
580 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
582 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
583 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
585 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
586 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
587 /* Prior to Haswell and Bay Trail we have to use 4-component formats
588 * to fake 3-component ones. In particular, we do this for
589 * half-float and 8 and 16-bit integer formats. This means that the
590 * vertex element may poke over the end of the buffer by 2 bytes.
592 const unsigned padding
=
593 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
594 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
595 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
602 if (uses_draw_params
) {
603 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
604 brw
->draw
.draw_params_bo
,
605 brw
->draw
.draw_params_offset
,
606 brw
->draw
.draw_params_bo
->size
,
611 if (uses_derived_draw_params
) {
612 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
613 brw
->draw
.derived_draw_params_bo
,
614 brw
->draw
.derived_draw_params_offset
,
615 brw
->draw
.derived_draw_params_bo
->size
,
621 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
622 * presumably for VertexID/InstanceID.
625 assert(nr_elements
<= 34);
626 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
628 assert(nr_elements
<= 18);
631 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
632 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
634 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
635 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
636 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
637 uint32_t format
= brw_get_vertex_surface_type(brw
, &glattrib
->Format
);
638 uint32_t comp0
= VFCOMP_STORE_SRC
;
639 uint32_t comp1
= VFCOMP_STORE_SRC
;
640 uint32_t comp2
= VFCOMP_STORE_SRC
;
641 uint32_t comp3
= VFCOMP_STORE_SRC
;
642 const unsigned num_uploads
= GEN_GEN
< 8 ?
643 uploads_needed(format
, input
->is_dual_slot
) : 1;
646 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
647 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
648 * element which has edge flag enabled."
650 assert(!(is_passthru_format(format
) && uses_edge_flag
));
653 /* The gen4 driver expects edgeflag to come in as a float, and passes
654 * that float on to the tests in the clipper. Mesa's current vertex
655 * attribute value for EdgeFlag is stored as a float, which works out.
656 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
657 * integer ubyte. Just rewrite that to convert to a float.
659 * Gen6+ passes edgeflag as sideband along with the vertex, instead
660 * of in the VUE. We have to upload it sideband as the last vertex
661 * element according to the B-Spec.
664 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
665 gen6_edgeflag_input
= input
;
670 for (unsigned c
= 0; c
< num_uploads
; c
++) {
671 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
672 downsize_format_if_needed(format
, c
);
673 /* If we need more that one upload, the offset stride would be 128
674 * bits (16 bytes), as for previous uploads we are using the full
676 const unsigned offset
= input
->offset
+ c
* 16;
678 const struct gl_array_attributes
*glattrib
= input
->glattrib
;
679 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
680 upload_format_size(upload_format
) : glattrib
->Format
.Size
;
683 case 0: comp0
= VFCOMP_STORE_0
;
684 case 1: comp1
= VFCOMP_STORE_0
;
685 case 2: comp2
= VFCOMP_STORE_0
;
687 if (GEN_GEN
>= 8 && glattrib
->Format
.Doubles
) {
688 comp3
= VFCOMP_STORE_0
;
689 } else if (glattrib
->Format
.Integer
) {
690 comp3
= VFCOMP_STORE_1_INT
;
692 comp3
= VFCOMP_STORE_1_FP
;
699 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
701 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
702 * formats, 64-bit components are stored in the URB without any
703 * conversion. In this case, vertex elements must be written as 128
704 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
705 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
706 * component into the URB, Component 1 must be specified as
707 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
708 * order to output a 128-bit vertex element, or Components 1-3 must
709 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
710 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
711 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
714 if (glattrib
->Format
.Doubles
&& !input
->is_dual_slot
) {
715 /* Store vertex elements which correspond to double and dvec2 vertex
716 * shader inputs as 128-bit vertex elements, instead of 256-bits.
718 comp2
= VFCOMP_NOSTORE
;
719 comp3
= VFCOMP_NOSTORE
;
723 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
724 .VertexBufferIndex
= input
->buffer
,
726 .SourceElementFormat
= upload_format
,
727 .SourceElementOffset
= offset
,
728 .Component0Control
= comp0
,
729 .Component1Control
= comp1
,
730 .Component2Control
= comp2
,
731 .Component3Control
= comp3
,
733 .DestinationElementOffset
= i
* 4,
737 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
738 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
742 if (needs_sgvs_element
) {
743 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
745 .Component0Control
= VFCOMP_STORE_0
,
746 .Component1Control
= VFCOMP_STORE_0
,
747 .Component2Control
= VFCOMP_STORE_0
,
748 .Component3Control
= VFCOMP_STORE_0
,
750 .DestinationElementOffset
= i
* 4,
755 if (uses_draw_params
) {
756 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
757 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
758 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
759 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
762 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
763 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
764 if (uses_draw_params
) {
765 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
766 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
769 if (vs_prog_data
->uses_vertexid
)
770 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
772 if (vs_prog_data
->uses_instanceid
)
773 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
776 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
777 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
780 if (uses_derived_draw_params
) {
781 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
783 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
784 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
785 .Component0Control
= VFCOMP_STORE_SRC
,
786 .Component1Control
= VFCOMP_STORE_SRC
,
787 .Component2Control
= VFCOMP_STORE_0
,
788 .Component3Control
= VFCOMP_STORE_0
,
790 .DestinationElementOffset
= i
* 4,
794 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
795 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
799 if (gen6_edgeflag_input
) {
800 const struct gl_array_attributes
*glattrib
= gen6_edgeflag_input
->glattrib
;
801 const uint32_t format
= brw_get_vertex_surface_type(brw
, &glattrib
->Format
);
803 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
805 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
806 .EdgeFlagEnable
= true,
807 .SourceElementFormat
= format
,
808 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
809 .Component0Control
= VFCOMP_STORE_SRC
,
810 .Component1Control
= VFCOMP_STORE_0
,
811 .Component2Control
= VFCOMP_STORE_0
,
812 .Component3Control
= VFCOMP_STORE_0
,
815 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
816 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
821 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
822 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
823 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
824 unsigned element_index
;
826 /* The edge flag element is reordered to be the last one in the code
827 * above so we need to compensate for that in the element indices used
830 if (input
== gen6_edgeflag_input
)
831 element_index
= nr_elements
- 1;
835 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
836 vfi
.VertexElementIndex
= element_index
;
837 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
838 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
842 if (vs_prog_data
->uses_drawid
) {
843 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
845 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
846 vfi
.VertexElementIndex
= element
;
852 static const struct brw_tracked_state
genX(vertices
) = {
854 .mesa
= _NEW_POLYGON
,
855 .brw
= BRW_NEW_BATCH
|
857 BRW_NEW_VERTEX_PROGRAM
|
859 BRW_NEW_VS_PROG_DATA
,
861 .emit
= genX(emit_vertices
),
865 genX(emit_index_buffer
)(struct brw_context
*brw
)
867 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
869 if (index_buffer
== NULL
)
872 vf_invalidate_for_ib_48bit_transition(brw
);
874 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
875 #if GEN_GEN < 8 && !GEN_IS_HASWELL
876 assert(brw
->ib
.enable_cut_index
== brw
->prim_restart
.enable_cut_index
);
877 ib
.CutIndexEnable
= brw
->ib
.enable_cut_index
;
879 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
881 /* The VF cache designers apparently cut corners, and made the cache
882 * only consider the bottom 32 bits of memory addresses. If you happen
883 * to have two index buffers which get placed exactly 4 GiB apart and
884 * use them in back-to-back draw calls, you can get collisions. To work
885 * around this problem, we restrict index buffers to the low 32 bits of
888 ib
.BufferStartingAddress
= ro_32_bo(brw
->ib
.bo
, 0);
890 ib
.MOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
891 ib
.BufferSize
= brw
->ib
.size
;
893 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
898 static const struct brw_tracked_state
genX(index_buffer
) = {
901 .brw
= BRW_NEW_BATCH
|
903 BRW_NEW_INDEX_BUFFER
,
905 .emit
= genX(emit_index_buffer
),
908 #if GEN_IS_HASWELL || GEN_GEN >= 8
910 genX(upload_cut_index
)(struct brw_context
*brw
)
912 const struct gl_context
*ctx
= &brw
->ctx
;
914 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
915 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
916 vf
.IndexedDrawCutIndexEnable
= true;
917 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
922 const struct brw_tracked_state
genX(cut_index
) = {
924 .mesa
= _NEW_TRANSFORM
,
925 .brw
= BRW_NEW_INDEX_BUFFER
,
927 .emit
= genX(upload_cut_index
),
932 genX(upload_vf_statistics
)(struct brw_context
*brw
)
934 brw_batch_emit(brw
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
935 vf
.StatisticsEnable
= true;
939 const struct brw_tracked_state
genX(vf_statistics
) = {
942 .brw
= BRW_NEW_BLORP
| BRW_NEW_CONTEXT
,
944 .emit
= genX(upload_vf_statistics
),
949 * Determine the appropriate attribute override value to store into the
950 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
951 * override value contains two pieces of information: the location of the
952 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
953 * flag indicating whether to "swizzle" the attribute based on the direction
954 * the triangle is facing.
956 * If an attribute is "swizzled", then the given VUE location is used for
957 * front-facing triangles, and the VUE location that immediately follows is
958 * used for back-facing triangles. We use this to implement the mapping from
959 * gl_FrontColor/gl_BackColor to gl_Color.
961 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
962 * being instructed to begin reading attribute data. It can be set to a
963 * nonzero value to prevent the SF unit from wasting time reading elements of
964 * the VUE that are not needed by the fragment shader. It is measured in
965 * 256-bit increments.
968 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
969 const struct brw_vue_map
*vue_map
,
970 int urb_entry_read_offset
, int fs_attr
,
971 bool two_side_color
, uint32_t *max_source_attr
)
973 /* Find the VUE slot for this attribute. */
974 int slot
= vue_map
->varying_to_slot
[fs_attr
];
976 /* Viewport and Layer are stored in the VUE header. We need to override
977 * them to zero if earlier stages didn't write them, as GL requires that
978 * they read back as zero when not explicitly set.
980 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
981 attr
->ComponentOverrideX
= true;
982 attr
->ComponentOverrideW
= true;
983 attr
->ConstantSource
= CONST_0000
;
985 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
986 attr
->ComponentOverrideY
= true;
987 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
988 attr
->ComponentOverrideZ
= true;
993 /* If there was only a back color written but not front, use back
994 * as the color instead of undefined
996 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
997 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
998 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
999 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
1002 /* This attribute does not exist in the VUE--that means that the vertex
1003 * shader did not write to it. This means that either:
1005 * (a) This attribute is a texture coordinate, and it is going to be
1006 * replaced with point coordinates (as a consequence of a call to
1007 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
1008 * hardware will ignore whatever attribute override we supply.
1010 * (b) This attribute is read by the fragment shader but not written by
1011 * the vertex shader, so its value is undefined. Therefore the
1012 * attribute override we supply doesn't matter.
1014 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
1015 * previous shader stage.
1017 * Note that we don't have to worry about the cases where the attribute
1018 * is gl_PointCoord or is undergoing point sprite coordinate
1019 * replacement, because in those cases, this function isn't called.
1021 * In case (c), we need to program the attribute overrides so that the
1022 * primitive ID will be stored in this slot. In every other case, the
1023 * attribute override we supply doesn't matter. So just go ahead and
1024 * program primitive ID in every case.
1026 attr
->ComponentOverrideW
= true;
1027 attr
->ComponentOverrideX
= true;
1028 attr
->ComponentOverrideY
= true;
1029 attr
->ComponentOverrideZ
= true;
1030 attr
->ConstantSource
= PRIM_ID
;
1034 /* Compute the location of the attribute relative to urb_entry_read_offset.
1035 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1036 * it counts for two 128-bit VUE slots.
1038 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1039 assert(source_attr
>= 0 && source_attr
< 32);
1041 /* If we are doing two-sided color, and the VUE slot following this one
1042 * represents a back-facing color, then we need to instruct the SF unit to
1043 * do back-facing swizzling.
1045 bool swizzling
= two_side_color
&&
1046 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1047 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1048 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1049 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1051 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1052 if (*max_source_attr
< source_attr
+ swizzling
)
1053 *max_source_attr
= source_attr
+ swizzling
;
1055 attr
->SourceAttribute
= source_attr
;
1057 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1062 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1063 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1064 uint32_t *point_sprite_enables
,
1065 uint32_t *urb_entry_read_length
,
1066 uint32_t *urb_entry_read_offset
)
1068 const struct gl_context
*ctx
= &brw
->ctx
;
1071 const struct gl_point_attrib
*point
= &ctx
->Point
;
1073 /* BRW_NEW_FRAGMENT_PROGRAM */
1074 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1076 /* BRW_NEW_FS_PROG_DATA */
1077 const struct brw_wm_prog_data
*wm_prog_data
=
1078 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1079 uint32_t max_source_attr
= 0;
1081 *point_sprite_enables
= 0;
1084 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1085 &brw
->vue_map_geom_out
);
1087 /* Each URB offset packs two varying slots */
1088 assert(first_slot
% 2 == 0);
1089 *urb_entry_read_offset
= first_slot
/ 2;
1091 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1092 * description of dw10 Point Sprite Texture Coordinate Enable:
1094 * "This field must be programmed to zero when non-point primitives
1097 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1098 * must be programmed to zero when rendering non-point primitives, but
1099 * the IvyBridge PRM does, and if we don't, we get garbage.
1101 * This is not required on Haswell, as the hardware ignores this state
1102 * when drawing non-points -- although we do still need to be careful to
1103 * correctly set the attr overrides.
1106 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1108 bool drawing_points
= brw_is_drawing_points(brw
);
1110 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1111 int input_index
= wm_prog_data
->urb_setup
[attr
];
1113 if (input_index
< 0)
1117 bool point_sprite
= false;
1118 if (drawing_points
) {
1119 if (point
->PointSprite
&&
1120 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1121 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1122 point_sprite
= true;
1125 if (attr
== VARYING_SLOT_PNTC
)
1126 point_sprite
= true;
1129 *point_sprite_enables
|= (1 << input_index
);
1132 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1133 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1135 if (!point_sprite
) {
1136 genX(get_attr_override
)(&attribute
,
1137 &brw
->vue_map_geom_out
,
1138 *urb_entry_read_offset
, attr
,
1139 _mesa_vertex_program_two_side_enabled(ctx
),
1143 /* The hardware can only do the overrides on 16 overrides at a
1144 * time, and the other up to 16 have to be lined up so that the
1145 * input index = the output index. We'll need to do some
1146 * tweaking to make sure that's the case.
1148 if (input_index
< 16)
1149 attr_overrides
[input_index
] = attribute
;
1151 assert(attribute
.SourceAttribute
== input_index
);
1154 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1155 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1157 * "This field should be set to the minimum length required to read the
1158 * maximum source attribute. The maximum source attribute is indicated
1159 * by the maximum value of the enabled Attribute # Source Attribute if
1160 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1161 * enable is not set.
1162 * read_length = ceiling((max_source_attr + 1) / 2)
1164 * [errata] Corruption/Hang possible if length programmed larger than
1167 * Similar text exists for Ivy Bridge.
1169 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1173 /* ---------------------------------------------------------------------- */
1176 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1178 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1180 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1184 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1186 struct gl_context
*ctx
= &brw
->ctx
;
1189 struct intel_renderbuffer
*depth_irb
=
1190 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1193 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1196 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1197 const int b
= stencil
->_BackFace
;
1199 if (depth
->Test
&& depth_irb
) {
1200 ds
->DepthTestEnable
= true;
1201 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1202 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1205 if (brw
->stencil_enabled
) {
1206 ds
->StencilTestEnable
= true;
1207 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1208 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1210 ds
->StencilTestFunction
=
1211 intel_translate_compare_func(stencil
->Function
[0]);
1213 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1214 ds
->StencilPassDepthPassOp
=
1215 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1216 ds
->StencilPassDepthFailOp
=
1217 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1219 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1221 if (brw
->stencil_two_sided
) {
1222 ds
->DoubleSidedStencilEnable
= true;
1223 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1224 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1226 ds
->BackfaceStencilTestFunction
=
1227 intel_translate_compare_func(stencil
->Function
[b
]);
1228 ds
->BackfaceStencilFailOp
=
1229 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1230 ds
->BackfaceStencilPassDepthPassOp
=
1231 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1232 ds
->BackfaceStencilPassDepthFailOp
=
1233 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1236 #if GEN_GEN <= 5 || GEN_GEN >= 9
1237 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1238 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1245 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1248 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1249 set_depth_stencil_bits(brw
, &wmds
);
1253 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1254 set_depth_stencil_bits(brw
, &ds
);
1257 /* Now upload a pointer to the indirect state */
1259 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1260 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1261 ptr
.DEPTH_STENCIL_STATEChange
= true;
1264 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1265 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1271 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1273 .mesa
= _NEW_BUFFERS
|
1276 .brw
= BRW_NEW_BLORP
|
1277 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1279 BRW_NEW_STATE_BASE_ADDRESS
),
1281 .emit
= genX(upload_depth_stencil_state
),
1285 /* ---------------------------------------------------------------------- */
1290 genX(upload_clip_state
)(struct brw_context
*brw
)
1292 struct gl_context
*ctx
= &brw
->ctx
;
1294 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1295 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1296 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1297 clip
.GRFRegisterCount
=
1298 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1299 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1300 clip
.SingleProgramFlow
= true;
1301 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1302 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1304 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1305 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1306 clip
.DispatchGRFStartRegisterForURBData
= 1;
1307 clip
.VertexURBEntryReadOffset
= 0;
1309 /* BRW_NEW_URB_FENCE */
1310 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1311 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1313 if (brw
->urb
.nr_clip_entries
>= 10) {
1314 /* Half of the URB entries go to each thread, and it has to be an
1317 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1319 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1320 * only 2 threads can output VUEs at a time.
1322 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1324 assert(brw
->urb
.nr_clip_entries
>= 5);
1325 clip
.MaximumNumberofThreads
= 1 - 1;
1328 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1329 clip
.UserClipFlagsMustClipEnable
= true;
1330 clip
.GuardbandClipTestEnable
= true;
1332 clip
.ClipperViewportStatePointer
=
1333 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1335 clip
.ScreenSpaceViewportXMin
= -1;
1336 clip
.ScreenSpaceViewportXMax
= 1;
1337 clip
.ScreenSpaceViewportYMin
= -1;
1338 clip
.ScreenSpaceViewportYMax
= 1;
1340 clip
.ViewportXYClipTestEnable
= true;
1341 clip
.ViewportZClipTestEnable
= !(ctx
->Transform
.DepthClampNear
&&
1342 ctx
->Transform
.DepthClampFar
);
1344 /* _NEW_TRANSFORM */
1345 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1346 clip
.UserClipDistanceClipTestEnableBitmask
=
1347 ctx
->Transform
.ClipPlanesEnabled
;
1349 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1352 clip
.UserClipDistanceClipTestEnableBitmask
=
1353 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1356 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1357 clip
.APIMode
= APIMODE_D3D
;
1359 clip
.APIMode
= APIMODE_OGL
;
1361 clip
.GuardbandClipTestEnable
= true;
1363 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1366 clip
.NegativeWClipTestEnable
= true;
1371 const struct brw_tracked_state
genX(clip_state
) = {
1373 .mesa
= _NEW_TRANSFORM
|
1375 .brw
= BRW_NEW_BATCH
|
1377 BRW_NEW_CLIP_PROG_DATA
|
1378 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1379 BRW_NEW_PROGRAM_CACHE
|
1382 .emit
= genX(upload_clip_state
),
1388 genX(upload_clip_state
)(struct brw_context
*brw
)
1390 struct gl_context
*ctx
= &brw
->ctx
;
1393 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1395 /* BRW_NEW_FS_PROG_DATA */
1396 struct brw_wm_prog_data
*wm_prog_data
=
1397 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1399 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1400 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1402 if (wm_prog_data
->barycentric_interp_modes
&
1403 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1404 clip
.NonPerspectiveBarycentricEnable
= true;
1407 clip
.EarlyCullEnable
= true;
1411 clip
.FrontWinding
= brw
->polygon_front_bit
!= fb
->FlipY
;
1413 if (ctx
->Polygon
.CullFlag
) {
1414 switch (ctx
->Polygon
.CullFaceMode
) {
1416 clip
.CullMode
= CULLMODE_FRONT
;
1419 clip
.CullMode
= CULLMODE_BACK
;
1421 case GL_FRONT_AND_BACK
:
1422 clip
.CullMode
= CULLMODE_BOTH
;
1425 unreachable("Should not get here: invalid CullFlag");
1428 clip
.CullMode
= CULLMODE_NONE
;
1433 clip
.UserClipDistanceCullTestEnableBitmask
=
1434 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1436 clip
.ViewportZClipTestEnable
= !(ctx
->Transform
.DepthClampNear
&&
1437 ctx
->Transform
.DepthClampFar
);
1441 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1442 clip
.TriangleStripListProvokingVertexSelect
= 0;
1443 clip
.TriangleFanProvokingVertexSelect
= 1;
1444 clip
.LineStripListProvokingVertexSelect
= 0;
1446 clip
.TriangleStripListProvokingVertexSelect
= 2;
1447 clip
.TriangleFanProvokingVertexSelect
= 2;
1448 clip
.LineStripListProvokingVertexSelect
= 1;
1451 /* _NEW_TRANSFORM */
1452 clip
.UserClipDistanceClipTestEnableBitmask
=
1453 ctx
->Transform
.ClipPlanesEnabled
;
1456 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1459 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1460 clip
.APIMode
= APIMODE_D3D
;
1462 clip
.APIMode
= APIMODE_OGL
;
1464 clip
.GuardbandClipTestEnable
= true;
1466 /* BRW_NEW_VIEWPORT_COUNT */
1467 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1469 if (ctx
->RasterDiscard
) {
1470 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1472 perf_debug("Rasterizer discard is currently implemented via the "
1473 "clipper; having the GS not write primitives would "
1474 "likely be faster.\n");
1477 clip
.ClipMode
= CLIPMODE_NORMAL
;
1480 clip
.ClipEnable
= true;
1483 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1485 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1486 clip
.ViewportXYClipTestEnable
= true;
1488 clip
.MinimumPointWidth
= 0.125;
1489 clip
.MaximumPointWidth
= 255.875;
1490 clip
.MaximumVPIndex
= viewport_count
- 1;
1491 if (_mesa_geometric_layers(fb
) == 0)
1492 clip
.ForceZeroRTAIndexEnable
= true;
1496 static const struct brw_tracked_state
genX(clip_state
) = {
1498 .mesa
= _NEW_BUFFERS
|
1502 .brw
= BRW_NEW_BLORP
|
1504 BRW_NEW_FS_PROG_DATA
|
1505 BRW_NEW_GS_PROG_DATA
|
1506 BRW_NEW_VS_PROG_DATA
|
1507 BRW_NEW_META_IN_PROGRESS
|
1509 BRW_NEW_RASTERIZER_DISCARD
|
1510 BRW_NEW_TES_PROG_DATA
|
1511 BRW_NEW_VIEWPORT_COUNT
,
1513 .emit
= genX(upload_clip_state
),
1517 /* ---------------------------------------------------------------------- */
1520 genX(upload_sf
)(struct brw_context
*brw
)
1522 struct gl_context
*ctx
= &brw
->ctx
;
1527 bool flip_y
= ctx
->DrawBuffer
->FlipY
;
1528 UNUSED
const bool multisampled_fbo
=
1529 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1533 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1535 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1537 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1538 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1539 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1540 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1541 sf
.DispatchGRFStartRegisterForURBData
= 3;
1542 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1543 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1544 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1545 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1547 /* STATE_PREFETCH command description describes this state as being
1548 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1551 sf
.SetupViewportStateOffset
=
1552 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1554 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1556 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1557 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1559 sf
.MaximumNumberofThreads
=
1560 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1562 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1564 sf
.DestinationOriginHorizontalBias
= 0.5;
1565 sf
.DestinationOriginVerticalBias
= 0.5;
1567 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1568 sf
.StatisticsEnable
= true;
1570 sf
.ViewportTransformEnable
= true;
1574 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1579 sf
.FrontWinding
= brw
->polygon_front_bit
!= flip_y
;
1581 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1582 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1583 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1585 switch (ctx
->Polygon
.FrontMode
) {
1587 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1590 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1593 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1596 unreachable("not reached");
1599 switch (ctx
->Polygon
.BackMode
) {
1601 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1604 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1607 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1610 unreachable("not reached");
1613 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1614 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1616 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1617 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1618 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1621 sf
.ScissorRectangleEnable
= true;
1623 if (ctx
->Polygon
.CullFlag
) {
1624 switch (ctx
->Polygon
.CullFaceMode
) {
1626 sf
.CullMode
= CULLMODE_FRONT
;
1629 sf
.CullMode
= CULLMODE_BACK
;
1631 case GL_FRONT_AND_BACK
:
1632 sf
.CullMode
= CULLMODE_BOTH
;
1635 unreachable("not reached");
1638 sf
.CullMode
= CULLMODE_NONE
;
1642 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1649 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1651 if (devinfo
->is_cherryview
)
1652 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1654 sf
.LineWidth
= brw_get_line_width(brw
);
1656 sf
.LineWidth
= brw_get_line_width(brw
);
1659 if (ctx
->Line
.SmoothFlag
) {
1660 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1662 sf
.AntiAliasingEnable
= true;
1666 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1667 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1668 /* Clamp to the hardware limits */
1669 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1671 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1672 if (use_state_point_size(brw
))
1673 sf
.PointWidthSource
= State
;
1676 /* _NEW_POINT | _NEW_MULTISAMPLE */
1677 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1678 !ctx
->Point
.PointSprite
)
1679 sf
.SmoothPointEnable
= true;
1684 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1686 const bool multisampled_fbo
=
1687 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1688 if (multisampled_fbo
)
1689 sf
.SmoothPointEnable
= false;
1692 #if GEN_IS_G4X || GEN_GEN >= 5
1693 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1697 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1698 sf
.TriangleStripListProvokingVertexSelect
= 2;
1699 sf
.TriangleFanProvokingVertexSelect
= 2;
1700 sf
.LineStripListProvokingVertexSelect
= 1;
1702 sf
.TriangleFanProvokingVertexSelect
= 1;
1706 /* BRW_NEW_FS_PROG_DATA */
1707 const struct brw_wm_prog_data
*wm_prog_data
=
1708 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1710 sf
.AttributeSwizzleEnable
= true;
1711 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1714 * Window coordinates in an FBO are inverted, which means point
1715 * sprite origin must be inverted, too.
1717 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) == flip_y
) {
1718 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1720 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1723 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1724 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1726 uint32_t urb_entry_read_length
;
1727 uint32_t urb_entry_read_offset
;
1728 uint32_t point_sprite_enables
;
1729 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1730 &urb_entry_read_length
,
1731 &urb_entry_read_offset
);
1732 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1733 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1734 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1735 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1740 static const struct brw_tracked_state
genX(sf_state
) = {
1742 .mesa
= _NEW_LIGHT
|
1746 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1747 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1748 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1749 .brw
= BRW_NEW_BLORP
|
1750 BRW_NEW_VUE_MAP_GEOM_OUT
|
1751 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1752 BRW_NEW_PROGRAM_CACHE
|
1753 BRW_NEW_SF_PROG_DATA
|
1757 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1758 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1759 BRW_NEW_GS_PROG_DATA
|
1761 BRW_NEW_TES_PROG_DATA
1763 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1764 BRW_NEW_FRAGMENT_PROGRAM
1767 .emit
= genX(upload_sf
),
1770 /* ---------------------------------------------------------------------- */
1773 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1775 struct gl_context
*ctx
= &brw
->ctx
;
1776 /* BRW_NEW_FRAGMENT_PROGRAM */
1777 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1781 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1782 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1783 uint64_t outputs_written
= fp
->info
.outputs_written
;
1786 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1787 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1788 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1797 genX(upload_wm
)(struct brw_context
*brw
)
1799 struct gl_context
*ctx
= &brw
->ctx
;
1801 /* BRW_NEW_FS_PROG_DATA */
1802 const struct brw_wm_prog_data
*wm_prog_data
=
1803 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1805 UNUSED
bool writes_depth
=
1806 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1807 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1808 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1811 /* We can't fold this into gen6_upload_wm_push_constants(), because
1812 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1813 * (3DSTATE_CONSTANT_PS [DevSNB]):
1815 * "[DevSNB]: This packet must be followed by WM_STATE."
1817 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1818 if (wm_prog_data
->base
.nr_params
!= 0) {
1819 wmcp
.Buffer0Valid
= true;
1820 /* Pointer to the WM constant buffer. Covered by the set of
1821 * state flags from gen6_upload_wm_push_constants.
1823 wmcp
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
1824 wmcp
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1830 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1832 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1833 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1837 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1838 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1839 wm
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1843 /* On gen4, we only have one shader kernel */
1844 if (brw_wm_state_has_ksp(wm
, 0)) {
1845 assert(brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0) == 0);
1846 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1847 wm
.GRFRegisterCount0
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 0);
1848 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1849 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 0);
1852 /* On gen5, we have multiple shader kernels but only one GRF start
1853 * register for all kernels
1855 wm
.KernelStartPointer0
= stage_state
->prog_offset
+
1856 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0);
1857 wm
.KernelStartPointer1
= stage_state
->prog_offset
+
1858 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 1);
1859 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1860 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 2);
1862 wm
.GRFRegisterCount0
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 0);
1863 wm
.GRFRegisterCount1
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 1);
1864 wm
.GRFRegisterCount2
= brw_wm_prog_data_reg_blocks(wm_prog_data
, wm
, 2);
1866 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1867 wm_prog_data
->base
.dispatch_grf_start_reg
;
1869 /* Dispatch GRF Start should be the same for all shaders on gen5 */
1870 if (brw_wm_state_has_ksp(wm
, 1)) {
1871 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1872 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 1));
1874 if (brw_wm_state_has_ksp(wm
, 2)) {
1875 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1876 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 2));
1879 /* On gen6, we have multiple shader kernels and we no longer specify a
1880 * register count for each one.
1882 wm
.KernelStartPointer0
= stage_state
->prog_offset
+
1883 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 0);
1884 wm
.KernelStartPointer1
= stage_state
->prog_offset
+
1885 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 1);
1886 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1887 brw_wm_prog_data_prog_offset(wm_prog_data
, wm
, 2);
1889 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1890 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 0);
1891 wm
.DispatchGRFStartRegisterForConstantSetupData1
=
1892 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 1);
1893 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1894 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, wm
, 2);
1898 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1899 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1900 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1901 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1902 wm
.SetupURBEntryReadOffset
= 0;
1903 wm
.EarlyDepthTestEnable
= true;
1907 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1908 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1910 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1911 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1913 if (stage_state
->sampler_count
)
1914 wm
.SamplerStatePointer
=
1915 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1917 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1918 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1921 if (ctx
->Polygon
.OffsetFill
) {
1922 wm
.GlobalDepthOffsetEnable
= true;
1923 /* Something weird going on with legacy_global_depth_bias,
1924 * offset_constant, scaling and MRD. This value passes glean
1925 * but gives some odd results elsewere (eg. the
1926 * quad-offset-units test).
1928 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1930 /* This is the only value that passes glean:
1932 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1935 wm
.DepthCoefficientURBReadOffset
= 1;
1938 /* BRW_NEW_STATS_WM */
1939 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1942 if (wm_prog_data
->base
.use_alt_mode
)
1943 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1946 wm
.SamplerCount
= (GEN_GEN
== 5 || GEN_GEN
== 11) ?
1947 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1949 wm
.BindingTableEntryCount
=
1950 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1951 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1954 wm
.DualSourceBlendEnable
=
1955 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1956 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1957 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1958 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1960 /* From the SNB PRM, volume 2 part 1, page 281:
1961 * "If the PS kernel does not need the Position XY Offsets
1962 * to compute a Position XY value, then this field should be
1963 * programmed to POSOFFSET_NONE."
1965 * "SW Recommendation: If the PS kernel needs the Position Offsets
1966 * to compute a Position XY value, this field should match Position
1967 * ZW Interpolation Mode to ensure a consistent position.xyzw
1969 * We only require XY sample offsets. So, this recommendation doesn't
1970 * look useful at the moment. We might need this in future.
1972 if (wm_prog_data
->uses_pos_offset
)
1973 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1975 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1978 if (wm_prog_data
->base
.total_scratch
) {
1979 wm
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
1980 wm
.PerThreadScratchSpace
=
1981 ffs(stage_state
->per_thread_scratch
) - 11;
1984 wm
.PixelShaderComputedDepth
= writes_depth
;
1988 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1991 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1996 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1999 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
2001 if (multisampled_fbo
) {
2002 /* _NEW_MULTISAMPLE */
2003 if (ctx
->Multisample
.Enabled
)
2004 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
2006 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
2008 if (wm_prog_data
->persample_dispatch
)
2009 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
2011 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
2013 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
2014 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
2017 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2018 if (wm_prog_data
->uses_kill
||
2019 _mesa_is_alpha_test_enabled(ctx
) ||
2020 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
2021 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
2022 wm
.PixelShaderKillsPixel
= true;
2025 /* _NEW_BUFFERS | _NEW_COLOR */
2026 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
2027 wm
.PixelShaderKillsPixel
||
2028 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
2029 wm
.ThreadDispatchEnable
= true;
2033 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2034 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
2037 /* The "UAV access enable" bits are unnecessary on HSW because they only
2038 * seem to have an effect on the HW-assisted coherency mechanism which we
2039 * don't need, and the rasterization-related UAV_ONLY flag and the
2040 * DISPATCH_ENABLE bit can be set independently from it.
2041 * C.f. gen8_upload_ps_extra().
2043 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
2047 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
2048 wm_prog_data
->has_side_effects
)
2054 /* BRW_NEW_FS_PROG_DATA */
2055 if (wm_prog_data
->early_fragment_tests
)
2056 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2057 else if (wm_prog_data
->has_side_effects
)
2058 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2063 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
2064 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
2065 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
2068 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
2073 static const struct brw_tracked_state
genX(wm_state
) = {
2077 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
2080 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2081 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2082 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2083 .brw
= BRW_NEW_BLORP
|
2084 BRW_NEW_FS_PROG_DATA
|
2085 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2086 BRW_NEW_FRAGMENT_PROGRAM
|
2087 BRW_NEW_PROGRAM_CACHE
|
2088 BRW_NEW_SAMPLER_STATE_TABLE
|
2091 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2093 .emit
= genX(upload_wm
),
2096 /* ---------------------------------------------------------------------- */
2098 /* We restrict scratch buffers to the bottom 32 bits of the address space
2099 * by using rw_32_bo().
2101 * General State Base Address is a bit broken. If the address + size as
2102 * seen by STATE_BASE_ADDRESS overflows 48 bits, the GPU appears to treat
2103 * all accesses to the buffer as being out of bounds and returns zero.
2106 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2107 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2108 /* WA_1606682166 */ \
2109 pkt.SamplerCount = \
2112 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2113 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to \
2114 * disable prefetching of binding tables in A0 and B0 steppings. \
2115 * TODO: Revisit this WA on C0 stepping. \
2117 pkt.BindingTableEntryCount = \
2120 stage_prog_data->binding_table.size_bytes / 4; \
2121 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2123 if (stage_prog_data->total_scratch) { \
2124 pkt.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0); \
2125 pkt.PerThreadScratchSpace = \
2126 ffs(stage_state->per_thread_scratch) - 11; \
2129 pkt.DispatchGRFStartRegisterForURBData = \
2130 stage_prog_data->dispatch_grf_start_reg; \
2131 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2132 pkt.prefix##URBEntryReadOffset = 0; \
2134 pkt.StatisticsEnable = true; \
2138 genX(upload_vs_state
)(struct brw_context
*brw
)
2140 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2141 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2142 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2144 /* BRW_NEW_VS_PROG_DATA */
2145 const struct brw_vue_prog_data
*vue_prog_data
=
2146 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2147 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2149 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2150 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2151 assert(GEN_GEN
< 11 ||
2152 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
2155 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2156 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2158 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2159 * command that causes the VS Function Enable to toggle. Pipeline
2160 * flush can be executed by sending a PIPE_CONTROL command with CS
2161 * stall bit set and a post sync operation.
2163 * We've already done such a flush at the start of state upload, so we
2164 * don't need to do another one here.
2166 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2167 if (stage_state
->push_const_size
!= 0) {
2168 cvs
.Buffer0Valid
= true;
2169 cvs
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
2170 cvs
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2175 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2176 gen7_emit_vs_workaround_flush(brw
);
2179 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2181 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2182 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2184 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2186 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2189 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2190 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2191 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2193 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2194 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2196 vs
.MaximumNumberofThreads
=
2197 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2199 vs
.StatisticsEnable
= false;
2200 vs
.SamplerStatePointer
=
2201 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2205 /* Force single program flow on Ironlake. We cannot reliably get
2206 * all applications working without it. See:
2207 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2209 * The most notable and reliably failing application is the Humus
2212 vs
.SingleProgramFlow
= true;
2213 vs
.SamplerCount
= 0; /* hardware requirement */
2217 vs
.SIMD8DispatchEnable
=
2218 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2220 vs
.UserClipDistanceCullTestEnableBitmask
=
2221 vue_prog_data
->cull_distance_mask
;
2226 /* Based on my reading of the simulator, the VS constants don't get
2227 * pulled into the VS FF unit until an appropriate pipeline flush
2228 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2229 * references to them into a little FIFO. The flushes are common,
2230 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2231 * the primitive to use the wrong constants. Then the FIFO
2232 * containing the constant setup gets added to again on the next
2233 * constants change, and eventually when a flush does happen the
2234 * unit is overwhelmed by constant changes and dies.
2236 * To avoid this, send a PIPE_CONTROL down the line that will
2237 * update the unit immediately loading the constants. The flush
2238 * type bits here were those set by the STATE_BASE_ADDRESS whose
2239 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2240 * bug reports that led to this workaround, and may be more than
2241 * what is strictly required to avoid the issue.
2243 brw_emit_pipe_control_flush(brw
,
2244 PIPE_CONTROL_DEPTH_STALL
|
2245 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2246 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2250 static const struct brw_tracked_state
genX(vs_state
) = {
2252 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2253 .brw
= BRW_NEW_BATCH
|
2256 BRW_NEW_VS_PROG_DATA
|
2257 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2258 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2259 BRW_NEW_PROGRAM_CACHE
|
2260 BRW_NEW_SAMPLER_STATE_TABLE
|
2264 .emit
= genX(upload_vs_state
),
2267 /* ---------------------------------------------------------------------- */
2270 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2272 struct gl_context
*ctx
= &brw
->ctx
;
2274 /* BRW_NEW_VIEWPORT_COUNT */
2275 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2277 struct GENX(CC_VIEWPORT
) ccv
;
2278 uint32_t cc_vp_offset
;
2280 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2283 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2284 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2285 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2286 if (ctx
->Transform
.DepthClampNear
&& ctx
->Transform
.DepthClampFar
) {
2287 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2288 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2289 } else if (ctx
->Transform
.DepthClampNear
) {
2290 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2291 ccv
.MaximumDepth
= 0.0;
2292 } else if (ctx
->Transform
.DepthClampFar
) {
2293 ccv
.MinimumDepth
= 0.0;
2294 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2296 ccv
.MinimumDepth
= 0.0;
2297 ccv
.MaximumDepth
= 1.0;
2299 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2300 cc_map
+= GENX(CC_VIEWPORT_length
);
2304 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2305 ptr
.CCViewportPointer
= cc_vp_offset
;
2308 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2309 vp
.CCViewportStateChange
= 1;
2310 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2313 brw
->cc
.vp_offset
= cc_vp_offset
;
2314 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2318 const struct brw_tracked_state
genX(cc_vp
) = {
2320 .mesa
= _NEW_TRANSFORM
|
2322 .brw
= BRW_NEW_BATCH
|
2324 BRW_NEW_VIEWPORT_COUNT
,
2326 .emit
= genX(upload_cc_viewport
)
2329 /* ---------------------------------------------------------------------- */
2332 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2333 bool flip_y
, unsigned fb_width
, unsigned fb_height
,
2334 struct GENX(SCISSOR_RECT
) *sc
)
2338 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2339 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2340 bbox
[2] = CLAMP(ctx
->ViewportArray
[i
].Y
, 0, fb_height
);
2341 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2342 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2344 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2345 /* If the scissor was out of bounds and got clamped to 0 width/height
2346 * at the bounds, the subtraction of 1 from maximums could produce a
2347 * negative number and thus not clip anything. Instead, just provide
2348 * a min > max scissor inside the bounds, which produces the expected
2351 sc
->ScissorRectangleXMin
= 1;
2352 sc
->ScissorRectangleXMax
= 0;
2353 sc
->ScissorRectangleYMin
= 1;
2354 sc
->ScissorRectangleYMax
= 0;
2355 } else if (!flip_y
) {
2356 /* texmemory: Y=0=bottom */
2357 sc
->ScissorRectangleXMin
= bbox
[0];
2358 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2359 sc
->ScissorRectangleYMin
= bbox
[2];
2360 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2362 /* memory: Y=0=top */
2363 sc
->ScissorRectangleXMin
= bbox
[0];
2364 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2365 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2366 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2372 genX(upload_scissor_state
)(struct brw_context
*brw
)
2374 struct gl_context
*ctx
= &brw
->ctx
;
2375 const bool flip_y
= ctx
->DrawBuffer
->FlipY
;
2376 struct GENX(SCISSOR_RECT
) scissor
;
2377 uint32_t scissor_state_offset
;
2378 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2379 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2380 uint32_t *scissor_map
;
2382 /* BRW_NEW_VIEWPORT_COUNT */
2383 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2385 scissor_map
= brw_state_batch(
2386 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2387 32, &scissor_state_offset
);
2389 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2391 /* The scissor only needs to handle the intersection of drawable and
2392 * scissor rect. Clipping to the boundaries of static shared buffers
2393 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2395 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2396 * inclusive but max is exclusive.
2398 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2399 set_scissor_bits(ctx
, i
, flip_y
, fb_width
, fb_height
, &scissor
);
2400 GENX(SCISSOR_RECT_pack
)(
2401 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2404 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2405 ptr
.ScissorRectPointer
= scissor_state_offset
;
2409 static const struct brw_tracked_state
genX(scissor_state
) = {
2411 .mesa
= _NEW_BUFFERS
|
2414 .brw
= BRW_NEW_BATCH
|
2416 BRW_NEW_VIEWPORT_COUNT
,
2418 .emit
= genX(upload_scissor_state
),
2422 /* ---------------------------------------------------------------------- */
2425 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2426 float m00
, float m11
, float m30
, float m31
,
2427 float *xmin
, float *xmax
,
2428 float *ymin
, float *ymax
)
2430 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2431 * Strips and Fans documentation:
2433 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2434 * fixed-point "guardband" range supported by the rasterization hardware"
2438 * "In almost all circumstances, if an object’s vertices are actually
2439 * modified by this clamping (i.e., had X or Y coordinates outside of
2440 * the guardband extent the rendered object will not match the intended
2441 * result. Therefore software should take steps to ensure that this does
2442 * not happen - e.g., by clipping objects such that they do not exceed
2443 * these limits after the Drawing Rectangle is applied."
2445 * I believe the fundamental restriction is that the rasterizer (in
2446 * the SF/WM stages) have a limit on the number of pixels that can be
2447 * rasterized. We need to ensure any coordinates beyond the rasterizer
2448 * limit are handled by the clipper. So effectively that limit becomes
2449 * the clipper's guardband size.
2451 * It goes on to say:
2453 * "In addition, in order to be correctly rendered, objects must have a
2454 * screenspace bounding box not exceeding 8K in the X or Y direction.
2455 * This additional restriction must also be comprehended by software,
2456 * i.e., enforced by use of clipping."
2458 * This makes no sense. Gen7+ hardware supports 16K render targets,
2459 * and you definitely need to be able to draw polygons that fill the
2460 * surface. Our assumption is that the rasterizer was limited to 8K
2461 * on Sandybridge, which only supports 8K surfaces, and it was actually
2462 * increased to 16K on Ivybridge and later.
2464 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2466 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2468 /* Workaround: prevent gpu hangs on SandyBridge
2469 * by disabling guardband clipping for odd dimensions.
2471 if (GEN_GEN
== 6 && (fb_width
& 1 || fb_height
& 1)) {
2479 if (m00
!= 0 && m11
!= 0) {
2480 /* First, we compute the screen-space render area */
2481 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2482 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2483 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2484 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2486 /* We want the guardband to be centered on that */
2487 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2488 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2489 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2490 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2492 /* Now we need it in native device coordinates */
2493 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2494 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2495 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2496 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2498 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2499 * flipped upside-down. X should be fine though.
2501 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2502 *xmin
= ndc_gb_xmin
;
2503 *xmax
= ndc_gb_xmax
;
2504 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2505 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2507 /* The viewport scales to 0, so nothing will be rendered. */
2516 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2518 struct gl_context
*ctx
= &brw
->ctx
;
2519 float y_scale
, y_bias
;
2521 /* BRW_NEW_VIEWPORT_COUNT */
2522 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2525 const bool flip_y
= ctx
->DrawBuffer
->FlipY
;
2526 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2527 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2531 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2532 uint32_t sf_clip_vp_offset
;
2533 uint32_t *sf_clip_map
=
2534 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2535 64, &sf_clip_vp_offset
);
2537 struct GENX(SF_VIEWPORT
) sfv
;
2538 struct GENX(CLIP_VIEWPORT
) clv
;
2539 uint32_t sf_vp_offset
, clip_vp_offset
;
2541 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2543 uint32_t *clip_map
=
2544 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2545 32, &clip_vp_offset
);
2551 y_bias
= (float)fb_height
;
2557 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2558 /* _NEW_VIEWPORT: Guardband Clipping */
2559 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2560 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2562 sfv
.ViewportMatrixElementm00
= scale
[0];
2563 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2564 sfv
.ViewportMatrixElementm22
= scale
[2],
2565 sfv
.ViewportMatrixElementm30
= translate
[0],
2566 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2567 sfv
.ViewportMatrixElementm32
= translate
[2],
2568 brw_calculate_guardband_size(fb_width
, fb_height
,
2569 sfv
.ViewportMatrixElementm00
,
2570 sfv
.ViewportMatrixElementm11
,
2571 sfv
.ViewportMatrixElementm30
,
2572 sfv
.ViewportMatrixElementm31
,
2573 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2576 clv
.XMinClipGuardband
= gb_xmin
;
2577 clv
.XMaxClipGuardband
= gb_xmax
;
2578 clv
.YMinClipGuardband
= gb_ymin
;
2579 clv
.YMaxClipGuardband
= gb_ymax
;
2582 set_scissor_bits(ctx
, i
, flip_y
, fb_width
, fb_height
,
2583 &sfv
.ScissorRectangle
);
2585 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2586 * The hardware will take the intersection of the drawing rectangle,
2587 * scissor rectangle, and the viewport extents. However, emitting
2588 * 3DSTATE_DRAWING_RECTANGLE is expensive since it requires a full
2589 * pipeline stall so we're better off just being a little more clever
2590 * with our viewport so we can emit it once at context creation time.
2592 const float viewport_Xmin
= MAX2(ctx
->ViewportArray
[i
].X
, 0);
2593 const float viewport_Ymin
= MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2594 const float viewport_Xmax
=
2595 MIN2(ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
, fb_width
);
2596 const float viewport_Ymax
=
2597 MIN2(ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
, fb_height
);
2600 sfv
.XMinViewPort
= viewport_Xmin
;
2601 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2602 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2603 sfv
.YMaxViewPort
= fb_height
- viewport_Ymin
- 1;
2605 sfv
.XMinViewPort
= viewport_Xmin
;
2606 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2607 sfv
.YMinViewPort
= viewport_Ymin
;
2608 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2613 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2614 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2616 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2617 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2618 sf_map
+= GENX(SF_VIEWPORT_length
);
2619 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2624 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2625 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2628 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2629 vp
.SFViewportStateChange
= 1;
2630 vp
.CLIPViewportStateChange
= 1;
2631 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2632 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2635 brw
->sf
.vp_offset
= sf_vp_offset
;
2636 brw
->clip
.vp_offset
= clip_vp_offset
;
2637 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2641 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2643 .mesa
= _NEW_BUFFERS
|
2645 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2646 .brw
= BRW_NEW_BATCH
|
2648 BRW_NEW_VIEWPORT_COUNT
,
2650 .emit
= genX(upload_sf_clip_viewport
),
2653 /* ---------------------------------------------------------------------- */
2656 genX(upload_gs_state
)(struct brw_context
*brw
)
2658 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2659 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2660 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2661 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2662 /* BRW_NEW_GEOMETRY_PROGRAM */
2663 bool active
= GEN_GEN
>= 6 && gs_prog
;
2665 /* BRW_NEW_GS_PROG_DATA */
2666 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2667 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2668 brw_vue_prog_data(stage_prog_data
);
2670 const struct brw_gs_prog_data
*gs_prog_data
=
2671 brw_gs_prog_data(stage_prog_data
);
2675 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2676 if (active
&& stage_state
->push_const_size
!= 0) {
2677 cgs
.Buffer0Valid
= true;
2678 cgs
.ConstantBody
.PointertoConstantBuffer0
= stage_state
->push_const_offset
;
2679 cgs
.ConstantBody
.ConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2684 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2686 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2687 * Geometry > Geometry Shader > State:
2689 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2690 * whole fixed function pipeline when the GS enable changes value in
2693 * The hardware architects have clarified that in this context "flush the
2694 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2697 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2698 gen7_emit_cs_stall_flush(brw
);
2702 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2704 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2705 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2710 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2713 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2714 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2715 gs
.ControlDataHeaderSize
=
2716 gs_prog_data
->control_data_header_size_hwords
;
2718 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2719 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2721 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2723 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2726 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2727 * Ivy Bridge and Haswell.
2729 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2730 * strip to be delivered to the geometry shader in an order that does
2731 * not strictly follow the OpenGL spec, but preserves triangle
2732 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2733 * the geometry shader sees triangles:
2735 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2737 * (Clearing the bit is even worse, because it fails to preserve
2740 * Triangle strips with adjacency always ordered in a way that preserves
2741 * triangle orientation but does not strictly follow the OpenGL spec,
2742 * regardless of the setting of this bit.
2744 * On Haswell, both triangle strips and triangle strips with adjacency
2745 * are always ordered in a way that preserves triangle orientation.
2746 * Setting this bit causes the ordering to strictly follow the OpenGL
2749 * So in either case we want to set the bit. Unfortunately on Ivy
2750 * Bridge this will get the order close to correct but not perfect.
2752 gs
.ReorderMode
= TRAILING
;
2753 gs
.MaximumNumberofThreads
=
2754 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2755 : (devinfo
->max_gs_threads
- 1);
2758 gs
.SOStatisticsEnable
= true;
2759 if (gs_prog
->info
.has_transform_feedback_varyings
)
2760 gs
.SVBIPayloadEnable
= _mesa_is_xfb_active_and_unpaused(ctx
);
2762 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2763 * was previously done for gen6.
2765 * TODO: test with both disabled to see if the HW is behaving
2766 * as expected, like in gen7.
2768 gs
.SingleProgramFlow
= true;
2769 gs
.VectorMaskEnable
= true;
2773 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2775 if (gs_prog_data
->static_vertex_count
!= -1) {
2776 gs
.StaticOutput
= true;
2777 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2779 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2781 gs
.UserClipDistanceCullTestEnableBitmask
=
2782 vue_prog_data
->cull_distance_mask
;
2784 const int urb_entry_write_offset
= 1;
2785 const uint32_t urb_entry_output_length
=
2786 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2787 urb_entry_write_offset
;
2789 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2790 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2796 if (!active
&& brw
->ff_gs
.prog_active
) {
2797 /* In gen6, transform feedback for the VS stage is done with an
2798 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2801 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2802 gs
.SingleProgramFlow
= true;
2803 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2804 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2807 gs
.GRFRegisterCount
=
2808 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2809 /* BRW_NEW_URB_FENCE */
2810 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2811 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2812 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2813 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2816 gs
.VectorMaskEnable
= true;
2817 gs
.SVBIPayloadEnable
= true;
2818 gs
.SVBIPostIncrementEnable
= true;
2819 gs
.SVBIPostIncrementValue
=
2820 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2821 gs
.SOStatisticsEnable
= true;
2822 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2826 if (!active
&& !brw
->ff_gs
.prog_active
) {
2828 gs
.DispatchGRFStartRegisterForURBData
= 1;
2830 gs
.IncludeVertexHandles
= true;
2836 gs
.StatisticsEnable
= true;
2838 #if GEN_GEN == 5 || GEN_GEN == 6
2839 gs
.RenderingEnabled
= true;
2842 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2847 brw
->gs
.enabled
= active
;
2851 static const struct brw_tracked_state
genX(gs_state
) = {
2853 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2854 .brw
= BRW_NEW_BATCH
|
2856 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2857 BRW_NEW_PROGRAM_CACHE
|
2859 BRW_NEW_VIEWPORT_COUNT
2861 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2862 BRW_NEW_GEOMETRY_PROGRAM
|
2863 BRW_NEW_GS_PROG_DATA
2865 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2867 .emit
= genX(upload_gs_state
),
2870 /* ---------------------------------------------------------------------- */
2872 UNUSED
static GLenum
2873 fix_dual_blend_alpha_to_one(GLenum function
)
2879 case GL_ONE_MINUS_SRC1_ALPHA
:
2886 #define blend_factor(x) brw_translate_blend_factor(x)
2887 #define blend_eqn(x) brw_translate_blend_equation(x)
2890 * Modify blend function to force destination alpha to 1.0
2892 * If \c function specifies a blend function that uses destination alpha,
2893 * replace it with a function that hard-wires destination alpha to 1.0. This
2894 * is used when rendering to xRGB targets.
2897 brw_fix_xRGB_alpha(GLenum function
)
2903 case GL_ONE_MINUS_DST_ALPHA
:
2904 case GL_SRC_ALPHA_SATURATE
:
2912 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2914 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2918 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2921 struct gl_context
*ctx
= &brw
->ctx
;
2924 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2926 bool independent_alpha_blend
= false;
2928 /* Used for implementing the following bit of GL_EXT_texture_integer:
2929 * "Per-fragment operations that require floating-point color
2930 * components, including multisample alpha operations, alpha test,
2931 * blending, and dithering, have no effect when the corresponding
2932 * colors are written to an integer color buffer."
2934 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2936 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2937 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2940 if (ctx
->Color
.ColorLogicOpEnabled
) {
2941 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2942 : GL_UNSIGNED_NORMALIZED
;
2943 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2944 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2945 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2947 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2948 _mesa_enum_to_string(rb_type
));
2949 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2950 entry
->LogicOpEnable
= true;
2951 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2953 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2954 && (GEN_GEN
<= 5 || !integer
)) {
2955 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2956 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2957 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2958 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2959 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2960 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2962 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2963 srcRGB
= dstRGB
= GL_ONE
;
2965 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2966 srcA
= dstA
= GL_ONE
;
2968 /* Due to hardware limitations, the destination may have information
2969 * in an alpha channel even when the format specifies no alpha
2970 * channel. In order to avoid getting any incorrect blending due to
2971 * that alpha channel, coerce the blend factors to values that will
2972 * not read the alpha channel, but will instead use the correct
2973 * implicit value for alpha.
2975 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2976 GL_TEXTURE_ALPHA_TYPE
)) {
2977 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2978 srcA
= brw_fix_xRGB_alpha(srcA
);
2979 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2980 dstA
= brw_fix_xRGB_alpha(dstA
);
2983 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2984 * "If Dual Source Blending is enabled, this bit must be disabled."
2986 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2987 * and leave it enabled anyway.
2989 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2990 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2991 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2992 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2993 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2996 /* BRW_NEW_FS_PROG_DATA */
2997 const struct brw_wm_prog_data
*wm_prog_data
=
2998 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3000 /* The Dual Source Blending documentation says:
3002 * "If SRC1 is included in a src/dst blend factor and
3003 * a DualSource RT Write message is not used, results
3004 * are UNDEFINED. (This reflects the same restriction in DX APIs,
3005 * where undefined results are produced if “o1” is not written
3006 * by a PS – there are no default values defined).
3007 * If SRC1 is not included in a src/dst blend factor,
3008 * dual source blending must be disabled."
3010 * There is no way to gracefully fix this undefined situation
3011 * so we just disable the blending to prevent possible issues.
3013 entry
->ColorBufferBlendEnable
=
3014 !ctx
->Color
.Blend
[0]._UsesDualSrc
|| wm_prog_data
->dual_src_blend
;
3016 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
3017 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
3018 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
3019 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
3020 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
3021 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
3023 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
3024 independent_alpha_blend
= true;
3027 return independent_alpha_blend
;
3032 genX(upload_blend_state
)(struct brw_context
*brw
)
3034 struct gl_context
*ctx
= &brw
->ctx
;
3037 /* We need at least one BLEND_STATE written, because we might do
3038 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
3039 * for computed depth or alpha test), which will do an FB write
3040 * with render target 0, which will reference BLEND_STATE[0] for
3041 * alpha test enable.
3043 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
3044 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
3045 nr_draw_buffers
= 1;
3047 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
3049 size
+= GENX(BLEND_STATE_length
) * 4;
3052 uint32_t *blend_map
;
3053 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
3056 struct GENX(BLEND_STATE
) blend
= { 0 };
3059 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3060 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3063 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
3064 * "If drawbuffer zero is not NONE and the buffer it references has an
3065 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
3066 * operations are skipped."
3068 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
3069 /* _NEW_MULTISAMPLE */
3070 if (_mesa_is_multisample_enabled(ctx
)) {
3071 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
3072 blend
.AlphaToCoverageEnable
= true;
3073 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
3075 if (ctx
->Multisample
.SampleAlphaToOne
)
3076 blend
.AlphaToOneEnable
= true;
3080 if (ctx
->Color
.AlphaEnabled
) {
3081 blend
.AlphaTestEnable
= true;
3082 blend
.AlphaTestFunction
=
3083 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3086 if (ctx
->Color
.DitherFlag
) {
3087 blend
.ColorDitherEnable
= true;
3092 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3093 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3097 blend
.IndependentAlphaBlendEnable
=
3098 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
3099 blend
.IndependentAlphaBlendEnable
;
3101 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
3102 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
3104 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
3105 * clamping in the fragment shader. For its clamping of
3106 * blending, the spec says:
3108 * "RESOLVED: For fixed-point color buffers, the inputs and
3109 * the result of the blending equation are clamped. For
3110 * floating-point color buffers, no clamping occurs."
3112 * So, generally, we want clamping to the render target's range.
3113 * And, good news, the hardware tables for both pre- and
3114 * post-blend color clamping are either ignored, or any are
3115 * allowed, or clamping is required but RT range clamping is a
3118 entry
.PreBlendColorClampEnable
= true;
3119 entry
.PostBlendColorClampEnable
= true;
3120 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
3122 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
3123 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
3124 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
3125 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
3128 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
3130 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3136 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3140 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3141 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3142 ptr
.BLEND_STATEChange
= true;
3145 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3146 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3148 ptr
.BlendStatePointerValid
= true;
3154 static const struct brw_tracked_state
genX(blend_state
) = {
3156 .mesa
= _NEW_BUFFERS
|
3159 .brw
= BRW_NEW_BATCH
|
3161 BRW_NEW_FS_PROG_DATA
|
3162 BRW_NEW_STATE_BASE_ADDRESS
,
3164 .emit
= genX(upload_blend_state
),
3168 /* ---------------------------------------------------------------------- */
3171 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3172 [MESA_SHADER_VERTEX
] = 21,
3173 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3174 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3175 [MESA_SHADER_GEOMETRY
] = 22,
3176 [MESA_SHADER_FRAGMENT
] = 23,
3177 [MESA_SHADER_COMPUTE
] = 0,
3181 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3183 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3184 struct gl_context
*ctx
= &brw
->ctx
;
3186 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3188 struct brw_stage_state
*stage_states
[] = {
3196 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3197 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3198 gen7_emit_vs_workaround_flush(brw
);
3200 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3201 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3202 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3204 if (!stage_state
->push_constants_dirty
)
3207 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3208 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3209 if (stage_state
->prog_data
) {
3210 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3211 /* The Skylake PRM contains the following restriction:
3213 * "The driver must ensure The following case does not occur
3214 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3215 * buffer 3 read length equal to zero committed followed by a
3216 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3219 * To avoid this, we program the buffers in the highest slots.
3220 * This way, slot 0 is only used if slot 3 is also used.
3224 for (int i
= 3; i
>= 0; i
--) {
3225 const struct brw_ubo_range
*range
=
3226 &stage_state
->prog_data
->ubo_ranges
[i
];
3228 if (range
->length
== 0)
3231 const struct gl_uniform_block
*block
=
3232 prog
->sh
.UniformBlocks
[range
->block
];
3233 const struct gl_buffer_binding
*binding
=
3234 &ctx
->UniformBufferBindings
[block
->Binding
];
3236 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3237 static unsigned msg_id
= 0;
3238 _mesa_gl_debugf(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3239 MESA_DEBUG_TYPE_UNDEFINED
,
3240 MESA_DEBUG_SEVERITY_HIGH
,
3241 "UBO %d unbound, %s shader uniform data "
3242 "will be undefined.",
3244 _mesa_shader_stage_to_string(stage
));
3248 assert(binding
->Offset
% 32 == 0);
3250 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3251 intel_buffer_object(binding
->BufferObject
),
3252 binding
->Offset
, range
->length
* 32, false);
3254 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3255 pkt
.ConstantBody
.Buffer
[n
] =
3256 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3260 if (stage_state
->push_const_size
> 0) {
3262 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3263 pkt
.ConstantBody
.Buffer
[n
] =
3264 ro_bo(stage_state
->push_const_bo
,
3265 stage_state
->push_const_offset
);
3268 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3269 pkt
.ConstantBody
.Buffer
[0].offset
=
3270 stage_state
->push_const_offset
| mocs
;
3275 stage_state
->push_constants_dirty
= false;
3276 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3280 const struct brw_tracked_state
genX(push_constant_packets
) = {
3283 .brw
= BRW_NEW_DRAW_CALL
,
3285 .emit
= genX(upload_push_constant_packets
),
3291 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3293 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3295 /* BRW_NEW_VERTEX_PROGRAM */
3296 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3297 /* BRW_NEW_VS_PROG_DATA */
3298 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3300 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3303 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3305 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3307 .brw
= BRW_NEW_BATCH
|
3309 BRW_NEW_VERTEX_PROGRAM
|
3310 BRW_NEW_VS_PROG_DATA
,
3312 .emit
= genX(upload_vs_push_constants
),
3316 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3318 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3320 /* BRW_NEW_GEOMETRY_PROGRAM */
3321 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3323 /* BRW_NEW_GS_PROG_DATA */
3324 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3326 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3329 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3331 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3333 .brw
= BRW_NEW_BATCH
|
3335 BRW_NEW_GEOMETRY_PROGRAM
|
3336 BRW_NEW_GS_PROG_DATA
,
3338 .emit
= genX(upload_gs_push_constants
),
3342 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3344 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3345 /* BRW_NEW_FRAGMENT_PROGRAM */
3346 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3347 /* BRW_NEW_FS_PROG_DATA */
3348 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3350 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3353 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3355 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3356 .brw
= BRW_NEW_BATCH
|
3358 BRW_NEW_FRAGMENT_PROGRAM
|
3359 BRW_NEW_FS_PROG_DATA
,
3361 .emit
= genX(upload_wm_push_constants
),
3365 /* ---------------------------------------------------------------------- */
3369 genX(determine_sample_mask
)(struct brw_context
*brw
)
3371 struct gl_context
*ctx
= &brw
->ctx
;
3372 float coverage
= 1.0f
;
3373 float coverage_invert
= false;
3374 unsigned sample_mask
= ~0u;
3376 /* BRW_NEW_NUM_SAMPLES */
3377 unsigned num_samples
= brw
->num_samples
;
3379 if (_mesa_is_multisample_enabled(ctx
)) {
3380 if (ctx
->Multisample
.SampleCoverage
) {
3381 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3382 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3384 if (ctx
->Multisample
.SampleMask
) {
3385 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3389 if (num_samples
> 1) {
3390 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3391 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3392 if (coverage_invert
)
3393 coverage_bits
^= (1 << num_samples
) - 1;
3394 return coverage_bits
& sample_mask
;
3401 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3402 unsigned num_samples
)
3404 unsigned log2_samples
= ffs(num_samples
) - 1;
3406 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3407 multi
.PixelLocation
= CENTER
;
3408 multi
.NumberofMultisamples
= log2_samples
;
3410 GEN_SAMPLE_POS_4X(multi
.Sample
);
3412 switch (num_samples
) {
3414 GEN_SAMPLE_POS_1X(multi
.Sample
);
3417 GEN_SAMPLE_POS_2X(multi
.Sample
);
3420 GEN_SAMPLE_POS_4X(multi
.Sample
);
3423 GEN_SAMPLE_POS_8X(multi
.Sample
);
3433 genX(upload_multisample_state
)(struct brw_context
*brw
)
3435 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3437 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3439 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3440 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3444 static const struct brw_tracked_state
genX(multisample_state
) = {
3446 .mesa
= _NEW_MULTISAMPLE
|
3447 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3448 .brw
= BRW_NEW_BLORP
|
3450 BRW_NEW_NUM_SAMPLES
,
3452 .emit
= genX(upload_multisample_state
)
3456 /* ---------------------------------------------------------------------- */
3459 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3461 struct gl_context
*ctx
= &brw
->ctx
;
3463 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3465 cc
.IndependentAlphaBlendEnable
=
3466 set_blend_entry_bits(brw
, &cc
, 0, false);
3467 set_depth_stencil_bits(brw
, &cc
);
3469 if (ctx
->Color
.AlphaEnabled
&&
3470 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3471 cc
.AlphaTestEnable
= true;
3472 cc
.AlphaTestFunction
=
3473 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3476 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3478 cc
.StatisticsEnable
= brw
->stats_wm
;
3480 cc
.CCViewportStatePointer
=
3481 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3484 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3485 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3486 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3487 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3491 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3492 cc
.BackfaceStencilReferenceValue
=
3493 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3499 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3500 ctx
->Color
.AlphaRef
);
3504 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3505 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3507 ptr
.ColorCalcStatePointerValid
= true;
3511 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3515 static const struct brw_tracked_state
genX(color_calc_state
) = {
3517 .mesa
= _NEW_COLOR
|
3519 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3522 .brw
= BRW_NEW_BATCH
|
3524 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3526 : BRW_NEW_CC_STATE
|
3527 BRW_NEW_STATE_BASE_ADDRESS
),
3529 .emit
= genX(upload_color_calc_state
),
3533 /* ---------------------------------------------------------------------- */
3537 genX(upload_sbe
)(struct brw_context
*brw
)
3539 struct gl_context
*ctx
= &brw
->ctx
;
3540 /* BRW_NEW_FRAGMENT_PROGRAM */
3541 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3542 /* BRW_NEW_FS_PROG_DATA */
3543 const struct brw_wm_prog_data
*wm_prog_data
=
3544 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3546 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3548 #define attr_overrides sbe.Attribute
3550 uint32_t urb_entry_read_length
;
3551 uint32_t urb_entry_read_offset
;
3552 uint32_t point_sprite_enables
;
3554 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3555 sbe
.AttributeSwizzleEnable
= true;
3556 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3559 bool flip_y
= ctx
->DrawBuffer
->FlipY
;
3563 * Window coordinates in an FBO are inverted, which means point
3564 * sprite origin must be inverted.
3566 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) == flip_y
)
3567 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3569 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3571 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3572 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3573 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3574 * BRW_NEW_VUE_MAP_GEOM_OUT
3576 genX(calculate_attr_overrides
)(brw
,
3578 &point_sprite_enables
,
3579 &urb_entry_read_length
,
3580 &urb_entry_read_offset
);
3582 /* Typically, the URB entry read length and offset should be programmed
3583 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3584 * stage which produces geometry. However, we don't know the proper
3585 * value until we call calculate_attr_overrides().
3587 * To fit with our existing code, we override the inherited values and
3588 * specify it here directly, as we did on previous generations.
3590 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3591 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3592 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3593 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3596 sbe
.ForceVertexURBEntryReadLength
= true;
3597 sbe
.ForceVertexURBEntryReadOffset
= true;
3601 /* prepare the active component dwords */
3602 for (int i
= 0; i
< 32; i
++)
3603 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3608 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3609 for (int i
= 0; i
< 16; i
++)
3610 sbes
.Attribute
[i
] = attr_overrides
[i
];
3614 #undef attr_overrides
3617 static const struct brw_tracked_state
genX(sbe_state
) = {
3619 .mesa
= _NEW_BUFFERS
|
3624 .brw
= BRW_NEW_BLORP
|
3626 BRW_NEW_FRAGMENT_PROGRAM
|
3627 BRW_NEW_FS_PROG_DATA
|
3628 BRW_NEW_GS_PROG_DATA
|
3629 BRW_NEW_TES_PROG_DATA
|
3630 BRW_NEW_VUE_MAP_GEOM_OUT
|
3631 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3634 .emit
= genX(upload_sbe
),
3638 /* ---------------------------------------------------------------------- */
3642 * Outputs the 3DSTATE_SO_DECL_LIST command.
3644 * The data output is a series of 64-bit entries containing a SO_DECL per
3645 * stream. We only have one stream of rendering coming out of the GS unit, so
3646 * we only emit stream 0 (low 16 bits) SO_DECLs.
3649 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3650 const struct brw_vue_map
*vue_map
)
3652 struct gl_context
*ctx
= &brw
->ctx
;
3653 /* BRW_NEW_TRANSFORM_FEEDBACK */
3654 struct gl_transform_feedback_object
*xfb_obj
=
3655 ctx
->TransformFeedback
.CurrentObject
;
3656 const struct gl_transform_feedback_info
*linked_xfb_info
=
3657 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3658 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3659 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3660 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3661 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3663 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3665 memset(so_decl
, 0, sizeof(so_decl
));
3667 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3668 * command feels strange -- each dword pair contains a SO_DECL per stream.
3670 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3671 const struct gl_transform_feedback_output
*output
=
3672 &linked_xfb_info
->Outputs
[i
];
3673 const int buffer
= output
->OutputBuffer
;
3674 const int varying
= output
->OutputRegister
;
3675 const unsigned stream_id
= output
->StreamId
;
3676 assert(stream_id
< MAX_VERTEX_STREAMS
);
3678 buffer_mask
[stream_id
] |= 1 << buffer
;
3680 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3682 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3683 * array. Instead, it simply increments DstOffset for the following
3684 * input by the number of components that should be skipped.
3686 * Our hardware is unusual in that it requires us to program SO_DECLs
3687 * for fake "hole" components, rather than simply taking the offset
3688 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3689 * program as many size = 4 holes as we can, then a final hole to
3690 * accommodate the final 1, 2, or 3 remaining.
3692 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3694 while (skip_components
> 0) {
3695 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3697 .OutputBufferSlot
= output
->OutputBuffer
,
3698 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3700 skip_components
-= 4;
3703 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3705 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3706 .OutputBufferSlot
= output
->OutputBuffer
,
3707 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3709 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3712 if (decls
[stream_id
] > max_decls
)
3713 max_decls
= decls
[stream_id
];
3717 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3718 .StreamtoBufferSelects0
= buffer_mask
[0],
3719 .StreamtoBufferSelects1
= buffer_mask
[1],
3720 .StreamtoBufferSelects2
= buffer_mask
[2],
3721 .StreamtoBufferSelects3
= buffer_mask
[3],
3722 .NumEntries0
= decls
[0],
3723 .NumEntries1
= decls
[1],
3724 .NumEntries2
= decls
[2],
3725 .NumEntries3
= decls
[3]);
3727 for (int i
= 0; i
< max_decls
; i
++) {
3728 GENX(SO_DECL_ENTRY_pack
)(
3729 brw
, dw
+ 2 + i
* 2,
3730 &(struct GENX(SO_DECL_ENTRY
)) {
3731 .Stream0Decl
= so_decl
[0][i
],
3732 .Stream1Decl
= so_decl
[1][i
],
3733 .Stream2Decl
= so_decl
[2][i
],
3734 .Stream3Decl
= so_decl
[3][i
],
3740 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3742 struct gl_context
*ctx
= &brw
->ctx
;
3743 /* BRW_NEW_TRANSFORM_FEEDBACK */
3744 struct gl_transform_feedback_object
*xfb_obj
=
3745 ctx
->TransformFeedback
.CurrentObject
;
3747 const struct gl_transform_feedback_info
*linked_xfb_info
=
3748 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3750 struct brw_transform_feedback_object
*brw_obj
=
3751 (struct brw_transform_feedback_object
*) xfb_obj
;
3752 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3755 /* Set up the up to 4 output buffers. These are the ranges defined in the
3756 * gl_transform_feedback_object.
3758 for (int i
= 0; i
< 4; i
++) {
3759 struct intel_buffer_object
*bufferobj
=
3760 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3761 uint32_t start
= xfb_obj
->Offset
[i
];
3762 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3763 uint32_t const size
= end
- start
;
3765 if (!bufferobj
|| !size
) {
3766 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3767 sob
.SOBufferIndex
= i
;
3772 assert(start
% 4 == 0);
3774 intel_bufferobj_buffer(brw
, bufferobj
, start
, size
, true);
3775 assert(end
<= bo
->size
);
3777 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3778 sob
.SOBufferIndex
= i
;
3780 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3782 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3783 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3785 sob
.SOBufferEnable
= true;
3786 sob
.StreamOffsetWriteEnable
= true;
3787 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3790 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3791 sob
.StreamOutputBufferOffsetAddress
=
3792 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3794 if (brw_obj
->zero_offsets
) {
3795 /* Zero out the offset and write that to offset_bo */
3796 sob
.StreamOffset
= 0;
3798 /* Use offset_bo as the "Stream Offset." */
3799 sob
.StreamOffset
= 0xFFFFFFFF;
3806 brw_obj
->zero_offsets
= false;
3811 query_active(struct gl_query_object
*q
)
3813 return q
&& q
->Active
;
3817 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3818 const struct brw_vue_map
*vue_map
)
3820 struct gl_context
*ctx
= &brw
->ctx
;
3821 /* BRW_NEW_TRANSFORM_FEEDBACK */
3822 struct gl_transform_feedback_object
*xfb_obj
=
3823 ctx
->TransformFeedback
.CurrentObject
;
3825 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3827 int urb_entry_read_offset
= 0;
3828 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3829 urb_entry_read_offset
;
3831 sos
.SOFunctionEnable
= true;
3832 sos
.SOStatisticsEnable
= true;
3834 /* BRW_NEW_RASTERIZER_DISCARD */
3835 if (ctx
->RasterDiscard
) {
3836 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3837 sos
.RenderingDisable
= true;
3839 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3840 "query active relies on the clipper.\n");
3845 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3846 sos
.ReorderMode
= TRAILING
;
3849 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3850 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3851 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3852 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3854 const struct gl_transform_feedback_info
*linked_xfb_info
=
3855 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3856 /* Set buffer pitches; 0 means unbound. */
3857 if (xfb_obj
->Buffers
[0])
3858 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3859 if (xfb_obj
->Buffers
[1])
3860 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3861 if (xfb_obj
->Buffers
[2])
3862 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3863 if (xfb_obj
->Buffers
[3])
3864 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3867 /* We always read the whole vertex. This could be reduced at some
3868 * point by reading less and offsetting the register index in the
3871 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3872 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3873 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3874 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3875 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3876 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3877 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3878 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3884 genX(upload_sol
)(struct brw_context
*brw
)
3886 struct gl_context
*ctx
= &brw
->ctx
;
3887 /* BRW_NEW_TRANSFORM_FEEDBACK */
3888 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3891 genX(upload_3dstate_so_buffers
)(brw
);
3893 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3894 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3897 /* Finally, set up the SOL stage. This command must always follow updates to
3898 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3899 * MMIO register updates (current performed by the kernel at each batch
3902 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3905 static const struct brw_tracked_state
genX(sol_state
) = {
3908 .brw
= BRW_NEW_BATCH
|
3910 BRW_NEW_RASTERIZER_DISCARD
|
3911 BRW_NEW_VUE_MAP_GEOM_OUT
|
3912 BRW_NEW_TRANSFORM_FEEDBACK
,
3914 .emit
= genX(upload_sol
),
3918 /* ---------------------------------------------------------------------- */
3922 genX(upload_ps
)(struct brw_context
*brw
)
3924 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3925 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3927 /* BRW_NEW_FS_PROG_DATA */
3928 const struct brw_wm_prog_data
*prog_data
=
3929 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3930 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3935 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3936 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3937 * incorrect for subspans where some of the pixels are unlit. We believe
3938 * the bit just didn't take effect in previous generations.
3940 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3943 * "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
3944 * Disable the Sampler state prefetch functionality in the SARB by
3945 * programming 0xB000[30] to '1'."
3947 ps
.SamplerCount
= GEN_GEN
== 11 ?
3948 0 : DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3950 /* BRW_NEW_FS_PROG_DATA */
3951 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to disable
3952 * prefetching of binding tables in A0 and B0 steppings.
3953 * TODO: Revisit this workaround on C0 stepping.
3955 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ?
3957 prog_data
->base
.binding_table
.size_bytes
/ 4;
3959 if (prog_data
->base
.use_alt_mode
)
3960 ps
.FloatingPointMode
= Alternate
;
3962 /* Haswell requires the sample mask to be set in this packet as well as
3963 * in 3DSTATE_SAMPLE_MASK; the values should match.
3966 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3968 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3971 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
3972 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
3973 * k, it implies 2(k+1) threads. It implicitly scales for different GT
3974 * levels (which have some # of PSDs).
3976 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
3979 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3981 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3983 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3986 if (prog_data
->base
.nr_params
> 0 ||
3987 prog_data
->base
.ubo_ranges
[0].length
> 0)
3988 ps
.PushConstantEnable
= true;
3991 /* From the IVB PRM, volume 2 part 1, page 287:
3992 * "This bit is inserted in the PS payload header and made available to
3993 * the DataPort (either via the message header or via header bypass) to
3994 * indicate that oMask data (one or two phases) is included in Render
3995 * Target Write messages. If present, the oMask data is used to mask off
3998 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4000 /* The hardware wedges if you have this bit set but don't turn on any
4001 * dual source blend factors.
4003 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
4005 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
4006 (ctx
->Color
.BlendEnabled
& 1) &&
4007 ctx
->Color
.Blend
[0]._UsesDualSrc
;
4009 /* BRW_NEW_FS_PROG_DATA */
4010 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
4013 /* From the documentation for this packet:
4014 * "If the PS kernel does not need the Position XY Offsets to
4015 * compute a Position Value, then this field should be programmed
4016 * to POSOFFSET_NONE."
4018 * "SW Recommendation: If the PS kernel needs the Position Offsets
4019 * to compute a Position XY value, this field should match Position
4020 * ZW Interpolation Mode to ensure a consistent position.xyzw
4023 * We only require XY sample offsets. So, this recommendation doesn't
4024 * look useful at the moment. We might need this in future.
4026 if (prog_data
->uses_pos_offset
)
4027 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
4029 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
4031 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
4032 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
4033 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
4035 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
4037 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
4038 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
4040 * Since 16x MSAA is first introduced on SKL, we don't need to apply
4041 * the workaround on any older hardware.
4043 * BRW_NEW_NUM_SAMPLES
4045 if (GEN_GEN
>= 9 && !prog_data
->persample_dispatch
&&
4046 brw
->num_samples
== 16) {
4047 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
4048 ps
._32PixelDispatchEnable
= false;
4051 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
4052 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
4053 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
4054 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
4055 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
4056 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
4058 ps
.KernelStartPointer0
= stage_state
->prog_offset
+
4059 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
4060 ps
.KernelStartPointer1
= stage_state
->prog_offset
+
4061 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
4062 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
4063 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
4065 if (prog_data
->base
.total_scratch
) {
4066 ps
.ScratchSpaceBasePointer
=
4067 rw_32_bo(stage_state
->scratch_bo
,
4068 ffs(stage_state
->per_thread_scratch
) - 11);
4073 static const struct brw_tracked_state
genX(ps_state
) = {
4075 .mesa
= _NEW_MULTISAMPLE
|
4076 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
4079 .brw
= BRW_NEW_BATCH
|
4081 BRW_NEW_FS_PROG_DATA
|
4082 (GEN_GEN
>= 9 ? BRW_NEW_NUM_SAMPLES
: 0),
4084 .emit
= genX(upload_ps
),
4088 /* ---------------------------------------------------------------------- */
4092 genX(upload_hs_state
)(struct brw_context
*brw
)
4094 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4095 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4096 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4097 const struct brw_vue_prog_data
*vue_prog_data
=
4098 brw_vue_prog_data(stage_prog_data
);
4100 /* BRW_NEW_TES_PROG_DATA */
4101 struct brw_tcs_prog_data
*tcs_prog_data
=
4102 brw_tcs_prog_data(stage_prog_data
);
4104 if (!tcs_prog_data
) {
4105 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
4107 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
4108 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
4110 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
4111 hs
.IncludeVertexHandles
= true;
4113 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
4116 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
4117 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
4123 static const struct brw_tracked_state
genX(hs_state
) = {
4126 .brw
= BRW_NEW_BATCH
|
4128 BRW_NEW_TCS_PROG_DATA
|
4129 BRW_NEW_TESS_PROGRAMS
,
4131 .emit
= genX(upload_hs_state
),
4135 genX(upload_ds_state
)(struct brw_context
*brw
)
4137 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4138 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4139 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4141 /* BRW_NEW_TES_PROG_DATA */
4142 const struct brw_tes_prog_data
*tes_prog_data
=
4143 brw_tes_prog_data(stage_prog_data
);
4144 const struct brw_vue_prog_data
*vue_prog_data
=
4145 brw_vue_prog_data(stage_prog_data
);
4147 if (!tes_prog_data
) {
4148 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
4150 assert(GEN_GEN
< 11 ||
4151 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
4153 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
4154 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
4156 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4157 ds
.ComputeWCoordinateEnable
=
4158 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4161 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
4162 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4163 ds
.UserClipDistanceCullTestEnableBitmask
=
4164 vue_prog_data
->cull_distance_mask
;
4170 static const struct brw_tracked_state
genX(ds_state
) = {
4173 .brw
= BRW_NEW_BATCH
|
4175 BRW_NEW_TESS_PROGRAMS
|
4176 BRW_NEW_TES_PROG_DATA
,
4178 .emit
= genX(upload_ds_state
),
4181 /* ---------------------------------------------------------------------- */
4184 upload_te_state(struct brw_context
*brw
)
4186 /* BRW_NEW_TESS_PROGRAMS */
4187 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4189 /* BRW_NEW_TES_PROG_DATA */
4190 const struct brw_tes_prog_data
*tes_prog_data
=
4191 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4194 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4195 te
.Partitioning
= tes_prog_data
->partitioning
;
4196 te
.OutputTopology
= tes_prog_data
->output_topology
;
4197 te
.TEDomain
= tes_prog_data
->domain
;
4199 te
.MaximumTessellationFactorOdd
= 63.0;
4200 te
.MaximumTessellationFactorNotOdd
= 64.0;
4203 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4207 static const struct brw_tracked_state
genX(te_state
) = {
4210 .brw
= BRW_NEW_BLORP
|
4212 BRW_NEW_TES_PROG_DATA
|
4213 BRW_NEW_TESS_PROGRAMS
,
4215 .emit
= upload_te_state
,
4218 /* ---------------------------------------------------------------------- */
4221 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4223 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4224 /* BRW_NEW_TESS_PROGRAMS */
4225 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4227 /* BRW_NEW_TES_PROG_DATA */
4228 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4229 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4232 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4234 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4235 .brw
= BRW_NEW_BATCH
|
4237 BRW_NEW_TESS_PROGRAMS
|
4238 BRW_NEW_TES_PROG_DATA
,
4240 .emit
= genX(upload_tes_push_constants
),
4244 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4246 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4247 /* BRW_NEW_TESS_PROGRAMS */
4248 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4250 /* BRW_NEW_TCS_PROG_DATA */
4251 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4253 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4256 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4258 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4259 .brw
= BRW_NEW_BATCH
|
4261 BRW_NEW_DEFAULT_TESS_LEVELS
|
4262 BRW_NEW_TESS_PROGRAMS
|
4263 BRW_NEW_TCS_PROG_DATA
,
4265 .emit
= genX(upload_tcs_push_constants
),
4270 /* ---------------------------------------------------------------------- */
4274 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4276 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4278 /* BRW_NEW_COMPUTE_PROGRAM */
4279 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4282 /* BRW_NEW_CS_PROG_DATA */
4283 struct brw_cs_prog_data
*cs_prog_data
=
4284 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4286 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4287 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4291 const struct brw_tracked_state
genX(cs_push_constants
) = {
4293 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4294 .brw
= BRW_NEW_BATCH
|
4296 BRW_NEW_COMPUTE_PROGRAM
|
4297 BRW_NEW_CS_PROG_DATA
,
4299 .emit
= genX(upload_cs_push_constants
),
4303 * Creates a new CS constant buffer reflecting the current CS program's
4304 * constants, if needed by the CS program.
4307 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4309 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4311 /* BRW_NEW_COMPUTE_PROGRAM */
4312 struct brw_program
*cp
=
4313 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4315 /* BRW_NEW_CS_PROG_DATA */
4316 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4318 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4319 /* _NEW_PROGRAM_CONSTANTS */
4320 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4321 stage_state
, prog_data
);
4324 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4326 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4327 .brw
= BRW_NEW_BATCH
|
4329 BRW_NEW_COMPUTE_PROGRAM
|
4330 BRW_NEW_CS_PROG_DATA
,
4332 .emit
= genX(upload_cs_pull_constants
),
4336 genX(upload_cs_state
)(struct brw_context
*brw
)
4338 if (!brw
->cs
.base
.prog_data
)
4342 uint32_t *desc
= (uint32_t*) brw_state_batch(
4343 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4346 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4347 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4348 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4349 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4351 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4352 brw_emit_buffer_surface_state(
4353 brw
, &stage_state
->surf_offset
[
4354 prog_data
->binding_table
.shader_time_start
],
4355 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4356 brw
->shader_time
.bo
->size
, 1,
4360 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4361 32, &stage_state
->bind_bo_offset
);
4363 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4365 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4366 * the only bits that are changed are scoreboard related: Scoreboard
4367 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4368 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4370 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4371 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4373 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4375 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4376 if (prog_data
->total_scratch
) {
4377 uint32_t per_thread_scratch_value
;
4380 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4381 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4383 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4384 } else if (GEN_IS_HASWELL
) {
4385 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4386 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4388 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4390 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4391 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4393 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4395 vfe
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
4396 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4399 /* If brw->screen->subslice_total is greater than one, then
4400 * devinfo->max_cs_threads stores number of threads per sub-slice;
4401 * thus we need to multiply by that number by subslices to get
4402 * the actual maximum number of threads; the -1 is because the HW
4403 * has a bias of 1 (would not make sense to say the maximum number
4406 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4407 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4408 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4410 vfe
.ResetGatewayTimer
=
4411 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4414 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4420 /* We are uploading duplicated copies of push constant uniforms for each
4421 * thread. Although the local id data needs to vary per thread, it won't
4422 * change for other uniform data. Unfortunately this duplication is
4423 * required for gen7. As of Haswell, this duplication can be avoided,
4424 * but this older mechanism with duplicated data continues to work.
4426 * FINISHME: As of Haswell, we could make use of the
4427 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4428 * field to only store one copy of uniform data.
4430 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4431 * which is described in the GPGPU_WALKER command and in the Broadwell
4432 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4433 * Operations => GPGPU Mode => Indirect Payload Storage.
4435 * Note: The constant data is built in brw_upload_cs_push_constants
4438 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4440 const uint32_t vfe_curbe_allocation
=
4441 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4442 cs_prog_data
->push
.cross_thread
.regs
, 2);
4443 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4446 if (cs_prog_data
->push
.total
.size
> 0) {
4447 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4448 curbe
.CURBETotalDataLength
=
4449 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4450 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4454 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4455 memcpy(bind
, stage_state
->surf_offset
,
4456 prog_data
->binding_table
.size_bytes
);
4457 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4458 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4459 .SamplerStatePointer
= stage_state
->sampler_offset
,
4460 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4461 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4462 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4463 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4464 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4465 prog_data
->total_shared
),
4466 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4467 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4468 .CrossThreadConstantDataReadLength
=
4469 cs_prog_data
->push
.cross_thread
.regs
,
4473 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4475 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4476 load
.InterfaceDescriptorTotalLength
=
4477 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4478 load
.InterfaceDescriptorDataStartAddress
= offset
;
4482 static const struct brw_tracked_state
genX(cs_state
) = {
4484 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4485 .brw
= BRW_NEW_BATCH
|
4487 BRW_NEW_CS_PROG_DATA
|
4488 BRW_NEW_SAMPLER_STATE_TABLE
|
4491 .emit
= genX(upload_cs_state
)
4494 #define GPGPU_DISPATCHDIMX 0x2500
4495 #define GPGPU_DISPATCHDIMY 0x2504
4496 #define GPGPU_DISPATCHDIMZ 0x2508
4498 #define MI_PREDICATE_SRC0 0x2400
4499 #define MI_PREDICATE_SRC1 0x2408
4502 prepare_indirect_gpgpu_walker(struct brw_context
*brw
)
4504 GLintptr indirect_offset
= brw
->compute
.num_work_groups_offset
;
4505 struct brw_bo
*bo
= brw
->compute
.num_work_groups_bo
;
4507 emit_lrm(brw
, GPGPU_DISPATCHDIMX
, ro_bo(bo
, indirect_offset
+ 0));
4508 emit_lrm(brw
, GPGPU_DISPATCHDIMY
, ro_bo(bo
, indirect_offset
+ 4));
4509 emit_lrm(brw
, GPGPU_DISPATCHDIMZ
, ro_bo(bo
, indirect_offset
+ 8));
4512 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
4513 emit_lri(brw
, MI_PREDICATE_SRC0
+ 4, 0);
4514 emit_lri(brw
, MI_PREDICATE_SRC1
, 0);
4515 emit_lri(brw
, MI_PREDICATE_SRC1
+ 4, 0);
4517 /* Load compute_dispatch_indirect_x_size into SRC0 */
4518 emit_lrm(brw
, MI_PREDICATE_SRC0
, ro_bo(bo
, indirect_offset
+ 0));
4520 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4521 brw_batch_emit(brw
, GENX(MI_PREDICATE
), mip
) {
4522 mip
.LoadOperation
= LOAD_LOAD
;
4523 mip
.CombineOperation
= COMBINE_SET
;
4524 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4527 /* Load compute_dispatch_indirect_y_size into SRC0 */
4528 emit_lrm(brw
, MI_PREDICATE_SRC0
, ro_bo(bo
, indirect_offset
+ 4));
4530 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4531 brw_batch_emit(brw
, GENX(MI_PREDICATE
), mip
) {
4532 mip
.LoadOperation
= LOAD_LOAD
;
4533 mip
.CombineOperation
= COMBINE_OR
;
4534 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4537 /* Load compute_dispatch_indirect_z_size into SRC0 */
4538 emit_lrm(brw
, MI_PREDICATE_SRC0
, ro_bo(bo
, indirect_offset
+ 8));
4540 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4541 brw_batch_emit(brw
, GENX(MI_PREDICATE
), mip
) {
4542 mip
.LoadOperation
= LOAD_LOAD
;
4543 mip
.CombineOperation
= COMBINE_OR
;
4544 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4547 /* predicate = !predicate; */
4548 #define COMPARE_FALSE 1
4549 brw_batch_emit(brw
, GENX(MI_PREDICATE
), mip
) {
4550 mip
.LoadOperation
= LOAD_LOADINV
;
4551 mip
.CombineOperation
= COMBINE_OR
;
4552 mip
.CompareOperation
= COMPARE_FALSE
;
4558 genX(emit_gpgpu_walker
)(struct brw_context
*brw
)
4560 const struct brw_cs_prog_data
*prog_data
=
4561 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4563 const GLuint
*num_groups
= brw
->compute
.num_work_groups
;
4565 bool indirect
= brw
->compute
.num_work_groups_bo
!= NULL
;
4567 prepare_indirect_gpgpu_walker(brw
);
4569 const unsigned simd_size
= prog_data
->simd_size
;
4570 unsigned group_size
= prog_data
->local_size
[0] *
4571 prog_data
->local_size
[1] * prog_data
->local_size
[2];
4573 uint32_t right_mask
= 0xffffffffu
>> (32 - simd_size
);
4574 const unsigned right_non_aligned
= group_size
& (simd_size
- 1);
4575 if (right_non_aligned
!= 0)
4576 right_mask
>>= (simd_size
- right_non_aligned
);
4578 brw_batch_emit(brw
, GENX(GPGPU_WALKER
), ggw
) {
4579 ggw
.IndirectParameterEnable
= indirect
;
4580 ggw
.PredicateEnable
= GEN_GEN
<= 7 && indirect
;
4581 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4582 ggw
.ThreadDepthCounterMaximum
= 0;
4583 ggw
.ThreadHeightCounterMaximum
= 0;
4584 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
4585 ggw
.ThreadGroupIDXDimension
= num_groups
[0];
4586 ggw
.ThreadGroupIDYDimension
= num_groups
[1];
4587 ggw
.ThreadGroupIDZDimension
= num_groups
[2];
4588 ggw
.RightExecutionMask
= right_mask
;
4589 ggw
.BottomExecutionMask
= 0xffffffff;
4592 brw_batch_emit(brw
, GENX(MEDIA_STATE_FLUSH
), msf
);
4597 /* ---------------------------------------------------------------------- */
4601 genX(upload_raster
)(struct brw_context
*brw
)
4603 const struct gl_context
*ctx
= &brw
->ctx
;
4606 const bool flip_y
= ctx
->DrawBuffer
->FlipY
;
4609 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4612 const struct gl_point_attrib
*point
= &ctx
->Point
;
4614 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4615 if (brw
->polygon_front_bit
!= flip_y
)
4616 raster
.FrontWinding
= CounterClockwise
;
4618 if (polygon
->CullFlag
) {
4619 switch (polygon
->CullFaceMode
) {
4621 raster
.CullMode
= CULLMODE_FRONT
;
4624 raster
.CullMode
= CULLMODE_BACK
;
4626 case GL_FRONT_AND_BACK
:
4627 raster
.CullMode
= CULLMODE_BOTH
;
4630 unreachable("not reached");
4633 raster
.CullMode
= CULLMODE_NONE
;
4636 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4638 raster
.DXMultisampleRasterizationEnable
=
4639 _mesa_is_multisample_enabled(ctx
);
4641 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4642 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4643 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4645 switch (polygon
->FrontMode
) {
4647 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4650 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4653 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4656 unreachable("not reached");
4659 switch (polygon
->BackMode
) {
4661 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4664 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4667 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4670 unreachable("not reached");
4674 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4678 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4680 const bool multisampled_fbo
=
4681 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4682 if (multisampled_fbo
)
4683 raster
.AntialiasingEnable
= false;
4687 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4689 /* _NEW_TRANSFORM */
4691 if (!(ctx
->Transform
.DepthClampNear
&&
4692 ctx
->Transform
.DepthClampFar
))
4693 raster
.ViewportZClipTestEnable
= true;
4697 if (!ctx
->Transform
.DepthClampNear
)
4698 raster
.ViewportZNearClipTestEnable
= true;
4700 if (!ctx
->Transform
.DepthClampFar
)
4701 raster
.ViewportZFarClipTestEnable
= true;
4704 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4706 raster
.ConservativeRasterizationEnable
=
4707 ctx
->IntelConservativeRasterization
;
4710 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4711 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4713 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4717 static const struct brw_tracked_state
genX(raster_state
) = {
4719 .mesa
= _NEW_BUFFERS
|
4726 .brw
= BRW_NEW_BLORP
|
4728 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4730 .emit
= genX(upload_raster
),
4734 /* ---------------------------------------------------------------------- */
4738 genX(upload_ps_extra
)(struct brw_context
*brw
)
4740 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4742 const struct brw_wm_prog_data
*prog_data
=
4743 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4745 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4746 psx
.PixelShaderValid
= true;
4747 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4748 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4749 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4750 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4751 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4752 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4754 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4755 if (prog_data
->uses_sample_mask
) {
4757 if (prog_data
->post_depth_coverage
)
4758 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4759 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4760 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4762 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4764 psx
.PixelShaderUsesInputCoverageMask
= true;
4768 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4770 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4771 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4774 /* The stricter cross-primitive coherency guarantees that the hardware
4775 * gives us with the "Accesses UAV" bit set for at least one shader stage
4776 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4777 * are redundant within the current image, atomic counter and SSBO GL
4778 * APIs, which all have very loose ordering and coherency requirements
4779 * and generally rely on the application to insert explicit barriers when
4780 * a shader invocation is expected to see the memory writes performed by
4781 * the invocations of some previous primitive. Regardless of the value
4782 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4783 * cause an in most cases useless DC flush when the lowermost stage with
4784 * the bit set finishes execution.
4786 * It would be nice to disable it, but in some cases we can't because on
4787 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4788 * signal (which could be set independently from the coherency mechanism
4789 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4790 * determine whether the hardware skips execution of the fragment shader
4791 * or not via the ThreadDispatchEnable signal. However if we know that
4792 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4793 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4794 * difference so we may just disable it here.
4796 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4797 * take into account KillPixels when no depth or stencil writes are
4798 * enabled. In order for occlusion queries to work correctly with no
4799 * attachments, we need to force-enable here.
4801 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4804 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4805 !brw_color_buffer_write_enabled(brw
))
4806 psx
.PixelShaderHasUAV
= true;
4810 const struct brw_tracked_state
genX(ps_extra
) = {
4812 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4813 .brw
= BRW_NEW_BLORP
|
4815 BRW_NEW_FRAGMENT_PROGRAM
|
4816 BRW_NEW_FS_PROG_DATA
|
4817 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4819 .emit
= genX(upload_ps_extra
),
4823 /* ---------------------------------------------------------------------- */
4827 genX(upload_ps_blend
)(struct brw_context
*brw
)
4829 struct gl_context
*ctx
= &brw
->ctx
;
4832 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4833 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4836 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4838 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4839 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4840 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4842 bool alpha_to_one
= false;
4844 if (!buffer0_is_integer
) {
4845 /* _NEW_MULTISAMPLE */
4847 if (_mesa_is_multisample_enabled(ctx
)) {
4848 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4849 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4852 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4855 /* Used for implementing the following bit of GL_EXT_texture_integer:
4856 * "Per-fragment operations that require floating-point color
4857 * components, including multisample alpha operations, alpha test,
4858 * blending, and dithering, have no effect when the corresponding
4859 * colors are written to an integer color buffer."
4861 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4862 * "If drawbuffer zero is not NONE and the buffer it references has an
4863 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4864 * operations are skipped."
4866 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4867 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4868 GLenum eqA
= color
->Blend
[0].EquationA
;
4869 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4870 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4871 GLenum srcA
= color
->Blend
[0].SrcA
;
4872 GLenum dstA
= color
->Blend
[0].DstA
;
4874 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4875 srcRGB
= dstRGB
= GL_ONE
;
4877 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4878 srcA
= dstA
= GL_ONE
;
4880 /* Due to hardware limitations, the destination may have information
4881 * in an alpha channel even when the format specifies no alpha
4882 * channel. In order to avoid getting any incorrect blending due to
4883 * that alpha channel, coerce the blend factors to values that will
4884 * not read the alpha channel, but will instead use the correct
4885 * implicit value for alpha.
4887 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4888 GL_TEXTURE_ALPHA_TYPE
)) {
4889 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4890 srcA
= brw_fix_xRGB_alpha(srcA
);
4891 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4892 dstA
= brw_fix_xRGB_alpha(dstA
);
4895 /* Alpha to One doesn't work with Dual Color Blending. Override
4896 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4898 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4899 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4900 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4901 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4902 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4905 /* BRW_NEW_FS_PROG_DATA */
4906 const struct brw_wm_prog_data
*wm_prog_data
=
4907 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4909 /* The Dual Source Blending documentation says:
4911 * "If SRC1 is included in a src/dst blend factor and
4912 * a DualSource RT Write message is not used, results
4913 * are UNDEFINED. (This reflects the same restriction in DX APIs,
4914 * where undefined results are produced if “o1” is not written
4915 * by a PS – there are no default values defined).
4916 * If SRC1 is not included in a src/dst blend factor,
4917 * dual source blending must be disabled."
4919 * There is no way to gracefully fix this undefined situation
4920 * so we just disable the blending to prevent possible issues.
4922 pb
.ColorBufferBlendEnable
=
4923 !color
->Blend
[0]._UsesDualSrc
|| wm_prog_data
->dual_src_blend
;
4924 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4925 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4926 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4927 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4929 pb
.IndependentAlphaBlendEnable
=
4930 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4935 static const struct brw_tracked_state
genX(ps_blend
) = {
4937 .mesa
= _NEW_BUFFERS
|
4940 .brw
= BRW_NEW_BLORP
|
4942 BRW_NEW_FRAGMENT_PROGRAM
|
4943 BRW_NEW_FS_PROG_DATA
,
4945 .emit
= genX(upload_ps_blend
)
4949 /* ---------------------------------------------------------------------- */
4953 genX(emit_vf_topology
)(struct brw_context
*brw
)
4955 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4956 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4960 static const struct brw_tracked_state
genX(vf_topology
) = {
4963 .brw
= BRW_NEW_BLORP
|
4966 .emit
= genX(emit_vf_topology
),
4970 /* ---------------------------------------------------------------------- */
4974 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4976 uint32_t offset_in_bytes
,
4979 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4980 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4981 mi_rpc
.ReportID
= report_id
;
4986 /* ---------------------------------------------------------------------- */
4989 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4992 genX(emit_sampler_state_pointers_xs
)(MAYBE_UNUSED
struct brw_context
*brw
,
4993 MAYBE_UNUSED
struct brw_stage_state
*stage_state
)
4996 static const uint16_t packet_headers
[] = {
4997 [MESA_SHADER_VERTEX
] = 43,
4998 [MESA_SHADER_TESS_CTRL
] = 44,
4999 [MESA_SHADER_TESS_EVAL
] = 45,
5000 [MESA_SHADER_GEOMETRY
] = 46,
5001 [MESA_SHADER_FRAGMENT
] = 47,
5004 /* Ivybridge requires a workaround flush before VS packets. */
5005 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
5006 stage_state
->stage
== MESA_SHADER_VERTEX
) {
5007 gen7_emit_vs_workaround_flush(brw
);
5010 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
5011 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
5012 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
5018 has_component(mesa_format format
, int i
)
5020 if (_mesa_is_format_color_format(format
))
5021 return _mesa_format_has_color_component(format
, i
);
5023 /* depth and stencil have only one component */
5028 * Upload SAMPLER_BORDER_COLOR_STATE.
5031 genX(upload_default_color
)(struct brw_context
*brw
,
5032 const struct gl_sampler_object
*sampler
,
5033 MAYBE_UNUSED mesa_format format
, GLenum base_format
,
5034 bool is_integer_format
, bool is_stencil_sampling
,
5035 uint32_t *sdc_offset
)
5037 union gl_color_union color
;
5039 switch (base_format
) {
5040 case GL_DEPTH_COMPONENT
:
5041 /* GL specs that border color for depth textures is taken from the
5042 * R channel, while the hardware uses A. Spam R into all the
5043 * channels for safety.
5045 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
5046 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
5047 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
5048 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
5054 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
5057 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
5058 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
5059 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
5060 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
5063 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
5064 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
5065 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
5066 color
.ui
[3] = float_as_int(1.0);
5068 case GL_LUMINANCE_ALPHA
:
5069 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
5070 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
5071 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
5072 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
5075 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
5076 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
5077 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
5078 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
5082 /* In some cases we use an RGBA surface format for GL RGB textures,
5083 * where we've initialized the A channel to 1.0. We also have to set
5084 * the border color alpha to 1.0 in that case.
5086 if (base_format
== GL_RGB
)
5087 color
.ui
[3] = float_as_int(1.0);
5092 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
5096 uint32_t *sdc
= brw_state_batch(
5097 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
5098 alignment
, sdc_offset
);
5100 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
5102 #define ASSIGN(dst, src) \
5107 #define ASSIGNu16(dst, src) \
5109 dst = (uint16_t)src; \
5112 #define ASSIGNu8(dst, src) \
5114 dst = (uint8_t)src; \
5117 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
5118 macro(state.BorderColor ## _color_type ## Red, src[0]); \
5119 macro(state.BorderColor ## _color_type ## Green, src[1]); \
5120 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
5121 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
5124 /* On Broadwell, the border color is represented as four 32-bit floats,
5125 * integers, or unsigned values, interpreted according to the surface
5126 * format. This matches the sampler->BorderColor union exactly; just
5127 * memcpy the values.
5129 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
5130 #elif GEN_IS_HASWELL
5131 if (is_integer_format
|| is_stencil_sampling
) {
5132 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
5133 const int bits_per_channel
=
5134 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
5136 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
5137 * "If any color channel is missing from the surface format,
5138 * corresponding border color should be programmed as zero and if
5139 * alpha channel is missing, corresponding Alpha border color should
5140 * be programmed as 1."
5142 unsigned c
[4] = { 0, 0, 0, 1 };
5143 for (int i
= 0; i
< 4; i
++) {
5144 if (has_component(format
, i
))
5148 switch (bits_per_channel
) {
5150 /* Copy RGBA in order. */
5151 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
5154 /* R10G10B10A2_UINT is treated like a 16-bit format. */
5156 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
5159 if (base_format
== GL_RG
) {
5160 /* Careful inspection of the tables reveals that for RG32 formats,
5161 * the green channel needs to go where blue normally belongs.
5163 state
.BorderColor32bitRed
= c
[0];
5164 state
.BorderColor32bitBlue
= c
[1];
5165 state
.BorderColor32bitAlpha
= 1;
5167 /* Copy RGBA in order. */
5168 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
5172 assert(!"Invalid number of bits per channel in integer format.");
5176 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5178 #elif GEN_GEN == 5 || GEN_GEN == 6
5179 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
5180 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
5181 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
5183 #define MESA_FLOAT_TO_HALF(dst, src) \
5184 dst = _mesa_float_to_half(src);
5186 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
5188 #undef MESA_FLOAT_TO_HALF
5190 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
5191 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
5192 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
5193 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
5195 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5197 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
5199 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
5203 #undef BORDER_COLOR_ATTR
5205 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
5209 translate_wrap_mode(GLenum wrap
, MAYBE_UNUSED
bool using_nearest
)
5216 /* GL_CLAMP is the weird mode where coordinates are clamped to
5217 * [0.0, 1.0], so linear filtering of coordinates outside of
5218 * [0.0, 1.0] give you half edge texel value and half border
5221 * Gen8+ supports this natively.
5223 return TCM_HALF_BORDER
;
5225 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
5226 * and set clamp_border here, which gets the result desired.
5227 * We just use clamp(_to_edge) for nearest, because for nearest
5228 * clamping to 1.0 gives border color instead of the desired
5234 return TCM_CLAMP_BORDER
;
5236 case GL_CLAMP_TO_EDGE
:
5238 case GL_CLAMP_TO_BORDER
:
5239 return TCM_CLAMP_BORDER
;
5240 case GL_MIRRORED_REPEAT
:
5242 case GL_MIRROR_CLAMP_TO_EDGE
:
5243 return TCM_MIRROR_ONCE
;
5250 * Return true if the given wrap mode requires the border color to exist.
5253 wrap_mode_needs_border_color(unsigned wrap_mode
)
5256 return wrap_mode
== TCM_CLAMP_BORDER
||
5257 wrap_mode
== TCM_HALF_BORDER
;
5259 return wrap_mode
== TCM_CLAMP_BORDER
;
5264 * Sets the sampler state for a single unit based off of the sampler key
5268 genX(update_sampler_state
)(struct brw_context
*brw
,
5269 GLenum target
, bool tex_cube_map_seamless
,
5270 GLfloat tex_unit_lod_bias
,
5271 mesa_format format
, GLenum base_format
,
5272 const struct gl_texture_object
*texObj
,
5273 const struct gl_sampler_object
*sampler
,
5274 uint32_t *sampler_state
)
5276 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
5278 /* Select min and mip filters. */
5279 switch (sampler
->MinFilter
) {
5281 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5282 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5285 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5286 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5288 case GL_NEAREST_MIPMAP_NEAREST
:
5289 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5290 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5292 case GL_LINEAR_MIPMAP_NEAREST
:
5293 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5294 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5296 case GL_NEAREST_MIPMAP_LINEAR
:
5297 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5298 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5300 case GL_LINEAR_MIPMAP_LINEAR
:
5301 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5302 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5305 unreachable("not reached");
5308 /* Select mag filter. */
5309 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5310 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5312 /* Enable anisotropic filtering if desired. */
5313 samp_st
.MaximumAnisotropy
= RATIO21
;
5315 if (sampler
->MaxAnisotropy
> 1.0f
) {
5316 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5317 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5318 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5319 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5321 if (sampler
->MaxAnisotropy
> 2.0f
) {
5322 samp_st
.MaximumAnisotropy
=
5323 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5327 /* Set address rounding bits if not using nearest filtering. */
5328 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5329 samp_st
.UAddressMinFilterRoundingEnable
= true;
5330 samp_st
.VAddressMinFilterRoundingEnable
= true;
5331 samp_st
.RAddressMinFilterRoundingEnable
= true;
5334 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5335 samp_st
.UAddressMagFilterRoundingEnable
= true;
5336 samp_st
.VAddressMagFilterRoundingEnable
= true;
5337 samp_st
.RAddressMagFilterRoundingEnable
= true;
5340 bool either_nearest
=
5341 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5342 unsigned wrap_s
= translate_wrap_mode(sampler
->WrapS
, either_nearest
);
5343 unsigned wrap_t
= translate_wrap_mode(sampler
->WrapT
, either_nearest
);
5344 unsigned wrap_r
= translate_wrap_mode(sampler
->WrapR
, either_nearest
);
5346 if (target
== GL_TEXTURE_CUBE_MAP
||
5347 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5348 /* Cube maps must use the same wrap mode for all three coordinate
5349 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5351 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5352 * integer formats. Fall back to CLAMP for now.
5354 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5355 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5364 } else if (target
== GL_TEXTURE_1D
) {
5365 /* There's a bug in 1D texture sampling - it actually pays
5366 * attention to the wrap_t value, though it should not.
5367 * Override the wrap_t value here to GL_REPEAT to keep
5368 * any nonexistent border pixels from floating in.
5373 samp_st
.TCXAddressControlMode
= wrap_s
;
5374 samp_st
.TCYAddressControlMode
= wrap_t
;
5375 samp_st
.TCZAddressControlMode
= wrap_r
;
5377 samp_st
.ShadowFunction
=
5378 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5379 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5382 /* Set shadow function. */
5383 samp_st
.AnisotropicAlgorithm
=
5384 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5385 EWAApproximation
: LEGACY
;
5389 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5392 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5393 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5394 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5395 samp_st
.TextureLODBias
=
5396 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5399 samp_st
.BaseMipLevel
=
5400 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5401 samp_st
.MinandMagStateNotEqual
=
5402 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5405 /* Upload the border color if necessary. If not, just point it at
5406 * offset 0 (the start of the batch) - the color should be ignored,
5407 * but that address won't fault in case something reads it anyway.
5409 uint32_t border_color_offset
= 0;
5410 if (wrap_mode_needs_border_color(wrap_s
) ||
5411 wrap_mode_needs_border_color(wrap_t
) ||
5412 wrap_mode_needs_border_color(wrap_r
)) {
5413 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5414 texObj
->_IsIntegerFormat
,
5415 texObj
->StencilSampling
,
5416 &border_color_offset
);
5419 samp_st
.BorderColorPointer
=
5420 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5422 samp_st
.BorderColorPointer
= border_color_offset
;
5426 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5428 samp_st
.LODPreClampEnable
= true;
5431 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5435 update_sampler_state(struct brw_context
*brw
,
5437 uint32_t *sampler_state
)
5439 struct gl_context
*ctx
= &brw
->ctx
;
5440 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5441 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5442 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5444 /* These don't use samplers at all. */
5445 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5448 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5449 genX(update_sampler_state
)(brw
, texObj
->Target
,
5450 ctx
->Texture
.CubeMapSeamless
,
5452 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5458 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5459 struct gl_program
*prog
,
5460 struct brw_stage_state
*stage_state
)
5462 struct gl_context
*ctx
= &brw
->ctx
;
5463 uint32_t sampler_count
= stage_state
->sampler_count
;
5465 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5467 if (sampler_count
== 0)
5470 /* SAMPLER_STATE is 4 DWords on all platforms. */
5471 const int dwords
= GENX(SAMPLER_STATE_length
);
5472 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5474 uint32_t *sampler_state
= brw_state_batch(brw
,
5475 sampler_count
* size_in_bytes
,
5476 32, &stage_state
->sampler_offset
);
5477 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5479 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5480 if (SamplersUsed
& (1 << s
)) {
5481 const unsigned unit
= prog
->SamplerUnits
[s
];
5482 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5483 update_sampler_state(brw
, unit
, sampler_state
);
5487 sampler_state
+= dwords
;
5490 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5491 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5492 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5494 /* Flag that the sampler state table pointer has changed; later atoms
5497 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5502 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5504 /* BRW_NEW_FRAGMENT_PROGRAM */
5505 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5506 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5509 static const struct brw_tracked_state
genX(fs_samplers
) = {
5511 .mesa
= _NEW_TEXTURE
,
5512 .brw
= BRW_NEW_BATCH
|
5514 BRW_NEW_FRAGMENT_PROGRAM
,
5516 .emit
= genX(upload_fs_samplers
),
5520 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5522 /* BRW_NEW_VERTEX_PROGRAM */
5523 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5524 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5527 static const struct brw_tracked_state
genX(vs_samplers
) = {
5529 .mesa
= _NEW_TEXTURE
,
5530 .brw
= BRW_NEW_BATCH
|
5532 BRW_NEW_VERTEX_PROGRAM
,
5534 .emit
= genX(upload_vs_samplers
),
5539 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5541 /* BRW_NEW_GEOMETRY_PROGRAM */
5542 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5546 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5550 static const struct brw_tracked_state
genX(gs_samplers
) = {
5552 .mesa
= _NEW_TEXTURE
,
5553 .brw
= BRW_NEW_BATCH
|
5555 BRW_NEW_GEOMETRY_PROGRAM
,
5557 .emit
= genX(upload_gs_samplers
),
5563 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5565 /* BRW_NEW_TESS_PROGRAMS */
5566 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5570 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5573 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5575 .mesa
= _NEW_TEXTURE
,
5576 .brw
= BRW_NEW_BATCH
|
5578 BRW_NEW_TESS_PROGRAMS
,
5580 .emit
= genX(upload_tcs_samplers
),
5586 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5588 /* BRW_NEW_TESS_PROGRAMS */
5589 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5593 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5596 static const struct brw_tracked_state
genX(tes_samplers
) = {
5598 .mesa
= _NEW_TEXTURE
,
5599 .brw
= BRW_NEW_BATCH
|
5601 BRW_NEW_TESS_PROGRAMS
,
5603 .emit
= genX(upload_tes_samplers
),
5609 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5611 /* BRW_NEW_COMPUTE_PROGRAM */
5612 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5616 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5619 const struct brw_tracked_state
genX(cs_samplers
) = {
5621 .mesa
= _NEW_TEXTURE
,
5622 .brw
= BRW_NEW_BATCH
|
5624 BRW_NEW_COMPUTE_PROGRAM
,
5626 .emit
= genX(upload_cs_samplers
),
5630 /* ---------------------------------------------------------------------- */
5634 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5636 struct gl_context
*ctx
= &brw
->ctx
;
5638 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5639 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5640 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5641 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5642 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5646 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5649 .brw
= BRW_NEW_CONTEXT
|
5652 .emit
= genX(upload_blend_constant_color
)
5656 /* ---------------------------------------------------------------------- */
5659 genX(init_atoms
)(struct brw_context
*brw
)
5662 static const struct brw_tracked_state
*render_atoms
[] =
5664 &genX(vf_statistics
),
5666 /* Once all the programs are done, we know how large urb entry
5667 * sizes need to be and can decide if we need to change the urb
5671 &brw_recalculate_urb_fence
,
5674 &genX(color_calc_state
),
5676 /* Surface state setup. Must come before the VS/WM unit. The binding
5677 * table upload must be last.
5679 &brw_vs_pull_constants
,
5680 &brw_wm_pull_constants
,
5681 &brw_renderbuffer_surfaces
,
5682 &brw_renderbuffer_read_surfaces
,
5683 &brw_texture_surfaces
,
5684 &brw_vs_binding_table
,
5685 &brw_wm_binding_table
,
5690 /* These set up state for brw_psp_urb_cbs */
5692 &genX(sf_clip_viewport
),
5694 &genX(vs_state
), /* always required, enabled or not */
5700 &brw_binding_table_pointers
,
5701 &genX(blend_constant_color
),
5705 &genX(polygon_stipple
),
5706 &genX(polygon_stipple_offset
),
5708 &genX(line_stipple
),
5712 &genX(drawing_rect
),
5713 &brw_indices
, /* must come before brw_vertices */
5714 &genX(index_buffer
),
5717 &brw_constant_buffer
5720 static const struct brw_tracked_state
*render_atoms
[] =
5722 &genX(vf_statistics
),
5724 &genX(sf_clip_viewport
),
5726 /* Command packets: */
5731 &genX(blend_state
), /* must do before cc unit */
5732 &genX(color_calc_state
), /* must do before cc unit */
5733 &genX(depth_stencil_state
), /* must do before cc unit */
5735 &genX(vs_push_constants
), /* Before vs_state */
5736 &genX(gs_push_constants
), /* Before gs_state */
5737 &genX(wm_push_constants
), /* Before wm_state */
5739 /* Surface state setup. Must come before the VS/WM unit. The binding
5740 * table upload must be last.
5742 &brw_vs_pull_constants
,
5743 &brw_vs_ubo_surfaces
,
5744 &brw_gs_pull_constants
,
5745 &brw_gs_ubo_surfaces
,
5746 &brw_wm_pull_constants
,
5747 &brw_wm_ubo_surfaces
,
5748 &gen6_renderbuffer_surfaces
,
5749 &brw_renderbuffer_read_surfaces
,
5750 &brw_texture_surfaces
,
5752 &brw_vs_binding_table
,
5753 &gen6_gs_binding_table
,
5754 &brw_wm_binding_table
,
5759 &gen6_sampler_state
,
5760 &genX(multisample_state
),
5768 &genX(scissor_state
),
5770 &gen6_binding_table_pointers
,
5774 &genX(polygon_stipple
),
5775 &genX(polygon_stipple_offset
),
5777 &genX(line_stipple
),
5779 &genX(drawing_rect
),
5781 &brw_indices
, /* must come before brw_vertices */
5782 &genX(index_buffer
),
5786 static const struct brw_tracked_state
*render_atoms
[] =
5788 &genX(vf_statistics
),
5790 /* Command packets: */
5793 &genX(sf_clip_viewport
),
5796 &gen7_push_constant_space
,
5798 &genX(blend_state
), /* must do before cc unit */
5799 &genX(color_calc_state
), /* must do before cc unit */
5800 &genX(depth_stencil_state
), /* must do before cc unit */
5802 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5803 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5804 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5805 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5806 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5808 &genX(vs_push_constants
), /* Before vs_state */
5809 &genX(tcs_push_constants
),
5810 &genX(tes_push_constants
),
5811 &genX(gs_push_constants
), /* Before gs_state */
5812 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5814 /* Surface state setup. Must come before the VS/WM unit. The binding
5815 * table upload must be last.
5817 &brw_vs_pull_constants
,
5818 &brw_vs_ubo_surfaces
,
5819 &brw_tcs_pull_constants
,
5820 &brw_tcs_ubo_surfaces
,
5821 &brw_tes_pull_constants
,
5822 &brw_tes_ubo_surfaces
,
5823 &brw_gs_pull_constants
,
5824 &brw_gs_ubo_surfaces
,
5825 &brw_wm_pull_constants
,
5826 &brw_wm_ubo_surfaces
,
5827 &gen6_renderbuffer_surfaces
,
5828 &brw_renderbuffer_read_surfaces
,
5829 &brw_texture_surfaces
,
5831 &genX(push_constant_packets
),
5833 &brw_vs_binding_table
,
5834 &brw_tcs_binding_table
,
5835 &brw_tes_binding_table
,
5836 &brw_gs_binding_table
,
5837 &brw_wm_binding_table
,
5841 &genX(tcs_samplers
),
5842 &genX(tes_samplers
),
5844 &genX(multisample_state
),
5858 &genX(scissor_state
),
5862 &genX(polygon_stipple
),
5863 &genX(polygon_stipple_offset
),
5865 &genX(line_stipple
),
5867 &genX(drawing_rect
),
5869 &brw_indices
, /* must come before brw_vertices */
5870 &genX(index_buffer
),
5878 static const struct brw_tracked_state
*render_atoms
[] =
5880 &genX(vf_statistics
),
5883 &genX(sf_clip_viewport
),
5886 &gen7_push_constant_space
,
5889 &genX(color_calc_state
),
5891 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5892 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5893 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5894 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5895 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5897 &genX(vs_push_constants
), /* Before vs_state */
5898 &genX(tcs_push_constants
),
5899 &genX(tes_push_constants
),
5900 &genX(gs_push_constants
), /* Before gs_state */
5901 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5903 /* Surface state setup. Must come before the VS/WM unit. The binding
5904 * table upload must be last.
5906 &brw_vs_pull_constants
,
5907 &brw_vs_ubo_surfaces
,
5908 &brw_tcs_pull_constants
,
5909 &brw_tcs_ubo_surfaces
,
5910 &brw_tes_pull_constants
,
5911 &brw_tes_ubo_surfaces
,
5912 &brw_gs_pull_constants
,
5913 &brw_gs_ubo_surfaces
,
5914 &brw_wm_pull_constants
,
5915 &brw_wm_ubo_surfaces
,
5916 &gen6_renderbuffer_surfaces
,
5917 &brw_renderbuffer_read_surfaces
,
5918 &brw_texture_surfaces
,
5920 &genX(push_constant_packets
),
5922 &brw_vs_binding_table
,
5923 &brw_tcs_binding_table
,
5924 &brw_tes_binding_table
,
5925 &brw_gs_binding_table
,
5926 &brw_wm_binding_table
,
5930 &genX(tcs_samplers
),
5931 &genX(tes_samplers
),
5933 &genX(multisample_state
),
5942 &genX(raster_state
),
5948 &genX(depth_stencil_state
),
5951 &genX(scissor_state
),
5955 &genX(polygon_stipple
),
5956 &genX(polygon_stipple_offset
),
5958 &genX(line_stipple
),
5960 &genX(drawing_rect
),
5965 &genX(index_buffer
),
5973 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5974 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5975 render_atoms
, ARRAY_SIZE(render_atoms
));
5978 static const struct brw_tracked_state
*compute_atoms
[] =
5981 &brw_cs_image_surfaces
,
5982 &genX(cs_push_constants
),
5983 &genX(cs_pull_constants
),
5984 &brw_cs_ubo_surfaces
,
5985 &brw_cs_texture_surfaces
,
5986 &brw_cs_work_groups_surface
,
5991 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5992 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5993 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5995 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);
5996 brw
->vtbl
.emit_compute_walker
= genX(emit_gpgpu_walker
);