2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 UNUSED
static struct brw_address
124 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
134 static struct brw_address
135 KSP(struct brw_context
*brw
, uint32_t offset
)
137 return ro_bo(brw
->cache
.bo
, offset
);
141 KSP(struct brw_context
*brw
, uint32_t offset
)
147 #include "genxml/genX_pack.h"
149 #define _brw_cmd_length(cmd) cmd ## _length
150 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
151 #define _brw_cmd_header(cmd) cmd ## _header
152 #define _brw_cmd_pack(cmd) cmd ## _pack
154 #define brw_batch_emit(brw, cmd, name) \
155 for (struct cmd name = { _brw_cmd_header(cmd) }, \
156 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
157 __builtin_expect(_dst != NULL, 1); \
158 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
161 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
162 uint32_t *_dw = emit_dwords(brw, n); \
163 struct cmd template = { \
164 _brw_cmd_header(cmd), \
165 .DWordLength = n - _brw_cmd_length_bias(cmd), \
168 _brw_cmd_pack(cmd)(brw, _dw, &template); \
169 _dw + 1; /* Array starts at dw[1] */ \
172 #define brw_state_emit(brw, cmd, align, offset, name) \
173 for (struct cmd name = {}, \
174 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
176 __builtin_expect(_dst != NULL, 1); \
177 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 * Polygon stipple packet
184 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
186 struct gl_context
*ctx
= &brw
->ctx
;
189 if (!ctx
->Polygon
.StippleFlag
)
192 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
193 /* Polygon stipple is provided in OpenGL order, i.e. bottom
194 * row first. If we're rendering to a window (i.e. the
195 * default frame buffer object, 0), then we need to invert
196 * it to match our pixel layout. But if we're rendering
197 * to a FBO (i.e. any named frame buffer object), we *don't*
198 * need to invert - we already match the layout.
200 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
201 for (unsigned i
= 0; i
< 32; i
++)
202 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
204 for (unsigned i
= 0; i
< 32; i
++)
205 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
210 static const struct brw_tracked_state
genX(polygon_stipple
) = {
212 .mesa
= _NEW_POLYGON
|
214 .brw
= BRW_NEW_CONTEXT
,
216 .emit
= genX(upload_polygon_stipple
),
220 * Polygon stipple offset packet
223 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
225 struct gl_context
*ctx
= &brw
->ctx
;
228 if (!ctx
->Polygon
.StippleFlag
)
231 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
234 * If we're drawing to a system window we have to invert the Y axis
235 * in order to match the OpenGL pixel coordinate system, and our
236 * offset must be matched to the window position. If we're drawing
237 * to a user-created FBO then our native pixel coordinate system
238 * works just fine, and there's no window system to worry about.
240 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
241 poly
.PolygonStippleYOffset
=
242 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
247 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
249 .mesa
= _NEW_BUFFERS
|
251 .brw
= BRW_NEW_CONTEXT
,
253 .emit
= genX(upload_polygon_stipple_offset
),
257 * Line stipple packet
260 genX(upload_line_stipple
)(struct brw_context
*brw
)
262 struct gl_context
*ctx
= &brw
->ctx
;
264 if (!ctx
->Line
.StippleFlag
)
267 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
268 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
270 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
271 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
275 static const struct brw_tracked_state
genX(line_stipple
) = {
278 .brw
= BRW_NEW_CONTEXT
,
280 .emit
= genX(upload_line_stipple
),
283 /* Constant single cliprect for framebuffer object or DRI2 drawing */
285 genX(upload_drawing_rect
)(struct brw_context
*brw
)
287 struct gl_context
*ctx
= &brw
->ctx
;
288 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
289 const unsigned int fb_width
= _mesa_geometric_width(fb
);
290 const unsigned int fb_height
= _mesa_geometric_height(fb
);
292 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
293 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
294 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
298 static const struct brw_tracked_state
genX(drawing_rect
) = {
300 .mesa
= _NEW_BUFFERS
,
301 .brw
= BRW_NEW_BLORP
|
304 .emit
= genX(upload_drawing_rect
),
308 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
312 unsigned start_offset
,
317 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
318 .VertexBufferIndex
= buffer_nr
,
319 .BufferPitch
= stride
,
320 .BufferStartingAddress
= ro_bo(bo
, start_offset
),
322 .BufferSize
= end_offset
- start_offset
,
326 .AddressModifyEnable
= true,
330 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
331 .InstanceDataStepRate
= step_rate
,
333 .EndAddress
= ro_bo(bo
, end_offset
- 1),
338 .VertexBufferMOCS
= ICL_MOCS_WB
,
340 .VertexBufferMOCS
= CNL_MOCS_WB
,
342 .VertexBufferMOCS
= SKL_MOCS_WB
,
344 .VertexBufferMOCS
= BDW_MOCS_WB
,
346 .VertexBufferMOCS
= GEN7_MOCS_L3
,
350 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
351 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
355 is_passthru_format(uint32_t format
)
358 case ISL_FORMAT_R64_PASSTHRU
:
359 case ISL_FORMAT_R64G64_PASSTHRU
:
360 case ISL_FORMAT_R64G64B64_PASSTHRU
:
361 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
369 uploads_needed(uint32_t format
,
372 if (!is_passthru_format(format
))
379 case ISL_FORMAT_R64_PASSTHRU
:
380 case ISL_FORMAT_R64G64_PASSTHRU
:
382 case ISL_FORMAT_R64G64B64_PASSTHRU
:
383 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
386 unreachable("not reached");
391 * Returns the format that we are finally going to use when upload a vertex
392 * element. It will only change if we are using *64*PASSTHRU formats, as for
393 * gen < 8 they need to be splitted on two *32*FLOAT formats.
395 * @upload points in which upload we are. Valid values are [0,1]
398 downsize_format_if_needed(uint32_t format
,
401 assert(upload
== 0 || upload
== 1);
403 if (!is_passthru_format(format
))
406 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
407 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
408 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
409 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
410 * flagging that we want to fill with zeroes this second forced upload.
413 case ISL_FORMAT_R64_PASSTHRU
:
414 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
415 : ISL_FORMAT_R32_FLOAT
;
416 case ISL_FORMAT_R64G64_PASSTHRU
:
417 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
418 : ISL_FORMAT_R32_FLOAT
;
419 case ISL_FORMAT_R64G64B64_PASSTHRU
:
420 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
421 : ISL_FORMAT_R32G32_FLOAT
;
422 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
423 return ISL_FORMAT_R32G32B32A32_FLOAT
;
425 unreachable("not reached");
430 * Returns the number of componentes associated with a format that is used on
431 * a 64 to 32 format split. See downsize_format()
434 upload_format_size(uint32_t upload_format
)
436 switch (upload_format
) {
437 case ISL_FORMAT_R32_FLOAT
:
439 /* downsized_format has returned this one in order to flag that we are
440 * performing a second upload which we want to have filled with
441 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
442 * vertex shader input variables.
446 case ISL_FORMAT_R32G32_FLOAT
:
448 case ISL_FORMAT_R32G32B32A32_FLOAT
:
451 unreachable("not reached");
456 genX(emit_vertices
)(struct brw_context
*brw
)
458 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
461 brw_prepare_vertices(brw
);
462 brw_prepare_shader_draw_parameters(brw
);
465 brw_emit_query_begin(brw
);
468 const struct brw_vs_prog_data
*vs_prog_data
=
469 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
472 struct gl_context
*ctx
= &brw
->ctx
;
473 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
474 ctx
->Polygon
.BackMode
!= GL_FILL
);
476 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
477 unsigned vue
= brw
->vb
.nr_enabled
;
479 /* The element for the edge flags must always be last, so we have to
480 * insert the SGVS before it in that case.
482 if (uses_edge_flag
) {
488 "Trying to insert VID/IID past 33rd vertex element, "
489 "need to reorder the vertex attrbutes.");
491 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
492 if (vs_prog_data
->uses_vertexid
) {
493 vfs
.VertexIDEnable
= true;
494 vfs
.VertexIDComponentNumber
= 2;
495 vfs
.VertexIDElementOffset
= vue
;
498 if (vs_prog_data
->uses_instanceid
) {
499 vfs
.InstanceIDEnable
= true;
500 vfs
.InstanceIDComponentNumber
= 3;
501 vfs
.InstanceIDElementOffset
= vue
;
505 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
506 vfi
.InstancingEnable
= true;
507 vfi
.VertexElementIndex
= vue
;
510 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
514 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
515 vs_prog_data
->uses_baseinstance
||
516 vs_prog_data
->uses_instanceid
||
517 vs_prog_data
->uses_vertexid
);
519 unsigned nr_elements
=
520 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
523 /* If any of the formats of vb.enabled needs more that one upload, we need
524 * to add it to nr_elements
526 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
527 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
528 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
530 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
535 /* If the VS doesn't read any inputs (calculating vertex position from
536 * a state variable for some reason, for example), emit a single pad
537 * VERTEX_ELEMENT struct and bail.
539 * The stale VB state stays in place, but they don't do anything unless
540 * a VE loads from them.
542 if (nr_elements
== 0) {
543 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
544 1 + GENX(VERTEX_ELEMENT_STATE_length
));
545 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
547 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
548 .Component0Control
= VFCOMP_STORE_0
,
549 .Component1Control
= VFCOMP_STORE_0
,
550 .Component2Control
= VFCOMP_STORE_0
,
551 .Component3Control
= VFCOMP_STORE_1_FP
,
553 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
557 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
558 const bool uses_draw_params
=
559 vs_prog_data
->uses_basevertex
||
560 vs_prog_data
->uses_baseinstance
;
561 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
562 uses_draw_params
+ vs_prog_data
->uses_drawid
;
565 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
567 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
568 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
570 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
571 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
572 /* Prior to Haswell and Bay Trail we have to use 4-component formats
573 * to fake 3-component ones. In particular, we do this for
574 * half-float and 8 and 16-bit integer formats. This means that the
575 * vertex element may poke over the end of the buffer by 2 bytes.
577 const unsigned padding
=
578 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
579 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
580 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
587 if (uses_draw_params
) {
588 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
589 brw
->draw
.draw_params_bo
,
590 brw
->draw
.draw_params_offset
,
591 brw
->draw
.draw_params_bo
->size
,
596 if (vs_prog_data
->uses_drawid
) {
597 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
598 brw
->draw
.draw_id_bo
,
599 brw
->draw
.draw_id_offset
,
600 brw
->draw
.draw_id_bo
->size
,
606 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
607 * presumably for VertexID/InstanceID.
610 assert(nr_elements
<= 34);
611 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
613 assert(nr_elements
<= 18);
616 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
617 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
619 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
620 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
621 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
622 uint32_t comp0
= VFCOMP_STORE_SRC
;
623 uint32_t comp1
= VFCOMP_STORE_SRC
;
624 uint32_t comp2
= VFCOMP_STORE_SRC
;
625 uint32_t comp3
= VFCOMP_STORE_SRC
;
626 const unsigned num_uploads
= GEN_GEN
< 8 ?
627 uploads_needed(format
, input
->is_dual_slot
) : 1;
630 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
631 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
632 * element which has edge flag enabled."
634 assert(!(is_passthru_format(format
) && uses_edge_flag
));
637 /* The gen4 driver expects edgeflag to come in as a float, and passes
638 * that float on to the tests in the clipper. Mesa's current vertex
639 * attribute value for EdgeFlag is stored as a float, which works out.
640 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
641 * integer ubyte. Just rewrite that to convert to a float.
643 * Gen6+ passes edgeflag as sideband along with the vertex, instead
644 * of in the VUE. We have to upload it sideband as the last vertex
645 * element according to the B-Spec.
648 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
649 gen6_edgeflag_input
= input
;
654 for (unsigned c
= 0; c
< num_uploads
; c
++) {
655 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
656 downsize_format_if_needed(format
, c
);
657 /* If we need more that one upload, the offset stride would be 128
658 * bits (16 bytes), as for previous uploads we are using the full
660 const unsigned offset
= input
->offset
+ c
* 16;
662 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
663 upload_format_size(upload_format
) : input
->glarray
->Size
;
666 case 0: comp0
= VFCOMP_STORE_0
;
667 case 1: comp1
= VFCOMP_STORE_0
;
668 case 2: comp2
= VFCOMP_STORE_0
;
670 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
671 comp3
= VFCOMP_STORE_0
;
672 } else if (input
->glarray
->Integer
) {
673 comp3
= VFCOMP_STORE_1_INT
;
675 comp3
= VFCOMP_STORE_1_FP
;
682 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
684 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
685 * formats, 64-bit components are stored in the URB without any
686 * conversion. In this case, vertex elements must be written as 128
687 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
688 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
689 * component into the URB, Component 1 must be specified as
690 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
691 * order to output a 128-bit vertex element, or Components 1-3 must
692 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
693 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
694 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
697 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
698 /* Store vertex elements which correspond to double and dvec2 vertex
699 * shader inputs as 128-bit vertex elements, instead of 256-bits.
701 comp2
= VFCOMP_NOSTORE
;
702 comp3
= VFCOMP_NOSTORE
;
706 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
707 .VertexBufferIndex
= input
->buffer
,
709 .SourceElementFormat
= upload_format
,
710 .SourceElementOffset
= offset
,
711 .Component0Control
= comp0
,
712 .Component1Control
= comp1
,
713 .Component2Control
= comp2
,
714 .Component3Control
= comp3
,
716 .DestinationElementOffset
= i
* 4,
720 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
721 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
725 if (needs_sgvs_element
) {
726 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
728 .Component0Control
= VFCOMP_STORE_0
,
729 .Component1Control
= VFCOMP_STORE_0
,
730 .Component2Control
= VFCOMP_STORE_0
,
731 .Component3Control
= VFCOMP_STORE_0
,
733 .DestinationElementOffset
= i
* 4,
738 if (vs_prog_data
->uses_basevertex
||
739 vs_prog_data
->uses_baseinstance
) {
740 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
741 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
742 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
743 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
746 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
747 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
748 if (vs_prog_data
->uses_basevertex
)
749 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
751 if (vs_prog_data
->uses_baseinstance
)
752 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
754 if (vs_prog_data
->uses_vertexid
)
755 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
757 if (vs_prog_data
->uses_instanceid
)
758 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
761 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
762 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
765 if (vs_prog_data
->uses_drawid
) {
766 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
768 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
769 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32_UINT
,
770 .Component0Control
= VFCOMP_STORE_SRC
,
771 .Component1Control
= VFCOMP_STORE_0
,
772 .Component2Control
= VFCOMP_STORE_0
,
773 .Component3Control
= VFCOMP_STORE_0
,
775 .DestinationElementOffset
= i
* 4,
779 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
780 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
784 if (gen6_edgeflag_input
) {
785 const uint32_t format
=
786 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
788 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
790 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
791 .EdgeFlagEnable
= true,
792 .SourceElementFormat
= format
,
793 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
794 .Component0Control
= VFCOMP_STORE_SRC
,
795 .Component1Control
= VFCOMP_STORE_0
,
796 .Component2Control
= VFCOMP_STORE_0
,
797 .Component3Control
= VFCOMP_STORE_0
,
800 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
801 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
806 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
807 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
808 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
809 unsigned element_index
;
811 /* The edge flag element is reordered to be the last one in the code
812 * above so we need to compensate for that in the element indices used
815 if (input
== gen6_edgeflag_input
)
816 element_index
= nr_elements
- 1;
820 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
821 vfi
.VertexElementIndex
= element_index
;
822 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
823 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
827 if (vs_prog_data
->uses_drawid
) {
828 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
830 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
831 vfi
.VertexElementIndex
= element
;
837 static const struct brw_tracked_state
genX(vertices
) = {
839 .mesa
= _NEW_POLYGON
,
840 .brw
= BRW_NEW_BATCH
|
843 BRW_NEW_VS_PROG_DATA
,
845 .emit
= genX(emit_vertices
),
849 genX(emit_index_buffer
)(struct brw_context
*brw
)
851 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
853 if (index_buffer
== NULL
)
856 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
857 #if GEN_GEN < 8 && !GEN_IS_HASWELL
858 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
860 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
861 ib
.BufferStartingAddress
= ro_bo(brw
->ib
.bo
, 0);
863 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
864 ib
.BufferSize
= brw
->ib
.size
;
866 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
871 static const struct brw_tracked_state
genX(index_buffer
) = {
874 .brw
= BRW_NEW_BATCH
|
876 BRW_NEW_INDEX_BUFFER
,
878 .emit
= genX(emit_index_buffer
),
881 #if GEN_IS_HASWELL || GEN_GEN >= 8
883 genX(upload_cut_index
)(struct brw_context
*brw
)
885 const struct gl_context
*ctx
= &brw
->ctx
;
887 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
888 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
889 vf
.IndexedDrawCutIndexEnable
= true;
890 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
895 const struct brw_tracked_state
genX(cut_index
) = {
897 .mesa
= _NEW_TRANSFORM
,
898 .brw
= BRW_NEW_INDEX_BUFFER
,
900 .emit
= genX(upload_cut_index
),
906 * Determine the appropriate attribute override value to store into the
907 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
908 * override value contains two pieces of information: the location of the
909 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
910 * flag indicating whether to "swizzle" the attribute based on the direction
911 * the triangle is facing.
913 * If an attribute is "swizzled", then the given VUE location is used for
914 * front-facing triangles, and the VUE location that immediately follows is
915 * used for back-facing triangles. We use this to implement the mapping from
916 * gl_FrontColor/gl_BackColor to gl_Color.
918 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
919 * being instructed to begin reading attribute data. It can be set to a
920 * nonzero value to prevent the SF unit from wasting time reading elements of
921 * the VUE that are not needed by the fragment shader. It is measured in
922 * 256-bit increments.
925 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
926 const struct brw_vue_map
*vue_map
,
927 int urb_entry_read_offset
, int fs_attr
,
928 bool two_side_color
, uint32_t *max_source_attr
)
930 /* Find the VUE slot for this attribute. */
931 int slot
= vue_map
->varying_to_slot
[fs_attr
];
933 /* Viewport and Layer are stored in the VUE header. We need to override
934 * them to zero if earlier stages didn't write them, as GL requires that
935 * they read back as zero when not explicitly set.
937 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
938 attr
->ComponentOverrideX
= true;
939 attr
->ComponentOverrideW
= true;
940 attr
->ConstantSource
= CONST_0000
;
942 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
943 attr
->ComponentOverrideY
= true;
944 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
945 attr
->ComponentOverrideZ
= true;
950 /* If there was only a back color written but not front, use back
951 * as the color instead of undefined
953 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
954 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
955 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
956 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
959 /* This attribute does not exist in the VUE--that means that the vertex
960 * shader did not write to it. This means that either:
962 * (a) This attribute is a texture coordinate, and it is going to be
963 * replaced with point coordinates (as a consequence of a call to
964 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
965 * hardware will ignore whatever attribute override we supply.
967 * (b) This attribute is read by the fragment shader but not written by
968 * the vertex shader, so its value is undefined. Therefore the
969 * attribute override we supply doesn't matter.
971 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
972 * previous shader stage.
974 * Note that we don't have to worry about the cases where the attribute
975 * is gl_PointCoord or is undergoing point sprite coordinate
976 * replacement, because in those cases, this function isn't called.
978 * In case (c), we need to program the attribute overrides so that the
979 * primitive ID will be stored in this slot. In every other case, the
980 * attribute override we supply doesn't matter. So just go ahead and
981 * program primitive ID in every case.
983 attr
->ComponentOverrideW
= true;
984 attr
->ComponentOverrideX
= true;
985 attr
->ComponentOverrideY
= true;
986 attr
->ComponentOverrideZ
= true;
987 attr
->ConstantSource
= PRIM_ID
;
991 /* Compute the location of the attribute relative to urb_entry_read_offset.
992 * Each increment of urb_entry_read_offset represents a 256-bit value, so
993 * it counts for two 128-bit VUE slots.
995 int source_attr
= slot
- 2 * urb_entry_read_offset
;
996 assert(source_attr
>= 0 && source_attr
< 32);
998 /* If we are doing two-sided color, and the VUE slot following this one
999 * represents a back-facing color, then we need to instruct the SF unit to
1000 * do back-facing swizzling.
1002 bool swizzling
= two_side_color
&&
1003 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1004 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1005 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1006 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1008 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1009 if (*max_source_attr
< source_attr
+ swizzling
)
1010 *max_source_attr
= source_attr
+ swizzling
;
1012 attr
->SourceAttribute
= source_attr
;
1014 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1019 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1020 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1021 uint32_t *point_sprite_enables
,
1022 uint32_t *urb_entry_read_length
,
1023 uint32_t *urb_entry_read_offset
)
1025 const struct gl_context
*ctx
= &brw
->ctx
;
1028 const struct gl_point_attrib
*point
= &ctx
->Point
;
1030 /* BRW_NEW_FRAGMENT_PROGRAM */
1031 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1033 /* BRW_NEW_FS_PROG_DATA */
1034 const struct brw_wm_prog_data
*wm_prog_data
=
1035 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1036 uint32_t max_source_attr
= 0;
1038 *point_sprite_enables
= 0;
1041 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1042 &brw
->vue_map_geom_out
);
1044 /* Each URB offset packs two varying slots */
1045 assert(first_slot
% 2 == 0);
1046 *urb_entry_read_offset
= first_slot
/ 2;
1048 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1049 * description of dw10 Point Sprite Texture Coordinate Enable:
1051 * "This field must be programmed to zero when non-point primitives
1054 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1055 * must be programmed to zero when rendering non-point primitives, but
1056 * the IvyBridge PRM does, and if we don't, we get garbage.
1058 * This is not required on Haswell, as the hardware ignores this state
1059 * when drawing non-points -- although we do still need to be careful to
1060 * correctly set the attr overrides.
1063 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1065 bool drawing_points
= brw_is_drawing_points(brw
);
1067 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1068 int input_index
= wm_prog_data
->urb_setup
[attr
];
1070 if (input_index
< 0)
1074 bool point_sprite
= false;
1075 if (drawing_points
) {
1076 if (point
->PointSprite
&&
1077 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1078 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1079 point_sprite
= true;
1082 if (attr
== VARYING_SLOT_PNTC
)
1083 point_sprite
= true;
1086 *point_sprite_enables
|= (1 << input_index
);
1089 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1090 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1092 if (!point_sprite
) {
1093 genX(get_attr_override
)(&attribute
,
1094 &brw
->vue_map_geom_out
,
1095 *urb_entry_read_offset
, attr
,
1096 _mesa_vertex_program_two_side_enabled(ctx
),
1100 /* The hardware can only do the overrides on 16 overrides at a
1101 * time, and the other up to 16 have to be lined up so that the
1102 * input index = the output index. We'll need to do some
1103 * tweaking to make sure that's the case.
1105 if (input_index
< 16)
1106 attr_overrides
[input_index
] = attribute
;
1108 assert(attribute
.SourceAttribute
== input_index
);
1111 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1112 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1114 * "This field should be set to the minimum length required to read the
1115 * maximum source attribute. The maximum source attribute is indicated
1116 * by the maximum value of the enabled Attribute # Source Attribute if
1117 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1118 * enable is not set.
1119 * read_length = ceiling((max_source_attr + 1) / 2)
1121 * [errata] Corruption/Hang possible if length programmed larger than
1124 * Similar text exists for Ivy Bridge.
1126 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1130 /* ---------------------------------------------------------------------- */
1133 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1135 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1137 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1141 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1143 struct gl_context
*ctx
= &brw
->ctx
;
1146 struct intel_renderbuffer
*depth_irb
=
1147 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1150 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1153 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1154 const int b
= stencil
->_BackFace
;
1156 if (depth
->Test
&& depth_irb
) {
1157 ds
->DepthTestEnable
= true;
1158 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1159 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1162 if (brw
->stencil_enabled
) {
1163 ds
->StencilTestEnable
= true;
1164 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1165 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1167 ds
->StencilTestFunction
=
1168 intel_translate_compare_func(stencil
->Function
[0]);
1170 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1171 ds
->StencilPassDepthPassOp
=
1172 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1173 ds
->StencilPassDepthFailOp
=
1174 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1176 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1178 if (brw
->stencil_two_sided
) {
1179 ds
->DoubleSidedStencilEnable
= true;
1180 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1181 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1183 ds
->BackfaceStencilTestFunction
=
1184 intel_translate_compare_func(stencil
->Function
[b
]);
1185 ds
->BackfaceStencilFailOp
=
1186 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1187 ds
->BackfaceStencilPassDepthPassOp
=
1188 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1189 ds
->BackfaceStencilPassDepthFailOp
=
1190 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1193 #if GEN_GEN <= 5 || GEN_GEN >= 9
1194 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1195 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1202 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1205 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1206 set_depth_stencil_bits(brw
, &wmds
);
1210 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1211 set_depth_stencil_bits(brw
, &ds
);
1214 /* Now upload a pointer to the indirect state */
1216 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1217 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1218 ptr
.DEPTH_STENCIL_STATEChange
= true;
1221 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1222 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1228 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1230 .mesa
= _NEW_BUFFERS
|
1233 .brw
= BRW_NEW_BLORP
|
1234 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1236 BRW_NEW_STATE_BASE_ADDRESS
),
1238 .emit
= genX(upload_depth_stencil_state
),
1242 /* ---------------------------------------------------------------------- */
1247 genX(upload_clip_state
)(struct brw_context
*brw
)
1249 struct gl_context
*ctx
= &brw
->ctx
;
1251 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1252 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1253 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1254 clip
.GRFRegisterCount
=
1255 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1256 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1257 clip
.SingleProgramFlow
= true;
1258 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1259 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1261 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1262 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1263 clip
.DispatchGRFStartRegisterForURBData
= 1;
1264 clip
.VertexURBEntryReadOffset
= 0;
1266 /* BRW_NEW_URB_FENCE */
1267 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1268 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1270 if (brw
->urb
.nr_clip_entries
>= 10) {
1271 /* Half of the URB entries go to each thread, and it has to be an
1274 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1276 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1277 * only 2 threads can output VUEs at a time.
1279 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1281 assert(brw
->urb
.nr_clip_entries
>= 5);
1282 clip
.MaximumNumberofThreads
= 1 - 1;
1285 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1286 clip
.UserClipFlagsMustClipEnable
= true;
1287 clip
.GuardbandClipTestEnable
= true;
1289 clip
.ClipperViewportStatePointer
=
1290 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1292 clip
.ScreenSpaceViewportXMin
= -1;
1293 clip
.ScreenSpaceViewportXMax
= 1;
1294 clip
.ScreenSpaceViewportYMin
= -1;
1295 clip
.ScreenSpaceViewportYMax
= 1;
1297 clip
.ViewportXYClipTestEnable
= true;
1298 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1300 /* _NEW_TRANSFORM */
1301 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1302 clip
.UserClipDistanceClipTestEnableBitmask
=
1303 ctx
->Transform
.ClipPlanesEnabled
;
1305 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1308 clip
.UserClipDistanceClipTestEnableBitmask
=
1309 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1312 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1313 clip
.APIMode
= APIMODE_D3D
;
1315 clip
.APIMode
= APIMODE_OGL
;
1317 clip
.GuardbandClipTestEnable
= true;
1319 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1322 clip
.NegativeWClipTestEnable
= true;
1327 const struct brw_tracked_state
genX(clip_state
) = {
1329 .mesa
= _NEW_TRANSFORM
|
1331 .brw
= BRW_NEW_BATCH
|
1333 BRW_NEW_CLIP_PROG_DATA
|
1334 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1335 BRW_NEW_PROGRAM_CACHE
|
1338 .emit
= genX(upload_clip_state
),
1344 genX(upload_clip_state
)(struct brw_context
*brw
)
1346 struct gl_context
*ctx
= &brw
->ctx
;
1349 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1351 /* BRW_NEW_FS_PROG_DATA */
1352 struct brw_wm_prog_data
*wm_prog_data
=
1353 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1355 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1356 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1358 if (wm_prog_data
->barycentric_interp_modes
&
1359 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1360 clip
.NonPerspectiveBarycentricEnable
= true;
1363 clip
.EarlyCullEnable
= true;
1367 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1369 if (ctx
->Polygon
.CullFlag
) {
1370 switch (ctx
->Polygon
.CullFaceMode
) {
1372 clip
.CullMode
= CULLMODE_FRONT
;
1375 clip
.CullMode
= CULLMODE_BACK
;
1377 case GL_FRONT_AND_BACK
:
1378 clip
.CullMode
= CULLMODE_BOTH
;
1381 unreachable("Should not get here: invalid CullFlag");
1384 clip
.CullMode
= CULLMODE_NONE
;
1389 clip
.UserClipDistanceCullTestEnableBitmask
=
1390 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1392 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1396 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1397 clip
.TriangleStripListProvokingVertexSelect
= 0;
1398 clip
.TriangleFanProvokingVertexSelect
= 1;
1399 clip
.LineStripListProvokingVertexSelect
= 0;
1401 clip
.TriangleStripListProvokingVertexSelect
= 2;
1402 clip
.TriangleFanProvokingVertexSelect
= 2;
1403 clip
.LineStripListProvokingVertexSelect
= 1;
1406 /* _NEW_TRANSFORM */
1407 clip
.UserClipDistanceClipTestEnableBitmask
=
1408 ctx
->Transform
.ClipPlanesEnabled
;
1411 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1414 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1415 clip
.APIMode
= APIMODE_D3D
;
1417 clip
.APIMode
= APIMODE_OGL
;
1419 clip
.GuardbandClipTestEnable
= true;
1421 /* BRW_NEW_VIEWPORT_COUNT */
1422 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1424 if (ctx
->RasterDiscard
) {
1425 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1427 perf_debug("Rasterizer discard is currently implemented via the "
1428 "clipper; having the GS not write primitives would "
1429 "likely be faster.\n");
1432 clip
.ClipMode
= CLIPMODE_NORMAL
;
1435 clip
.ClipEnable
= true;
1438 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1440 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1441 clip
.ViewportXYClipTestEnable
= true;
1443 clip
.MinimumPointWidth
= 0.125;
1444 clip
.MaximumPointWidth
= 255.875;
1445 clip
.MaximumVPIndex
= viewport_count
- 1;
1446 if (_mesa_geometric_layers(fb
) == 0)
1447 clip
.ForceZeroRTAIndexEnable
= true;
1451 static const struct brw_tracked_state
genX(clip_state
) = {
1453 .mesa
= _NEW_BUFFERS
|
1457 .brw
= BRW_NEW_BLORP
|
1459 BRW_NEW_FS_PROG_DATA
|
1460 BRW_NEW_GS_PROG_DATA
|
1461 BRW_NEW_VS_PROG_DATA
|
1462 BRW_NEW_META_IN_PROGRESS
|
1464 BRW_NEW_RASTERIZER_DISCARD
|
1465 BRW_NEW_TES_PROG_DATA
|
1466 BRW_NEW_VIEWPORT_COUNT
,
1468 .emit
= genX(upload_clip_state
),
1472 /* ---------------------------------------------------------------------- */
1475 genX(upload_sf
)(struct brw_context
*brw
)
1477 struct gl_context
*ctx
= &brw
->ctx
;
1482 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1483 UNUSED
const bool multisampled_fbo
=
1484 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1488 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1490 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1492 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1493 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1494 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1495 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1496 sf
.DispatchGRFStartRegisterForURBData
= 3;
1497 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1498 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1499 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1500 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1502 /* STATE_PREFETCH command description describes this state as being
1503 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1506 sf
.SetupViewportStateOffset
=
1507 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1509 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1511 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1512 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1514 sf
.MaximumNumberofThreads
=
1515 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1517 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1519 sf
.DestinationOriginHorizontalBias
= 0.5;
1520 sf
.DestinationOriginVerticalBias
= 0.5;
1522 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1523 sf
.StatisticsEnable
= true;
1525 sf
.ViewportTransformEnable
= true;
1529 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1534 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1536 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1537 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1538 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1540 switch (ctx
->Polygon
.FrontMode
) {
1542 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1545 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1548 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1551 unreachable("not reached");
1554 switch (ctx
->Polygon
.BackMode
) {
1556 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1559 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1562 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1565 unreachable("not reached");
1568 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1569 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1571 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1572 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1573 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1576 sf
.ScissorRectangleEnable
= true;
1578 if (ctx
->Polygon
.CullFlag
) {
1579 switch (ctx
->Polygon
.CullFaceMode
) {
1581 sf
.CullMode
= CULLMODE_FRONT
;
1584 sf
.CullMode
= CULLMODE_BACK
;
1586 case GL_FRONT_AND_BACK
:
1587 sf
.CullMode
= CULLMODE_BOTH
;
1590 unreachable("not reached");
1593 sf
.CullMode
= CULLMODE_NONE
;
1597 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1604 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1606 if (devinfo
->is_cherryview
)
1607 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1609 sf
.LineWidth
= brw_get_line_width(brw
);
1611 sf
.LineWidth
= brw_get_line_width(brw
);
1614 if (ctx
->Line
.SmoothFlag
) {
1615 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1617 sf
.AntiAliasingEnable
= true;
1621 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1622 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1623 /* Clamp to the hardware limits */
1624 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1626 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1627 if (use_state_point_size(brw
))
1628 sf
.PointWidthSource
= State
;
1631 /* _NEW_POINT | _NEW_MULTISAMPLE */
1632 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1633 !ctx
->Point
.PointSprite
)
1634 sf
.SmoothPointEnable
= true;
1639 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1641 const bool multisampled_fbo
=
1642 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1643 if (multisampled_fbo
)
1644 sf
.SmoothPointEnable
= false;
1647 #if GEN_IS_G4X || GEN_GEN >= 5
1648 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1652 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1653 sf
.TriangleStripListProvokingVertexSelect
= 2;
1654 sf
.TriangleFanProvokingVertexSelect
= 2;
1655 sf
.LineStripListProvokingVertexSelect
= 1;
1657 sf
.TriangleFanProvokingVertexSelect
= 1;
1661 /* BRW_NEW_FS_PROG_DATA */
1662 const struct brw_wm_prog_data
*wm_prog_data
=
1663 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1665 sf
.AttributeSwizzleEnable
= true;
1666 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1669 * Window coordinates in an FBO are inverted, which means point
1670 * sprite origin must be inverted, too.
1672 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1673 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1675 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1678 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1679 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1681 uint32_t urb_entry_read_length
;
1682 uint32_t urb_entry_read_offset
;
1683 uint32_t point_sprite_enables
;
1684 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1685 &urb_entry_read_length
,
1686 &urb_entry_read_offset
);
1687 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1688 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1689 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1690 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1695 static const struct brw_tracked_state
genX(sf_state
) = {
1697 .mesa
= _NEW_LIGHT
|
1701 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1702 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1703 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1704 .brw
= BRW_NEW_BLORP
|
1705 BRW_NEW_VUE_MAP_GEOM_OUT
|
1706 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1707 BRW_NEW_PROGRAM_CACHE
|
1708 BRW_NEW_SF_PROG_DATA
|
1712 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1713 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1714 BRW_NEW_GS_PROG_DATA
|
1716 BRW_NEW_TES_PROG_DATA
1718 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1719 BRW_NEW_FRAGMENT_PROGRAM
1722 .emit
= genX(upload_sf
),
1725 /* ---------------------------------------------------------------------- */
1728 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1730 struct gl_context
*ctx
= &brw
->ctx
;
1731 /* BRW_NEW_FRAGMENT_PROGRAM */
1732 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1736 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1737 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1738 uint64_t outputs_written
= fp
->info
.outputs_written
;
1741 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1742 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1743 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1752 genX(upload_wm
)(struct brw_context
*brw
)
1754 struct gl_context
*ctx
= &brw
->ctx
;
1756 /* BRW_NEW_FS_PROG_DATA */
1757 const struct brw_wm_prog_data
*wm_prog_data
=
1758 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1760 UNUSED
bool writes_depth
=
1761 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1762 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1763 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1766 /* We can't fold this into gen6_upload_wm_push_constants(), because
1767 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1768 * (3DSTATE_CONSTANT_PS [DevSNB]):
1770 * "[DevSNB]: This packet must be followed by WM_STATE."
1772 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1773 if (wm_prog_data
->base
.nr_params
!= 0) {
1774 wmcp
.Buffer0Valid
= true;
1775 /* Pointer to the WM constant buffer. Covered by the set of
1776 * state flags from gen6_upload_wm_push_constants.
1778 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1779 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1785 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1786 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1787 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1789 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1790 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1792 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1793 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1794 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1795 /* These two fields should be the same pre-gen6, which is why we
1796 * only have one hardware field to program for both dispatch
1799 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1800 wm_prog_data
->dispatch_grf_start_reg_2
);
1803 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1804 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1806 if (stage_state
->sampler_count
)
1807 wm
.SamplerStatePointer
=
1808 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1810 if (wm_prog_data
->prog_offset_2
)
1811 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1814 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1815 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1816 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1817 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1818 wm
.EarlyDepthTestEnable
= true;
1819 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1820 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1823 if (ctx
->Polygon
.OffsetFill
) {
1824 wm
.GlobalDepthOffsetEnable
= true;
1825 /* Something weird going on with legacy_global_depth_bias,
1826 * offset_constant, scaling and MRD. This value passes glean
1827 * but gives some odd results elsewere (eg. the
1828 * quad-offset-units test).
1830 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1832 /* This is the only value that passes glean:
1834 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1837 wm
.DepthCoefficientURBReadOffset
= 1;
1840 /* BRW_NEW_STATS_WM */
1841 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1844 if (wm_prog_data
->base
.use_alt_mode
)
1845 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1847 wm
.SamplerCount
= GEN_GEN
== 5 ?
1848 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1850 wm
.BindingTableEntryCount
=
1851 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1852 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1853 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1854 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1855 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1856 wm_prog_data
->base
.dispatch_grf_start_reg
;
1858 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1859 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1863 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1864 wm
.KernelStartPointer2
=
1865 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1870 wm
.DualSourceBlendEnable
=
1871 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1872 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1873 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1874 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1876 /* From the SNB PRM, volume 2 part 1, page 281:
1877 * "If the PS kernel does not need the Position XY Offsets
1878 * to compute a Position XY value, then this field should be
1879 * programmed to POSOFFSET_NONE."
1881 * "SW Recommendation: If the PS kernel needs the Position Offsets
1882 * to compute a Position XY value, this field should match Position
1883 * ZW Interpolation Mode to ensure a consistent position.xyzw
1885 * We only require XY sample offsets. So, this recommendation doesn't
1886 * look useful at the moment. We might need this in future.
1888 if (wm_prog_data
->uses_pos_offset
)
1889 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1891 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1893 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1894 wm_prog_data
->dispatch_grf_start_reg_2
;
1897 if (wm_prog_data
->base
.total_scratch
) {
1898 wm
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
1899 wm
.PerThreadScratchSpace
=
1900 ffs(stage_state
->per_thread_scratch
) - 11;
1903 wm
.PixelShaderComputedDepth
= writes_depth
;
1907 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1910 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1915 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1918 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1920 if (multisampled_fbo
) {
1921 /* _NEW_MULTISAMPLE */
1922 if (ctx
->Multisample
.Enabled
)
1923 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1925 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1927 if (wm_prog_data
->persample_dispatch
)
1928 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1930 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1932 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1933 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1936 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1937 if (wm_prog_data
->uses_kill
||
1938 _mesa_is_alpha_test_enabled(ctx
) ||
1939 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1940 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1941 wm
.PixelShaderKillsPixel
= true;
1944 /* _NEW_BUFFERS | _NEW_COLOR */
1945 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1946 wm
.PixelShaderKillsPixel
||
1947 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1948 wm
.ThreadDispatchEnable
= true;
1952 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1953 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1956 /* The "UAV access enable" bits are unnecessary on HSW because they only
1957 * seem to have an effect on the HW-assisted coherency mechanism which we
1958 * don't need, and the rasterization-related UAV_ONLY flag and the
1959 * DISPATCH_ENABLE bit can be set independently from it.
1960 * C.f. gen8_upload_ps_extra().
1962 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1966 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1967 wm_prog_data
->has_side_effects
)
1973 /* BRW_NEW_FS_PROG_DATA */
1974 if (wm_prog_data
->early_fragment_tests
)
1975 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1976 else if (wm_prog_data
->has_side_effects
)
1977 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1982 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
1983 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
1984 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1987 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
1992 static const struct brw_tracked_state
genX(wm_state
) = {
1996 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1999 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2000 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2001 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2002 .brw
= BRW_NEW_BLORP
|
2003 BRW_NEW_FS_PROG_DATA
|
2004 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2005 BRW_NEW_FRAGMENT_PROGRAM
|
2006 BRW_NEW_PROGRAM_CACHE
|
2007 BRW_NEW_SAMPLER_STATE_TABLE
|
2010 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2012 .emit
= genX(upload_wm
),
2015 /* ---------------------------------------------------------------------- */
2017 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2018 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2019 pkt.SamplerCount = \
2020 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2021 pkt.BindingTableEntryCount = \
2022 stage_prog_data->binding_table.size_bytes / 4; \
2023 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2025 if (stage_prog_data->total_scratch) { \
2026 pkt.ScratchSpaceBasePointer = rw_bo(stage_state->scratch_bo, 0); \
2027 pkt.PerThreadScratchSpace = \
2028 ffs(stage_state->per_thread_scratch) - 11; \
2031 pkt.DispatchGRFStartRegisterForURBData = \
2032 stage_prog_data->dispatch_grf_start_reg; \
2033 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2034 pkt.prefix##URBEntryReadOffset = 0; \
2036 pkt.StatisticsEnable = true; \
2040 genX(upload_vs_state
)(struct brw_context
*brw
)
2042 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2043 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2044 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2046 /* BRW_NEW_VS_PROG_DATA */
2047 const struct brw_vue_prog_data
*vue_prog_data
=
2048 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2049 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2051 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2052 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2053 assert(GEN_GEN
< 11 ||
2054 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
2057 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2058 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2060 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2061 * command that causes the VS Function Enable to toggle. Pipeline
2062 * flush can be executed by sending a PIPE_CONTROL command with CS
2063 * stall bit set and a post sync operation.
2065 * We've already done such a flush at the start of state upload, so we
2066 * don't need to do another one here.
2068 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2069 if (stage_state
->push_const_size
!= 0) {
2070 cvs
.Buffer0Valid
= true;
2071 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2072 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2077 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2078 gen7_emit_vs_workaround_flush(brw
);
2081 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2083 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2084 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2086 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2088 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2091 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2092 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2093 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2095 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2096 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2098 vs
.MaximumNumberofThreads
=
2099 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2101 vs
.StatisticsEnable
= false;
2102 vs
.SamplerStatePointer
=
2103 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2107 /* Force single program flow on Ironlake. We cannot reliably get
2108 * all applications working without it. See:
2109 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2111 * The most notable and reliably failing application is the Humus
2114 vs
.SingleProgramFlow
= true;
2115 vs
.SamplerCount
= 0; /* hardware requirement */
2119 vs
.SIMD8DispatchEnable
=
2120 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2122 vs
.UserClipDistanceCullTestEnableBitmask
=
2123 vue_prog_data
->cull_distance_mask
;
2128 /* Based on my reading of the simulator, the VS constants don't get
2129 * pulled into the VS FF unit until an appropriate pipeline flush
2130 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2131 * references to them into a little FIFO. The flushes are common,
2132 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2133 * the primitive to use the wrong constants. Then the FIFO
2134 * containing the constant setup gets added to again on the next
2135 * constants change, and eventually when a flush does happen the
2136 * unit is overwhelmed by constant changes and dies.
2138 * To avoid this, send a PIPE_CONTROL down the line that will
2139 * update the unit immediately loading the constants. The flush
2140 * type bits here were those set by the STATE_BASE_ADDRESS whose
2141 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2142 * bug reports that led to this workaround, and may be more than
2143 * what is strictly required to avoid the issue.
2145 brw_emit_pipe_control_flush(brw
,
2146 PIPE_CONTROL_DEPTH_STALL
|
2147 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2148 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2152 static const struct brw_tracked_state
genX(vs_state
) = {
2154 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2155 .brw
= BRW_NEW_BATCH
|
2158 BRW_NEW_VS_PROG_DATA
|
2159 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2160 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2161 BRW_NEW_PROGRAM_CACHE
|
2162 BRW_NEW_SAMPLER_STATE_TABLE
|
2166 .emit
= genX(upload_vs_state
),
2169 /* ---------------------------------------------------------------------- */
2172 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2174 struct gl_context
*ctx
= &brw
->ctx
;
2176 /* BRW_NEW_VIEWPORT_COUNT */
2177 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2179 struct GENX(CC_VIEWPORT
) ccv
;
2180 uint32_t cc_vp_offset
;
2182 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2185 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2186 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2187 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2188 if (ctx
->Transform
.DepthClamp
) {
2189 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2190 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2192 ccv
.MinimumDepth
= 0.0;
2193 ccv
.MaximumDepth
= 1.0;
2195 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2196 cc_map
+= GENX(CC_VIEWPORT_length
);
2200 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2201 ptr
.CCViewportPointer
= cc_vp_offset
;
2204 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2205 vp
.CCViewportStateChange
= 1;
2206 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2209 brw
->cc
.vp_offset
= cc_vp_offset
;
2210 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2214 const struct brw_tracked_state
genX(cc_vp
) = {
2216 .mesa
= _NEW_TRANSFORM
|
2218 .brw
= BRW_NEW_BATCH
|
2220 BRW_NEW_VIEWPORT_COUNT
,
2222 .emit
= genX(upload_cc_viewport
)
2225 /* ---------------------------------------------------------------------- */
2228 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2229 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2230 struct GENX(SCISSOR_RECT
) *sc
)
2234 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2235 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2236 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2237 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2238 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2240 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2241 /* If the scissor was out of bounds and got clamped to 0 width/height
2242 * at the bounds, the subtraction of 1 from maximums could produce a
2243 * negative number and thus not clip anything. Instead, just provide
2244 * a min > max scissor inside the bounds, which produces the expected
2247 sc
->ScissorRectangleXMin
= 1;
2248 sc
->ScissorRectangleXMax
= 0;
2249 sc
->ScissorRectangleYMin
= 1;
2250 sc
->ScissorRectangleYMax
= 0;
2251 } else if (render_to_fbo
) {
2252 /* texmemory: Y=0=bottom */
2253 sc
->ScissorRectangleXMin
= bbox
[0];
2254 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2255 sc
->ScissorRectangleYMin
= bbox
[2];
2256 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2258 /* memory: Y=0=top */
2259 sc
->ScissorRectangleXMin
= bbox
[0];
2260 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2261 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2262 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2268 genX(upload_scissor_state
)(struct brw_context
*brw
)
2270 struct gl_context
*ctx
= &brw
->ctx
;
2271 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2272 struct GENX(SCISSOR_RECT
) scissor
;
2273 uint32_t scissor_state_offset
;
2274 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2275 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2276 uint32_t *scissor_map
;
2278 /* BRW_NEW_VIEWPORT_COUNT */
2279 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2281 scissor_map
= brw_state_batch(
2282 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2283 32, &scissor_state_offset
);
2285 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2287 /* The scissor only needs to handle the intersection of drawable and
2288 * scissor rect. Clipping to the boundaries of static shared buffers
2289 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2291 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2292 * inclusive but max is exclusive.
2294 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2295 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2296 GENX(SCISSOR_RECT_pack
)(
2297 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2300 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2301 ptr
.ScissorRectPointer
= scissor_state_offset
;
2305 static const struct brw_tracked_state
genX(scissor_state
) = {
2307 .mesa
= _NEW_BUFFERS
|
2310 .brw
= BRW_NEW_BATCH
|
2312 BRW_NEW_VIEWPORT_COUNT
,
2314 .emit
= genX(upload_scissor_state
),
2318 /* ---------------------------------------------------------------------- */
2321 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2322 float m00
, float m11
, float m30
, float m31
,
2323 float *xmin
, float *xmax
,
2324 float *ymin
, float *ymax
)
2326 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2327 * Strips and Fans documentation:
2329 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2330 * fixed-point "guardband" range supported by the rasterization hardware"
2334 * "In almost all circumstances, if an object’s vertices are actually
2335 * modified by this clamping (i.e., had X or Y coordinates outside of
2336 * the guardband extent the rendered object will not match the intended
2337 * result. Therefore software should take steps to ensure that this does
2338 * not happen - e.g., by clipping objects such that they do not exceed
2339 * these limits after the Drawing Rectangle is applied."
2341 * I believe the fundamental restriction is that the rasterizer (in
2342 * the SF/WM stages) have a limit on the number of pixels that can be
2343 * rasterized. We need to ensure any coordinates beyond the rasterizer
2344 * limit are handled by the clipper. So effectively that limit becomes
2345 * the clipper's guardband size.
2347 * It goes on to say:
2349 * "In addition, in order to be correctly rendered, objects must have a
2350 * screenspace bounding box not exceeding 8K in the X or Y direction.
2351 * This additional restriction must also be comprehended by software,
2352 * i.e., enforced by use of clipping."
2354 * This makes no sense. Gen7+ hardware supports 16K render targets,
2355 * and you definitely need to be able to draw polygons that fill the
2356 * surface. Our assumption is that the rasterizer was limited to 8K
2357 * on Sandybridge, which only supports 8K surfaces, and it was actually
2358 * increased to 16K on Ivybridge and later.
2360 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2362 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2364 if (m00
!= 0 && m11
!= 0) {
2365 /* First, we compute the screen-space render area */
2366 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2367 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2368 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2369 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2371 /* We want the guardband to be centered on that */
2372 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2373 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2374 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2375 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2377 /* Now we need it in native device coordinates */
2378 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2379 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2380 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2381 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2383 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2384 * flipped upside-down. X should be fine though.
2386 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2387 *xmin
= ndc_gb_xmin
;
2388 *xmax
= ndc_gb_xmax
;
2389 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2390 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2392 /* The viewport scales to 0, so nothing will be rendered. */
2401 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2403 struct gl_context
*ctx
= &brw
->ctx
;
2404 float y_scale
, y_bias
;
2406 /* BRW_NEW_VIEWPORT_COUNT */
2407 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2410 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2411 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2412 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2416 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2417 uint32_t sf_clip_vp_offset
;
2418 uint32_t *sf_clip_map
=
2419 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2420 64, &sf_clip_vp_offset
);
2422 struct GENX(SF_VIEWPORT
) sfv
;
2423 struct GENX(CLIP_VIEWPORT
) clv
;
2424 uint32_t sf_vp_offset
, clip_vp_offset
;
2426 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2428 uint32_t *clip_map
=
2429 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2430 32, &clip_vp_offset
);
2434 if (render_to_fbo
) {
2439 y_bias
= (float)fb_height
;
2442 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2443 /* _NEW_VIEWPORT: Guardband Clipping */
2444 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2445 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2447 sfv
.ViewportMatrixElementm00
= scale
[0];
2448 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2449 sfv
.ViewportMatrixElementm22
= scale
[2],
2450 sfv
.ViewportMatrixElementm30
= translate
[0],
2451 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2452 sfv
.ViewportMatrixElementm32
= translate
[2],
2453 brw_calculate_guardband_size(fb_width
, fb_height
,
2454 sfv
.ViewportMatrixElementm00
,
2455 sfv
.ViewportMatrixElementm11
,
2456 sfv
.ViewportMatrixElementm30
,
2457 sfv
.ViewportMatrixElementm31
,
2458 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2461 clv
.XMinClipGuardband
= gb_xmin
;
2462 clv
.XMaxClipGuardband
= gb_xmax
;
2463 clv
.YMinClipGuardband
= gb_ymin
;
2464 clv
.YMaxClipGuardband
= gb_ymax
;
2467 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2468 &sfv
.ScissorRectangle
);
2470 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2471 * The hardware will take the intersection of the drawing rectangle,
2472 * scissor rectangle, and the viewport extents. However, emitting
2473 * 3DSTATE_DRAWING_RECTANGLE is expensive since it requires a full
2474 * pipeline stall so we're better off just being a little more clever
2475 * with our viewport so we can emit it once at context creation time.
2477 const float viewport_Xmin
= MAX2(ctx
->ViewportArray
[i
].X
, 0);
2478 const float viewport_Ymin
= MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2479 const float viewport_Xmax
=
2480 MIN2(ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
, fb_width
);
2481 const float viewport_Ymax
=
2482 MIN2(ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
, fb_height
);
2484 if (render_to_fbo
) {
2485 sfv
.XMinViewPort
= viewport_Xmin
;
2486 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2487 sfv
.YMinViewPort
= viewport_Ymin
;
2488 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2490 sfv
.XMinViewPort
= viewport_Xmin
;
2491 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2492 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2493 sfv
.YMaxViewPort
= fb_height
- viewport_Ymin
- 1;
2498 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2499 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2501 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2502 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2503 sf_map
+= GENX(SF_VIEWPORT_length
);
2504 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2509 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2510 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2513 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2514 vp
.SFViewportStateChange
= 1;
2515 vp
.CLIPViewportStateChange
= 1;
2516 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2517 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2520 brw
->sf
.vp_offset
= sf_vp_offset
;
2521 brw
->clip
.vp_offset
= clip_vp_offset
;
2522 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2526 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2528 .mesa
= _NEW_BUFFERS
|
2530 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2531 .brw
= BRW_NEW_BATCH
|
2533 BRW_NEW_VIEWPORT_COUNT
,
2535 .emit
= genX(upload_sf_clip_viewport
),
2538 /* ---------------------------------------------------------------------- */
2541 genX(upload_gs_state
)(struct brw_context
*brw
)
2543 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2544 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2545 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2546 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2547 /* BRW_NEW_GEOMETRY_PROGRAM */
2548 bool active
= GEN_GEN
>= 6 && gs_prog
;
2550 /* BRW_NEW_GS_PROG_DATA */
2551 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2552 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2553 brw_vue_prog_data(stage_prog_data
);
2555 const struct brw_gs_prog_data
*gs_prog_data
=
2556 brw_gs_prog_data(stage_prog_data
);
2560 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2561 if (active
&& stage_state
->push_const_size
!= 0) {
2562 cgs
.Buffer0Valid
= true;
2563 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2564 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2569 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2571 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2572 * Geometry > Geometry Shader > State:
2574 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2575 * whole fixed function pipeline when the GS enable changes value in
2578 * The hardware architects have clarified that in this context "flush the
2579 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2582 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2583 gen7_emit_cs_stall_flush(brw
);
2587 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2589 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2590 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2595 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2598 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2599 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2600 gs
.ControlDataHeaderSize
=
2601 gs_prog_data
->control_data_header_size_hwords
;
2603 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2604 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2606 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2608 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2611 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2612 * Ivy Bridge and Haswell.
2614 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2615 * strip to be delivered to the geometry shader in an order that does
2616 * not strictly follow the OpenGL spec, but preserves triangle
2617 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2618 * the geometry shader sees triangles:
2620 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2622 * (Clearing the bit is even worse, because it fails to preserve
2625 * Triangle strips with adjacency always ordered in a way that preserves
2626 * triangle orientation but does not strictly follow the OpenGL spec,
2627 * regardless of the setting of this bit.
2629 * On Haswell, both triangle strips and triangle strips with adjacency
2630 * are always ordered in a way that preserves triangle orientation.
2631 * Setting this bit causes the ordering to strictly follow the OpenGL
2634 * So in either case we want to set the bit. Unfortunately on Ivy
2635 * Bridge this will get the order close to correct but not perfect.
2637 gs
.ReorderMode
= TRAILING
;
2638 gs
.MaximumNumberofThreads
=
2639 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2640 : (devinfo
->max_gs_threads
- 1);
2643 gs
.SOStatisticsEnable
= true;
2644 if (gs_prog
->info
.has_transform_feedback_varyings
)
2645 gs
.SVBIPayloadEnable
= true;
2647 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2648 * was previously done for gen6.
2650 * TODO: test with both disabled to see if the HW is behaving
2651 * as expected, like in gen7.
2653 gs
.SingleProgramFlow
= true;
2654 gs
.VectorMaskEnable
= true;
2658 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2660 if (gs_prog_data
->static_vertex_count
!= -1) {
2661 gs
.StaticOutput
= true;
2662 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2664 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2666 gs
.UserClipDistanceCullTestEnableBitmask
=
2667 vue_prog_data
->cull_distance_mask
;
2669 const int urb_entry_write_offset
= 1;
2670 const uint32_t urb_entry_output_length
=
2671 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2672 urb_entry_write_offset
;
2674 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2675 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2681 if (!active
&& brw
->ff_gs
.prog_active
) {
2682 /* In gen6, transform feedback for the VS stage is done with an
2683 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2686 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2687 gs
.SingleProgramFlow
= true;
2688 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2689 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2692 gs
.GRFRegisterCount
=
2693 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2694 /* BRW_NEW_URB_FENCE */
2695 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2696 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2697 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2698 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2701 gs
.VectorMaskEnable
= true;
2702 gs
.SVBIPayloadEnable
= true;
2703 gs
.SVBIPostIncrementEnable
= true;
2704 gs
.SVBIPostIncrementValue
=
2705 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2706 gs
.SOStatisticsEnable
= true;
2707 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2711 if (!active
&& !brw
->ff_gs
.prog_active
) {
2713 gs
.DispatchGRFStartRegisterForURBData
= 1;
2715 gs
.IncludeVertexHandles
= true;
2721 gs
.StatisticsEnable
= true;
2723 #if GEN_GEN == 5 || GEN_GEN == 6
2724 gs
.RenderingEnabled
= true;
2727 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2732 brw
->gs
.enabled
= active
;
2736 static const struct brw_tracked_state
genX(gs_state
) = {
2738 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2739 .brw
= BRW_NEW_BATCH
|
2741 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2742 BRW_NEW_PROGRAM_CACHE
|
2744 BRW_NEW_VIEWPORT_COUNT
2746 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2747 BRW_NEW_GEOMETRY_PROGRAM
|
2748 BRW_NEW_GS_PROG_DATA
2750 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2752 .emit
= genX(upload_gs_state
),
2755 /* ---------------------------------------------------------------------- */
2757 UNUSED
static GLenum
2758 fix_dual_blend_alpha_to_one(GLenum function
)
2764 case GL_ONE_MINUS_SRC1_ALPHA
:
2771 #define blend_factor(x) brw_translate_blend_factor(x)
2772 #define blend_eqn(x) brw_translate_blend_equation(x)
2775 * Modify blend function to force destination alpha to 1.0
2777 * If \c function specifies a blend function that uses destination alpha,
2778 * replace it with a function that hard-wires destination alpha to 1.0. This
2779 * is used when rendering to xRGB targets.
2782 brw_fix_xRGB_alpha(GLenum function
)
2788 case GL_ONE_MINUS_DST_ALPHA
:
2789 case GL_SRC_ALPHA_SATURATE
:
2797 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2799 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2803 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2806 struct gl_context
*ctx
= &brw
->ctx
;
2809 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2811 bool independent_alpha_blend
= false;
2813 /* Used for implementing the following bit of GL_EXT_texture_integer:
2814 * "Per-fragment operations that require floating-point color
2815 * components, including multisample alpha operations, alpha test,
2816 * blending, and dithering, have no effect when the corresponding
2817 * colors are written to an integer color buffer."
2819 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2821 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2822 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2825 if (ctx
->Color
.ColorLogicOpEnabled
) {
2826 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2827 : GL_UNSIGNED_NORMALIZED
;
2828 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2829 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2830 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2832 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2833 _mesa_enum_to_string(rb_type
));
2834 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2835 entry
->LogicOpEnable
= true;
2836 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2838 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2839 && (GEN_GEN
<= 5 || !integer
)) {
2840 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2841 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2842 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2843 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2844 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2845 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2847 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2848 srcRGB
= dstRGB
= GL_ONE
;
2850 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2851 srcA
= dstA
= GL_ONE
;
2853 /* Due to hardware limitations, the destination may have information
2854 * in an alpha channel even when the format specifies no alpha
2855 * channel. In order to avoid getting any incorrect blending due to
2856 * that alpha channel, coerce the blend factors to values that will
2857 * not read the alpha channel, but will instead use the correct
2858 * implicit value for alpha.
2860 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2861 GL_TEXTURE_ALPHA_TYPE
)) {
2862 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2863 srcA
= brw_fix_xRGB_alpha(srcA
);
2864 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2865 dstA
= brw_fix_xRGB_alpha(dstA
);
2868 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2869 * "If Dual Source Blending is enabled, this bit must be disabled."
2871 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2872 * and leave it enabled anyway.
2874 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2875 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2876 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2877 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2878 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2881 entry
->ColorBufferBlendEnable
= true;
2882 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2883 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2884 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2885 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2886 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2887 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2889 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2890 independent_alpha_blend
= true;
2893 return independent_alpha_blend
;
2898 genX(upload_blend_state
)(struct brw_context
*brw
)
2900 struct gl_context
*ctx
= &brw
->ctx
;
2903 /* We need at least one BLEND_STATE written, because we might do
2904 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2905 * for computed depth or alpha test), which will do an FB write
2906 * with render target 0, which will reference BLEND_STATE[0] for
2907 * alpha test enable.
2909 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2910 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2911 nr_draw_buffers
= 1;
2913 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2915 size
+= GENX(BLEND_STATE_length
) * 4;
2918 uint32_t *blend_map
;
2919 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2922 struct GENX(BLEND_STATE
) blend
= { 0 };
2925 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2926 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2929 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2930 * "If drawbuffer zero is not NONE and the buffer it references has an
2931 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2932 * operations are skipped."
2934 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2935 /* _NEW_MULTISAMPLE */
2936 if (_mesa_is_multisample_enabled(ctx
)) {
2937 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2938 blend
.AlphaToCoverageEnable
= true;
2939 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2941 if (ctx
->Multisample
.SampleAlphaToOne
)
2942 blend
.AlphaToOneEnable
= true;
2946 if (ctx
->Color
.AlphaEnabled
) {
2947 blend
.AlphaTestEnable
= true;
2948 blend
.AlphaTestFunction
=
2949 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2952 if (ctx
->Color
.DitherFlag
) {
2953 blend
.ColorDitherEnable
= true;
2958 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2959 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2963 blend
.IndependentAlphaBlendEnable
=
2964 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
2965 blend
.IndependentAlphaBlendEnable
;
2967 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2968 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2970 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2971 * clamping in the fragment shader. For its clamping of
2972 * blending, the spec says:
2974 * "RESOLVED: For fixed-point color buffers, the inputs and
2975 * the result of the blending equation are clamped. For
2976 * floating-point color buffers, no clamping occurs."
2978 * So, generally, we want clamping to the render target's range.
2979 * And, good news, the hardware tables for both pre- and
2980 * post-blend color clamping are either ignored, or any are
2981 * allowed, or clamping is required but RT range clamping is a
2984 entry
.PreBlendColorClampEnable
= true;
2985 entry
.PostBlendColorClampEnable
= true;
2986 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2988 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
2989 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
2990 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
2991 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
2994 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2996 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3002 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3006 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3007 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3008 ptr
.BLEND_STATEChange
= true;
3011 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3012 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3014 ptr
.BlendStatePointerValid
= true;
3020 static const struct brw_tracked_state
genX(blend_state
) = {
3022 .mesa
= _NEW_BUFFERS
|
3025 .brw
= BRW_NEW_BATCH
|
3027 BRW_NEW_STATE_BASE_ADDRESS
,
3029 .emit
= genX(upload_blend_state
),
3033 /* ---------------------------------------------------------------------- */
3036 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3037 [MESA_SHADER_VERTEX
] = 21,
3038 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3039 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3040 [MESA_SHADER_GEOMETRY
] = 22,
3041 [MESA_SHADER_FRAGMENT
] = 23,
3042 [MESA_SHADER_COMPUTE
] = 0,
3046 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3048 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3049 struct gl_context
*ctx
= &brw
->ctx
;
3051 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3053 struct brw_stage_state
*stage_states
[] = {
3061 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3062 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3063 gen7_emit_vs_workaround_flush(brw
);
3065 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3066 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3067 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3069 if (!stage_state
->push_constants_dirty
)
3072 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3073 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3074 if (stage_state
->prog_data
) {
3075 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3076 /* The Skylake PRM contains the following restriction:
3078 * "The driver must ensure The following case does not occur
3079 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3080 * buffer 3 read length equal to zero committed followed by a
3081 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3084 * To avoid this, we program the buffers in the highest slots.
3085 * This way, slot 0 is only used if slot 3 is also used.
3089 for (int i
= 3; i
>= 0; i
--) {
3090 const struct brw_ubo_range
*range
=
3091 &stage_state
->prog_data
->ubo_ranges
[i
];
3093 if (range
->length
== 0)
3096 const struct gl_uniform_block
*block
=
3097 prog
->sh
.UniformBlocks
[range
->block
];
3098 const struct gl_buffer_binding
*binding
=
3099 &ctx
->UniformBufferBindings
[block
->Binding
];
3101 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3102 static unsigned msg_id
= 0;
3103 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3104 MESA_DEBUG_TYPE_UNDEFINED
,
3105 MESA_DEBUG_SEVERITY_HIGH
,
3106 "UBO %d unbound, %s shader uniform data "
3107 "will be undefined.",
3109 _mesa_shader_stage_to_string(stage
));
3113 assert(binding
->Offset
% 32 == 0);
3115 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3116 intel_buffer_object(binding
->BufferObject
),
3117 binding
->Offset
, range
->length
* 32, false);
3119 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3120 pkt
.ConstantBody
.Buffer
[n
] =
3121 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3125 if (stage_state
->push_const_size
> 0) {
3127 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3128 pkt
.ConstantBody
.Buffer
[n
] =
3129 ro_bo(stage_state
->push_const_bo
,
3130 stage_state
->push_const_offset
);
3133 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3134 pkt
.ConstantBody
.Buffer
[0].offset
=
3135 stage_state
->push_const_offset
| mocs
;
3140 stage_state
->push_constants_dirty
= false;
3141 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3145 const struct brw_tracked_state
genX(push_constant_packets
) = {
3148 .brw
= BRW_NEW_DRAW_CALL
,
3150 .emit
= genX(upload_push_constant_packets
),
3156 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3158 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3160 /* BRW_NEW_VERTEX_PROGRAM */
3161 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3162 /* BRW_NEW_VS_PROG_DATA */
3163 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3165 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3168 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3170 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3172 .brw
= BRW_NEW_BATCH
|
3174 BRW_NEW_VERTEX_PROGRAM
|
3175 BRW_NEW_VS_PROG_DATA
,
3177 .emit
= genX(upload_vs_push_constants
),
3181 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3183 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3185 /* BRW_NEW_GEOMETRY_PROGRAM */
3186 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3188 /* BRW_NEW_GS_PROG_DATA */
3189 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3191 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3194 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3196 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3198 .brw
= BRW_NEW_BATCH
|
3200 BRW_NEW_GEOMETRY_PROGRAM
|
3201 BRW_NEW_GS_PROG_DATA
,
3203 .emit
= genX(upload_gs_push_constants
),
3207 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3209 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3210 /* BRW_NEW_FRAGMENT_PROGRAM */
3211 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3212 /* BRW_NEW_FS_PROG_DATA */
3213 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3215 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3218 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3220 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3221 .brw
= BRW_NEW_BATCH
|
3223 BRW_NEW_FRAGMENT_PROGRAM
|
3224 BRW_NEW_FS_PROG_DATA
,
3226 .emit
= genX(upload_wm_push_constants
),
3230 /* ---------------------------------------------------------------------- */
3234 genX(determine_sample_mask
)(struct brw_context
*brw
)
3236 struct gl_context
*ctx
= &brw
->ctx
;
3237 float coverage
= 1.0f
;
3238 float coverage_invert
= false;
3239 unsigned sample_mask
= ~0u;
3241 /* BRW_NEW_NUM_SAMPLES */
3242 unsigned num_samples
= brw
->num_samples
;
3244 if (_mesa_is_multisample_enabled(ctx
)) {
3245 if (ctx
->Multisample
.SampleCoverage
) {
3246 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3247 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3249 if (ctx
->Multisample
.SampleMask
) {
3250 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3254 if (num_samples
> 1) {
3255 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3256 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3257 if (coverage_invert
)
3258 coverage_bits
^= (1 << num_samples
) - 1;
3259 return coverage_bits
& sample_mask
;
3266 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3267 unsigned num_samples
)
3269 unsigned log2_samples
= ffs(num_samples
) - 1;
3271 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3272 multi
.PixelLocation
= CENTER
;
3273 multi
.NumberofMultisamples
= log2_samples
;
3275 GEN_SAMPLE_POS_4X(multi
.Sample
);
3277 switch (num_samples
) {
3279 GEN_SAMPLE_POS_1X(multi
.Sample
);
3282 GEN_SAMPLE_POS_2X(multi
.Sample
);
3285 GEN_SAMPLE_POS_4X(multi
.Sample
);
3288 GEN_SAMPLE_POS_8X(multi
.Sample
);
3298 genX(upload_multisample_state
)(struct brw_context
*brw
)
3300 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3302 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3304 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3305 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3309 static const struct brw_tracked_state
genX(multisample_state
) = {
3311 .mesa
= _NEW_MULTISAMPLE
|
3312 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3313 .brw
= BRW_NEW_BLORP
|
3315 BRW_NEW_NUM_SAMPLES
,
3317 .emit
= genX(upload_multisample_state
)
3321 /* ---------------------------------------------------------------------- */
3324 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3326 struct gl_context
*ctx
= &brw
->ctx
;
3328 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3330 cc
.IndependentAlphaBlendEnable
=
3331 set_blend_entry_bits(brw
, &cc
, 0, false);
3332 set_depth_stencil_bits(brw
, &cc
);
3334 if (ctx
->Color
.AlphaEnabled
&&
3335 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3336 cc
.AlphaTestEnable
= true;
3337 cc
.AlphaTestFunction
=
3338 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3341 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3343 cc
.StatisticsEnable
= brw
->stats_wm
;
3345 cc
.CCViewportStatePointer
=
3346 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3349 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3350 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3351 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3352 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3356 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3357 cc
.BackfaceStencilReferenceValue
=
3358 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3364 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3365 ctx
->Color
.AlphaRef
);
3369 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3370 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3372 ptr
.ColorCalcStatePointerValid
= true;
3376 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3380 static const struct brw_tracked_state
genX(color_calc_state
) = {
3382 .mesa
= _NEW_COLOR
|
3384 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3387 .brw
= BRW_NEW_BATCH
|
3389 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3391 : BRW_NEW_CC_STATE
|
3392 BRW_NEW_STATE_BASE_ADDRESS
),
3394 .emit
= genX(upload_color_calc_state
),
3398 /* ---------------------------------------------------------------------- */
3402 genX(upload_sbe
)(struct brw_context
*brw
)
3404 struct gl_context
*ctx
= &brw
->ctx
;
3405 /* BRW_NEW_FRAGMENT_PROGRAM */
3406 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3407 /* BRW_NEW_FS_PROG_DATA */
3408 const struct brw_wm_prog_data
*wm_prog_data
=
3409 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3411 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3413 #define attr_overrides sbe.Attribute
3415 uint32_t urb_entry_read_length
;
3416 uint32_t urb_entry_read_offset
;
3417 uint32_t point_sprite_enables
;
3419 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3420 sbe
.AttributeSwizzleEnable
= true;
3421 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3424 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3428 * Window coordinates in an FBO are inverted, which means point
3429 * sprite origin must be inverted.
3431 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3432 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3434 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3436 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3437 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3438 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3439 * BRW_NEW_VUE_MAP_GEOM_OUT
3441 genX(calculate_attr_overrides
)(brw
,
3443 &point_sprite_enables
,
3444 &urb_entry_read_length
,
3445 &urb_entry_read_offset
);
3447 /* Typically, the URB entry read length and offset should be programmed
3448 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3449 * stage which produces geometry. However, we don't know the proper
3450 * value until we call calculate_attr_overrides().
3452 * To fit with our existing code, we override the inherited values and
3453 * specify it here directly, as we did on previous generations.
3455 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3456 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3457 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3458 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3461 sbe
.ForceVertexURBEntryReadLength
= true;
3462 sbe
.ForceVertexURBEntryReadOffset
= true;
3466 /* prepare the active component dwords */
3467 const int num_inputs
= urb_entry_read_length
* 2;
3468 for (int input_index
= 0; input_index
< num_inputs
; input_index
++) {
3469 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3475 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3476 for (int i
= 0; i
< 16; i
++)
3477 sbes
.Attribute
[i
] = attr_overrides
[i
];
3481 #undef attr_overrides
3484 static const struct brw_tracked_state
genX(sbe_state
) = {
3486 .mesa
= _NEW_BUFFERS
|
3491 .brw
= BRW_NEW_BLORP
|
3493 BRW_NEW_FRAGMENT_PROGRAM
|
3494 BRW_NEW_FS_PROG_DATA
|
3495 BRW_NEW_GS_PROG_DATA
|
3496 BRW_NEW_TES_PROG_DATA
|
3497 BRW_NEW_VUE_MAP_GEOM_OUT
|
3498 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3501 .emit
= genX(upload_sbe
),
3505 /* ---------------------------------------------------------------------- */
3509 * Outputs the 3DSTATE_SO_DECL_LIST command.
3511 * The data output is a series of 64-bit entries containing a SO_DECL per
3512 * stream. We only have one stream of rendering coming out of the GS unit, so
3513 * we only emit stream 0 (low 16 bits) SO_DECLs.
3516 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3517 const struct brw_vue_map
*vue_map
)
3519 struct gl_context
*ctx
= &brw
->ctx
;
3520 /* BRW_NEW_TRANSFORM_FEEDBACK */
3521 struct gl_transform_feedback_object
*xfb_obj
=
3522 ctx
->TransformFeedback
.CurrentObject
;
3523 const struct gl_transform_feedback_info
*linked_xfb_info
=
3524 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3525 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3526 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3527 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3528 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3530 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3532 memset(so_decl
, 0, sizeof(so_decl
));
3534 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3535 * command feels strange -- each dword pair contains a SO_DECL per stream.
3537 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3538 const struct gl_transform_feedback_output
*output
=
3539 &linked_xfb_info
->Outputs
[i
];
3540 const int buffer
= output
->OutputBuffer
;
3541 const int varying
= output
->OutputRegister
;
3542 const unsigned stream_id
= output
->StreamId
;
3543 assert(stream_id
< MAX_VERTEX_STREAMS
);
3545 buffer_mask
[stream_id
] |= 1 << buffer
;
3547 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3549 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3550 * array. Instead, it simply increments DstOffset for the following
3551 * input by the number of components that should be skipped.
3553 * Our hardware is unusual in that it requires us to program SO_DECLs
3554 * for fake "hole" components, rather than simply taking the offset
3555 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3556 * program as many size = 4 holes as we can, then a final hole to
3557 * accommodate the final 1, 2, or 3 remaining.
3559 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3561 while (skip_components
> 0) {
3562 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3564 .OutputBufferSlot
= output
->OutputBuffer
,
3565 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3567 skip_components
-= 4;
3570 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3572 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3573 .OutputBufferSlot
= output
->OutputBuffer
,
3574 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3576 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3579 if (decls
[stream_id
] > max_decls
)
3580 max_decls
= decls
[stream_id
];
3584 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3585 .StreamtoBufferSelects0
= buffer_mask
[0],
3586 .StreamtoBufferSelects1
= buffer_mask
[1],
3587 .StreamtoBufferSelects2
= buffer_mask
[2],
3588 .StreamtoBufferSelects3
= buffer_mask
[3],
3589 .NumEntries0
= decls
[0],
3590 .NumEntries1
= decls
[1],
3591 .NumEntries2
= decls
[2],
3592 .NumEntries3
= decls
[3]);
3594 for (int i
= 0; i
< max_decls
; i
++) {
3595 GENX(SO_DECL_ENTRY_pack
)(
3596 brw
, dw
+ 2 + i
* 2,
3597 &(struct GENX(SO_DECL_ENTRY
)) {
3598 .Stream0Decl
= so_decl
[0][i
],
3599 .Stream1Decl
= so_decl
[1][i
],
3600 .Stream2Decl
= so_decl
[2][i
],
3601 .Stream3Decl
= so_decl
[3][i
],
3607 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3609 struct gl_context
*ctx
= &brw
->ctx
;
3610 /* BRW_NEW_TRANSFORM_FEEDBACK */
3611 struct gl_transform_feedback_object
*xfb_obj
=
3612 ctx
->TransformFeedback
.CurrentObject
;
3614 const struct gl_transform_feedback_info
*linked_xfb_info
=
3615 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3617 struct brw_transform_feedback_object
*brw_obj
=
3618 (struct brw_transform_feedback_object
*) xfb_obj
;
3619 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3622 /* Set up the up to 4 output buffers. These are the ranges defined in the
3623 * gl_transform_feedback_object.
3625 for (int i
= 0; i
< 4; i
++) {
3626 struct intel_buffer_object
*bufferobj
=
3627 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3630 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3631 sob
.SOBufferIndex
= i
;
3636 uint32_t start
= xfb_obj
->Offset
[i
];
3637 assert(start
% 4 == 0);
3638 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3640 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3641 assert(end
<= bo
->size
);
3643 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3644 sob
.SOBufferIndex
= i
;
3646 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3648 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3649 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3651 sob
.SOBufferEnable
= true;
3652 sob
.StreamOffsetWriteEnable
= true;
3653 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3654 sob
.SOBufferMOCS
= mocs_wb
;
3656 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3657 sob
.StreamOutputBufferOffsetAddress
=
3658 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3660 if (brw_obj
->zero_offsets
) {
3661 /* Zero out the offset and write that to offset_bo */
3662 sob
.StreamOffset
= 0;
3664 /* Use offset_bo as the "Stream Offset." */
3665 sob
.StreamOffset
= 0xFFFFFFFF;
3672 brw_obj
->zero_offsets
= false;
3677 query_active(struct gl_query_object
*q
)
3679 return q
&& q
->Active
;
3683 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3684 const struct brw_vue_map
*vue_map
)
3686 struct gl_context
*ctx
= &brw
->ctx
;
3687 /* BRW_NEW_TRANSFORM_FEEDBACK */
3688 struct gl_transform_feedback_object
*xfb_obj
=
3689 ctx
->TransformFeedback
.CurrentObject
;
3691 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3693 int urb_entry_read_offset
= 0;
3694 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3695 urb_entry_read_offset
;
3697 sos
.SOFunctionEnable
= true;
3698 sos
.SOStatisticsEnable
= true;
3700 /* BRW_NEW_RASTERIZER_DISCARD */
3701 if (ctx
->RasterDiscard
) {
3702 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3703 sos
.RenderingDisable
= true;
3705 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3706 "query active relies on the clipper.\n");
3711 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3712 sos
.ReorderMode
= TRAILING
;
3715 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3716 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3717 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3718 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3720 const struct gl_transform_feedback_info
*linked_xfb_info
=
3721 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3722 /* Set buffer pitches; 0 means unbound. */
3723 if (xfb_obj
->Buffers
[0])
3724 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3725 if (xfb_obj
->Buffers
[1])
3726 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3727 if (xfb_obj
->Buffers
[2])
3728 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3729 if (xfb_obj
->Buffers
[3])
3730 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3733 /* We always read the whole vertex. This could be reduced at some
3734 * point by reading less and offsetting the register index in the
3737 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3738 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3739 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3740 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3741 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3742 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3743 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3744 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3750 genX(upload_sol
)(struct brw_context
*brw
)
3752 struct gl_context
*ctx
= &brw
->ctx
;
3753 /* BRW_NEW_TRANSFORM_FEEDBACK */
3754 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3757 genX(upload_3dstate_so_buffers
)(brw
);
3759 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3760 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3763 /* Finally, set up the SOL stage. This command must always follow updates to
3764 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3765 * MMIO register updates (current performed by the kernel at each batch
3768 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3771 static const struct brw_tracked_state
genX(sol_state
) = {
3774 .brw
= BRW_NEW_BATCH
|
3776 BRW_NEW_RASTERIZER_DISCARD
|
3777 BRW_NEW_VUE_MAP_GEOM_OUT
|
3778 BRW_NEW_TRANSFORM_FEEDBACK
,
3780 .emit
= genX(upload_sol
),
3784 /* ---------------------------------------------------------------------- */
3788 genX(upload_ps
)(struct brw_context
*brw
)
3790 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3791 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3793 /* BRW_NEW_FS_PROG_DATA */
3794 const struct brw_wm_prog_data
*prog_data
=
3795 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3796 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3801 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3802 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3803 * incorrect for subspans where some of the pixels are unlit. We believe
3804 * the bit just didn't take effect in previous generations.
3806 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3809 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3811 /* BRW_NEW_FS_PROG_DATA */
3812 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3814 if (prog_data
->base
.use_alt_mode
)
3815 ps
.FloatingPointMode
= Alternate
;
3817 /* Haswell requires the sample mask to be set in this packet as well as
3818 * in 3DSTATE_SAMPLE_MASK; the values should match.
3821 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3823 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3826 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
3827 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
3828 * k, it implies 2(k+1) threads. It implicitly scales for different GT
3829 * levels (which have some # of PSDs).
3831 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
3834 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3836 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3838 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3841 if (prog_data
->base
.nr_params
> 0 ||
3842 prog_data
->base
.ubo_ranges
[0].length
> 0)
3843 ps
.PushConstantEnable
= true;
3846 /* From the IVB PRM, volume 2 part 1, page 287:
3847 * "This bit is inserted in the PS payload header and made available to
3848 * the DataPort (either via the message header or via header bypass) to
3849 * indicate that oMask data (one or two phases) is included in Render
3850 * Target Write messages. If present, the oMask data is used to mask off
3853 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3855 /* The hardware wedges if you have this bit set but don't turn on any
3856 * dual source blend factors.
3858 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3860 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3861 (ctx
->Color
.BlendEnabled
& 1) &&
3862 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3864 /* BRW_NEW_FS_PROG_DATA */
3865 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3868 /* From the documentation for this packet:
3869 * "If the PS kernel does not need the Position XY Offsets to
3870 * compute a Position Value, then this field should be programmed
3871 * to POSOFFSET_NONE."
3873 * "SW Recommendation: If the PS kernel needs the Position Offsets
3874 * to compute a Position XY value, this field should match Position
3875 * ZW Interpolation Mode to ensure a consistent position.xyzw
3878 * We only require XY sample offsets. So, this recommendation doesn't
3879 * look useful at the moment. We might need this in future.
3881 if (prog_data
->uses_pos_offset
)
3882 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3884 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3886 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3887 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3888 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3889 prog_data
->base
.dispatch_grf_start_reg
;
3890 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3891 prog_data
->dispatch_grf_start_reg_2
;
3893 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3894 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3895 prog_data
->prog_offset_2
;
3897 if (prog_data
->base
.total_scratch
) {
3898 ps
.ScratchSpaceBasePointer
=
3899 rw_bo(stage_state
->scratch_bo
,
3900 ffs(stage_state
->per_thread_scratch
) - 11);
3905 static const struct brw_tracked_state
genX(ps_state
) = {
3907 .mesa
= _NEW_MULTISAMPLE
|
3908 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3911 .brw
= BRW_NEW_BATCH
|
3913 BRW_NEW_FS_PROG_DATA
,
3915 .emit
= genX(upload_ps
),
3919 /* ---------------------------------------------------------------------- */
3923 genX(upload_hs_state
)(struct brw_context
*brw
)
3925 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3926 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3927 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3928 const struct brw_vue_prog_data
*vue_prog_data
=
3929 brw_vue_prog_data(stage_prog_data
);
3931 /* BRW_NEW_TES_PROG_DATA */
3932 struct brw_tcs_prog_data
*tcs_prog_data
=
3933 brw_tcs_prog_data(stage_prog_data
);
3935 if (!tcs_prog_data
) {
3936 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3938 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3939 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3941 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3942 hs
.IncludeVertexHandles
= true;
3944 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3949 static const struct brw_tracked_state
genX(hs_state
) = {
3952 .brw
= BRW_NEW_BATCH
|
3954 BRW_NEW_TCS_PROG_DATA
|
3955 BRW_NEW_TESS_PROGRAMS
,
3957 .emit
= genX(upload_hs_state
),
3961 genX(upload_ds_state
)(struct brw_context
*brw
)
3963 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3964 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3965 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3967 /* BRW_NEW_TES_PROG_DATA */
3968 const struct brw_tes_prog_data
*tes_prog_data
=
3969 brw_tes_prog_data(stage_prog_data
);
3970 const struct brw_vue_prog_data
*vue_prog_data
=
3971 brw_vue_prog_data(stage_prog_data
);
3973 if (!tes_prog_data
) {
3974 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3976 assert(GEN_GEN
< 11 ||
3977 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
3979 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3980 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3982 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3983 ds
.ComputeWCoordinateEnable
=
3984 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3987 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3988 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3989 ds
.UserClipDistanceCullTestEnableBitmask
=
3990 vue_prog_data
->cull_distance_mask
;
3996 static const struct brw_tracked_state
genX(ds_state
) = {
3999 .brw
= BRW_NEW_BATCH
|
4001 BRW_NEW_TESS_PROGRAMS
|
4002 BRW_NEW_TES_PROG_DATA
,
4004 .emit
= genX(upload_ds_state
),
4007 /* ---------------------------------------------------------------------- */
4010 upload_te_state(struct brw_context
*brw
)
4012 /* BRW_NEW_TESS_PROGRAMS */
4013 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4015 /* BRW_NEW_TES_PROG_DATA */
4016 const struct brw_tes_prog_data
*tes_prog_data
=
4017 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4020 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4021 te
.Partitioning
= tes_prog_data
->partitioning
;
4022 te
.OutputTopology
= tes_prog_data
->output_topology
;
4023 te
.TEDomain
= tes_prog_data
->domain
;
4025 te
.MaximumTessellationFactorOdd
= 63.0;
4026 te
.MaximumTessellationFactorNotOdd
= 64.0;
4029 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4033 static const struct brw_tracked_state
genX(te_state
) = {
4036 .brw
= BRW_NEW_BLORP
|
4038 BRW_NEW_TES_PROG_DATA
|
4039 BRW_NEW_TESS_PROGRAMS
,
4041 .emit
= upload_te_state
,
4044 /* ---------------------------------------------------------------------- */
4047 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4049 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4050 /* BRW_NEW_TESS_PROGRAMS */
4051 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4053 /* BRW_NEW_TES_PROG_DATA */
4054 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4055 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4058 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4060 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4061 .brw
= BRW_NEW_BATCH
|
4063 BRW_NEW_TESS_PROGRAMS
|
4064 BRW_NEW_TES_PROG_DATA
,
4066 .emit
= genX(upload_tes_push_constants
),
4070 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4072 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4073 /* BRW_NEW_TESS_PROGRAMS */
4074 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4076 /* BRW_NEW_TCS_PROG_DATA */
4077 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4079 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4082 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4084 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4085 .brw
= BRW_NEW_BATCH
|
4087 BRW_NEW_DEFAULT_TESS_LEVELS
|
4088 BRW_NEW_TESS_PROGRAMS
|
4089 BRW_NEW_TCS_PROG_DATA
,
4091 .emit
= genX(upload_tcs_push_constants
),
4096 /* ---------------------------------------------------------------------- */
4100 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4102 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4104 /* BRW_NEW_COMPUTE_PROGRAM */
4105 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4108 /* BRW_NEW_CS_PROG_DATA */
4109 struct brw_cs_prog_data
*cs_prog_data
=
4110 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4112 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4113 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4117 const struct brw_tracked_state
genX(cs_push_constants
) = {
4119 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4120 .brw
= BRW_NEW_BATCH
|
4122 BRW_NEW_COMPUTE_PROGRAM
|
4123 BRW_NEW_CS_PROG_DATA
,
4125 .emit
= genX(upload_cs_push_constants
),
4129 * Creates a new CS constant buffer reflecting the current CS program's
4130 * constants, if needed by the CS program.
4133 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4135 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4137 /* BRW_NEW_COMPUTE_PROGRAM */
4138 struct brw_program
*cp
=
4139 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4141 /* BRW_NEW_CS_PROG_DATA */
4142 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4144 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4145 /* _NEW_PROGRAM_CONSTANTS */
4146 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4147 stage_state
, prog_data
);
4150 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4152 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4153 .brw
= BRW_NEW_BATCH
|
4155 BRW_NEW_COMPUTE_PROGRAM
|
4156 BRW_NEW_CS_PROG_DATA
,
4158 .emit
= genX(upload_cs_pull_constants
),
4162 genX(upload_cs_state
)(struct brw_context
*brw
)
4164 if (!brw
->cs
.base
.prog_data
)
4168 uint32_t *desc
= (uint32_t*) brw_state_batch(
4169 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4172 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4173 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4174 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4175 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4177 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4178 brw_emit_buffer_surface_state(
4179 brw
, &stage_state
->surf_offset
[
4180 prog_data
->binding_table
.shader_time_start
],
4181 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4182 brw
->shader_time
.bo
->size
, 1,
4186 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4187 32, &stage_state
->bind_bo_offset
);
4189 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4191 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4192 * the only bits that are changed are scoreboard related: Scoreboard
4193 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4194 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4196 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4197 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4199 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4201 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4202 if (prog_data
->total_scratch
) {
4203 uint32_t per_thread_scratch_value
;
4206 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4207 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4209 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4210 } else if (GEN_IS_HASWELL
) {
4211 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4212 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4214 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4216 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4217 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4219 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4221 vfe
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
4222 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4225 /* If brw->screen->subslice_total is greater than one, then
4226 * devinfo->max_cs_threads stores number of threads per sub-slice;
4227 * thus we need to multiply by that number by subslices to get
4228 * the actual maximum number of threads; the -1 is because the HW
4229 * has a bias of 1 (would not make sense to say the maximum number
4232 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4233 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4234 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4236 vfe
.ResetGatewayTimer
=
4237 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4240 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4246 /* We are uploading duplicated copies of push constant uniforms for each
4247 * thread. Although the local id data needs to vary per thread, it won't
4248 * change for other uniform data. Unfortunately this duplication is
4249 * required for gen7. As of Haswell, this duplication can be avoided,
4250 * but this older mechanism with duplicated data continues to work.
4252 * FINISHME: As of Haswell, we could make use of the
4253 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4254 * field to only store one copy of uniform data.
4256 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4257 * which is described in the GPGPU_WALKER command and in the Broadwell
4258 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4259 * Operations => GPGPU Mode => Indirect Payload Storage.
4261 * Note: The constant data is built in brw_upload_cs_push_constants
4264 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4266 const uint32_t vfe_curbe_allocation
=
4267 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4268 cs_prog_data
->push
.cross_thread
.regs
, 2);
4269 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4272 if (cs_prog_data
->push
.total
.size
> 0) {
4273 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4274 curbe
.CURBETotalDataLength
=
4275 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4276 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4280 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4281 memcpy(bind
, stage_state
->surf_offset
,
4282 prog_data
->binding_table
.size_bytes
);
4283 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4284 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4285 .SamplerStatePointer
= stage_state
->sampler_offset
,
4286 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4287 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4288 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4289 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4290 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4291 prog_data
->total_shared
),
4292 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4293 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4294 .CrossThreadConstantDataReadLength
=
4295 cs_prog_data
->push
.cross_thread
.regs
,
4299 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4301 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4302 load
.InterfaceDescriptorTotalLength
=
4303 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4304 load
.InterfaceDescriptorDataStartAddress
= offset
;
4308 static const struct brw_tracked_state
genX(cs_state
) = {
4310 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4311 .brw
= BRW_NEW_BATCH
|
4313 BRW_NEW_CS_PROG_DATA
|
4314 BRW_NEW_SAMPLER_STATE_TABLE
|
4317 .emit
= genX(upload_cs_state
)
4322 /* ---------------------------------------------------------------------- */
4326 genX(upload_raster
)(struct brw_context
*brw
)
4328 const struct gl_context
*ctx
= &brw
->ctx
;
4331 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4334 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4337 const struct gl_point_attrib
*point
= &ctx
->Point
;
4339 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4340 if (brw
->polygon_front_bit
== render_to_fbo
)
4341 raster
.FrontWinding
= CounterClockwise
;
4343 if (polygon
->CullFlag
) {
4344 switch (polygon
->CullFaceMode
) {
4346 raster
.CullMode
= CULLMODE_FRONT
;
4349 raster
.CullMode
= CULLMODE_BACK
;
4351 case GL_FRONT_AND_BACK
:
4352 raster
.CullMode
= CULLMODE_BOTH
;
4355 unreachable("not reached");
4358 raster
.CullMode
= CULLMODE_NONE
;
4361 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4363 raster
.DXMultisampleRasterizationEnable
=
4364 _mesa_is_multisample_enabled(ctx
);
4366 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4367 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4368 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4370 switch (polygon
->FrontMode
) {
4372 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4375 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4378 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4381 unreachable("not reached");
4384 switch (polygon
->BackMode
) {
4386 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4389 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4392 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4395 unreachable("not reached");
4399 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4403 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4405 const bool multisampled_fbo
=
4406 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4407 if (multisampled_fbo
)
4408 raster
.AntialiasingEnable
= false;
4412 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4414 /* _NEW_TRANSFORM */
4415 if (!ctx
->Transform
.DepthClamp
) {
4417 raster
.ViewportZFarClipTestEnable
= true;
4418 raster
.ViewportZNearClipTestEnable
= true;
4420 raster
.ViewportZClipTestEnable
= true;
4424 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4426 raster
.ConservativeRasterizationEnable
=
4427 ctx
->IntelConservativeRasterization
;
4430 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4431 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4433 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4437 static const struct brw_tracked_state
genX(raster_state
) = {
4439 .mesa
= _NEW_BUFFERS
|
4446 .brw
= BRW_NEW_BLORP
|
4448 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4450 .emit
= genX(upload_raster
),
4454 /* ---------------------------------------------------------------------- */
4458 genX(upload_ps_extra
)(struct brw_context
*brw
)
4460 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4462 const struct brw_wm_prog_data
*prog_data
=
4463 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4465 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4466 psx
.PixelShaderValid
= true;
4467 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4468 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4469 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4470 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4471 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4472 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4474 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4475 if (prog_data
->uses_sample_mask
) {
4477 if (prog_data
->post_depth_coverage
)
4478 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4479 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4480 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4482 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4484 psx
.PixelShaderUsesInputCoverageMask
= true;
4488 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4490 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4491 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4494 /* The stricter cross-primitive coherency guarantees that the hardware
4495 * gives us with the "Accesses UAV" bit set for at least one shader stage
4496 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4497 * are redundant within the current image, atomic counter and SSBO GL
4498 * APIs, which all have very loose ordering and coherency requirements
4499 * and generally rely on the application to insert explicit barriers when
4500 * a shader invocation is expected to see the memory writes performed by
4501 * the invocations of some previous primitive. Regardless of the value
4502 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4503 * cause an in most cases useless DC flush when the lowermost stage with
4504 * the bit set finishes execution.
4506 * It would be nice to disable it, but in some cases we can't because on
4507 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4508 * signal (which could be set independently from the coherency mechanism
4509 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4510 * determine whether the hardware skips execution of the fragment shader
4511 * or not via the ThreadDispatchEnable signal. However if we know that
4512 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4513 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4514 * difference so we may just disable it here.
4516 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4517 * take into account KillPixels when no depth or stencil writes are
4518 * enabled. In order for occlusion queries to work correctly with no
4519 * attachments, we need to force-enable here.
4521 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4524 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4525 !brw_color_buffer_write_enabled(brw
))
4526 psx
.PixelShaderHasUAV
= true;
4530 const struct brw_tracked_state
genX(ps_extra
) = {
4532 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4533 .brw
= BRW_NEW_BLORP
|
4535 BRW_NEW_FRAGMENT_PROGRAM
|
4536 BRW_NEW_FS_PROG_DATA
|
4537 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4539 .emit
= genX(upload_ps_extra
),
4543 /* ---------------------------------------------------------------------- */
4547 genX(upload_ps_blend
)(struct brw_context
*brw
)
4549 struct gl_context
*ctx
= &brw
->ctx
;
4552 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4553 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4556 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4558 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4559 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4560 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4562 bool alpha_to_one
= false;
4564 if (!buffer0_is_integer
) {
4565 /* _NEW_MULTISAMPLE */
4567 if (_mesa_is_multisample_enabled(ctx
)) {
4568 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4569 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4572 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4575 /* Used for implementing the following bit of GL_EXT_texture_integer:
4576 * "Per-fragment operations that require floating-point color
4577 * components, including multisample alpha operations, alpha test,
4578 * blending, and dithering, have no effect when the corresponding
4579 * colors are written to an integer color buffer."
4581 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4582 * "If drawbuffer zero is not NONE and the buffer it references has an
4583 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4584 * operations are skipped."
4586 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4587 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4588 GLenum eqA
= color
->Blend
[0].EquationA
;
4589 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4590 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4591 GLenum srcA
= color
->Blend
[0].SrcA
;
4592 GLenum dstA
= color
->Blend
[0].DstA
;
4594 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4595 srcRGB
= dstRGB
= GL_ONE
;
4597 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4598 srcA
= dstA
= GL_ONE
;
4600 /* Due to hardware limitations, the destination may have information
4601 * in an alpha channel even when the format specifies no alpha
4602 * channel. In order to avoid getting any incorrect blending due to
4603 * that alpha channel, coerce the blend factors to values that will
4604 * not read the alpha channel, but will instead use the correct
4605 * implicit value for alpha.
4607 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4608 GL_TEXTURE_ALPHA_TYPE
)) {
4609 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4610 srcA
= brw_fix_xRGB_alpha(srcA
);
4611 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4612 dstA
= brw_fix_xRGB_alpha(dstA
);
4615 /* Alpha to One doesn't work with Dual Color Blending. Override
4616 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4618 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4619 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4620 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4621 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4622 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4625 pb
.ColorBufferBlendEnable
= true;
4626 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4627 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4628 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4629 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4631 pb
.IndependentAlphaBlendEnable
=
4632 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4637 static const struct brw_tracked_state
genX(ps_blend
) = {
4639 .mesa
= _NEW_BUFFERS
|
4642 .brw
= BRW_NEW_BLORP
|
4644 BRW_NEW_FRAGMENT_PROGRAM
,
4646 .emit
= genX(upload_ps_blend
)
4650 /* ---------------------------------------------------------------------- */
4654 genX(emit_vf_topology
)(struct brw_context
*brw
)
4656 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4657 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4661 static const struct brw_tracked_state
genX(vf_topology
) = {
4664 .brw
= BRW_NEW_BLORP
|
4667 .emit
= genX(emit_vf_topology
),
4671 /* ---------------------------------------------------------------------- */
4675 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4677 uint32_t offset_in_bytes
,
4680 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4681 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4682 mi_rpc
.ReportID
= report_id
;
4687 /* ---------------------------------------------------------------------- */
4690 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4693 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4694 struct brw_stage_state
*stage_state
)
4697 static const uint16_t packet_headers
[] = {
4698 [MESA_SHADER_VERTEX
] = 43,
4699 [MESA_SHADER_TESS_CTRL
] = 44,
4700 [MESA_SHADER_TESS_EVAL
] = 45,
4701 [MESA_SHADER_GEOMETRY
] = 46,
4702 [MESA_SHADER_FRAGMENT
] = 47,
4705 /* Ivybridge requires a workaround flush before VS packets. */
4706 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4707 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4708 gen7_emit_vs_workaround_flush(brw
);
4711 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4712 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4713 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4719 has_component(mesa_format format
, int i
)
4721 if (_mesa_is_format_color_format(format
))
4722 return _mesa_format_has_color_component(format
, i
);
4724 /* depth and stencil have only one component */
4729 * Upload SAMPLER_BORDER_COLOR_STATE.
4732 genX(upload_default_color
)(struct brw_context
*brw
,
4733 const struct gl_sampler_object
*sampler
,
4734 mesa_format format
, GLenum base_format
,
4735 bool is_integer_format
, bool is_stencil_sampling
,
4736 uint32_t *sdc_offset
)
4738 union gl_color_union color
;
4740 switch (base_format
) {
4741 case GL_DEPTH_COMPONENT
:
4742 /* GL specs that border color for depth textures is taken from the
4743 * R channel, while the hardware uses A. Spam R into all the
4744 * channels for safety.
4746 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4747 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4748 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4749 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4755 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4758 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4759 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4760 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4761 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4764 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4765 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4766 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4767 color
.ui
[3] = float_as_int(1.0);
4769 case GL_LUMINANCE_ALPHA
:
4770 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4771 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4772 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4773 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4776 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4777 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4778 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4779 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4783 /* In some cases we use an RGBA surface format for GL RGB textures,
4784 * where we've initialized the A channel to 1.0. We also have to set
4785 * the border color alpha to 1.0 in that case.
4787 if (base_format
== GL_RGB
)
4788 color
.ui
[3] = float_as_int(1.0);
4793 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4797 uint32_t *sdc
= brw_state_batch(
4798 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4799 alignment
, sdc_offset
);
4801 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4803 #define ASSIGN(dst, src) \
4808 #define ASSIGNu16(dst, src) \
4810 dst = (uint16_t)src; \
4813 #define ASSIGNu8(dst, src) \
4815 dst = (uint8_t)src; \
4818 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4819 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4820 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4821 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4822 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4825 /* On Broadwell, the border color is represented as four 32-bit floats,
4826 * integers, or unsigned values, interpreted according to the surface
4827 * format. This matches the sampler->BorderColor union exactly; just
4828 * memcpy the values.
4830 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4831 #elif GEN_IS_HASWELL
4832 if (is_integer_format
|| is_stencil_sampling
) {
4833 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4834 const int bits_per_channel
=
4835 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4837 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4838 * "If any color channel is missing from the surface format,
4839 * corresponding border color should be programmed as zero and if
4840 * alpha channel is missing, corresponding Alpha border color should
4841 * be programmed as 1."
4843 unsigned c
[4] = { 0, 0, 0, 1 };
4844 for (int i
= 0; i
< 4; i
++) {
4845 if (has_component(format
, i
))
4849 switch (bits_per_channel
) {
4851 /* Copy RGBA in order. */
4852 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4855 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4857 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4860 if (base_format
== GL_RG
) {
4861 /* Careful inspection of the tables reveals that for RG32 formats,
4862 * the green channel needs to go where blue normally belongs.
4864 state
.BorderColor32bitRed
= c
[0];
4865 state
.BorderColor32bitBlue
= c
[1];
4866 state
.BorderColor32bitAlpha
= 1;
4868 /* Copy RGBA in order. */
4869 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4873 assert(!"Invalid number of bits per channel in integer format.");
4877 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4879 #elif GEN_GEN == 5 || GEN_GEN == 6
4880 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4881 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4882 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4884 #define MESA_FLOAT_TO_HALF(dst, src) \
4885 dst = _mesa_float_to_half(src);
4887 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4889 #undef MESA_FLOAT_TO_HALF
4891 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4892 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4893 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4894 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4896 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4898 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4900 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4904 #undef BORDER_COLOR_ATTR
4906 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4910 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4917 /* GL_CLAMP is the weird mode where coordinates are clamped to
4918 * [0.0, 1.0], so linear filtering of coordinates outside of
4919 * [0.0, 1.0] give you half edge texel value and half border
4922 * Gen8+ supports this natively.
4924 return TCM_HALF_BORDER
;
4926 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4927 * and set clamp_border here, which gets the result desired.
4928 * We just use clamp(_to_edge) for nearest, because for nearest
4929 * clamping to 1.0 gives border color instead of the desired
4935 return TCM_CLAMP_BORDER
;
4937 case GL_CLAMP_TO_EDGE
:
4939 case GL_CLAMP_TO_BORDER
:
4940 return TCM_CLAMP_BORDER
;
4941 case GL_MIRRORED_REPEAT
:
4943 case GL_MIRROR_CLAMP_TO_EDGE
:
4944 return TCM_MIRROR_ONCE
;
4951 * Return true if the given wrap mode requires the border color to exist.
4954 wrap_mode_needs_border_color(unsigned wrap_mode
)
4957 return wrap_mode
== TCM_CLAMP_BORDER
||
4958 wrap_mode
== TCM_HALF_BORDER
;
4960 return wrap_mode
== TCM_CLAMP_BORDER
;
4965 * Sets the sampler state for a single unit based off of the sampler key
4969 genX(update_sampler_state
)(struct brw_context
*brw
,
4970 GLenum target
, bool tex_cube_map_seamless
,
4971 GLfloat tex_unit_lod_bias
,
4972 mesa_format format
, GLenum base_format
,
4973 const struct gl_texture_object
*texObj
,
4974 const struct gl_sampler_object
*sampler
,
4975 uint32_t *sampler_state
,
4976 uint32_t batch_offset_for_sampler_state
)
4978 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
4980 /* Select min and mip filters. */
4981 switch (sampler
->MinFilter
) {
4983 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4984 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4987 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4988 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4990 case GL_NEAREST_MIPMAP_NEAREST
:
4991 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4992 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4994 case GL_LINEAR_MIPMAP_NEAREST
:
4995 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4996 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4998 case GL_NEAREST_MIPMAP_LINEAR
:
4999 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5000 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5002 case GL_LINEAR_MIPMAP_LINEAR
:
5003 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5004 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5007 unreachable("not reached");
5010 /* Select mag filter. */
5011 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5012 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5014 /* Enable anisotropic filtering if desired. */
5015 samp_st
.MaximumAnisotropy
= RATIO21
;
5017 if (sampler
->MaxAnisotropy
> 1.0f
) {
5018 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5019 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5020 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5021 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5023 if (sampler
->MaxAnisotropy
> 2.0f
) {
5024 samp_st
.MaximumAnisotropy
=
5025 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5029 /* Set address rounding bits if not using nearest filtering. */
5030 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5031 samp_st
.UAddressMinFilterRoundingEnable
= true;
5032 samp_st
.VAddressMinFilterRoundingEnable
= true;
5033 samp_st
.RAddressMinFilterRoundingEnable
= true;
5036 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5037 samp_st
.UAddressMagFilterRoundingEnable
= true;
5038 samp_st
.VAddressMagFilterRoundingEnable
= true;
5039 samp_st
.RAddressMagFilterRoundingEnable
= true;
5042 bool either_nearest
=
5043 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5044 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
5045 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
5046 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
5048 if (target
== GL_TEXTURE_CUBE_MAP
||
5049 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5050 /* Cube maps must use the same wrap mode for all three coordinate
5051 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5053 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5054 * integer formats. Fall back to CLAMP for now.
5056 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5057 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5066 } else if (target
== GL_TEXTURE_1D
) {
5067 /* There's a bug in 1D texture sampling - it actually pays
5068 * attention to the wrap_t value, though it should not.
5069 * Override the wrap_t value here to GL_REPEAT to keep
5070 * any nonexistent border pixels from floating in.
5075 samp_st
.TCXAddressControlMode
= wrap_s
;
5076 samp_st
.TCYAddressControlMode
= wrap_t
;
5077 samp_st
.TCZAddressControlMode
= wrap_r
;
5079 samp_st
.ShadowFunction
=
5080 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5081 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5084 /* Set shadow function. */
5085 samp_st
.AnisotropicAlgorithm
=
5086 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5087 EWAApproximation
: LEGACY
;
5091 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5094 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5095 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5096 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5097 samp_st
.TextureLODBias
=
5098 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5101 samp_st
.BaseMipLevel
=
5102 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5103 samp_st
.MinandMagStateNotEqual
=
5104 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5107 /* Upload the border color if necessary. If not, just point it at
5108 * offset 0 (the start of the batch) - the color should be ignored,
5109 * but that address won't fault in case something reads it anyway.
5111 uint32_t border_color_offset
= 0;
5112 if (wrap_mode_needs_border_color(wrap_s
) ||
5113 wrap_mode_needs_border_color(wrap_t
) ||
5114 wrap_mode_needs_border_color(wrap_r
)) {
5115 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5116 texObj
->_IsIntegerFormat
,
5117 texObj
->StencilSampling
,
5118 &border_color_offset
);
5121 samp_st
.BorderColorPointer
=
5122 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5124 samp_st
.BorderColorPointer
= border_color_offset
;
5128 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5130 samp_st
.LODPreClampEnable
= true;
5133 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5137 update_sampler_state(struct brw_context
*brw
,
5139 uint32_t *sampler_state
,
5140 uint32_t batch_offset_for_sampler_state
)
5142 struct gl_context
*ctx
= &brw
->ctx
;
5143 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5144 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5145 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5147 /* These don't use samplers at all. */
5148 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5151 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5152 genX(update_sampler_state
)(brw
, texObj
->Target
,
5153 ctx
->Texture
.CubeMapSeamless
,
5155 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5157 sampler_state
, batch_offset_for_sampler_state
);
5161 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5162 struct gl_program
*prog
,
5163 struct brw_stage_state
*stage_state
)
5165 struct gl_context
*ctx
= &brw
->ctx
;
5166 uint32_t sampler_count
= stage_state
->sampler_count
;
5168 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5170 if (sampler_count
== 0)
5173 /* SAMPLER_STATE is 4 DWords on all platforms. */
5174 const int dwords
= GENX(SAMPLER_STATE_length
);
5175 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5177 uint32_t *sampler_state
= brw_state_batch(brw
,
5178 sampler_count
* size_in_bytes
,
5179 32, &stage_state
->sampler_offset
);
5180 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5182 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
5184 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5185 if (SamplersUsed
& (1 << s
)) {
5186 const unsigned unit
= prog
->SamplerUnits
[s
];
5187 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5188 update_sampler_state(brw
, unit
, sampler_state
,
5189 batch_offset_for_sampler_state
);
5193 sampler_state
+= dwords
;
5194 batch_offset_for_sampler_state
+= size_in_bytes
;
5197 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5198 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5199 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5201 /* Flag that the sampler state table pointer has changed; later atoms
5204 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5209 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5211 /* BRW_NEW_FRAGMENT_PROGRAM */
5212 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5213 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5216 static const struct brw_tracked_state
genX(fs_samplers
) = {
5218 .mesa
= _NEW_TEXTURE
,
5219 .brw
= BRW_NEW_BATCH
|
5221 BRW_NEW_FRAGMENT_PROGRAM
,
5223 .emit
= genX(upload_fs_samplers
),
5227 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5229 /* BRW_NEW_VERTEX_PROGRAM */
5230 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5231 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5234 static const struct brw_tracked_state
genX(vs_samplers
) = {
5236 .mesa
= _NEW_TEXTURE
,
5237 .brw
= BRW_NEW_BATCH
|
5239 BRW_NEW_VERTEX_PROGRAM
,
5241 .emit
= genX(upload_vs_samplers
),
5246 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5248 /* BRW_NEW_GEOMETRY_PROGRAM */
5249 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5253 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5257 static const struct brw_tracked_state
genX(gs_samplers
) = {
5259 .mesa
= _NEW_TEXTURE
,
5260 .brw
= BRW_NEW_BATCH
|
5262 BRW_NEW_GEOMETRY_PROGRAM
,
5264 .emit
= genX(upload_gs_samplers
),
5270 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5272 /* BRW_NEW_TESS_PROGRAMS */
5273 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5277 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5280 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5282 .mesa
= _NEW_TEXTURE
,
5283 .brw
= BRW_NEW_BATCH
|
5285 BRW_NEW_TESS_PROGRAMS
,
5287 .emit
= genX(upload_tcs_samplers
),
5293 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5295 /* BRW_NEW_TESS_PROGRAMS */
5296 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5300 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5303 static const struct brw_tracked_state
genX(tes_samplers
) = {
5305 .mesa
= _NEW_TEXTURE
,
5306 .brw
= BRW_NEW_BATCH
|
5308 BRW_NEW_TESS_PROGRAMS
,
5310 .emit
= genX(upload_tes_samplers
),
5316 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5318 /* BRW_NEW_COMPUTE_PROGRAM */
5319 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5323 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5326 const struct brw_tracked_state
genX(cs_samplers
) = {
5328 .mesa
= _NEW_TEXTURE
,
5329 .brw
= BRW_NEW_BATCH
|
5331 BRW_NEW_COMPUTE_PROGRAM
,
5333 .emit
= genX(upload_cs_samplers
),
5337 /* ---------------------------------------------------------------------- */
5341 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5343 struct gl_context
*ctx
= &brw
->ctx
;
5345 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5346 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5347 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5348 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5349 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5353 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5356 .brw
= BRW_NEW_CONTEXT
|
5359 .emit
= genX(upload_blend_constant_color
)
5363 /* ---------------------------------------------------------------------- */
5366 genX(init_atoms
)(struct brw_context
*brw
)
5369 static const struct brw_tracked_state
*render_atoms
[] =
5371 /* Once all the programs are done, we know how large urb entry
5372 * sizes need to be and can decide if we need to change the urb
5376 &brw_recalculate_urb_fence
,
5379 &genX(color_calc_state
),
5381 /* Surface state setup. Must come before the VS/WM unit. The binding
5382 * table upload must be last.
5384 &brw_vs_pull_constants
,
5385 &brw_wm_pull_constants
,
5386 &brw_renderbuffer_surfaces
,
5387 &brw_renderbuffer_read_surfaces
,
5388 &brw_texture_surfaces
,
5389 &brw_vs_binding_table
,
5390 &brw_wm_binding_table
,
5395 /* These set up state for brw_psp_urb_cbs */
5397 &genX(sf_clip_viewport
),
5399 &genX(vs_state
), /* always required, enabled or not */
5405 &brw_binding_table_pointers
,
5406 &genX(blend_constant_color
),
5410 &genX(polygon_stipple
),
5411 &genX(polygon_stipple_offset
),
5413 &genX(line_stipple
),
5417 &genX(drawing_rect
),
5418 &brw_indices
, /* must come before brw_vertices */
5419 &genX(index_buffer
),
5422 &brw_constant_buffer
5425 static const struct brw_tracked_state
*render_atoms
[] =
5427 &genX(sf_clip_viewport
),
5429 /* Command packets: */
5434 &genX(blend_state
), /* must do before cc unit */
5435 &genX(color_calc_state
), /* must do before cc unit */
5436 &genX(depth_stencil_state
), /* must do before cc unit */
5438 &genX(vs_push_constants
), /* Before vs_state */
5439 &genX(gs_push_constants
), /* Before gs_state */
5440 &genX(wm_push_constants
), /* Before wm_state */
5442 /* Surface state setup. Must come before the VS/WM unit. The binding
5443 * table upload must be last.
5445 &brw_vs_pull_constants
,
5446 &brw_vs_ubo_surfaces
,
5447 &brw_gs_pull_constants
,
5448 &brw_gs_ubo_surfaces
,
5449 &brw_wm_pull_constants
,
5450 &brw_wm_ubo_surfaces
,
5451 &gen6_renderbuffer_surfaces
,
5452 &brw_renderbuffer_read_surfaces
,
5453 &brw_texture_surfaces
,
5455 &brw_vs_binding_table
,
5456 &gen6_gs_binding_table
,
5457 &brw_wm_binding_table
,
5462 &gen6_sampler_state
,
5463 &genX(multisample_state
),
5471 &genX(scissor_state
),
5473 &gen6_binding_table_pointers
,
5477 &genX(polygon_stipple
),
5478 &genX(polygon_stipple_offset
),
5480 &genX(line_stipple
),
5482 &genX(drawing_rect
),
5484 &brw_indices
, /* must come before brw_vertices */
5485 &genX(index_buffer
),
5489 static const struct brw_tracked_state
*render_atoms
[] =
5491 /* Command packets: */
5494 &genX(sf_clip_viewport
),
5497 &gen7_push_constant_space
,
5499 &genX(blend_state
), /* must do before cc unit */
5500 &genX(color_calc_state
), /* must do before cc unit */
5501 &genX(depth_stencil_state
), /* must do before cc unit */
5503 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5504 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5505 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5506 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5507 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5509 &genX(vs_push_constants
), /* Before vs_state */
5510 &genX(tcs_push_constants
),
5511 &genX(tes_push_constants
),
5512 &genX(gs_push_constants
), /* Before gs_state */
5513 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5515 /* Surface state setup. Must come before the VS/WM unit. The binding
5516 * table upload must be last.
5518 &brw_vs_pull_constants
,
5519 &brw_vs_ubo_surfaces
,
5520 &brw_tcs_pull_constants
,
5521 &brw_tcs_ubo_surfaces
,
5522 &brw_tes_pull_constants
,
5523 &brw_tes_ubo_surfaces
,
5524 &brw_gs_pull_constants
,
5525 &brw_gs_ubo_surfaces
,
5526 &brw_wm_pull_constants
,
5527 &brw_wm_ubo_surfaces
,
5528 &gen6_renderbuffer_surfaces
,
5529 &brw_renderbuffer_read_surfaces
,
5530 &brw_texture_surfaces
,
5532 &genX(push_constant_packets
),
5534 &brw_vs_binding_table
,
5535 &brw_tcs_binding_table
,
5536 &brw_tes_binding_table
,
5537 &brw_gs_binding_table
,
5538 &brw_wm_binding_table
,
5542 &genX(tcs_samplers
),
5543 &genX(tes_samplers
),
5545 &genX(multisample_state
),
5559 &genX(scissor_state
),
5563 &genX(polygon_stipple
),
5564 &genX(polygon_stipple_offset
),
5566 &genX(line_stipple
),
5568 &genX(drawing_rect
),
5570 &brw_indices
, /* must come before brw_vertices */
5571 &genX(index_buffer
),
5579 static const struct brw_tracked_state
*render_atoms
[] =
5582 &genX(sf_clip_viewport
),
5585 &gen7_push_constant_space
,
5588 &genX(color_calc_state
),
5590 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5591 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5592 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5593 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5594 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5596 &genX(vs_push_constants
), /* Before vs_state */
5597 &genX(tcs_push_constants
),
5598 &genX(tes_push_constants
),
5599 &genX(gs_push_constants
), /* Before gs_state */
5600 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5602 /* Surface state setup. Must come before the VS/WM unit. The binding
5603 * table upload must be last.
5605 &brw_vs_pull_constants
,
5606 &brw_vs_ubo_surfaces
,
5607 &brw_tcs_pull_constants
,
5608 &brw_tcs_ubo_surfaces
,
5609 &brw_tes_pull_constants
,
5610 &brw_tes_ubo_surfaces
,
5611 &brw_gs_pull_constants
,
5612 &brw_gs_ubo_surfaces
,
5613 &brw_wm_pull_constants
,
5614 &brw_wm_ubo_surfaces
,
5615 &gen6_renderbuffer_surfaces
,
5616 &brw_renderbuffer_read_surfaces
,
5617 &brw_texture_surfaces
,
5619 &genX(push_constant_packets
),
5621 &brw_vs_binding_table
,
5622 &brw_tcs_binding_table
,
5623 &brw_tes_binding_table
,
5624 &brw_gs_binding_table
,
5625 &brw_wm_binding_table
,
5629 &genX(tcs_samplers
),
5630 &genX(tes_samplers
),
5632 &genX(multisample_state
),
5641 &genX(raster_state
),
5647 &genX(depth_stencil_state
),
5650 &genX(scissor_state
),
5654 &genX(polygon_stipple
),
5655 &genX(polygon_stipple_offset
),
5657 &genX(line_stipple
),
5659 &genX(drawing_rect
),
5664 &genX(index_buffer
),
5672 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5673 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5674 render_atoms
, ARRAY_SIZE(render_atoms
));
5677 static const struct brw_tracked_state
*compute_atoms
[] =
5680 &brw_cs_image_surfaces
,
5681 &genX(cs_push_constants
),
5682 &genX(cs_pull_constants
),
5683 &brw_cs_ubo_surfaces
,
5684 &brw_cs_texture_surfaces
,
5685 &brw_cs_work_groups_surface
,
5690 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5691 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5692 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5694 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);