2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_defines.h"
41 #include "brw_multisample_state.h"
42 #include "brw_state.h"
46 #include "intel_batchbuffer.h"
47 #include "intel_buffer_objects.h"
48 #include "intel_fbo.h"
50 #include "main/enums.h"
51 #include "main/fbobject.h"
52 #include "main/framebuffer.h"
53 #include "main/glformats.h"
54 #include "main/samplerobj.h"
55 #include "main/shaderapi.h"
56 #include "main/stencil.h"
57 #include "main/transformfeedback.h"
58 #include "main/varray.h"
59 #include "main/viewport.h"
60 #include "util/half_float.h"
63 emit_dwords(struct brw_context
*brw
, unsigned n
)
65 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
66 uint32_t *map
= brw
->batch
.map_next
;
67 brw
->batch
.map_next
+= n
;
68 intel_batchbuffer_advance(brw
);
78 #define __gen_address_type struct brw_address
79 #define __gen_user_data struct brw_context
82 __gen_combine_address(struct brw_context
*brw
, void *location
,
83 struct brw_address address
, uint32_t delta
)
85 struct intel_batchbuffer
*batch
= &brw
->batch
;
88 if (address
.bo
== NULL
) {
89 return address
.offset
+ delta
;
91 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
92 offset
= (char *) location
- (char *) brw
->batch
.state_map
;
93 return brw_state_reloc(batch
, offset
, address
.bo
,
94 address
.offset
+ delta
,
98 assert(!brw_ptr_in_state_buffer(batch
, location
));
100 offset
= (char *) location
- (char *) brw
->batch
.map
;
101 return brw_batch_reloc(batch
, offset
, address
.bo
,
102 address
.offset
+ delta
,
103 address
.reloc_flags
);
107 static struct brw_address
108 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
110 return (struct brw_address
) {
113 .reloc_flags
= RELOC_WRITE
,
117 static struct brw_address
118 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
120 return (struct brw_address
) {
126 UNUSED
static struct brw_address
127 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
129 return (struct brw_address
) {
132 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
137 static struct brw_address
138 KSP(struct brw_context
*brw
, uint32_t offset
)
140 return ro_bo(brw
->cache
.bo
, offset
);
144 KSP(struct brw_context
*brw
, uint32_t offset
)
150 #include "genxml/genX_pack.h"
152 #define _brw_cmd_length(cmd) cmd ## _length
153 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
154 #define _brw_cmd_header(cmd) cmd ## _header
155 #define _brw_cmd_pack(cmd) cmd ## _pack
157 #define brw_batch_emit(brw, cmd, name) \
158 for (struct cmd name = { _brw_cmd_header(cmd) }, \
159 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
160 __builtin_expect(_dst != NULL, 1); \
161 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
164 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
165 uint32_t *_dw = emit_dwords(brw, n); \
166 struct cmd template = { \
167 _brw_cmd_header(cmd), \
168 .DWordLength = n - _brw_cmd_length_bias(cmd), \
171 _brw_cmd_pack(cmd)(brw, _dw, &template); \
172 _dw + 1; /* Array starts at dw[1] */ \
175 #define brw_state_emit(brw, cmd, align, offset, name) \
176 for (struct cmd name = {}, \
177 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
179 __builtin_expect(_dst != NULL, 1); \
180 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
184 * Polygon stipple packet
187 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
189 struct gl_context
*ctx
= &brw
->ctx
;
192 if (!ctx
->Polygon
.StippleFlag
)
195 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
196 /* Polygon stipple is provided in OpenGL order, i.e. bottom
197 * row first. If we're rendering to a window (i.e. the
198 * default frame buffer object, 0), then we need to invert
199 * it to match our pixel layout. But if we're rendering
200 * to a FBO (i.e. any named frame buffer object), we *don't*
201 * need to invert - we already match the layout.
203 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
204 for (unsigned i
= 0; i
< 32; i
++)
205 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
207 for (unsigned i
= 0; i
< 32; i
++)
208 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
213 static const struct brw_tracked_state
genX(polygon_stipple
) = {
215 .mesa
= _NEW_POLYGON
|
217 .brw
= BRW_NEW_CONTEXT
,
219 .emit
= genX(upload_polygon_stipple
),
223 * Polygon stipple offset packet
226 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
228 struct gl_context
*ctx
= &brw
->ctx
;
231 if (!ctx
->Polygon
.StippleFlag
)
234 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
237 * If we're drawing to a system window we have to invert the Y axis
238 * in order to match the OpenGL pixel coordinate system, and our
239 * offset must be matched to the window position. If we're drawing
240 * to a user-created FBO then our native pixel coordinate system
241 * works just fine, and there's no window system to worry about.
243 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
244 poly
.PolygonStippleYOffset
=
245 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
250 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
252 .mesa
= _NEW_BUFFERS
|
254 .brw
= BRW_NEW_CONTEXT
,
256 .emit
= genX(upload_polygon_stipple_offset
),
260 * Line stipple packet
263 genX(upload_line_stipple
)(struct brw_context
*brw
)
265 struct gl_context
*ctx
= &brw
->ctx
;
267 if (!ctx
->Line
.StippleFlag
)
270 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
271 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
273 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
274 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
278 static const struct brw_tracked_state
genX(line_stipple
) = {
281 .brw
= BRW_NEW_CONTEXT
,
283 .emit
= genX(upload_line_stipple
),
286 /* Constant single cliprect for framebuffer object or DRI2 drawing */
288 genX(upload_drawing_rect
)(struct brw_context
*brw
)
290 struct gl_context
*ctx
= &brw
->ctx
;
291 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
292 const unsigned int fb_width
= _mesa_geometric_width(fb
);
293 const unsigned int fb_height
= _mesa_geometric_height(fb
);
295 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
296 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
297 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
301 static const struct brw_tracked_state
genX(drawing_rect
) = {
303 .mesa
= _NEW_BUFFERS
,
304 .brw
= BRW_NEW_BLORP
|
307 .emit
= genX(upload_drawing_rect
),
311 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
315 unsigned start_offset
,
320 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
321 .VertexBufferIndex
= buffer_nr
,
322 .BufferPitch
= stride
,
323 .BufferStartingAddress
= ro_bo(bo
, start_offset
),
325 .BufferSize
= end_offset
- start_offset
,
329 .AddressModifyEnable
= true,
333 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
334 .InstanceDataStepRate
= step_rate
,
336 .EndAddress
= ro_bo(bo
, end_offset
- 1),
341 .VertexBufferMOCS
= CNL_MOCS_WB
,
343 .VertexBufferMOCS
= SKL_MOCS_WB
,
345 .VertexBufferMOCS
= BDW_MOCS_WB
,
347 .VertexBufferMOCS
= GEN7_MOCS_L3
,
351 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
352 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
356 is_passthru_format(uint32_t format
)
359 case ISL_FORMAT_R64_PASSTHRU
:
360 case ISL_FORMAT_R64G64_PASSTHRU
:
361 case ISL_FORMAT_R64G64B64_PASSTHRU
:
362 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
370 uploads_needed(uint32_t format
)
372 if (!is_passthru_format(format
))
376 case ISL_FORMAT_R64_PASSTHRU
:
377 case ISL_FORMAT_R64G64_PASSTHRU
:
379 case ISL_FORMAT_R64G64B64_PASSTHRU
:
380 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
383 unreachable("not reached");
388 * Returns the format that we are finally going to use when upload a vertex
389 * element. It will only change if we are using *64*PASSTHRU formats, as for
390 * gen < 8 they need to be splitted on two *32*FLOAT formats.
392 * @upload points in which upload we are. Valid values are [0,1]
395 downsize_format_if_needed(uint32_t format
,
398 assert(upload
== 0 || upload
== 1);
400 if (!is_passthru_format(format
))
404 case ISL_FORMAT_R64_PASSTHRU
:
405 return ISL_FORMAT_R32G32_FLOAT
;
406 case ISL_FORMAT_R64G64_PASSTHRU
:
407 return ISL_FORMAT_R32G32B32A32_FLOAT
;
408 case ISL_FORMAT_R64G64B64_PASSTHRU
:
409 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
410 : ISL_FORMAT_R32G32_FLOAT
;
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
412 return ISL_FORMAT_R32G32B32A32_FLOAT
;
414 unreachable("not reached");
419 * Returns the number of componentes associated with a format that is used on
420 * a 64 to 32 format split. See downsize_format()
423 upload_format_size(uint32_t upload_format
)
425 switch (upload_format
) {
426 case ISL_FORMAT_R32G32_FLOAT
:
428 case ISL_FORMAT_R32G32B32A32_FLOAT
:
431 unreachable("not reached");
436 genX(emit_vertices
)(struct brw_context
*brw
)
438 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
441 brw_prepare_vertices(brw
);
442 brw_prepare_shader_draw_parameters(brw
);
445 brw_emit_query_begin(brw
);
448 const struct brw_vs_prog_data
*vs_prog_data
=
449 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
452 struct gl_context
*ctx
= &brw
->ctx
;
453 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
454 ctx
->Polygon
.BackMode
!= GL_FILL
);
456 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
457 unsigned vue
= brw
->vb
.nr_enabled
;
459 /* The element for the edge flags must always be last, so we have to
460 * insert the SGVS before it in that case.
462 if (uses_edge_flag
) {
468 "Trying to insert VID/IID past 33rd vertex element, "
469 "need to reorder the vertex attrbutes.");
471 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
472 if (vs_prog_data
->uses_vertexid
) {
473 vfs
.VertexIDEnable
= true;
474 vfs
.VertexIDComponentNumber
= 2;
475 vfs
.VertexIDElementOffset
= vue
;
478 if (vs_prog_data
->uses_instanceid
) {
479 vfs
.InstanceIDEnable
= true;
480 vfs
.InstanceIDComponentNumber
= 3;
481 vfs
.InstanceIDElementOffset
= vue
;
485 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
486 vfi
.InstancingEnable
= true;
487 vfi
.VertexElementIndex
= vue
;
490 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
493 /* Normally we don't need an element for the SGVS attribute because the
494 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
495 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
496 * we're using draw parameters then we need an element for the those
497 * values. Additionally if there is an edge flag element then the SGVS
498 * can't be inserted past that so we need a dummy element to ensure that
499 * the edge flag is the last one.
501 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
502 vs_prog_data
->uses_baseinstance
||
503 ((vs_prog_data
->uses_instanceid
||
504 vs_prog_data
->uses_vertexid
)
507 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
508 vs_prog_data
->uses_baseinstance
||
509 vs_prog_data
->uses_instanceid
||
510 vs_prog_data
->uses_vertexid
);
512 unsigned nr_elements
=
513 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
516 /* If any of the formats of vb.enabled needs more that one upload, we need
517 * to add it to nr_elements
519 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
520 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
521 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
523 if (uploads_needed(format
) > 1)
528 /* If the VS doesn't read any inputs (calculating vertex position from
529 * a state variable for some reason, for example), emit a single pad
530 * VERTEX_ELEMENT struct and bail.
532 * The stale VB state stays in place, but they don't do anything unless
533 * a VE loads from them.
535 if (nr_elements
== 0) {
536 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
537 1 + GENX(VERTEX_ELEMENT_STATE_length
));
538 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
540 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
541 .Component0Control
= VFCOMP_STORE_0
,
542 .Component1Control
= VFCOMP_STORE_0
,
543 .Component2Control
= VFCOMP_STORE_0
,
544 .Component3Control
= VFCOMP_STORE_1_FP
,
546 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
550 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
551 const bool uses_draw_params
=
552 vs_prog_data
->uses_basevertex
||
553 vs_prog_data
->uses_baseinstance
;
554 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
555 uses_draw_params
+ vs_prog_data
->uses_drawid
;
558 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
560 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
561 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
563 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
564 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
565 /* Prior to Haswell and Bay Trail we have to use 4-component formats
566 * to fake 3-component ones. In particular, we do this for
567 * half-float and 8 and 16-bit integer formats. This means that the
568 * vertex element may poke over the end of the buffer by 2 bytes.
570 const unsigned padding
=
571 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
572 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
573 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
580 if (uses_draw_params
) {
581 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
582 brw
->draw
.draw_params_bo
,
583 brw
->draw
.draw_params_offset
,
584 brw
->draw
.draw_params_bo
->size
,
589 if (vs_prog_data
->uses_drawid
) {
590 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
591 brw
->draw
.draw_id_bo
,
592 brw
->draw
.draw_id_offset
,
593 brw
->draw
.draw_id_bo
->size
,
599 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
600 * presumably for VertexID/InstanceID.
603 assert(nr_elements
<= 34);
604 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
606 assert(nr_elements
<= 18);
609 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
610 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
612 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
613 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
614 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
615 uint32_t comp0
= VFCOMP_STORE_SRC
;
616 uint32_t comp1
= VFCOMP_STORE_SRC
;
617 uint32_t comp2
= VFCOMP_STORE_SRC
;
618 uint32_t comp3
= VFCOMP_STORE_SRC
;
619 const unsigned num_uploads
= GEN_GEN
< 8 ? uploads_needed(format
) : 1;
622 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
623 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
624 * element which has edge flag enabled."
626 assert(!(is_passthru_format(format
) && uses_edge_flag
));
629 /* The gen4 driver expects edgeflag to come in as a float, and passes
630 * that float on to the tests in the clipper. Mesa's current vertex
631 * attribute value for EdgeFlag is stored as a float, which works out.
632 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
633 * integer ubyte. Just rewrite that to convert to a float.
635 * Gen6+ passes edgeflag as sideband along with the vertex, instead
636 * of in the VUE. We have to upload it sideband as the last vertex
637 * element according to the B-Spec.
640 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
641 gen6_edgeflag_input
= input
;
646 for (unsigned c
= 0; c
< num_uploads
; c
++) {
647 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
648 downsize_format_if_needed(format
, c
);
649 /* If we need more that one upload, the offset stride would be 128
650 * bits (16 bytes), as for previous uploads we are using the full
652 const unsigned offset
= input
->offset
+ c
* 16;
654 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
655 upload_format_size(upload_format
) : input
->glarray
->Size
;
658 case 0: comp0
= VFCOMP_STORE_0
;
659 case 1: comp1
= VFCOMP_STORE_0
;
660 case 2: comp2
= VFCOMP_STORE_0
;
662 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
663 comp3
= VFCOMP_STORE_0
;
664 } else if (input
->glarray
->Integer
) {
665 comp3
= VFCOMP_STORE_1_INT
;
667 comp3
= VFCOMP_STORE_1_FP
;
674 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
676 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
677 * formats, 64-bit components are stored in the URB without any
678 * conversion. In this case, vertex elements must be written as 128
679 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
680 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
681 * component into the URB, Component 1 must be specified as
682 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
683 * order to output a 128-bit vertex element, or Components 1-3 must
684 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
685 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
686 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
689 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
690 /* Store vertex elements which correspond to double and dvec2 vertex
691 * shader inputs as 128-bit vertex elements, instead of 256-bits.
693 comp2
= VFCOMP_NOSTORE
;
694 comp3
= VFCOMP_NOSTORE
;
698 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
699 .VertexBufferIndex
= input
->buffer
,
701 .SourceElementFormat
= upload_format
,
702 .SourceElementOffset
= offset
,
703 .Component0Control
= comp0
,
704 .Component1Control
= comp1
,
705 .Component2Control
= comp2
,
706 .Component3Control
= comp3
,
708 .DestinationElementOffset
= i
* 4,
712 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
713 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
717 if (needs_sgvs_element
) {
718 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
720 .Component0Control
= VFCOMP_STORE_0
,
721 .Component1Control
= VFCOMP_STORE_0
,
722 .Component2Control
= VFCOMP_STORE_0
,
723 .Component3Control
= VFCOMP_STORE_0
,
725 .DestinationElementOffset
= i
* 4,
730 if (vs_prog_data
->uses_basevertex
||
731 vs_prog_data
->uses_baseinstance
) {
732 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
733 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
734 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
735 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
738 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
739 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
740 if (vs_prog_data
->uses_basevertex
)
741 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
743 if (vs_prog_data
->uses_baseinstance
)
744 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
746 if (vs_prog_data
->uses_vertexid
)
747 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
749 if (vs_prog_data
->uses_instanceid
)
750 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
753 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
754 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
757 if (vs_prog_data
->uses_drawid
) {
758 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
760 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
761 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32_UINT
,
762 .Component0Control
= VFCOMP_STORE_SRC
,
763 .Component1Control
= VFCOMP_STORE_0
,
764 .Component2Control
= VFCOMP_STORE_0
,
765 .Component3Control
= VFCOMP_STORE_0
,
767 .DestinationElementOffset
= i
* 4,
771 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
772 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
776 if (gen6_edgeflag_input
) {
777 const uint32_t format
=
778 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
780 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
782 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
783 .EdgeFlagEnable
= true,
784 .SourceElementFormat
= format
,
785 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
786 .Component0Control
= VFCOMP_STORE_SRC
,
787 .Component1Control
= VFCOMP_STORE_0
,
788 .Component2Control
= VFCOMP_STORE_0
,
789 .Component3Control
= VFCOMP_STORE_0
,
792 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
793 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
798 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
799 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
800 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
801 unsigned element_index
;
803 /* The edge flag element is reordered to be the last one in the code
804 * above so we need to compensate for that in the element indices used
807 if (input
== gen6_edgeflag_input
)
808 element_index
= nr_elements
- 1;
812 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
813 vfi
.VertexElementIndex
= element_index
;
814 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
815 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
819 if (vs_prog_data
->uses_drawid
) {
820 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
822 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
823 vfi
.VertexElementIndex
= element
;
829 static const struct brw_tracked_state
genX(vertices
) = {
831 .mesa
= _NEW_POLYGON
,
832 .brw
= BRW_NEW_BATCH
|
835 BRW_NEW_VS_PROG_DATA
,
837 .emit
= genX(emit_vertices
),
841 genX(emit_index_buffer
)(struct brw_context
*brw
)
843 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
845 if (index_buffer
== NULL
)
848 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
849 #if GEN_GEN < 8 && !GEN_IS_HASWELL
850 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
852 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
853 ib
.BufferStartingAddress
= ro_bo(brw
->ib
.bo
, 0);
855 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
856 ib
.BufferSize
= brw
->ib
.size
;
858 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
863 static const struct brw_tracked_state
genX(index_buffer
) = {
866 .brw
= BRW_NEW_BATCH
|
868 BRW_NEW_INDEX_BUFFER
,
870 .emit
= genX(emit_index_buffer
),
873 #if GEN_IS_HASWELL || GEN_GEN >= 8
875 genX(upload_cut_index
)(struct brw_context
*brw
)
877 const struct gl_context
*ctx
= &brw
->ctx
;
879 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
880 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
881 vf
.IndexedDrawCutIndexEnable
= true;
882 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
887 const struct brw_tracked_state
genX(cut_index
) = {
889 .mesa
= _NEW_TRANSFORM
,
890 .brw
= BRW_NEW_INDEX_BUFFER
,
892 .emit
= genX(upload_cut_index
),
898 * Determine the appropriate attribute override value to store into the
899 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
900 * override value contains two pieces of information: the location of the
901 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
902 * flag indicating whether to "swizzle" the attribute based on the direction
903 * the triangle is facing.
905 * If an attribute is "swizzled", then the given VUE location is used for
906 * front-facing triangles, and the VUE location that immediately follows is
907 * used for back-facing triangles. We use this to implement the mapping from
908 * gl_FrontColor/gl_BackColor to gl_Color.
910 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
911 * being instructed to begin reading attribute data. It can be set to a
912 * nonzero value to prevent the SF unit from wasting time reading elements of
913 * the VUE that are not needed by the fragment shader. It is measured in
914 * 256-bit increments.
917 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
918 const struct brw_vue_map
*vue_map
,
919 int urb_entry_read_offset
, int fs_attr
,
920 bool two_side_color
, uint32_t *max_source_attr
)
922 /* Find the VUE slot for this attribute. */
923 int slot
= vue_map
->varying_to_slot
[fs_attr
];
925 /* Viewport and Layer are stored in the VUE header. We need to override
926 * them to zero if earlier stages didn't write them, as GL requires that
927 * they read back as zero when not explicitly set.
929 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
930 attr
->ComponentOverrideX
= true;
931 attr
->ComponentOverrideW
= true;
932 attr
->ConstantSource
= CONST_0000
;
934 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
935 attr
->ComponentOverrideY
= true;
936 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
937 attr
->ComponentOverrideZ
= true;
942 /* If there was only a back color written but not front, use back
943 * as the color instead of undefined
945 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
946 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
947 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
948 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
951 /* This attribute does not exist in the VUE--that means that the vertex
952 * shader did not write to it. This means that either:
954 * (a) This attribute is a texture coordinate, and it is going to be
955 * replaced with point coordinates (as a consequence of a call to
956 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
957 * hardware will ignore whatever attribute override we supply.
959 * (b) This attribute is read by the fragment shader but not written by
960 * the vertex shader, so its value is undefined. Therefore the
961 * attribute override we supply doesn't matter.
963 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
964 * previous shader stage.
966 * Note that we don't have to worry about the cases where the attribute
967 * is gl_PointCoord or is undergoing point sprite coordinate
968 * replacement, because in those cases, this function isn't called.
970 * In case (c), we need to program the attribute overrides so that the
971 * primitive ID will be stored in this slot. In every other case, the
972 * attribute override we supply doesn't matter. So just go ahead and
973 * program primitive ID in every case.
975 attr
->ComponentOverrideW
= true;
976 attr
->ComponentOverrideX
= true;
977 attr
->ComponentOverrideY
= true;
978 attr
->ComponentOverrideZ
= true;
979 attr
->ConstantSource
= PRIM_ID
;
983 /* Compute the location of the attribute relative to urb_entry_read_offset.
984 * Each increment of urb_entry_read_offset represents a 256-bit value, so
985 * it counts for two 128-bit VUE slots.
987 int source_attr
= slot
- 2 * urb_entry_read_offset
;
988 assert(source_attr
>= 0 && source_attr
< 32);
990 /* If we are doing two-sided color, and the VUE slot following this one
991 * represents a back-facing color, then we need to instruct the SF unit to
992 * do back-facing swizzling.
994 bool swizzling
= two_side_color
&&
995 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
996 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
997 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
998 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1000 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1001 if (*max_source_attr
< source_attr
+ swizzling
)
1002 *max_source_attr
= source_attr
+ swizzling
;
1004 attr
->SourceAttribute
= source_attr
;
1006 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1011 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1012 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1013 uint32_t *point_sprite_enables
,
1014 uint32_t *urb_entry_read_length
,
1015 uint32_t *urb_entry_read_offset
)
1017 const struct gl_context
*ctx
= &brw
->ctx
;
1020 const struct gl_point_attrib
*point
= &ctx
->Point
;
1022 /* BRW_NEW_FRAGMENT_PROGRAM */
1023 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1025 /* BRW_NEW_FS_PROG_DATA */
1026 const struct brw_wm_prog_data
*wm_prog_data
=
1027 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1028 uint32_t max_source_attr
= 0;
1030 *point_sprite_enables
= 0;
1033 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1034 &brw
->vue_map_geom_out
);
1036 /* Each URB offset packs two varying slots */
1037 assert(first_slot
% 2 == 0);
1038 *urb_entry_read_offset
= first_slot
/ 2;
1040 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1041 * description of dw10 Point Sprite Texture Coordinate Enable:
1043 * "This field must be programmed to zero when non-point primitives
1046 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1047 * must be programmed to zero when rendering non-point primitives, but
1048 * the IvyBridge PRM does, and if we don't, we get garbage.
1050 * This is not required on Haswell, as the hardware ignores this state
1051 * when drawing non-points -- although we do still need to be careful to
1052 * correctly set the attr overrides.
1055 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1057 bool drawing_points
= brw_is_drawing_points(brw
);
1059 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1060 int input_index
= wm_prog_data
->urb_setup
[attr
];
1062 if (input_index
< 0)
1066 bool point_sprite
= false;
1067 if (drawing_points
) {
1068 if (point
->PointSprite
&&
1069 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1070 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1071 point_sprite
= true;
1074 if (attr
== VARYING_SLOT_PNTC
)
1075 point_sprite
= true;
1078 *point_sprite_enables
|= (1 << input_index
);
1081 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1082 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1084 if (!point_sprite
) {
1085 genX(get_attr_override
)(&attribute
,
1086 &brw
->vue_map_geom_out
,
1087 *urb_entry_read_offset
, attr
,
1088 _mesa_vertex_program_two_side_enabled(ctx
),
1092 /* The hardware can only do the overrides on 16 overrides at a
1093 * time, and the other up to 16 have to be lined up so that the
1094 * input index = the output index. We'll need to do some
1095 * tweaking to make sure that's the case.
1097 if (input_index
< 16)
1098 attr_overrides
[input_index
] = attribute
;
1100 assert(attribute
.SourceAttribute
== input_index
);
1103 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1104 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1106 * "This field should be set to the minimum length required to read the
1107 * maximum source attribute. The maximum source attribute is indicated
1108 * by the maximum value of the enabled Attribute # Source Attribute if
1109 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1110 * enable is not set.
1111 * read_length = ceiling((max_source_attr + 1) / 2)
1113 * [errata] Corruption/Hang possible if length programmed larger than
1116 * Similar text exists for Ivy Bridge.
1118 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1122 /* ---------------------------------------------------------------------- */
1125 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1127 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1129 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1133 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1135 struct gl_context
*ctx
= &brw
->ctx
;
1138 struct intel_renderbuffer
*depth_irb
=
1139 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1142 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1145 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1146 const int b
= stencil
->_BackFace
;
1148 if (depth
->Test
&& depth_irb
) {
1149 ds
->DepthTestEnable
= true;
1150 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1151 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1154 if (brw
->stencil_enabled
) {
1155 ds
->StencilTestEnable
= true;
1156 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1157 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1159 ds
->StencilTestFunction
=
1160 intel_translate_compare_func(stencil
->Function
[0]);
1162 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1163 ds
->StencilPassDepthPassOp
=
1164 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1165 ds
->StencilPassDepthFailOp
=
1166 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1168 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1170 if (brw
->stencil_two_sided
) {
1171 ds
->DoubleSidedStencilEnable
= true;
1172 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1173 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1175 ds
->BackfaceStencilTestFunction
=
1176 intel_translate_compare_func(stencil
->Function
[b
]);
1177 ds
->BackfaceStencilFailOp
=
1178 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1179 ds
->BackfaceStencilPassDepthPassOp
=
1180 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1181 ds
->BackfaceStencilPassDepthFailOp
=
1182 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1185 #if GEN_GEN <= 5 || GEN_GEN >= 9
1186 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1187 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1194 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1197 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1198 set_depth_stencil_bits(brw
, &wmds
);
1202 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1203 set_depth_stencil_bits(brw
, &ds
);
1206 /* Now upload a pointer to the indirect state */
1208 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1209 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1210 ptr
.DEPTH_STENCIL_STATEChange
= true;
1213 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1214 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1220 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1222 .mesa
= _NEW_BUFFERS
|
1225 .brw
= BRW_NEW_BLORP
|
1226 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1228 BRW_NEW_STATE_BASE_ADDRESS
),
1230 .emit
= genX(upload_depth_stencil_state
),
1234 /* ---------------------------------------------------------------------- */
1239 genX(upload_clip_state
)(struct brw_context
*brw
)
1241 struct gl_context
*ctx
= &brw
->ctx
;
1243 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1244 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1245 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1246 clip
.GRFRegisterCount
=
1247 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1248 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1249 clip
.SingleProgramFlow
= true;
1250 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1251 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1253 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1254 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1255 clip
.DispatchGRFStartRegisterForURBData
= 1;
1256 clip
.VertexURBEntryReadOffset
= 0;
1258 /* BRW_NEW_URB_FENCE */
1259 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1260 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1262 if (brw
->urb
.nr_clip_entries
>= 10) {
1263 /* Half of the URB entries go to each thread, and it has to be an
1266 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1268 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1269 * only 2 threads can output VUEs at a time.
1271 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1273 assert(brw
->urb
.nr_clip_entries
>= 5);
1274 clip
.MaximumNumberofThreads
= 1 - 1;
1277 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1278 clip
.UserClipFlagsMustClipEnable
= true;
1279 clip
.GuardbandClipTestEnable
= true;
1281 clip
.ClipperViewportStatePointer
=
1282 ro_bo(brw
->batch
.state_bo
, brw
->clip
.vp_offset
);
1284 clip
.ScreenSpaceViewportXMin
= -1;
1285 clip
.ScreenSpaceViewportXMax
= 1;
1286 clip
.ScreenSpaceViewportYMin
= -1;
1287 clip
.ScreenSpaceViewportYMax
= 1;
1289 clip
.ViewportXYClipTestEnable
= true;
1290 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1292 /* _NEW_TRANSFORM */
1293 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1294 clip
.UserClipDistanceClipTestEnableBitmask
=
1295 ctx
->Transform
.ClipPlanesEnabled
;
1297 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1300 clip
.UserClipDistanceClipTestEnableBitmask
=
1301 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1304 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1305 clip
.APIMode
= APIMODE_D3D
;
1307 clip
.APIMode
= APIMODE_OGL
;
1309 clip
.GuardbandClipTestEnable
= true;
1311 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1314 clip
.NegativeWClipTestEnable
= true;
1319 const struct brw_tracked_state
genX(clip_state
) = {
1321 .mesa
= _NEW_TRANSFORM
|
1323 .brw
= BRW_NEW_BATCH
|
1325 BRW_NEW_CLIP_PROG_DATA
|
1326 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1327 BRW_NEW_PROGRAM_CACHE
|
1330 .emit
= genX(upload_clip_state
),
1336 genX(upload_clip_state
)(struct brw_context
*brw
)
1338 struct gl_context
*ctx
= &brw
->ctx
;
1341 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1343 /* BRW_NEW_FS_PROG_DATA */
1344 struct brw_wm_prog_data
*wm_prog_data
=
1345 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1347 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1348 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1350 if (wm_prog_data
->barycentric_interp_modes
&
1351 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1352 clip
.NonPerspectiveBarycentricEnable
= true;
1355 clip
.EarlyCullEnable
= true;
1359 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1361 if (ctx
->Polygon
.CullFlag
) {
1362 switch (ctx
->Polygon
.CullFaceMode
) {
1364 clip
.CullMode
= CULLMODE_FRONT
;
1367 clip
.CullMode
= CULLMODE_BACK
;
1369 case GL_FRONT_AND_BACK
:
1370 clip
.CullMode
= CULLMODE_BOTH
;
1373 unreachable("Should not get here: invalid CullFlag");
1376 clip
.CullMode
= CULLMODE_NONE
;
1381 clip
.UserClipDistanceCullTestEnableBitmask
=
1382 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1384 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1388 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1389 clip
.TriangleStripListProvokingVertexSelect
= 0;
1390 clip
.TriangleFanProvokingVertexSelect
= 1;
1391 clip
.LineStripListProvokingVertexSelect
= 0;
1393 clip
.TriangleStripListProvokingVertexSelect
= 2;
1394 clip
.TriangleFanProvokingVertexSelect
= 2;
1395 clip
.LineStripListProvokingVertexSelect
= 1;
1398 /* _NEW_TRANSFORM */
1399 clip
.UserClipDistanceClipTestEnableBitmask
=
1400 ctx
->Transform
.ClipPlanesEnabled
;
1403 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1406 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1407 clip
.APIMode
= APIMODE_D3D
;
1409 clip
.APIMode
= APIMODE_OGL
;
1411 clip
.GuardbandClipTestEnable
= true;
1413 /* BRW_NEW_VIEWPORT_COUNT */
1414 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1416 if (ctx
->RasterDiscard
) {
1417 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1419 perf_debug("Rasterizer discard is currently implemented via the "
1420 "clipper; having the GS not write primitives would "
1421 "likely be faster.\n");
1424 clip
.ClipMode
= CLIPMODE_NORMAL
;
1427 clip
.ClipEnable
= true;
1430 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1432 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1433 clip
.ViewportXYClipTestEnable
= true;
1435 clip
.MinimumPointWidth
= 0.125;
1436 clip
.MaximumPointWidth
= 255.875;
1437 clip
.MaximumVPIndex
= viewport_count
- 1;
1438 if (_mesa_geometric_layers(fb
) == 0)
1439 clip
.ForceZeroRTAIndexEnable
= true;
1443 static const struct brw_tracked_state
genX(clip_state
) = {
1445 .mesa
= _NEW_BUFFERS
|
1449 .brw
= BRW_NEW_BLORP
|
1451 BRW_NEW_FS_PROG_DATA
|
1452 BRW_NEW_GS_PROG_DATA
|
1453 BRW_NEW_VS_PROG_DATA
|
1454 BRW_NEW_META_IN_PROGRESS
|
1456 BRW_NEW_RASTERIZER_DISCARD
|
1457 BRW_NEW_TES_PROG_DATA
|
1458 BRW_NEW_VIEWPORT_COUNT
,
1460 .emit
= genX(upload_clip_state
),
1464 /* ---------------------------------------------------------------------- */
1467 genX(upload_sf
)(struct brw_context
*brw
)
1469 struct gl_context
*ctx
= &brw
->ctx
;
1474 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1475 UNUSED
const bool multisampled_fbo
=
1476 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1480 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1482 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1484 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1485 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1486 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1487 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1488 sf
.DispatchGRFStartRegisterForURBData
= 3;
1489 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1490 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1491 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1492 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1494 /* STATE_PREFETCH command description describes this state as being
1495 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1498 sf
.SetupViewportStateOffset
=
1499 ro_bo(brw
->batch
.state_bo
, brw
->sf
.vp_offset
);
1501 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1503 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1504 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1506 sf
.MaximumNumberofThreads
=
1507 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1509 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1511 sf
.DestinationOriginHorizontalBias
= 0.5;
1512 sf
.DestinationOriginVerticalBias
= 0.5;
1514 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1515 sf
.StatisticsEnable
= true;
1517 sf
.ViewportTransformEnable
= true;
1521 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1526 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1528 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1529 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1530 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1532 switch (ctx
->Polygon
.FrontMode
) {
1534 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1537 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1540 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1543 unreachable("not reached");
1546 switch (ctx
->Polygon
.BackMode
) {
1548 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1551 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1554 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1557 unreachable("not reached");
1560 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1561 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1563 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1564 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1565 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1568 sf
.ScissorRectangleEnable
= true;
1570 if (ctx
->Polygon
.CullFlag
) {
1571 switch (ctx
->Polygon
.CullFaceMode
) {
1573 sf
.CullMode
= CULLMODE_FRONT
;
1576 sf
.CullMode
= CULLMODE_BACK
;
1578 case GL_FRONT_AND_BACK
:
1579 sf
.CullMode
= CULLMODE_BOTH
;
1582 unreachable("not reached");
1585 sf
.CullMode
= CULLMODE_NONE
;
1589 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1596 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1598 if (devinfo
->is_cherryview
)
1599 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1601 sf
.LineWidth
= brw_get_line_width(brw
);
1603 sf
.LineWidth
= brw_get_line_width(brw
);
1606 if (ctx
->Line
.SmoothFlag
) {
1607 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1609 sf
.AntiAliasingEnable
= true;
1613 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1614 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1615 /* Clamp to the hardware limits */
1616 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1618 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1619 if (use_state_point_size(brw
))
1620 sf
.PointWidthSource
= State
;
1623 /* _NEW_POINT | _NEW_MULTISAMPLE */
1624 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1625 !ctx
->Point
.PointSprite
)
1626 sf
.SmoothPointEnable
= true;
1631 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1633 const bool multisampled_fbo
=
1634 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1635 if (multisampled_fbo
)
1636 sf
.SmoothPointEnable
= false;
1639 #if GEN_IS_G4X || GEN_GEN >= 5
1640 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1644 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1645 sf
.TriangleStripListProvokingVertexSelect
= 2;
1646 sf
.TriangleFanProvokingVertexSelect
= 2;
1647 sf
.LineStripListProvokingVertexSelect
= 1;
1649 sf
.TriangleFanProvokingVertexSelect
= 1;
1653 /* BRW_NEW_FS_PROG_DATA */
1654 const struct brw_wm_prog_data
*wm_prog_data
=
1655 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1657 sf
.AttributeSwizzleEnable
= true;
1658 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1661 * Window coordinates in an FBO are inverted, which means point
1662 * sprite origin must be inverted, too.
1664 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1665 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1667 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1670 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1671 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1673 uint32_t urb_entry_read_length
;
1674 uint32_t urb_entry_read_offset
;
1675 uint32_t point_sprite_enables
;
1676 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1677 &urb_entry_read_length
,
1678 &urb_entry_read_offset
);
1679 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1680 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1681 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1682 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1687 static const struct brw_tracked_state
genX(sf_state
) = {
1689 .mesa
= _NEW_LIGHT
|
1693 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1694 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1695 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1696 .brw
= BRW_NEW_BLORP
|
1697 BRW_NEW_VUE_MAP_GEOM_OUT
|
1698 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1699 BRW_NEW_PROGRAM_CACHE
|
1700 BRW_NEW_SF_PROG_DATA
|
1704 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1705 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1706 BRW_NEW_GS_PROG_DATA
|
1708 BRW_NEW_TES_PROG_DATA
1710 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1711 BRW_NEW_FRAGMENT_PROGRAM
1714 .emit
= genX(upload_sf
),
1717 /* ---------------------------------------------------------------------- */
1720 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1722 struct gl_context
*ctx
= &brw
->ctx
;
1723 /* BRW_NEW_FRAGMENT_PROGRAM */
1724 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1728 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1729 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1730 uint64_t outputs_written
= fp
->info
.outputs_written
;
1733 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1734 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1735 (ctx
->Color
.ColorMask
[i
][0] ||
1736 ctx
->Color
.ColorMask
[i
][1] ||
1737 ctx
->Color
.ColorMask
[i
][2] ||
1738 ctx
->Color
.ColorMask
[i
][3])) {
1747 genX(upload_wm
)(struct brw_context
*brw
)
1749 struct gl_context
*ctx
= &brw
->ctx
;
1751 /* BRW_NEW_FS_PROG_DATA */
1752 const struct brw_wm_prog_data
*wm_prog_data
=
1753 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1755 UNUSED
bool writes_depth
=
1756 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1757 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1758 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1761 /* We can't fold this into gen6_upload_wm_push_constants(), because
1762 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1763 * (3DSTATE_CONSTANT_PS [DevSNB]):
1765 * "[DevSNB]: This packet must be followed by WM_STATE."
1767 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1768 if (wm_prog_data
->base
.nr_params
!= 0) {
1769 wmcp
.Buffer0Valid
= true;
1770 /* Pointer to the WM constant buffer. Covered by the set of
1771 * state flags from gen6_upload_wm_push_constants.
1773 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1774 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1780 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1781 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1782 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1784 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1785 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1787 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1788 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1789 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1790 /* These two fields should be the same pre-gen6, which is why we
1791 * only have one hardware field to program for both dispatch
1794 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1795 wm_prog_data
->dispatch_grf_start_reg_2
);
1798 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1799 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1801 if (stage_state
->sampler_count
)
1802 wm
.SamplerStatePointer
=
1803 ro_bo(brw
->batch
.state_bo
, stage_state
->sampler_offset
);
1805 if (wm_prog_data
->prog_offset_2
)
1806 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1809 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1810 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1811 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1812 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1813 wm
.EarlyDepthTestEnable
= true;
1814 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1815 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1818 if (ctx
->Polygon
.OffsetFill
) {
1819 wm
.GlobalDepthOffsetEnable
= true;
1820 /* Something weird going on with legacy_global_depth_bias,
1821 * offset_constant, scaling and MRD. This value passes glean
1822 * but gives some odd results elsewere (eg. the
1823 * quad-offset-units test).
1825 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1827 /* This is the only value that passes glean:
1829 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1832 wm
.DepthCoefficientURBReadOffset
= 1;
1835 /* BRW_NEW_STATS_WM */
1836 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1839 if (wm_prog_data
->base
.use_alt_mode
)
1840 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1842 wm
.SamplerCount
= GEN_GEN
== 5 ?
1843 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1845 wm
.BindingTableEntryCount
=
1846 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1847 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1848 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1849 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1850 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1851 wm_prog_data
->base
.dispatch_grf_start_reg
;
1853 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1854 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1858 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1859 wm
.KernelStartPointer2
=
1860 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1865 wm
.DualSourceBlendEnable
=
1866 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1867 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1868 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1869 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1871 /* From the SNB PRM, volume 2 part 1, page 281:
1872 * "If the PS kernel does not need the Position XY Offsets
1873 * to compute a Position XY value, then this field should be
1874 * programmed to POSOFFSET_NONE."
1876 * "SW Recommendation: If the PS kernel needs the Position Offsets
1877 * to compute a Position XY value, this field should match Position
1878 * ZW Interpolation Mode to ensure a consistent position.xyzw
1880 * We only require XY sample offsets. So, this recommendation doesn't
1881 * look useful at the moment. We might need this in future.
1883 if (wm_prog_data
->uses_pos_offset
)
1884 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1886 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1888 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1889 wm_prog_data
->dispatch_grf_start_reg_2
;
1892 if (wm_prog_data
->base
.total_scratch
) {
1893 wm
.ScratchSpaceBasePointer
= rw_bo(stage_state
->scratch_bo
, 0);
1894 wm
.PerThreadScratchSpace
=
1895 ffs(stage_state
->per_thread_scratch
) - 11;
1898 wm
.PixelShaderComputedDepth
= writes_depth
;
1902 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1905 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1910 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1913 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1915 if (multisampled_fbo
) {
1916 /* _NEW_MULTISAMPLE */
1917 if (ctx
->Multisample
.Enabled
)
1918 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1920 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1922 if (wm_prog_data
->persample_dispatch
)
1923 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1925 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1927 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1928 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1931 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1932 if (wm_prog_data
->uses_kill
||
1933 _mesa_is_alpha_test_enabled(ctx
) ||
1934 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1935 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1936 wm
.PixelShaderKillsPixel
= true;
1939 /* _NEW_BUFFERS | _NEW_COLOR */
1940 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1941 wm
.PixelShaderKillsPixel
||
1942 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1943 wm
.ThreadDispatchEnable
= true;
1947 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1948 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1951 /* The "UAV access enable" bits are unnecessary on HSW because they only
1952 * seem to have an effect on the HW-assisted coherency mechanism which we
1953 * don't need, and the rasterization-related UAV_ONLY flag and the
1954 * DISPATCH_ENABLE bit can be set independently from it.
1955 * C.f. gen8_upload_ps_extra().
1957 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1961 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1962 wm_prog_data
->has_side_effects
)
1968 /* BRW_NEW_FS_PROG_DATA */
1969 if (wm_prog_data
->early_fragment_tests
)
1970 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1971 else if (wm_prog_data
->has_side_effects
)
1972 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1977 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
1978 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
1979 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1982 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
1987 static const struct brw_tracked_state
genX(wm_state
) = {
1991 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1994 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
1995 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
1996 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
1997 .brw
= BRW_NEW_BLORP
|
1998 BRW_NEW_FS_PROG_DATA
|
1999 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2000 BRW_NEW_FRAGMENT_PROGRAM
|
2001 BRW_NEW_PROGRAM_CACHE
|
2002 BRW_NEW_SAMPLER_STATE_TABLE
|
2005 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2007 .emit
= genX(upload_wm
),
2010 /* ---------------------------------------------------------------------- */
2012 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2013 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2014 pkt.SamplerCount = \
2015 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2016 pkt.BindingTableEntryCount = \
2017 stage_prog_data->binding_table.size_bytes / 4; \
2018 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2020 if (stage_prog_data->total_scratch) { \
2021 pkt.ScratchSpaceBasePointer = rw_bo(stage_state->scratch_bo, 0); \
2022 pkt.PerThreadScratchSpace = \
2023 ffs(stage_state->per_thread_scratch) - 11; \
2026 pkt.DispatchGRFStartRegisterForURBData = \
2027 stage_prog_data->dispatch_grf_start_reg; \
2028 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2029 pkt.prefix##URBEntryReadOffset = 0; \
2031 pkt.StatisticsEnable = true; \
2035 genX(upload_vs_state
)(struct brw_context
*brw
)
2037 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2038 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2039 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2041 /* BRW_NEW_VS_PROG_DATA */
2042 const struct brw_vue_prog_data
*vue_prog_data
=
2043 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2044 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2046 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2047 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2050 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2051 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2053 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2054 * command that causes the VS Function Enable to toggle. Pipeline
2055 * flush can be executed by sending a PIPE_CONTROL command with CS
2056 * stall bit set and a post sync operation.
2058 * We've already done such a flush at the start of state upload, so we
2059 * don't need to do another one here.
2061 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2062 if (stage_state
->push_const_size
!= 0) {
2063 cvs
.Buffer0Valid
= true;
2064 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2065 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2070 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2071 gen7_emit_vs_workaround_flush(brw
);
2074 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2076 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2077 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2079 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2081 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2084 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2085 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2086 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2088 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2089 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2091 vs
.MaximumNumberofThreads
=
2092 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2094 vs
.StatisticsEnable
= false;
2095 vs
.SamplerStatePointer
=
2096 ro_bo(brw
->batch
.state_bo
, stage_state
->sampler_offset
);
2100 /* Force single program flow on Ironlake. We cannot reliably get
2101 * all applications working without it. See:
2102 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2104 * The most notable and reliably failing application is the Humus
2107 vs
.SingleProgramFlow
= true;
2108 vs
.SamplerCount
= 0; /* hardware requirement */
2112 vs
.SIMD8DispatchEnable
=
2113 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2115 vs
.UserClipDistanceCullTestEnableBitmask
=
2116 vue_prog_data
->cull_distance_mask
;
2121 /* Based on my reading of the simulator, the VS constants don't get
2122 * pulled into the VS FF unit until an appropriate pipeline flush
2123 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2124 * references to them into a little FIFO. The flushes are common,
2125 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2126 * the primitive to use the wrong constants. Then the FIFO
2127 * containing the constant setup gets added to again on the next
2128 * constants change, and eventually when a flush does happen the
2129 * unit is overwhelmed by constant changes and dies.
2131 * To avoid this, send a PIPE_CONTROL down the line that will
2132 * update the unit immediately loading the constants. The flush
2133 * type bits here were those set by the STATE_BASE_ADDRESS whose
2134 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2135 * bug reports that led to this workaround, and may be more than
2136 * what is strictly required to avoid the issue.
2138 brw_emit_pipe_control_flush(brw
,
2139 PIPE_CONTROL_DEPTH_STALL
|
2140 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2141 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2145 static const struct brw_tracked_state
genX(vs_state
) = {
2147 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2148 .brw
= BRW_NEW_BATCH
|
2151 BRW_NEW_VS_PROG_DATA
|
2152 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2153 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2154 BRW_NEW_PROGRAM_CACHE
|
2155 BRW_NEW_SAMPLER_STATE_TABLE
|
2159 .emit
= genX(upload_vs_state
),
2162 /* ---------------------------------------------------------------------- */
2165 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2167 struct gl_context
*ctx
= &brw
->ctx
;
2169 /* BRW_NEW_VIEWPORT_COUNT */
2170 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2172 struct GENX(CC_VIEWPORT
) ccv
;
2173 uint32_t cc_vp_offset
;
2175 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2178 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2179 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2180 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2181 if (ctx
->Transform
.DepthClamp
) {
2182 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2183 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2185 ccv
.MinimumDepth
= 0.0;
2186 ccv
.MaximumDepth
= 1.0;
2188 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2189 cc_map
+= GENX(CC_VIEWPORT_length
);
2193 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2194 ptr
.CCViewportPointer
= cc_vp_offset
;
2197 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2198 vp
.CCViewportStateChange
= 1;
2199 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2202 brw
->cc
.vp_offset
= cc_vp_offset
;
2203 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2207 const struct brw_tracked_state
genX(cc_vp
) = {
2209 .mesa
= _NEW_TRANSFORM
|
2211 .brw
= BRW_NEW_BATCH
|
2213 BRW_NEW_VIEWPORT_COUNT
,
2215 .emit
= genX(upload_cc_viewport
)
2218 /* ---------------------------------------------------------------------- */
2221 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2222 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2223 struct GENX(SCISSOR_RECT
) *sc
)
2227 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2228 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2229 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2230 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2231 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2233 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2234 /* If the scissor was out of bounds and got clamped to 0 width/height
2235 * at the bounds, the subtraction of 1 from maximums could produce a
2236 * negative number and thus not clip anything. Instead, just provide
2237 * a min > max scissor inside the bounds, which produces the expected
2240 sc
->ScissorRectangleXMin
= 1;
2241 sc
->ScissorRectangleXMax
= 0;
2242 sc
->ScissorRectangleYMin
= 1;
2243 sc
->ScissorRectangleYMax
= 0;
2244 } else if (render_to_fbo
) {
2245 /* texmemory: Y=0=bottom */
2246 sc
->ScissorRectangleXMin
= bbox
[0];
2247 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2248 sc
->ScissorRectangleYMin
= bbox
[2];
2249 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2251 /* memory: Y=0=top */
2252 sc
->ScissorRectangleXMin
= bbox
[0];
2253 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2254 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2255 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2261 genX(upload_scissor_state
)(struct brw_context
*brw
)
2263 struct gl_context
*ctx
= &brw
->ctx
;
2264 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2265 struct GENX(SCISSOR_RECT
) scissor
;
2266 uint32_t scissor_state_offset
;
2267 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2268 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2269 uint32_t *scissor_map
;
2271 /* BRW_NEW_VIEWPORT_COUNT */
2272 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2274 scissor_map
= brw_state_batch(
2275 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2276 32, &scissor_state_offset
);
2278 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2280 /* The scissor only needs to handle the intersection of drawable and
2281 * scissor rect. Clipping to the boundaries of static shared buffers
2282 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2284 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2285 * inclusive but max is exclusive.
2287 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2288 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2289 GENX(SCISSOR_RECT_pack
)(
2290 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2293 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2294 ptr
.ScissorRectPointer
= scissor_state_offset
;
2298 static const struct brw_tracked_state
genX(scissor_state
) = {
2300 .mesa
= _NEW_BUFFERS
|
2303 .brw
= BRW_NEW_BATCH
|
2305 BRW_NEW_VIEWPORT_COUNT
,
2307 .emit
= genX(upload_scissor_state
),
2311 /* ---------------------------------------------------------------------- */
2314 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2315 float m00
, float m11
, float m30
, float m31
,
2316 float *xmin
, float *xmax
,
2317 float *ymin
, float *ymax
)
2319 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2320 * Strips and Fans documentation:
2322 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2323 * fixed-point "guardband" range supported by the rasterization hardware"
2327 * "In almost all circumstances, if an object’s vertices are actually
2328 * modified by this clamping (i.e., had X or Y coordinates outside of
2329 * the guardband extent the rendered object will not match the intended
2330 * result. Therefore software should take steps to ensure that this does
2331 * not happen - e.g., by clipping objects such that they do not exceed
2332 * these limits after the Drawing Rectangle is applied."
2334 * I believe the fundamental restriction is that the rasterizer (in
2335 * the SF/WM stages) have a limit on the number of pixels that can be
2336 * rasterized. We need to ensure any coordinates beyond the rasterizer
2337 * limit are handled by the clipper. So effectively that limit becomes
2338 * the clipper's guardband size.
2340 * It goes on to say:
2342 * "In addition, in order to be correctly rendered, objects must have a
2343 * screenspace bounding box not exceeding 8K in the X or Y direction.
2344 * This additional restriction must also be comprehended by software,
2345 * i.e., enforced by use of clipping."
2347 * This makes no sense. Gen7+ hardware supports 16K render targets,
2348 * and you definitely need to be able to draw polygons that fill the
2349 * surface. Our assumption is that the rasterizer was limited to 8K
2350 * on Sandybridge, which only supports 8K surfaces, and it was actually
2351 * increased to 16K on Ivybridge and later.
2353 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2355 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2357 if (m00
!= 0 && m11
!= 0) {
2358 /* First, we compute the screen-space render area */
2359 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2360 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2361 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2362 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2364 /* We want the guardband to be centered on that */
2365 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2366 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2367 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2368 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2370 /* Now we need it in native device coordinates */
2371 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2372 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2373 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2374 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2376 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2377 * flipped upside-down. X should be fine though.
2379 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2380 *xmin
= ndc_gb_xmin
;
2381 *xmax
= ndc_gb_xmax
;
2382 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2383 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2385 /* The viewport scales to 0, so nothing will be rendered. */
2394 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2396 struct gl_context
*ctx
= &brw
->ctx
;
2397 float y_scale
, y_bias
;
2399 /* BRW_NEW_VIEWPORT_COUNT */
2400 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2403 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2404 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2405 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2409 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2410 uint32_t sf_clip_vp_offset
;
2411 uint32_t *sf_clip_map
=
2412 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2413 64, &sf_clip_vp_offset
);
2415 struct GENX(SF_VIEWPORT
) sfv
;
2416 struct GENX(CLIP_VIEWPORT
) clv
;
2417 uint32_t sf_vp_offset
, clip_vp_offset
;
2419 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2421 uint32_t *clip_map
=
2422 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2423 32, &clip_vp_offset
);
2427 if (render_to_fbo
) {
2432 y_bias
= (float)fb_height
;
2435 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2436 /* _NEW_VIEWPORT: Guardband Clipping */
2437 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2438 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2440 sfv
.ViewportMatrixElementm00
= scale
[0];
2441 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2442 sfv
.ViewportMatrixElementm22
= scale
[2],
2443 sfv
.ViewportMatrixElementm30
= translate
[0],
2444 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2445 sfv
.ViewportMatrixElementm32
= translate
[2],
2446 brw_calculate_guardband_size(fb_width
, fb_height
,
2447 sfv
.ViewportMatrixElementm00
,
2448 sfv
.ViewportMatrixElementm11
,
2449 sfv
.ViewportMatrixElementm30
,
2450 sfv
.ViewportMatrixElementm31
,
2451 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2454 clv
.XMinClipGuardband
= gb_xmin
;
2455 clv
.XMaxClipGuardband
= gb_xmax
;
2456 clv
.YMinClipGuardband
= gb_ymin
;
2457 clv
.YMaxClipGuardband
= gb_ymax
;
2460 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2461 &sfv
.ScissorRectangle
);
2463 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2464 * The hardware will take the intersection of the drawing rectangle,
2465 * scissor rectangle, and the viewport extents. We don't need to be
2466 * smart, and can therefore just program the viewport extents.
2468 const float viewport_Xmax
=
2469 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2470 const float viewport_Ymax
=
2471 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2473 if (render_to_fbo
) {
2474 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2475 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2476 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2477 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2479 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2480 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2481 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2482 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2487 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2488 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2490 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2491 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2492 sf_map
+= GENX(SF_VIEWPORT_length
);
2493 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2498 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2499 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2502 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2503 vp
.SFViewportStateChange
= 1;
2504 vp
.CLIPViewportStateChange
= 1;
2505 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2506 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2509 brw
->sf
.vp_offset
= sf_vp_offset
;
2510 brw
->clip
.vp_offset
= clip_vp_offset
;
2511 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2515 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2517 .mesa
= _NEW_BUFFERS
|
2519 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2520 .brw
= BRW_NEW_BATCH
|
2522 BRW_NEW_VIEWPORT_COUNT
,
2524 .emit
= genX(upload_sf_clip_viewport
),
2527 /* ---------------------------------------------------------------------- */
2530 genX(upload_gs_state
)(struct brw_context
*brw
)
2532 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2533 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2534 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2535 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2536 /* BRW_NEW_GEOMETRY_PROGRAM */
2537 bool active
= GEN_GEN
>= 6 && gs_prog
;
2539 /* BRW_NEW_GS_PROG_DATA */
2540 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2541 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2542 brw_vue_prog_data(stage_prog_data
);
2544 const struct brw_gs_prog_data
*gs_prog_data
=
2545 brw_gs_prog_data(stage_prog_data
);
2549 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2550 if (active
&& stage_state
->push_const_size
!= 0) {
2551 cgs
.Buffer0Valid
= true;
2552 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2553 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2558 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2560 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2561 * Geometry > Geometry Shader > State:
2563 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2564 * whole fixed function pipeline when the GS enable changes value in
2567 * The hardware architects have clarified that in this context "flush the
2568 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2571 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2572 gen7_emit_cs_stall_flush(brw
);
2576 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2578 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2579 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2584 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2587 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2588 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2589 gs
.ControlDataHeaderSize
=
2590 gs_prog_data
->control_data_header_size_hwords
;
2592 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2593 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2595 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2597 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2600 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2601 * Ivy Bridge and Haswell.
2603 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2604 * strip to be delivered to the geometry shader in an order that does
2605 * not strictly follow the OpenGL spec, but preserves triangle
2606 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2607 * the geometry shader sees triangles:
2609 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2611 * (Clearing the bit is even worse, because it fails to preserve
2614 * Triangle strips with adjacency always ordered in a way that preserves
2615 * triangle orientation but does not strictly follow the OpenGL spec,
2616 * regardless of the setting of this bit.
2618 * On Haswell, both triangle strips and triangle strips with adjacency
2619 * are always ordered in a way that preserves triangle orientation.
2620 * Setting this bit causes the ordering to strictly follow the OpenGL
2623 * So in either case we want to set the bit. Unfortunately on Ivy
2624 * Bridge this will get the order close to correct but not perfect.
2626 gs
.ReorderMode
= TRAILING
;
2627 gs
.MaximumNumberofThreads
=
2628 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2629 : (devinfo
->max_gs_threads
- 1);
2632 gs
.SOStatisticsEnable
= true;
2633 if (gs_prog
->info
.has_transform_feedback_varyings
)
2634 gs
.SVBIPayloadEnable
= true;
2636 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2637 * was previously done for gen6.
2639 * TODO: test with both disabled to see if the HW is behaving
2640 * as expected, like in gen7.
2642 gs
.SingleProgramFlow
= true;
2643 gs
.VectorMaskEnable
= true;
2647 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2649 if (gs_prog_data
->static_vertex_count
!= -1) {
2650 gs
.StaticOutput
= true;
2651 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2653 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2655 gs
.UserClipDistanceCullTestEnableBitmask
=
2656 vue_prog_data
->cull_distance_mask
;
2658 const int urb_entry_write_offset
= 1;
2659 const uint32_t urb_entry_output_length
=
2660 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2661 urb_entry_write_offset
;
2663 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2664 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2670 if (!active
&& brw
->ff_gs
.prog_active
) {
2671 /* In gen6, transform feedback for the VS stage is done with an
2672 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2675 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2676 gs
.SingleProgramFlow
= true;
2677 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2678 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2681 gs
.GRFRegisterCount
=
2682 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2683 /* BRW_NEW_URB_FENCE */
2684 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2685 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2686 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2687 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2690 gs
.VectorMaskEnable
= true;
2691 gs
.SVBIPayloadEnable
= true;
2692 gs
.SVBIPostIncrementEnable
= true;
2693 gs
.SVBIPostIncrementValue
=
2694 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2695 gs
.SOStatisticsEnable
= true;
2696 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2700 if (!active
&& !brw
->ff_gs
.prog_active
) {
2702 gs
.DispatchGRFStartRegisterForURBData
= 1;
2704 gs
.IncludeVertexHandles
= true;
2710 gs
.StatisticsEnable
= true;
2712 #if GEN_GEN == 5 || GEN_GEN == 6
2713 gs
.RenderingEnabled
= true;
2716 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2721 brw
->gs
.enabled
= active
;
2725 static const struct brw_tracked_state
genX(gs_state
) = {
2727 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2728 .brw
= BRW_NEW_BATCH
|
2730 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2731 BRW_NEW_PROGRAM_CACHE
|
2733 BRW_NEW_VIEWPORT_COUNT
2735 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2736 BRW_NEW_GEOMETRY_PROGRAM
|
2737 BRW_NEW_GS_PROG_DATA
2739 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2741 .emit
= genX(upload_gs_state
),
2744 /* ---------------------------------------------------------------------- */
2746 UNUSED
static GLenum
2747 fix_dual_blend_alpha_to_one(GLenum function
)
2753 case GL_ONE_MINUS_SRC1_ALPHA
:
2760 #define blend_factor(x) brw_translate_blend_factor(x)
2761 #define blend_eqn(x) brw_translate_blend_equation(x)
2764 * Modify blend function to force destination alpha to 1.0
2766 * If \c function specifies a blend function that uses destination alpha,
2767 * replace it with a function that hard-wires destination alpha to 1.0. This
2768 * is used when rendering to xRGB targets.
2771 brw_fix_xRGB_alpha(GLenum function
)
2777 case GL_ONE_MINUS_DST_ALPHA
:
2778 case GL_SRC_ALPHA_SATURATE
:
2786 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2788 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2792 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2795 struct gl_context
*ctx
= &brw
->ctx
;
2798 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2800 bool independent_alpha_blend
= false;
2802 /* Used for implementing the following bit of GL_EXT_texture_integer:
2803 * "Per-fragment operations that require floating-point color
2804 * components, including multisample alpha operations, alpha test,
2805 * blending, and dithering, have no effect when the corresponding
2806 * colors are written to an integer color buffer."
2808 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2810 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2811 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2814 if (ctx
->Color
.ColorLogicOpEnabled
) {
2815 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2816 : GL_UNSIGNED_NORMALIZED
;
2817 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2818 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2819 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2821 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2822 _mesa_enum_to_string(rb_type
));
2823 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2824 entry
->LogicOpEnable
= true;
2825 entry
->LogicOpFunction
=
2826 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2828 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2829 && (GEN_GEN
<= 5 || !integer
)) {
2830 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2831 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2832 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2833 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2834 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2835 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2837 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2838 srcRGB
= dstRGB
= GL_ONE
;
2840 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2841 srcA
= dstA
= GL_ONE
;
2843 /* Due to hardware limitations, the destination may have information
2844 * in an alpha channel even when the format specifies no alpha
2845 * channel. In order to avoid getting any incorrect blending due to
2846 * that alpha channel, coerce the blend factors to values that will
2847 * not read the alpha channel, but will instead use the correct
2848 * implicit value for alpha.
2850 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2851 GL_TEXTURE_ALPHA_TYPE
)) {
2852 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2853 srcA
= brw_fix_xRGB_alpha(srcA
);
2854 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2855 dstA
= brw_fix_xRGB_alpha(dstA
);
2858 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2859 * "If Dual Source Blending is enabled, this bit must be disabled."
2861 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2862 * and leave it enabled anyway.
2864 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2865 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2866 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2867 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2868 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2871 entry
->ColorBufferBlendEnable
= true;
2872 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2873 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2874 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2875 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2876 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2877 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2879 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2880 independent_alpha_blend
= true;
2883 return independent_alpha_blend
;
2888 genX(upload_blend_state
)(struct brw_context
*brw
)
2890 struct gl_context
*ctx
= &brw
->ctx
;
2893 /* We need at least one BLEND_STATE written, because we might do
2894 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2895 * for computed depth or alpha test), which will do an FB write
2896 * with render target 0, which will reference BLEND_STATE[0] for
2897 * alpha test enable.
2899 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2900 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2901 nr_draw_buffers
= 1;
2903 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2905 size
+= GENX(BLEND_STATE_length
) * 4;
2908 uint32_t *blend_map
;
2909 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2912 struct GENX(BLEND_STATE
) blend
= { 0 };
2915 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2916 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2919 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2920 * "If drawbuffer zero is not NONE and the buffer it references has an
2921 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2922 * operations are skipped."
2924 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2925 /* _NEW_MULTISAMPLE */
2926 if (_mesa_is_multisample_enabled(ctx
)) {
2927 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2928 blend
.AlphaToCoverageEnable
= true;
2929 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2931 if (ctx
->Multisample
.SampleAlphaToOne
)
2932 blend
.AlphaToOneEnable
= true;
2936 if (ctx
->Color
.AlphaEnabled
) {
2937 blend
.AlphaTestEnable
= true;
2938 blend
.AlphaTestFunction
=
2939 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2942 if (ctx
->Color
.DitherFlag
) {
2943 blend
.ColorDitherEnable
= true;
2948 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2949 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2953 blend
.IndependentAlphaBlendEnable
=
2954 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
2955 blend
.IndependentAlphaBlendEnable
;
2957 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2958 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2960 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2961 * clamping in the fragment shader. For its clamping of
2962 * blending, the spec says:
2964 * "RESOLVED: For fixed-point color buffers, the inputs and
2965 * the result of the blending equation are clamped. For
2966 * floating-point color buffers, no clamping occurs."
2968 * So, generally, we want clamping to the render target's range.
2969 * And, good news, the hardware tables for both pre- and
2970 * post-blend color clamping are either ignored, or any are
2971 * allowed, or clamping is required but RT range clamping is a
2974 entry
.PreBlendColorClampEnable
= true;
2975 entry
.PostBlendColorClampEnable
= true;
2976 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2978 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2979 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2980 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2981 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2984 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2986 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2992 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2996 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2997 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2998 ptr
.BLEND_STATEChange
= true;
3001 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3002 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3004 ptr
.BlendStatePointerValid
= true;
3010 static const struct brw_tracked_state
genX(blend_state
) = {
3012 .mesa
= _NEW_BUFFERS
|
3015 .brw
= BRW_NEW_BATCH
|
3017 BRW_NEW_STATE_BASE_ADDRESS
,
3019 .emit
= genX(upload_blend_state
),
3023 /* ---------------------------------------------------------------------- */
3026 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3027 [MESA_SHADER_VERTEX
] = 21,
3028 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3029 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3030 [MESA_SHADER_GEOMETRY
] = 22,
3031 [MESA_SHADER_FRAGMENT
] = 23,
3032 [MESA_SHADER_COMPUTE
] = 0,
3036 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3038 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3039 struct gl_context
*ctx
= &brw
->ctx
;
3041 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3043 struct brw_stage_state
*stage_states
[] = {
3051 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3052 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3053 gen7_emit_vs_workaround_flush(brw
);
3055 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3056 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3057 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3059 if (!stage_state
->push_constants_dirty
)
3062 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3063 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3064 if (stage_state
->prog_data
) {
3065 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3066 /* The Skylake PRM contains the following restriction:
3068 * "The driver must ensure The following case does not occur
3069 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3070 * buffer 3 read length equal to zero committed followed by a
3071 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3074 * To avoid this, we program the buffers in the highest slots.
3075 * This way, slot 0 is only used if slot 3 is also used.
3079 for (int i
= 3; i
>= 0; i
--) {
3080 const struct brw_ubo_range
*range
=
3081 &stage_state
->prog_data
->ubo_ranges
[i
];
3083 if (range
->length
== 0)
3086 const struct gl_uniform_block
*block
=
3087 prog
->sh
.UniformBlocks
[range
->block
];
3088 const struct gl_buffer_binding
*binding
=
3089 &ctx
->UniformBufferBindings
[block
->Binding
];
3091 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3092 static unsigned msg_id
= 0;
3093 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3094 MESA_DEBUG_TYPE_UNDEFINED
,
3095 MESA_DEBUG_SEVERITY_HIGH
,
3096 "UBO %d unbound, %s shader uniform data "
3097 "will be undefined.",
3099 _mesa_shader_stage_to_string(stage
));
3103 assert(binding
->Offset
% 32 == 0);
3105 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3106 intel_buffer_object(binding
->BufferObject
),
3107 binding
->Offset
, range
->length
* 32, false);
3109 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3110 pkt
.ConstantBody
.Buffer
[n
] =
3111 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3115 if (stage_state
->push_const_size
> 0) {
3117 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3118 pkt
.ConstantBody
.Buffer
[n
] =
3119 ro_bo(stage_state
->push_const_bo
,
3120 stage_state
->push_const_offset
);
3123 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3124 pkt
.ConstantBody
.Buffer
[0].offset
=
3125 stage_state
->push_const_offset
| mocs
;
3130 stage_state
->push_constants_dirty
= false;
3131 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3135 const struct brw_tracked_state
genX(push_constant_packets
) = {
3138 .brw
= BRW_NEW_DRAW_CALL
,
3140 .emit
= genX(upload_push_constant_packets
),
3146 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3148 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3150 /* BRW_NEW_VERTEX_PROGRAM */
3151 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3152 /* BRW_NEW_VS_PROG_DATA */
3153 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3155 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3158 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3160 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3162 .brw
= BRW_NEW_BATCH
|
3164 BRW_NEW_VERTEX_PROGRAM
|
3165 BRW_NEW_VS_PROG_DATA
,
3167 .emit
= genX(upload_vs_push_constants
),
3171 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3173 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3175 /* BRW_NEW_GEOMETRY_PROGRAM */
3176 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3178 /* BRW_NEW_GS_PROG_DATA */
3179 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3181 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3184 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3186 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3188 .brw
= BRW_NEW_BATCH
|
3190 BRW_NEW_GEOMETRY_PROGRAM
|
3191 BRW_NEW_GS_PROG_DATA
,
3193 .emit
= genX(upload_gs_push_constants
),
3197 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3199 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3200 /* BRW_NEW_FRAGMENT_PROGRAM */
3201 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3202 /* BRW_NEW_FS_PROG_DATA */
3203 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3205 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3208 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3210 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3211 .brw
= BRW_NEW_BATCH
|
3213 BRW_NEW_FRAGMENT_PROGRAM
|
3214 BRW_NEW_FS_PROG_DATA
,
3216 .emit
= genX(upload_wm_push_constants
),
3220 /* ---------------------------------------------------------------------- */
3224 genX(determine_sample_mask
)(struct brw_context
*brw
)
3226 struct gl_context
*ctx
= &brw
->ctx
;
3227 float coverage
= 1.0f
;
3228 float coverage_invert
= false;
3229 unsigned sample_mask
= ~0u;
3231 /* BRW_NEW_NUM_SAMPLES */
3232 unsigned num_samples
= brw
->num_samples
;
3234 if (_mesa_is_multisample_enabled(ctx
)) {
3235 if (ctx
->Multisample
.SampleCoverage
) {
3236 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3237 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3239 if (ctx
->Multisample
.SampleMask
) {
3240 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3244 if (num_samples
> 1) {
3245 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3246 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3247 if (coverage_invert
)
3248 coverage_bits
^= (1 << num_samples
) - 1;
3249 return coverage_bits
& sample_mask
;
3256 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3257 unsigned num_samples
)
3259 unsigned log2_samples
= ffs(num_samples
) - 1;
3261 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3262 multi
.PixelLocation
= CENTER
;
3263 multi
.NumberofMultisamples
= log2_samples
;
3265 GEN_SAMPLE_POS_4X(multi
.Sample
);
3267 switch (num_samples
) {
3269 GEN_SAMPLE_POS_1X(multi
.Sample
);
3272 GEN_SAMPLE_POS_2X(multi
.Sample
);
3275 GEN_SAMPLE_POS_4X(multi
.Sample
);
3278 GEN_SAMPLE_POS_8X(multi
.Sample
);
3288 genX(upload_multisample_state
)(struct brw_context
*brw
)
3290 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3292 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3294 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3295 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3299 static const struct brw_tracked_state
genX(multisample_state
) = {
3301 .mesa
= _NEW_MULTISAMPLE
,
3302 .brw
= BRW_NEW_BLORP
|
3304 BRW_NEW_NUM_SAMPLES
,
3306 .emit
= genX(upload_multisample_state
)
3310 /* ---------------------------------------------------------------------- */
3313 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3315 struct gl_context
*ctx
= &brw
->ctx
;
3317 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3319 cc
.IndependentAlphaBlendEnable
=
3320 set_blend_entry_bits(brw
, &cc
, 0, false);
3321 set_depth_stencil_bits(brw
, &cc
);
3323 if (ctx
->Color
.AlphaEnabled
&&
3324 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3325 cc
.AlphaTestEnable
= true;
3326 cc
.AlphaTestFunction
=
3327 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3330 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3332 cc
.StatisticsEnable
= brw
->stats_wm
;
3334 cc
.CCViewportStatePointer
=
3335 ro_bo(brw
->batch
.state_bo
, brw
->cc
.vp_offset
);
3338 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3339 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3340 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3341 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3345 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3346 cc
.BackfaceStencilReferenceValue
=
3347 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3353 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3354 ctx
->Color
.AlphaRef
);
3358 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3359 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3361 ptr
.ColorCalcStatePointerValid
= true;
3365 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3369 static const struct brw_tracked_state
genX(color_calc_state
) = {
3371 .mesa
= _NEW_COLOR
|
3373 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3376 .brw
= BRW_NEW_BATCH
|
3378 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3380 : BRW_NEW_CC_STATE
|
3381 BRW_NEW_STATE_BASE_ADDRESS
),
3383 .emit
= genX(upload_color_calc_state
),
3387 /* ---------------------------------------------------------------------- */
3391 genX(upload_sbe
)(struct brw_context
*brw
)
3393 struct gl_context
*ctx
= &brw
->ctx
;
3394 /* BRW_NEW_FRAGMENT_PROGRAM */
3395 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3396 /* BRW_NEW_FS_PROG_DATA */
3397 const struct brw_wm_prog_data
*wm_prog_data
=
3398 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3400 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3402 #define attr_overrides sbe.Attribute
3404 uint32_t urb_entry_read_length
;
3405 uint32_t urb_entry_read_offset
;
3406 uint32_t point_sprite_enables
;
3408 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3409 sbe
.AttributeSwizzleEnable
= true;
3410 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3413 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3417 * Window coordinates in an FBO are inverted, which means point
3418 * sprite origin must be inverted.
3420 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3421 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3423 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3425 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3426 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3427 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3428 * BRW_NEW_VUE_MAP_GEOM_OUT
3430 genX(calculate_attr_overrides
)(brw
,
3432 &point_sprite_enables
,
3433 &urb_entry_read_length
,
3434 &urb_entry_read_offset
);
3436 /* Typically, the URB entry read length and offset should be programmed
3437 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3438 * stage which produces geometry. However, we don't know the proper
3439 * value until we call calculate_attr_overrides().
3441 * To fit with our existing code, we override the inherited values and
3442 * specify it here directly, as we did on previous generations.
3444 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3445 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3446 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3447 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3450 sbe
.ForceVertexURBEntryReadLength
= true;
3451 sbe
.ForceVertexURBEntryReadOffset
= true;
3455 /* prepare the active component dwords */
3456 const int num_inputs
= urb_entry_read_length
* 2;
3457 for (int input_index
= 0; input_index
< num_inputs
; input_index
++) {
3458 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3464 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3465 for (int i
= 0; i
< 16; i
++)
3466 sbes
.Attribute
[i
] = attr_overrides
[i
];
3470 #undef attr_overrides
3473 static const struct brw_tracked_state
genX(sbe_state
) = {
3475 .mesa
= _NEW_BUFFERS
|
3480 .brw
= BRW_NEW_BLORP
|
3482 BRW_NEW_FRAGMENT_PROGRAM
|
3483 BRW_NEW_FS_PROG_DATA
|
3484 BRW_NEW_GS_PROG_DATA
|
3485 BRW_NEW_TES_PROG_DATA
|
3486 BRW_NEW_VUE_MAP_GEOM_OUT
|
3487 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3490 .emit
= genX(upload_sbe
),
3494 /* ---------------------------------------------------------------------- */
3498 * Outputs the 3DSTATE_SO_DECL_LIST command.
3500 * The data output is a series of 64-bit entries containing a SO_DECL per
3501 * stream. We only have one stream of rendering coming out of the GS unit, so
3502 * we only emit stream 0 (low 16 bits) SO_DECLs.
3505 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3506 const struct brw_vue_map
*vue_map
)
3508 struct gl_context
*ctx
= &brw
->ctx
;
3509 /* BRW_NEW_TRANSFORM_FEEDBACK */
3510 struct gl_transform_feedback_object
*xfb_obj
=
3511 ctx
->TransformFeedback
.CurrentObject
;
3512 const struct gl_transform_feedback_info
*linked_xfb_info
=
3513 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3514 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3515 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3516 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3517 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3519 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3521 memset(so_decl
, 0, sizeof(so_decl
));
3523 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3524 * command feels strange -- each dword pair contains a SO_DECL per stream.
3526 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3527 const struct gl_transform_feedback_output
*output
=
3528 &linked_xfb_info
->Outputs
[i
];
3529 const int buffer
= output
->OutputBuffer
;
3530 const int varying
= output
->OutputRegister
;
3531 const unsigned stream_id
= output
->StreamId
;
3532 assert(stream_id
< MAX_VERTEX_STREAMS
);
3534 buffer_mask
[stream_id
] |= 1 << buffer
;
3536 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3538 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3539 * array. Instead, it simply increments DstOffset for the following
3540 * input by the number of components that should be skipped.
3542 * Our hardware is unusual in that it requires us to program SO_DECLs
3543 * for fake "hole" components, rather than simply taking the offset
3544 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3545 * program as many size = 4 holes as we can, then a final hole to
3546 * accommodate the final 1, 2, or 3 remaining.
3548 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3550 while (skip_components
> 0) {
3551 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3553 .OutputBufferSlot
= output
->OutputBuffer
,
3554 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3556 skip_components
-= 4;
3559 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3561 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3562 .OutputBufferSlot
= output
->OutputBuffer
,
3563 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3565 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3568 if (decls
[stream_id
] > max_decls
)
3569 max_decls
= decls
[stream_id
];
3573 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3574 .StreamtoBufferSelects0
= buffer_mask
[0],
3575 .StreamtoBufferSelects1
= buffer_mask
[1],
3576 .StreamtoBufferSelects2
= buffer_mask
[2],
3577 .StreamtoBufferSelects3
= buffer_mask
[3],
3578 .NumEntries0
= decls
[0],
3579 .NumEntries1
= decls
[1],
3580 .NumEntries2
= decls
[2],
3581 .NumEntries3
= decls
[3]);
3583 for (int i
= 0; i
< max_decls
; i
++) {
3584 GENX(SO_DECL_ENTRY_pack
)(
3585 brw
, dw
+ 2 + i
* 2,
3586 &(struct GENX(SO_DECL_ENTRY
)) {
3587 .Stream0Decl
= so_decl
[0][i
],
3588 .Stream1Decl
= so_decl
[1][i
],
3589 .Stream2Decl
= so_decl
[2][i
],
3590 .Stream3Decl
= so_decl
[3][i
],
3596 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3598 struct gl_context
*ctx
= &brw
->ctx
;
3599 /* BRW_NEW_TRANSFORM_FEEDBACK */
3600 struct gl_transform_feedback_object
*xfb_obj
=
3601 ctx
->TransformFeedback
.CurrentObject
;
3603 const struct gl_transform_feedback_info
*linked_xfb_info
=
3604 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3606 struct brw_transform_feedback_object
*brw_obj
=
3607 (struct brw_transform_feedback_object
*) xfb_obj
;
3608 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3611 /* Set up the up to 4 output buffers. These are the ranges defined in the
3612 * gl_transform_feedback_object.
3614 for (int i
= 0; i
< 4; i
++) {
3615 struct intel_buffer_object
*bufferobj
=
3616 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3619 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3620 sob
.SOBufferIndex
= i
;
3625 uint32_t start
= xfb_obj
->Offset
[i
];
3626 assert(start
% 4 == 0);
3627 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3629 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3630 assert(end
<= bo
->size
);
3632 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3633 sob
.SOBufferIndex
= i
;
3635 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3637 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3638 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3640 sob
.SOBufferEnable
= true;
3641 sob
.StreamOffsetWriteEnable
= true;
3642 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3643 sob
.SOBufferMOCS
= mocs_wb
;
3645 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3646 sob
.StreamOutputBufferOffsetAddress
=
3647 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3649 if (brw_obj
->zero_offsets
) {
3650 /* Zero out the offset and write that to offset_bo */
3651 sob
.StreamOffset
= 0;
3653 /* Use offset_bo as the "Stream Offset." */
3654 sob
.StreamOffset
= 0xFFFFFFFF;
3661 brw_obj
->zero_offsets
= false;
3666 query_active(struct gl_query_object
*q
)
3668 return q
&& q
->Active
;
3672 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3673 const struct brw_vue_map
*vue_map
)
3675 struct gl_context
*ctx
= &brw
->ctx
;
3676 /* BRW_NEW_TRANSFORM_FEEDBACK */
3677 struct gl_transform_feedback_object
*xfb_obj
=
3678 ctx
->TransformFeedback
.CurrentObject
;
3680 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3682 int urb_entry_read_offset
= 0;
3683 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3684 urb_entry_read_offset
;
3686 sos
.SOFunctionEnable
= true;
3687 sos
.SOStatisticsEnable
= true;
3689 /* BRW_NEW_RASTERIZER_DISCARD */
3690 if (ctx
->RasterDiscard
) {
3691 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3692 sos
.RenderingDisable
= true;
3694 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3695 "query active relies on the clipper.\n");
3700 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3701 sos
.ReorderMode
= TRAILING
;
3704 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3705 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3706 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3707 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3709 const struct gl_transform_feedback_info
*linked_xfb_info
=
3710 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3711 /* Set buffer pitches; 0 means unbound. */
3712 if (xfb_obj
->Buffers
[0])
3713 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3714 if (xfb_obj
->Buffers
[1])
3715 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3716 if (xfb_obj
->Buffers
[2])
3717 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3718 if (xfb_obj
->Buffers
[3])
3719 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3722 /* We always read the whole vertex. This could be reduced at some
3723 * point by reading less and offsetting the register index in the
3726 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3727 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3728 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3729 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3730 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3731 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3732 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3733 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3739 genX(upload_sol
)(struct brw_context
*brw
)
3741 struct gl_context
*ctx
= &brw
->ctx
;
3742 /* BRW_NEW_TRANSFORM_FEEDBACK */
3743 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3746 genX(upload_3dstate_so_buffers
)(brw
);
3748 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3749 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3752 /* Finally, set up the SOL stage. This command must always follow updates to
3753 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3754 * MMIO register updates (current performed by the kernel at each batch
3757 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3760 static const struct brw_tracked_state
genX(sol_state
) = {
3763 .brw
= BRW_NEW_BATCH
|
3765 BRW_NEW_RASTERIZER_DISCARD
|
3766 BRW_NEW_VUE_MAP_GEOM_OUT
|
3767 BRW_NEW_TRANSFORM_FEEDBACK
,
3769 .emit
= genX(upload_sol
),
3773 /* ---------------------------------------------------------------------- */
3777 genX(upload_ps
)(struct brw_context
*brw
)
3779 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3780 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3782 /* BRW_NEW_FS_PROG_DATA */
3783 const struct brw_wm_prog_data
*prog_data
=
3784 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3785 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3790 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3791 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3792 * incorrect for subspans where some of the pixels are unlit. We believe
3793 * the bit just didn't take effect in previous generations.
3795 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3798 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3800 /* BRW_NEW_FS_PROG_DATA */
3801 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3803 if (prog_data
->base
.use_alt_mode
)
3804 ps
.FloatingPointMode
= Alternate
;
3806 /* Haswell requires the sample mask to be set in this packet as well as
3807 * in 3DSTATE_SAMPLE_MASK; the values should match.
3810 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3812 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3815 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3816 * it implicitly scales for different GT levels (which have some # of
3819 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3822 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3824 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3826 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3829 if (prog_data
->base
.nr_params
> 0 ||
3830 prog_data
->base
.ubo_ranges
[0].length
> 0)
3831 ps
.PushConstantEnable
= true;
3834 /* From the IVB PRM, volume 2 part 1, page 287:
3835 * "This bit is inserted in the PS payload header and made available to
3836 * the DataPort (either via the message header or via header bypass) to
3837 * indicate that oMask data (one or two phases) is included in Render
3838 * Target Write messages. If present, the oMask data is used to mask off
3841 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3843 /* The hardware wedges if you have this bit set but don't turn on any
3844 * dual source blend factors.
3846 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3848 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3849 (ctx
->Color
.BlendEnabled
& 1) &&
3850 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3852 /* BRW_NEW_FS_PROG_DATA */
3853 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3856 /* From the documentation for this packet:
3857 * "If the PS kernel does not need the Position XY Offsets to
3858 * compute a Position Value, then this field should be programmed
3859 * to POSOFFSET_NONE."
3861 * "SW Recommendation: If the PS kernel needs the Position Offsets
3862 * to compute a Position XY value, this field should match Position
3863 * ZW Interpolation Mode to ensure a consistent position.xyzw
3866 * We only require XY sample offsets. So, this recommendation doesn't
3867 * look useful at the moment. We might need this in future.
3869 if (prog_data
->uses_pos_offset
)
3870 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3872 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3874 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3875 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3876 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3877 prog_data
->base
.dispatch_grf_start_reg
;
3878 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3879 prog_data
->dispatch_grf_start_reg_2
;
3881 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3882 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3883 prog_data
->prog_offset_2
;
3885 if (prog_data
->base
.total_scratch
) {
3886 ps
.ScratchSpaceBasePointer
=
3887 rw_bo(stage_state
->scratch_bo
,
3888 ffs(stage_state
->per_thread_scratch
) - 11);
3893 static const struct brw_tracked_state
genX(ps_state
) = {
3895 .mesa
= _NEW_MULTISAMPLE
|
3896 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3899 .brw
= BRW_NEW_BATCH
|
3901 BRW_NEW_FS_PROG_DATA
,
3903 .emit
= genX(upload_ps
),
3907 /* ---------------------------------------------------------------------- */
3911 genX(upload_hs_state
)(struct brw_context
*brw
)
3913 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3914 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3915 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3916 const struct brw_vue_prog_data
*vue_prog_data
=
3917 brw_vue_prog_data(stage_prog_data
);
3919 /* BRW_NEW_TES_PROG_DATA */
3920 struct brw_tcs_prog_data
*tcs_prog_data
=
3921 brw_tcs_prog_data(stage_prog_data
);
3923 if (!tcs_prog_data
) {
3924 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3926 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3927 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3929 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3930 hs
.IncludeVertexHandles
= true;
3932 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3937 static const struct brw_tracked_state
genX(hs_state
) = {
3940 .brw
= BRW_NEW_BATCH
|
3942 BRW_NEW_TCS_PROG_DATA
|
3943 BRW_NEW_TESS_PROGRAMS
,
3945 .emit
= genX(upload_hs_state
),
3949 genX(upload_ds_state
)(struct brw_context
*brw
)
3951 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3952 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3953 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3955 /* BRW_NEW_TES_PROG_DATA */
3956 const struct brw_tes_prog_data
*tes_prog_data
=
3957 brw_tes_prog_data(stage_prog_data
);
3958 const struct brw_vue_prog_data
*vue_prog_data
=
3959 brw_vue_prog_data(stage_prog_data
);
3961 if (!tes_prog_data
) {
3962 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3964 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3965 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3967 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3968 ds
.ComputeWCoordinateEnable
=
3969 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3972 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3973 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3974 ds
.UserClipDistanceCullTestEnableBitmask
=
3975 vue_prog_data
->cull_distance_mask
;
3981 static const struct brw_tracked_state
genX(ds_state
) = {
3984 .brw
= BRW_NEW_BATCH
|
3986 BRW_NEW_TESS_PROGRAMS
|
3987 BRW_NEW_TES_PROG_DATA
,
3989 .emit
= genX(upload_ds_state
),
3992 /* ---------------------------------------------------------------------- */
3995 upload_te_state(struct brw_context
*brw
)
3997 /* BRW_NEW_TESS_PROGRAMS */
3998 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4000 /* BRW_NEW_TES_PROG_DATA */
4001 const struct brw_tes_prog_data
*tes_prog_data
=
4002 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4005 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4006 te
.Partitioning
= tes_prog_data
->partitioning
;
4007 te
.OutputTopology
= tes_prog_data
->output_topology
;
4008 te
.TEDomain
= tes_prog_data
->domain
;
4010 te
.MaximumTessellationFactorOdd
= 63.0;
4011 te
.MaximumTessellationFactorNotOdd
= 64.0;
4014 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4018 static const struct brw_tracked_state
genX(te_state
) = {
4021 .brw
= BRW_NEW_BLORP
|
4023 BRW_NEW_TES_PROG_DATA
|
4024 BRW_NEW_TESS_PROGRAMS
,
4026 .emit
= upload_te_state
,
4029 /* ---------------------------------------------------------------------- */
4032 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4034 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4035 /* BRW_NEW_TESS_PROGRAMS */
4036 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4038 /* BRW_NEW_TES_PROG_DATA */
4039 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4040 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4043 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4045 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4046 .brw
= BRW_NEW_BATCH
|
4048 BRW_NEW_TESS_PROGRAMS
|
4049 BRW_NEW_TES_PROG_DATA
,
4051 .emit
= genX(upload_tes_push_constants
),
4055 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4057 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4058 /* BRW_NEW_TESS_PROGRAMS */
4059 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4061 /* BRW_NEW_TCS_PROG_DATA */
4062 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4064 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4067 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4069 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4070 .brw
= BRW_NEW_BATCH
|
4072 BRW_NEW_DEFAULT_TESS_LEVELS
|
4073 BRW_NEW_TESS_PROGRAMS
|
4074 BRW_NEW_TCS_PROG_DATA
,
4076 .emit
= genX(upload_tcs_push_constants
),
4081 /* ---------------------------------------------------------------------- */
4085 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4087 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4089 /* BRW_NEW_COMPUTE_PROGRAM */
4090 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4093 /* BRW_NEW_CS_PROG_DATA */
4094 struct brw_cs_prog_data
*cs_prog_data
=
4095 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4097 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4098 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4102 const struct brw_tracked_state
genX(cs_push_constants
) = {
4104 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4105 .brw
= BRW_NEW_BATCH
|
4107 BRW_NEW_COMPUTE_PROGRAM
|
4108 BRW_NEW_CS_PROG_DATA
,
4110 .emit
= genX(upload_cs_push_constants
),
4114 * Creates a new CS constant buffer reflecting the current CS program's
4115 * constants, if needed by the CS program.
4118 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4120 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4122 /* BRW_NEW_COMPUTE_PROGRAM */
4123 struct brw_program
*cp
=
4124 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4126 /* BRW_NEW_CS_PROG_DATA */
4127 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4129 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4130 /* _NEW_PROGRAM_CONSTANTS */
4131 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4132 stage_state
, prog_data
);
4135 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4137 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4138 .brw
= BRW_NEW_BATCH
|
4140 BRW_NEW_COMPUTE_PROGRAM
|
4141 BRW_NEW_CS_PROG_DATA
,
4143 .emit
= genX(upload_cs_pull_constants
),
4147 genX(upload_cs_state
)(struct brw_context
*brw
)
4149 if (!brw
->cs
.base
.prog_data
)
4153 uint32_t *desc
= (uint32_t*) brw_state_batch(
4154 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4157 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4158 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4159 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4160 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4162 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4163 brw_emit_buffer_surface_state(
4164 brw
, &stage_state
->surf_offset
[
4165 prog_data
->binding_table
.shader_time_start
],
4166 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4167 brw
->shader_time
.bo
->size
, 1,
4171 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4172 32, &stage_state
->bind_bo_offset
);
4174 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4175 if (prog_data
->total_scratch
) {
4179 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4180 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4182 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 11;
4183 } else if (GEN_IS_HASWELL
) {
4184 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4185 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4187 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 12;
4189 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4190 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4192 bo_offset
= stage_state
->per_thread_scratch
/ 1024 - 1;
4194 vfe
.ScratchSpaceBasePointer
=
4195 rw_bo(stage_state
->scratch_bo
, bo_offset
);
4198 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4199 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4200 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4201 vfe
.ResetGatewayTimer
=
4202 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4204 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4210 /* We are uploading duplicated copies of push constant uniforms for each
4211 * thread. Although the local id data needs to vary per thread, it won't
4212 * change for other uniform data. Unfortunately this duplication is
4213 * required for gen7. As of Haswell, this duplication can be avoided,
4214 * but this older mechanism with duplicated data continues to work.
4216 * FINISHME: As of Haswell, we could make use of the
4217 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4218 * field to only store one copy of uniform data.
4220 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4221 * which is described in the GPGPU_WALKER command and in the Broadwell
4222 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4223 * Operations => GPGPU Mode => Indirect Payload Storage.
4225 * Note: The constant data is built in brw_upload_cs_push_constants
4228 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4230 const uint32_t vfe_curbe_allocation
=
4231 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4232 cs_prog_data
->push
.cross_thread
.regs
, 2);
4233 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4236 if (cs_prog_data
->push
.total
.size
> 0) {
4237 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4238 curbe
.CURBETotalDataLength
=
4239 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4240 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4244 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4245 memcpy(bind
, stage_state
->surf_offset
,
4246 prog_data
->binding_table
.size_bytes
);
4247 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4248 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4249 .SamplerStatePointer
= stage_state
->sampler_offset
,
4250 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4251 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4252 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4253 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4254 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4255 prog_data
->total_shared
),
4256 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4257 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4258 .CrossThreadConstantDataReadLength
=
4259 cs_prog_data
->push
.cross_thread
.regs
,
4263 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4265 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4266 load
.InterfaceDescriptorTotalLength
=
4267 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4268 load
.InterfaceDescriptorDataStartAddress
= offset
;
4272 static const struct brw_tracked_state
genX(cs_state
) = {
4274 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4275 .brw
= BRW_NEW_BATCH
|
4277 BRW_NEW_CS_PROG_DATA
|
4278 BRW_NEW_SAMPLER_STATE_TABLE
|
4281 .emit
= genX(upload_cs_state
)
4286 /* ---------------------------------------------------------------------- */
4290 genX(upload_raster
)(struct brw_context
*brw
)
4292 struct gl_context
*ctx
= &brw
->ctx
;
4295 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4298 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4301 struct gl_point_attrib
*point
= &ctx
->Point
;
4303 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4304 if (brw
->polygon_front_bit
== render_to_fbo
)
4305 raster
.FrontWinding
= CounterClockwise
;
4307 if (polygon
->CullFlag
) {
4308 switch (polygon
->CullFaceMode
) {
4310 raster
.CullMode
= CULLMODE_FRONT
;
4313 raster
.CullMode
= CULLMODE_BACK
;
4315 case GL_FRONT_AND_BACK
:
4316 raster
.CullMode
= CULLMODE_BOTH
;
4319 unreachable("not reached");
4322 raster
.CullMode
= CULLMODE_NONE
;
4325 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4327 raster
.DXMultisampleRasterizationEnable
=
4328 _mesa_is_multisample_enabled(ctx
);
4330 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4331 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4332 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4334 switch (polygon
->FrontMode
) {
4336 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4339 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4342 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4345 unreachable("not reached");
4348 switch (polygon
->BackMode
) {
4350 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4353 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4356 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4359 unreachable("not reached");
4363 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4367 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4369 const bool multisampled_fbo
=
4370 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4371 if (multisampled_fbo
)
4372 raster
.AntialiasingEnable
= false;
4376 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4378 /* _NEW_TRANSFORM */
4379 if (!ctx
->Transform
.DepthClamp
) {
4381 raster
.ViewportZFarClipTestEnable
= true;
4382 raster
.ViewportZNearClipTestEnable
= true;
4384 raster
.ViewportZClipTestEnable
= true;
4388 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4390 raster
.ConservativeRasterizationEnable
=
4391 ctx
->IntelConservativeRasterization
;
4394 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4395 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4397 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4401 static const struct brw_tracked_state
genX(raster_state
) = {
4403 .mesa
= _NEW_BUFFERS
|
4410 .brw
= BRW_NEW_BLORP
|
4412 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4414 .emit
= genX(upload_raster
),
4418 /* ---------------------------------------------------------------------- */
4422 genX(upload_ps_extra
)(struct brw_context
*brw
)
4424 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4426 const struct brw_wm_prog_data
*prog_data
=
4427 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4429 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4430 psx
.PixelShaderValid
= true;
4431 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4432 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4433 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4434 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4435 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4436 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4438 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4439 if (prog_data
->uses_sample_mask
) {
4441 if (prog_data
->post_depth_coverage
)
4442 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4443 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4444 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4446 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4448 psx
.PixelShaderUsesInputCoverageMask
= true;
4452 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4454 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4455 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4458 /* The stricter cross-primitive coherency guarantees that the hardware
4459 * gives us with the "Accesses UAV" bit set for at least one shader stage
4460 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4461 * are redundant within the current image, atomic counter and SSBO GL
4462 * APIs, which all have very loose ordering and coherency requirements
4463 * and generally rely on the application to insert explicit barriers when
4464 * a shader invocation is expected to see the memory writes performed by
4465 * the invocations of some previous primitive. Regardless of the value
4466 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4467 * cause an in most cases useless DC flush when the lowermost stage with
4468 * the bit set finishes execution.
4470 * It would be nice to disable it, but in some cases we can't because on
4471 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4472 * signal (which could be set independently from the coherency mechanism
4473 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4474 * determine whether the hardware skips execution of the fragment shader
4475 * or not via the ThreadDispatchEnable signal. However if we know that
4476 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4477 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4478 * difference so we may just disable it here.
4480 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4481 * take into account KillPixels when no depth or stencil writes are
4482 * enabled. In order for occlusion queries to work correctly with no
4483 * attachments, we need to force-enable here.
4485 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4488 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4489 !brw_color_buffer_write_enabled(brw
))
4490 psx
.PixelShaderHasUAV
= true;
4494 const struct brw_tracked_state
genX(ps_extra
) = {
4496 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4497 .brw
= BRW_NEW_BLORP
|
4499 BRW_NEW_FRAGMENT_PROGRAM
|
4500 BRW_NEW_FS_PROG_DATA
|
4501 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4503 .emit
= genX(upload_ps_extra
),
4507 /* ---------------------------------------------------------------------- */
4511 genX(upload_ps_blend
)(struct brw_context
*brw
)
4513 struct gl_context
*ctx
= &brw
->ctx
;
4516 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4517 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4520 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4522 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4523 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4524 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4526 bool alpha_to_one
= false;
4528 if (!buffer0_is_integer
) {
4529 /* _NEW_MULTISAMPLE */
4531 if (_mesa_is_multisample_enabled(ctx
)) {
4532 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4533 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4536 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4539 /* Used for implementing the following bit of GL_EXT_texture_integer:
4540 * "Per-fragment operations that require floating-point color
4541 * components, including multisample alpha operations, alpha test,
4542 * blending, and dithering, have no effect when the corresponding
4543 * colors are written to an integer color buffer."
4545 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4546 * "If drawbuffer zero is not NONE and the buffer it references has an
4547 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4548 * operations are skipped."
4550 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4551 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4552 GLenum eqA
= color
->Blend
[0].EquationA
;
4553 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4554 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4555 GLenum srcA
= color
->Blend
[0].SrcA
;
4556 GLenum dstA
= color
->Blend
[0].DstA
;
4558 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4559 srcRGB
= dstRGB
= GL_ONE
;
4561 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4562 srcA
= dstA
= GL_ONE
;
4564 /* Due to hardware limitations, the destination may have information
4565 * in an alpha channel even when the format specifies no alpha
4566 * channel. In order to avoid getting any incorrect blending due to
4567 * that alpha channel, coerce the blend factors to values that will
4568 * not read the alpha channel, but will instead use the correct
4569 * implicit value for alpha.
4571 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4572 GL_TEXTURE_ALPHA_TYPE
)) {
4573 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4574 srcA
= brw_fix_xRGB_alpha(srcA
);
4575 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4576 dstA
= brw_fix_xRGB_alpha(dstA
);
4579 /* Alpha to One doesn't work with Dual Color Blending. Override
4580 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4582 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4583 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4584 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4585 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4586 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4589 pb
.ColorBufferBlendEnable
= true;
4590 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4591 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4592 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4593 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4595 pb
.IndependentAlphaBlendEnable
=
4596 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4601 static const struct brw_tracked_state
genX(ps_blend
) = {
4603 .mesa
= _NEW_BUFFERS
|
4606 .brw
= BRW_NEW_BLORP
|
4608 BRW_NEW_FRAGMENT_PROGRAM
,
4610 .emit
= genX(upload_ps_blend
)
4614 /* ---------------------------------------------------------------------- */
4618 genX(emit_vf_topology
)(struct brw_context
*brw
)
4620 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4621 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4625 static const struct brw_tracked_state
genX(vf_topology
) = {
4628 .brw
= BRW_NEW_BLORP
|
4631 .emit
= genX(emit_vf_topology
),
4635 /* ---------------------------------------------------------------------- */
4639 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4641 uint32_t offset_in_bytes
,
4644 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4645 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4646 mi_rpc
.ReportID
= report_id
;
4651 /* ---------------------------------------------------------------------- */
4654 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4657 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4658 struct brw_stage_state
*stage_state
)
4661 static const uint16_t packet_headers
[] = {
4662 [MESA_SHADER_VERTEX
] = 43,
4663 [MESA_SHADER_TESS_CTRL
] = 44,
4664 [MESA_SHADER_TESS_EVAL
] = 45,
4665 [MESA_SHADER_GEOMETRY
] = 46,
4666 [MESA_SHADER_FRAGMENT
] = 47,
4669 /* Ivybridge requires a workaround flush before VS packets. */
4670 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4671 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4672 gen7_emit_vs_workaround_flush(brw
);
4675 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4676 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4677 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4683 has_component(mesa_format format
, int i
)
4685 if (_mesa_is_format_color_format(format
))
4686 return _mesa_format_has_color_component(format
, i
);
4688 /* depth and stencil have only one component */
4693 * Upload SAMPLER_BORDER_COLOR_STATE.
4696 genX(upload_default_color
)(struct brw_context
*brw
,
4697 const struct gl_sampler_object
*sampler
,
4698 mesa_format format
, GLenum base_format
,
4699 bool is_integer_format
, bool is_stencil_sampling
,
4700 uint32_t *sdc_offset
)
4702 union gl_color_union color
;
4704 switch (base_format
) {
4705 case GL_DEPTH_COMPONENT
:
4706 /* GL specs that border color for depth textures is taken from the
4707 * R channel, while the hardware uses A. Spam R into all the
4708 * channels for safety.
4710 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4711 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4712 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4713 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4719 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4722 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4723 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4724 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4725 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4728 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4729 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4730 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4731 color
.ui
[3] = float_as_int(1.0);
4733 case GL_LUMINANCE_ALPHA
:
4734 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4735 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4736 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4737 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4740 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4741 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4742 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4743 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4747 /* In some cases we use an RGBA surface format for GL RGB textures,
4748 * where we've initialized the A channel to 1.0. We also have to set
4749 * the border color alpha to 1.0 in that case.
4751 if (base_format
== GL_RGB
)
4752 color
.ui
[3] = float_as_int(1.0);
4757 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4761 uint32_t *sdc
= brw_state_batch(
4762 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4763 alignment
, sdc_offset
);
4765 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4767 #define ASSIGN(dst, src) \
4772 #define ASSIGNu16(dst, src) \
4774 dst = (uint16_t)src; \
4777 #define ASSIGNu8(dst, src) \
4779 dst = (uint8_t)src; \
4782 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4783 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4784 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4785 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4786 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4789 /* On Broadwell, the border color is represented as four 32-bit floats,
4790 * integers, or unsigned values, interpreted according to the surface
4791 * format. This matches the sampler->BorderColor union exactly; just
4792 * memcpy the values.
4794 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4795 #elif GEN_IS_HASWELL
4796 if (is_integer_format
|| is_stencil_sampling
) {
4797 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4798 const int bits_per_channel
=
4799 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4801 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4802 * "If any color channel is missing from the surface format,
4803 * corresponding border color should be programmed as zero and if
4804 * alpha channel is missing, corresponding Alpha border color should
4805 * be programmed as 1."
4807 unsigned c
[4] = { 0, 0, 0, 1 };
4808 for (int i
= 0; i
< 4; i
++) {
4809 if (has_component(format
, i
))
4813 switch (bits_per_channel
) {
4815 /* Copy RGBA in order. */
4816 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4819 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4821 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4824 if (base_format
== GL_RG
) {
4825 /* Careful inspection of the tables reveals that for RG32 formats,
4826 * the green channel needs to go where blue normally belongs.
4828 state
.BorderColor32bitRed
= c
[0];
4829 state
.BorderColor32bitBlue
= c
[1];
4830 state
.BorderColor32bitAlpha
= 1;
4832 /* Copy RGBA in order. */
4833 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4837 assert(!"Invalid number of bits per channel in integer format.");
4841 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4843 #elif GEN_GEN == 5 || GEN_GEN == 6
4844 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4845 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4846 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4848 #define MESA_FLOAT_TO_HALF(dst, src) \
4849 dst = _mesa_float_to_half(src);
4851 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4853 #undef MESA_FLOAT_TO_HALF
4855 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4856 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4857 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4858 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4860 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4862 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4864 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4868 #undef BORDER_COLOR_ATTR
4870 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4874 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4881 /* GL_CLAMP is the weird mode where coordinates are clamped to
4882 * [0.0, 1.0], so linear filtering of coordinates outside of
4883 * [0.0, 1.0] give you half edge texel value and half border
4886 * Gen8+ supports this natively.
4888 return TCM_HALF_BORDER
;
4890 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4891 * and set clamp_border here, which gets the result desired.
4892 * We just use clamp(_to_edge) for nearest, because for nearest
4893 * clamping to 1.0 gives border color instead of the desired
4899 return TCM_CLAMP_BORDER
;
4901 case GL_CLAMP_TO_EDGE
:
4903 case GL_CLAMP_TO_BORDER
:
4904 return TCM_CLAMP_BORDER
;
4905 case GL_MIRRORED_REPEAT
:
4907 case GL_MIRROR_CLAMP_TO_EDGE
:
4908 return TCM_MIRROR_ONCE
;
4915 * Return true if the given wrap mode requires the border color to exist.
4918 wrap_mode_needs_border_color(unsigned wrap_mode
)
4921 return wrap_mode
== TCM_CLAMP_BORDER
||
4922 wrap_mode
== TCM_HALF_BORDER
;
4924 return wrap_mode
== TCM_CLAMP_BORDER
;
4929 * Sets the sampler state for a single unit based off of the sampler key
4933 genX(update_sampler_state
)(struct brw_context
*brw
,
4934 GLenum target
, bool tex_cube_map_seamless
,
4935 GLfloat tex_unit_lod_bias
,
4936 mesa_format format
, GLenum base_format
,
4937 const struct gl_texture_object
*texObj
,
4938 const struct gl_sampler_object
*sampler
,
4939 uint32_t *sampler_state
,
4940 uint32_t batch_offset_for_sampler_state
)
4942 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
4944 /* Select min and mip filters. */
4945 switch (sampler
->MinFilter
) {
4947 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4948 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4951 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4952 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
4954 case GL_NEAREST_MIPMAP_NEAREST
:
4955 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4956 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4958 case GL_LINEAR_MIPMAP_NEAREST
:
4959 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4960 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
4962 case GL_NEAREST_MIPMAP_LINEAR
:
4963 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
4964 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4966 case GL_LINEAR_MIPMAP_LINEAR
:
4967 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
4968 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
4971 unreachable("not reached");
4974 /* Select mag filter. */
4975 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
4976 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
4978 /* Enable anisotropic filtering if desired. */
4979 samp_st
.MaximumAnisotropy
= RATIO21
;
4981 if (sampler
->MaxAnisotropy
> 1.0f
) {
4982 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
4983 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
4984 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
4985 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
4987 if (sampler
->MaxAnisotropy
> 2.0f
) {
4988 samp_st
.MaximumAnisotropy
=
4989 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
4993 /* Set address rounding bits if not using nearest filtering. */
4994 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
4995 samp_st
.UAddressMinFilterRoundingEnable
= true;
4996 samp_st
.VAddressMinFilterRoundingEnable
= true;
4997 samp_st
.RAddressMinFilterRoundingEnable
= true;
5000 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5001 samp_st
.UAddressMagFilterRoundingEnable
= true;
5002 samp_st
.VAddressMagFilterRoundingEnable
= true;
5003 samp_st
.RAddressMagFilterRoundingEnable
= true;
5006 bool either_nearest
=
5007 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5008 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
5009 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
5010 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
5012 if (target
== GL_TEXTURE_CUBE_MAP
||
5013 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5014 /* Cube maps must use the same wrap mode for all three coordinate
5015 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5017 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5018 * integer formats. Fall back to CLAMP for now.
5020 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5021 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5030 } else if (target
== GL_TEXTURE_1D
) {
5031 /* There's a bug in 1D texture sampling - it actually pays
5032 * attention to the wrap_t value, though it should not.
5033 * Override the wrap_t value here to GL_REPEAT to keep
5034 * any nonexistent border pixels from floating in.
5039 samp_st
.TCXAddressControlMode
= wrap_s
;
5040 samp_st
.TCYAddressControlMode
= wrap_t
;
5041 samp_st
.TCZAddressControlMode
= wrap_r
;
5043 samp_st
.ShadowFunction
=
5044 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5045 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5048 /* Set shadow function. */
5049 samp_st
.AnisotropicAlgorithm
=
5050 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5051 EWAApproximation
: LEGACY
;
5055 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5058 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5059 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5060 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5061 samp_st
.TextureLODBias
=
5062 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5065 samp_st
.BaseMipLevel
=
5066 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5067 samp_st
.MinandMagStateNotEqual
=
5068 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5071 /* Upload the border color if necessary. If not, just point it at
5072 * offset 0 (the start of the batch) - the color should be ignored,
5073 * but that address won't fault in case something reads it anyway.
5075 uint32_t border_color_offset
= 0;
5076 if (wrap_mode_needs_border_color(wrap_s
) ||
5077 wrap_mode_needs_border_color(wrap_t
) ||
5078 wrap_mode_needs_border_color(wrap_r
)) {
5079 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5080 texObj
->_IsIntegerFormat
,
5081 texObj
->StencilSampling
,
5082 &border_color_offset
);
5085 samp_st
.BorderColorPointer
=
5086 ro_bo(brw
->batch
.state_bo
, border_color_offset
);
5088 samp_st
.BorderColorPointer
= border_color_offset
;
5092 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5094 samp_st
.LODPreClampEnable
= true;
5097 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5101 update_sampler_state(struct brw_context
*brw
,
5103 uint32_t *sampler_state
,
5104 uint32_t batch_offset_for_sampler_state
)
5106 struct gl_context
*ctx
= &brw
->ctx
;
5107 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5108 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5109 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5111 /* These don't use samplers at all. */
5112 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5115 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5116 genX(update_sampler_state
)(brw
, texObj
->Target
,
5117 ctx
->Texture
.CubeMapSeamless
,
5119 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5121 sampler_state
, batch_offset_for_sampler_state
);
5125 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5126 struct gl_program
*prog
,
5127 struct brw_stage_state
*stage_state
)
5129 struct gl_context
*ctx
= &brw
->ctx
;
5130 uint32_t sampler_count
= stage_state
->sampler_count
;
5132 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5134 if (sampler_count
== 0)
5137 /* SAMPLER_STATE is 4 DWords on all platforms. */
5138 const int dwords
= GENX(SAMPLER_STATE_length
);
5139 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5141 uint32_t *sampler_state
= brw_state_batch(brw
,
5142 sampler_count
* size_in_bytes
,
5143 32, &stage_state
->sampler_offset
);
5144 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5146 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
5148 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5149 if (SamplersUsed
& (1 << s
)) {
5150 const unsigned unit
= prog
->SamplerUnits
[s
];
5151 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5152 update_sampler_state(brw
, unit
, sampler_state
,
5153 batch_offset_for_sampler_state
);
5157 sampler_state
+= dwords
;
5158 batch_offset_for_sampler_state
+= size_in_bytes
;
5161 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5162 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5163 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5165 /* Flag that the sampler state table pointer has changed; later atoms
5168 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5173 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5175 /* BRW_NEW_FRAGMENT_PROGRAM */
5176 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5177 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5180 static const struct brw_tracked_state
genX(fs_samplers
) = {
5182 .mesa
= _NEW_TEXTURE
,
5183 .brw
= BRW_NEW_BATCH
|
5185 BRW_NEW_FRAGMENT_PROGRAM
,
5187 .emit
= genX(upload_fs_samplers
),
5191 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5193 /* BRW_NEW_VERTEX_PROGRAM */
5194 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5195 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5198 static const struct brw_tracked_state
genX(vs_samplers
) = {
5200 .mesa
= _NEW_TEXTURE
,
5201 .brw
= BRW_NEW_BATCH
|
5203 BRW_NEW_VERTEX_PROGRAM
,
5205 .emit
= genX(upload_vs_samplers
),
5210 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5212 /* BRW_NEW_GEOMETRY_PROGRAM */
5213 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5217 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5221 static const struct brw_tracked_state
genX(gs_samplers
) = {
5223 .mesa
= _NEW_TEXTURE
,
5224 .brw
= BRW_NEW_BATCH
|
5226 BRW_NEW_GEOMETRY_PROGRAM
,
5228 .emit
= genX(upload_gs_samplers
),
5234 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5236 /* BRW_NEW_TESS_PROGRAMS */
5237 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5241 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5244 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5246 .mesa
= _NEW_TEXTURE
,
5247 .brw
= BRW_NEW_BATCH
|
5249 BRW_NEW_TESS_PROGRAMS
,
5251 .emit
= genX(upload_tcs_samplers
),
5257 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5259 /* BRW_NEW_TESS_PROGRAMS */
5260 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5264 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5267 static const struct brw_tracked_state
genX(tes_samplers
) = {
5269 .mesa
= _NEW_TEXTURE
,
5270 .brw
= BRW_NEW_BATCH
|
5272 BRW_NEW_TESS_PROGRAMS
,
5274 .emit
= genX(upload_tes_samplers
),
5280 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5282 /* BRW_NEW_COMPUTE_PROGRAM */
5283 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5287 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5290 const struct brw_tracked_state
genX(cs_samplers
) = {
5292 .mesa
= _NEW_TEXTURE
,
5293 .brw
= BRW_NEW_BATCH
|
5295 BRW_NEW_COMPUTE_PROGRAM
,
5297 .emit
= genX(upload_cs_samplers
),
5301 /* ---------------------------------------------------------------------- */
5305 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5307 struct gl_context
*ctx
= &brw
->ctx
;
5309 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5310 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5311 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5312 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5313 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5317 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5320 .brw
= BRW_NEW_CONTEXT
|
5323 .emit
= genX(upload_blend_constant_color
)
5327 /* ---------------------------------------------------------------------- */
5330 genX(init_atoms
)(struct brw_context
*brw
)
5333 static const struct brw_tracked_state
*render_atoms
[] =
5335 /* Once all the programs are done, we know how large urb entry
5336 * sizes need to be and can decide if we need to change the urb
5340 &brw_recalculate_urb_fence
,
5343 &genX(color_calc_state
),
5345 /* Surface state setup. Must come before the VS/WM unit. The binding
5346 * table upload must be last.
5348 &brw_vs_pull_constants
,
5349 &brw_wm_pull_constants
,
5350 &brw_renderbuffer_surfaces
,
5351 &brw_renderbuffer_read_surfaces
,
5352 &brw_texture_surfaces
,
5353 &brw_vs_binding_table
,
5354 &brw_wm_binding_table
,
5359 /* These set up state for brw_psp_urb_cbs */
5361 &genX(sf_clip_viewport
),
5363 &genX(vs_state
), /* always required, enabled or not */
5369 &brw_binding_table_pointers
,
5370 &genX(blend_constant_color
),
5374 &genX(polygon_stipple
),
5375 &genX(polygon_stipple_offset
),
5377 &genX(line_stipple
),
5381 &genX(drawing_rect
),
5382 &brw_indices
, /* must come before brw_vertices */
5383 &genX(index_buffer
),
5386 &brw_constant_buffer
5389 static const struct brw_tracked_state
*render_atoms
[] =
5391 &genX(sf_clip_viewport
),
5393 /* Command packets: */
5398 &genX(blend_state
), /* must do before cc unit */
5399 &genX(color_calc_state
), /* must do before cc unit */
5400 &genX(depth_stencil_state
), /* must do before cc unit */
5402 &genX(vs_push_constants
), /* Before vs_state */
5403 &genX(gs_push_constants
), /* Before gs_state */
5404 &genX(wm_push_constants
), /* Before wm_state */
5406 /* Surface state setup. Must come before the VS/WM unit. The binding
5407 * table upload must be last.
5409 &brw_vs_pull_constants
,
5410 &brw_vs_ubo_surfaces
,
5411 &brw_gs_pull_constants
,
5412 &brw_gs_ubo_surfaces
,
5413 &brw_wm_pull_constants
,
5414 &brw_wm_ubo_surfaces
,
5415 &gen6_renderbuffer_surfaces
,
5416 &brw_renderbuffer_read_surfaces
,
5417 &brw_texture_surfaces
,
5419 &brw_vs_binding_table
,
5420 &gen6_gs_binding_table
,
5421 &brw_wm_binding_table
,
5426 &gen6_sampler_state
,
5427 &genX(multisample_state
),
5435 &genX(scissor_state
),
5437 &gen6_binding_table_pointers
,
5441 &genX(polygon_stipple
),
5442 &genX(polygon_stipple_offset
),
5444 &genX(line_stipple
),
5446 &genX(drawing_rect
),
5448 &brw_indices
, /* must come before brw_vertices */
5449 &genX(index_buffer
),
5453 static const struct brw_tracked_state
*render_atoms
[] =
5455 /* Command packets: */
5458 &genX(sf_clip_viewport
),
5461 &gen7_push_constant_space
,
5463 &genX(blend_state
), /* must do before cc unit */
5464 &genX(color_calc_state
), /* must do before cc unit */
5465 &genX(depth_stencil_state
), /* must do before cc unit */
5467 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5468 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5469 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5470 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5471 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5473 &genX(vs_push_constants
), /* Before vs_state */
5474 &genX(tcs_push_constants
),
5475 &genX(tes_push_constants
),
5476 &genX(gs_push_constants
), /* Before gs_state */
5477 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5479 /* Surface state setup. Must come before the VS/WM unit. The binding
5480 * table upload must be last.
5482 &brw_vs_pull_constants
,
5483 &brw_vs_ubo_surfaces
,
5484 &brw_tcs_pull_constants
,
5485 &brw_tcs_ubo_surfaces
,
5486 &brw_tes_pull_constants
,
5487 &brw_tes_ubo_surfaces
,
5488 &brw_gs_pull_constants
,
5489 &brw_gs_ubo_surfaces
,
5490 &brw_wm_pull_constants
,
5491 &brw_wm_ubo_surfaces
,
5492 &gen6_renderbuffer_surfaces
,
5493 &brw_renderbuffer_read_surfaces
,
5494 &brw_texture_surfaces
,
5496 &genX(push_constant_packets
),
5498 &brw_vs_binding_table
,
5499 &brw_tcs_binding_table
,
5500 &brw_tes_binding_table
,
5501 &brw_gs_binding_table
,
5502 &brw_wm_binding_table
,
5506 &genX(tcs_samplers
),
5507 &genX(tes_samplers
),
5509 &genX(multisample_state
),
5523 &genX(scissor_state
),
5527 &genX(polygon_stipple
),
5528 &genX(polygon_stipple_offset
),
5530 &genX(line_stipple
),
5532 &genX(drawing_rect
),
5534 &brw_indices
, /* must come before brw_vertices */
5535 &genX(index_buffer
),
5543 static const struct brw_tracked_state
*render_atoms
[] =
5546 &genX(sf_clip_viewport
),
5549 &gen7_push_constant_space
,
5552 &genX(color_calc_state
),
5554 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5555 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5556 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5557 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5558 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5560 &genX(vs_push_constants
), /* Before vs_state */
5561 &genX(tcs_push_constants
),
5562 &genX(tes_push_constants
),
5563 &genX(gs_push_constants
), /* Before gs_state */
5564 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5566 /* Surface state setup. Must come before the VS/WM unit. The binding
5567 * table upload must be last.
5569 &brw_vs_pull_constants
,
5570 &brw_vs_ubo_surfaces
,
5571 &brw_tcs_pull_constants
,
5572 &brw_tcs_ubo_surfaces
,
5573 &brw_tes_pull_constants
,
5574 &brw_tes_ubo_surfaces
,
5575 &brw_gs_pull_constants
,
5576 &brw_gs_ubo_surfaces
,
5577 &brw_wm_pull_constants
,
5578 &brw_wm_ubo_surfaces
,
5579 &gen6_renderbuffer_surfaces
,
5580 &brw_renderbuffer_read_surfaces
,
5581 &brw_texture_surfaces
,
5583 &genX(push_constant_packets
),
5585 &brw_vs_binding_table
,
5586 &brw_tcs_binding_table
,
5587 &brw_tes_binding_table
,
5588 &brw_gs_binding_table
,
5589 &brw_wm_binding_table
,
5593 &genX(tcs_samplers
),
5594 &genX(tes_samplers
),
5596 &genX(multisample_state
),
5605 &genX(raster_state
),
5611 &genX(depth_stencil_state
),
5614 &genX(scissor_state
),
5618 &genX(polygon_stipple
),
5619 &genX(polygon_stipple_offset
),
5621 &genX(line_stipple
),
5623 &genX(drawing_rect
),
5628 &genX(index_buffer
),
5636 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5637 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5638 render_atoms
, ARRAY_SIZE(render_atoms
));
5641 static const struct brw_tracked_state
*compute_atoms
[] =
5644 &brw_cs_image_surfaces
,
5645 &genX(cs_push_constants
),
5646 &genX(cs_pull_constants
),
5647 &brw_cs_ubo_surfaces
,
5648 &brw_cs_texture_surfaces
,
5649 &brw_cs_work_groups_surface
,
5654 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5655 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5656 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5658 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);