2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
35 #include "brw_context.h"
37 #include "brw_defines.h"
40 #include "brw_multisample_state.h"
41 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
46 #include "intel_buffer_objects.h"
47 #include "intel_fbo.h"
49 #include "main/enums.h"
50 #include "main/fbobject.h"
51 #include "main/framebuffer.h"
52 #include "main/glformats.h"
53 #include "main/shaderapi.h"
54 #include "main/stencil.h"
55 #include "main/transformfeedback.h"
56 #include "main/varray.h"
57 #include "main/viewport.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
71 uint32_t read_domains
;
72 uint32_t write_domain
;
77 emit_reloc(struct brw_context
*brw
,
78 void *location
, struct brw_address address
, uint32_t delta
)
80 uint32_t offset
= (char *) location
- (char *) brw
->batch
.map
;
82 return brw_emit_reloc(&brw
->batch
, offset
, address
.bo
,
83 address
.offset
+ delta
,
85 address
.write_domain
);
88 #define __gen_address_type struct brw_address
89 #define __gen_user_data struct brw_context
92 __gen_combine_address(struct brw_context
*brw
, void *location
,
93 struct brw_address address
, uint32_t delta
)
95 if (address
.bo
== NULL
) {
96 return address
.offset
+ delta
;
98 return emit_reloc(brw
, location
, address
, delta
);
102 static inline struct brw_address
103 render_bo(struct brw_bo
*bo
, uint32_t offset
)
105 return (struct brw_address
) {
108 .read_domains
= I915_GEM_DOMAIN_RENDER
,
109 .write_domain
= I915_GEM_DOMAIN_RENDER
,
113 static inline struct brw_address
114 render_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
116 return (struct brw_address
) {
119 .read_domains
= I915_GEM_DOMAIN_RENDER
,
124 static inline struct brw_address
125 instruction_bo(struct brw_bo
*bo
, uint32_t offset
)
127 return (struct brw_address
) {
130 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
131 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
135 static inline struct brw_address
136 vertex_bo(struct brw_bo
*bo
, uint32_t offset
)
138 return (struct brw_address
) {
141 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
146 #include "genxml/genX_pack.h"
148 #define _brw_cmd_length(cmd) cmd ## _length
149 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
150 #define _brw_cmd_header(cmd) cmd ## _header
151 #define _brw_cmd_pack(cmd) cmd ## _pack
153 #define brw_batch_emit(brw, cmd, name) \
154 for (struct cmd name = { _brw_cmd_header(cmd) }, \
155 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
156 __builtin_expect(_dst != NULL, 1); \
157 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
160 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
161 uint32_t *_dw = emit_dwords(brw, n); \
162 struct cmd template = { \
163 _brw_cmd_header(cmd), \
164 .DWordLength = n - _brw_cmd_length_bias(cmd), \
167 _brw_cmd_pack(cmd)(brw, _dw, &template); \
168 _dw + 1; /* Array starts at dw[1] */ \
171 #define brw_state_emit(brw, cmd, align, offset, name) \
172 for (struct cmd name = { 0, }, \
173 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
175 __builtin_expect(_dst != NULL, 1); \
176 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
180 * Polygon stipple packet
183 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
185 struct gl_context
*ctx
= &brw
->ctx
;
188 if (!ctx
->Polygon
.StippleFlag
)
191 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
192 /* Polygon stipple is provided in OpenGL order, i.e. bottom
193 * row first. If we're rendering to a window (i.e. the
194 * default frame buffer object, 0), then we need to invert
195 * it to match our pixel layout. But if we're rendering
196 * to a FBO (i.e. any named frame buffer object), we *don't*
197 * need to invert - we already match the layout.
199 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
200 for (unsigned i
= 0; i
< 32; i
++)
201 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
203 for (unsigned i
= 0; i
< 32; i
++)
204 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
209 static const struct brw_tracked_state
genX(polygon_stipple
) = {
211 .mesa
= _NEW_POLYGON
|
213 .brw
= BRW_NEW_CONTEXT
,
215 .emit
= genX(upload_polygon_stipple
),
219 * Polygon stipple offset packet
222 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
224 struct gl_context
*ctx
= &brw
->ctx
;
227 if (!ctx
->Polygon
.StippleFlag
)
230 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
233 * If we're drawing to a system window we have to invert the Y axis
234 * in order to match the OpenGL pixel coordinate system, and our
235 * offset must be matched to the window position. If we're drawing
236 * to a user-created FBO then our native pixel coordinate system
237 * works just fine, and there's no window system to worry about.
239 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
240 poly
.PolygonStippleYOffset
=
241 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
246 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
248 .mesa
= _NEW_BUFFERS
|
250 .brw
= BRW_NEW_CONTEXT
,
252 .emit
= genX(upload_polygon_stipple_offset
),
256 * Line stipple packet
259 genX(upload_line_stipple
)(struct brw_context
*brw
)
261 struct gl_context
*ctx
= &brw
->ctx
;
263 if (!ctx
->Line
.StippleFlag
)
266 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
267 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
269 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
270 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
274 static const struct brw_tracked_state
genX(line_stipple
) = {
277 .brw
= BRW_NEW_CONTEXT
,
279 .emit
= genX(upload_line_stipple
),
282 /* Constant single cliprect for framebuffer object or DRI2 drawing */
284 genX(upload_drawing_rect
)(struct brw_context
*brw
)
286 struct gl_context
*ctx
= &brw
->ctx
;
287 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
288 const unsigned int fb_width
= _mesa_geometric_width(fb
);
289 const unsigned int fb_height
= _mesa_geometric_height(fb
);
291 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
292 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
293 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
297 static const struct brw_tracked_state
genX(drawing_rect
) = {
299 .mesa
= _NEW_BUFFERS
,
300 .brw
= BRW_NEW_BLORP
|
303 .emit
= genX(upload_drawing_rect
),
307 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
311 unsigned start_offset
,
316 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
317 .VertexBufferIndex
= buffer_nr
,
318 .BufferPitch
= stride
,
319 .BufferStartingAddress
= vertex_bo(bo
, start_offset
),
321 .BufferSize
= end_offset
- start_offset
,
325 .AddressModifyEnable
= true,
329 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
330 .InstanceDataStepRate
= step_rate
,
332 .EndAddress
= vertex_bo(bo
, end_offset
- 1),
337 .VertexBufferMOCS
= SKL_MOCS_WB
,
339 .VertexBufferMOCS
= BDW_MOCS_WB
,
341 .VertexBufferMOCS
= GEN7_MOCS_L3
,
345 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
346 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
350 is_passthru_format(uint32_t format
)
353 case ISL_FORMAT_R64_PASSTHRU
:
354 case ISL_FORMAT_R64G64_PASSTHRU
:
355 case ISL_FORMAT_R64G64B64_PASSTHRU
:
356 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
364 genX(uploads_needed
)(uint32_t format
)
366 if (!is_passthru_format(format
))
370 case ISL_FORMAT_R64_PASSTHRU
:
371 case ISL_FORMAT_R64G64_PASSTHRU
:
373 case ISL_FORMAT_R64G64B64_PASSTHRU
:
374 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
377 unreachable("not reached");
382 * Returns the format that we are finally going to use when upload a vertex
383 * element. It will only change if we are using *64*PASSTHRU formats, as for
384 * gen < 8 they need to be splitted on two *32*FLOAT formats.
386 * @upload points in which upload we are. Valid values are [0,1]
389 downsize_format_if_needed(uint32_t format
,
392 assert(upload
== 0 || upload
== 1);
394 if (!is_passthru_format(format
))
398 case ISL_FORMAT_R64_PASSTHRU
:
399 return ISL_FORMAT_R32G32_FLOAT
;
400 case ISL_FORMAT_R64G64_PASSTHRU
:
401 return ISL_FORMAT_R32G32B32A32_FLOAT
;
402 case ISL_FORMAT_R64G64B64_PASSTHRU
:
403 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
404 : ISL_FORMAT_R32G32_FLOAT
;
405 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
406 return ISL_FORMAT_R32G32B32A32_FLOAT
;
408 unreachable("not reached");
413 * Returns the number of componentes associated with a format that is used on
414 * a 64 to 32 format split. See downsize_format()
417 upload_format_size(uint32_t upload_format
)
419 switch (upload_format
) {
420 case ISL_FORMAT_R32G32_FLOAT
:
422 case ISL_FORMAT_R32G32B32A32_FLOAT
:
425 unreachable("not reached");
430 genX(emit_vertices
)(struct brw_context
*brw
)
434 brw_prepare_vertices(brw
);
435 brw_prepare_shader_draw_parameters(brw
);
438 brw_emit_query_begin(brw
);
441 const struct brw_vs_prog_data
*vs_prog_data
=
442 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
445 struct gl_context
*ctx
= &brw
->ctx
;
446 bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
447 ctx
->Polygon
.BackMode
!= GL_FILL
);
449 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
450 unsigned vue
= brw
->vb
.nr_enabled
;
452 /* The element for the edge flags must always be last, so we have to
453 * insert the SGVS before it in that case.
455 if (uses_edge_flag
) {
461 "Trying to insert VID/IID past 33rd vertex element, "
462 "need to reorder the vertex attrbutes.");
464 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
465 if (vs_prog_data
->uses_vertexid
) {
466 vfs
.VertexIDEnable
= true;
467 vfs
.VertexIDComponentNumber
= 2;
468 vfs
.VertexIDElementOffset
= vue
;
471 if (vs_prog_data
->uses_instanceid
) {
472 vfs
.InstanceIDEnable
= true;
473 vfs
.InstanceIDComponentNumber
= 3;
474 vfs
.InstanceIDElementOffset
= vue
;
478 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
479 vfi
.InstancingEnable
= true;
480 vfi
.VertexElementIndex
= vue
;
483 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
486 /* Normally we don't need an element for the SGVS attribute because the
487 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
488 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
489 * we're using draw parameters then we need an element for the those
490 * values. Additionally if there is an edge flag element then the SGVS
491 * can't be inserted past that so we need a dummy element to ensure that
492 * the edge flag is the last one.
494 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
495 vs_prog_data
->uses_baseinstance
||
496 ((vs_prog_data
->uses_instanceid
||
497 vs_prog_data
->uses_vertexid
)
500 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
501 vs_prog_data
->uses_baseinstance
||
502 vs_prog_data
->uses_instanceid
||
503 vs_prog_data
->uses_vertexid
);
505 unsigned nr_elements
=
506 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
509 /* If any of the formats of vb.enabled needs more that one upload, we need
510 * to add it to nr_elements
512 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
513 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
514 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
516 if (genX(uploads_needed(format
)) > 1)
521 /* If the VS doesn't read any inputs (calculating vertex position from
522 * a state variable for some reason, for example), emit a single pad
523 * VERTEX_ELEMENT struct and bail.
525 * The stale VB state stays in place, but they don't do anything unless
526 * a VE loads from them.
528 if (nr_elements
== 0) {
529 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
), 1 + GENX(VERTEX_ELEMENT_STATE_length
));
530 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
532 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
533 .Component0Control
= VFCOMP_STORE_0
,
534 .Component1Control
= VFCOMP_STORE_0
,
535 .Component2Control
= VFCOMP_STORE_0
,
536 .Component3Control
= VFCOMP_STORE_1_FP
,
538 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
542 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
543 const bool uses_draw_params
=
544 vs_prog_data
->uses_basevertex
||
545 vs_prog_data
->uses_baseinstance
;
546 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
547 uses_draw_params
+ vs_prog_data
->uses_drawid
;
551 assert(nr_buffers
<= 33);
553 assert(nr_buffers
<= 17);
555 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
557 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
558 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
560 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
561 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
562 /* Prior to Haswell and Bay Trail we have to use 4-component formats
563 * to fake 3-component ones. In particular, we do this for
564 * half-float and 8 and 16-bit integer formats. This means that the
565 * vertex element may poke over the end of the buffer by 2 bytes.
568 (GEN_GEN
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
569 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
571 buffer
->offset
+ buffer
->size
+ padding
,
576 if (uses_draw_params
) {
577 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
578 brw
->draw
.draw_params_bo
,
579 brw
->draw
.draw_params_offset
,
580 brw
->draw
.draw_params_bo
->size
,
585 if (vs_prog_data
->uses_drawid
) {
586 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
587 brw
->draw
.draw_id_bo
,
588 brw
->draw
.draw_id_offset
,
589 brw
->draw
.draw_id_bo
->size
,
595 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
596 * presumably for VertexID/InstanceID.
599 assert(nr_elements
<= 34);
600 struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
602 assert(nr_elements
<= 18);
605 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
606 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
608 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
609 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
610 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
611 uint32_t comp0
= VFCOMP_STORE_SRC
;
612 uint32_t comp1
= VFCOMP_STORE_SRC
;
613 uint32_t comp2
= VFCOMP_STORE_SRC
;
614 uint32_t comp3
= VFCOMP_STORE_SRC
;
615 unsigned num_uploads
= 1;
618 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
619 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
620 * element which has edge flag enabled."
622 assert(!(is_passthru_format(format
) && uses_edge_flag
));
625 /* The gen4 driver expects edgeflag to come in as a float, and passes
626 * that float on to the tests in the clipper. Mesa's current vertex
627 * attribute value for EdgeFlag is stored as a float, which works out.
628 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
629 * integer ubyte. Just rewrite that to convert to a float.
631 * Gen6+ passes edgeflag as sideband along with the vertex, instead
632 * of in the VUE. We have to upload it sideband as the last vertex
633 * element according to the B-Spec.
636 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
637 gen6_edgeflag_input
= input
;
643 num_uploads
= genX(uploads_needed(format
));
646 for (unsigned c
= 0; c
< num_uploads
; c
++) {
647 uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
648 downsize_format_if_needed(format
, c
);
649 /* If we need more that one upload, the offset stride would be 128
650 * bits (16 bytes), as for previous uploads we are using the full
652 unsigned int offset
= input
->offset
+ c
* 16;
653 int size
= input
->glarray
->Size
;
655 if (GEN_GEN
< 8 && is_passthru_format(format
))
656 size
= upload_format_size(upload_format
);
659 case 0: comp0
= VFCOMP_STORE_0
;
660 case 1: comp1
= VFCOMP_STORE_0
;
661 case 2: comp2
= VFCOMP_STORE_0
;
663 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
664 comp3
= VFCOMP_STORE_0
;
665 } else if (input
->glarray
->Integer
) {
666 comp3
= VFCOMP_STORE_1_INT
;
668 comp3
= VFCOMP_STORE_1_FP
;
675 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
677 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
678 * formats, 64-bit components are stored in the URB without any
679 * conversion. In this case, vertex elements must be written as 128
680 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
681 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
682 * component into the URB, Component 1 must be specified as
683 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
684 * order to output a 128-bit vertex element, or Components 1-3 must
685 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
686 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
687 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
690 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
691 /* Store vertex elements which correspond to double and dvec2 vertex
692 * shader inputs as 128-bit vertex elements, instead of 256-bits.
694 comp2
= VFCOMP_NOSTORE
;
695 comp3
= VFCOMP_NOSTORE
;
699 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
700 .VertexBufferIndex
= input
->buffer
,
702 .SourceElementFormat
= upload_format
,
703 .SourceElementOffset
= offset
,
704 .Component0Control
= comp0
,
705 .Component1Control
= comp1
,
706 .Component2Control
= comp2
,
707 .Component3Control
= comp3
,
709 .DestinationElementOffset
= i
* 4,
713 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
714 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
718 if (needs_sgvs_element
) {
719 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
721 .Component0Control
= VFCOMP_STORE_0
,
722 .Component1Control
= VFCOMP_STORE_0
,
723 .Component2Control
= VFCOMP_STORE_0
,
724 .Component3Control
= VFCOMP_STORE_0
,
726 .DestinationElementOffset
= i
* 4,
731 if (vs_prog_data
->uses_basevertex
||
732 vs_prog_data
->uses_baseinstance
) {
733 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
734 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
735 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
736 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
739 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
740 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
741 if (vs_prog_data
->uses_basevertex
)
742 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
744 if (vs_prog_data
->uses_baseinstance
)
745 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
747 if (vs_prog_data
->uses_vertexid
)
748 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
750 if (vs_prog_data
->uses_instanceid
)
751 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
754 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
755 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
758 if (vs_prog_data
->uses_drawid
) {
759 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
761 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
762 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
763 .Component0Control
= VFCOMP_STORE_SRC
,
764 .Component1Control
= VFCOMP_STORE_0
,
765 .Component2Control
= VFCOMP_STORE_0
,
766 .Component3Control
= VFCOMP_STORE_0
,
768 .DestinationElementOffset
= i
* 4,
772 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
773 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
777 if (gen6_edgeflag_input
) {
779 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
781 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
783 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
784 .EdgeFlagEnable
= true,
785 .SourceElementFormat
= format
,
786 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
787 .Component0Control
= VFCOMP_STORE_SRC
,
788 .Component1Control
= VFCOMP_STORE_0
,
789 .Component2Control
= VFCOMP_STORE_0
,
790 .Component3Control
= VFCOMP_STORE_0
,
793 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
794 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
799 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
800 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
801 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
802 unsigned element_index
;
804 /* The edge flag element is reordered to be the last one in the code
805 * above so we need to compensate for that in the element indices used
808 if (input
== gen6_edgeflag_input
)
809 element_index
= nr_elements
- 1;
813 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
814 vfi
.VertexElementIndex
= element_index
;
815 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
816 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
820 if (vs_prog_data
->uses_drawid
) {
821 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
823 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
824 vfi
.VertexElementIndex
= element
;
830 static const struct brw_tracked_state
genX(vertices
) = {
832 .mesa
= _NEW_POLYGON
,
833 .brw
= BRW_NEW_BATCH
|
836 BRW_NEW_VS_PROG_DATA
,
838 .emit
= genX(emit_vertices
),
841 #if GEN_IS_HASWELL || GEN_GEN >= 8
843 genX(upload_cut_index
)(struct brw_context
*brw
)
845 const struct gl_context
*ctx
= &brw
->ctx
;
847 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
848 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
849 vf
.IndexedDrawCutIndexEnable
= true;
850 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
855 const struct brw_tracked_state
genX(cut_index
) = {
857 .mesa
= _NEW_TRANSFORM
,
858 .brw
= BRW_NEW_INDEX_BUFFER
,
860 .emit
= genX(upload_cut_index
),
866 * Determine the appropriate attribute override value to store into the
867 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
868 * override value contains two pieces of information: the location of the
869 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
870 * flag indicating whether to "swizzle" the attribute based on the direction
871 * the triangle is facing.
873 * If an attribute is "swizzled", then the given VUE location is used for
874 * front-facing triangles, and the VUE location that immediately follows is
875 * used for back-facing triangles. We use this to implement the mapping from
876 * gl_FrontColor/gl_BackColor to gl_Color.
878 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
879 * being instructed to begin reading attribute data. It can be set to a
880 * nonzero value to prevent the SF unit from wasting time reading elements of
881 * the VUE that are not needed by the fragment shader. It is measured in
882 * 256-bit increments.
885 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
886 const struct brw_vue_map
*vue_map
,
887 int urb_entry_read_offset
, int fs_attr
,
888 bool two_side_color
, uint32_t *max_source_attr
)
890 /* Find the VUE slot for this attribute. */
891 int slot
= vue_map
->varying_to_slot
[fs_attr
];
893 /* Viewport and Layer are stored in the VUE header. We need to override
894 * them to zero if earlier stages didn't write them, as GL requires that
895 * they read back as zero when not explicitly set.
897 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
898 attr
->ComponentOverrideX
= true;
899 attr
->ComponentOverrideW
= true;
900 attr
->ConstantSource
= CONST_0000
;
902 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
903 attr
->ComponentOverrideY
= true;
904 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
905 attr
->ComponentOverrideZ
= true;
910 /* If there was only a back color written but not front, use back
911 * as the color instead of undefined
913 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
914 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
915 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
916 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
919 /* This attribute does not exist in the VUE--that means that the vertex
920 * shader did not write to it. This means that either:
922 * (a) This attribute is a texture coordinate, and it is going to be
923 * replaced with point coordinates (as a consequence of a call to
924 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
925 * hardware will ignore whatever attribute override we supply.
927 * (b) This attribute is read by the fragment shader but not written by
928 * the vertex shader, so its value is undefined. Therefore the
929 * attribute override we supply doesn't matter.
931 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
932 * previous shader stage.
934 * Note that we don't have to worry about the cases where the attribute
935 * is gl_PointCoord or is undergoing point sprite coordinate
936 * replacement, because in those cases, this function isn't called.
938 * In case (c), we need to program the attribute overrides so that the
939 * primitive ID will be stored in this slot. In every other case, the
940 * attribute override we supply doesn't matter. So just go ahead and
941 * program primitive ID in every case.
943 attr
->ComponentOverrideW
= true;
944 attr
->ComponentOverrideX
= true;
945 attr
->ComponentOverrideY
= true;
946 attr
->ComponentOverrideZ
= true;
947 attr
->ConstantSource
= PRIM_ID
;
951 /* Compute the location of the attribute relative to urb_entry_read_offset.
952 * Each increment of urb_entry_read_offset represents a 256-bit value, so
953 * it counts for two 128-bit VUE slots.
955 int source_attr
= slot
- 2 * urb_entry_read_offset
;
956 assert(source_attr
>= 0 && source_attr
< 32);
958 /* If we are doing two-sided color, and the VUE slot following this one
959 * represents a back-facing color, then we need to instruct the SF unit to
960 * do back-facing swizzling.
962 bool swizzling
= two_side_color
&&
963 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
964 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
965 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
966 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
968 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
969 if (*max_source_attr
< source_attr
+ swizzling
)
970 *max_source_attr
= source_attr
+ swizzling
;
972 attr
->SourceAttribute
= source_attr
;
974 attr
->SwizzleSelect
= INPUTATTR_FACING
;
979 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
980 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
981 uint32_t *point_sprite_enables
,
982 uint32_t *urb_entry_read_length
,
983 uint32_t *urb_entry_read_offset
)
985 const struct gl_context
*ctx
= &brw
->ctx
;
988 const struct gl_point_attrib
*point
= &ctx
->Point
;
990 /* BRW_NEW_FS_PROG_DATA */
991 const struct brw_wm_prog_data
*wm_prog_data
=
992 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
993 uint32_t max_source_attr
= 0;
995 *point_sprite_enables
= 0;
997 /* BRW_NEW_FRAGMENT_PROGRAM
999 * If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
1000 * the full vertex header. Otherwise, we can program the SF to start
1001 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
1002 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1003 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
1006 bool fs_needs_vue_header
= brw
->fragment_program
->info
.inputs_read
&
1007 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1009 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
1011 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1012 * description of dw10 Point Sprite Texture Coordinate Enable:
1014 * "This field must be programmed to zero when non-point primitives
1017 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1018 * must be programmed to zero when rendering non-point primitives, but
1019 * the IvyBridge PRM does, and if we don't, we get garbage.
1021 * This is not required on Haswell, as the hardware ignores this state
1022 * when drawing non-points -- although we do still need to be careful to
1023 * correctly set the attr overrides.
1026 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1028 bool drawing_points
= brw_is_drawing_points(brw
);
1030 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1031 int input_index
= wm_prog_data
->urb_setup
[attr
];
1033 if (input_index
< 0)
1037 bool point_sprite
= false;
1038 if (drawing_points
) {
1039 if (point
->PointSprite
&&
1040 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1041 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1042 point_sprite
= true;
1045 if (attr
== VARYING_SLOT_PNTC
)
1046 point_sprite
= true;
1049 *point_sprite_enables
|= (1 << input_index
);
1052 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1053 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1055 if (!point_sprite
) {
1056 genX(get_attr_override
)(&attribute
,
1057 &brw
->vue_map_geom_out
,
1058 *urb_entry_read_offset
, attr
,
1059 brw
->ctx
.VertexProgram
._TwoSideEnabled
,
1063 /* The hardware can only do the overrides on 16 overrides at a
1064 * time, and the other up to 16 have to be lined up so that the
1065 * input index = the output index. We'll need to do some
1066 * tweaking to make sure that's the case.
1068 if (input_index
< 16)
1069 attr_overrides
[input_index
] = attribute
;
1071 assert(attribute
.SourceAttribute
== input_index
);
1074 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1075 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1077 * "This field should be set to the minimum length required to read the
1078 * maximum source attribute. The maximum source attribute is indicated
1079 * by the maximum value of the enabled Attribute # Source Attribute if
1080 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1081 * enable is not set.
1082 * read_length = ceiling((max_source_attr + 1) / 2)
1084 * [errata] Corruption/Hang possible if length programmed larger than
1087 * Similar text exists for Ivy Bridge.
1089 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1092 /* ---------------------------------------------------------------------- */
1095 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1097 struct gl_context
*ctx
= &brw
->ctx
;
1100 struct intel_renderbuffer
*depth_irb
=
1101 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1104 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1107 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1108 const int b
= stencil
->_BackFace
;
1111 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1114 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, wmds
) {
1116 if (depth
->Test
&& depth_irb
) {
1117 wmds
.DepthTestEnable
= true;
1118 wmds
.DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1119 wmds
.DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1122 if (stencil
->_Enabled
) {
1123 wmds
.StencilTestEnable
= true;
1124 wmds
.StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1125 wmds
.StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1127 wmds
.StencilTestFunction
=
1128 intel_translate_compare_func(stencil
->Function
[0]);
1129 wmds
.StencilFailOp
=
1130 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1131 wmds
.StencilPassDepthPassOp
=
1132 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1133 wmds
.StencilPassDepthFailOp
=
1134 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1136 wmds
.StencilBufferWriteEnable
= stencil
->_WriteEnabled
;
1138 if (stencil
->_TestTwoSide
) {
1139 wmds
.DoubleSidedStencilEnable
= true;
1140 wmds
.BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1141 wmds
.BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1143 wmds
.BackfaceStencilTestFunction
=
1144 intel_translate_compare_func(stencil
->Function
[b
]);
1145 wmds
.BackfaceStencilFailOp
=
1146 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1147 wmds
.BackfaceStencilPassDepthPassOp
=
1148 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1149 wmds
.BackfaceStencilPassDepthFailOp
=
1150 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1154 wmds
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1155 wmds
.BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1161 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1162 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1163 ptr
.DEPTH_STENCIL_STATEChange
= true;
1166 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1167 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1172 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1174 .mesa
= _NEW_BUFFERS
|
1177 .brw
= BRW_NEW_BLORP
|
1178 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1180 BRW_NEW_STATE_BASE_ADDRESS
),
1182 .emit
= genX(upload_depth_stencil_state
),
1185 /* ---------------------------------------------------------------------- */
1188 genX(upload_clip_state
)(struct brw_context
*brw
)
1190 struct gl_context
*ctx
= &brw
->ctx
;
1193 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1195 /* BRW_NEW_FS_PROG_DATA */
1196 struct brw_wm_prog_data
*wm_prog_data
=
1197 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1199 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1200 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1202 if (wm_prog_data
->barycentric_interp_modes
&
1203 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1204 clip
.NonPerspectiveBarycentricEnable
= true;
1207 clip
.EarlyCullEnable
= true;
1211 clip
.FrontWinding
= ctx
->Polygon
._FrontBit
== _mesa_is_user_fbo(fb
);
1213 if (ctx
->Polygon
.CullFlag
) {
1214 switch (ctx
->Polygon
.CullFaceMode
) {
1216 clip
.CullMode
= CULLMODE_FRONT
;
1219 clip
.CullMode
= CULLMODE_BACK
;
1221 case GL_FRONT_AND_BACK
:
1222 clip
.CullMode
= CULLMODE_BOTH
;
1225 unreachable("Should not get here: invalid CullFlag");
1228 clip
.CullMode
= CULLMODE_NONE
;
1233 clip
.UserClipDistanceCullTestEnableBitmask
=
1234 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1236 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1240 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1241 clip
.TriangleStripListProvokingVertexSelect
= 0;
1242 clip
.TriangleFanProvokingVertexSelect
= 1;
1243 clip
.LineStripListProvokingVertexSelect
= 0;
1245 clip
.TriangleStripListProvokingVertexSelect
= 2;
1246 clip
.TriangleFanProvokingVertexSelect
= 2;
1247 clip
.LineStripListProvokingVertexSelect
= 1;
1250 /* _NEW_TRANSFORM */
1251 clip
.UserClipDistanceClipTestEnableBitmask
=
1252 ctx
->Transform
.ClipPlanesEnabled
;
1255 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1258 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1259 clip
.APIMode
= APIMODE_D3D
;
1261 clip
.APIMode
= APIMODE_OGL
;
1263 clip
.GuardbandClipTestEnable
= true;
1265 /* BRW_NEW_VIEWPORT_COUNT */
1266 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1268 if (ctx
->RasterDiscard
) {
1269 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1271 perf_debug("Rasterizer discard is currently implemented via the "
1272 "clipper; having the GS not write primitives would "
1273 "likely be faster.\n");
1276 clip
.ClipMode
= CLIPMODE_NORMAL
;
1279 clip
.ClipEnable
= brw
->primitive
!= _3DPRIM_RECTLIST
;
1282 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1284 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1285 clip
.ViewportXYClipTestEnable
= true;
1287 clip
.MinimumPointWidth
= 0.125;
1288 clip
.MaximumPointWidth
= 255.875;
1289 clip
.MaximumVPIndex
= viewport_count
- 1;
1290 if (_mesa_geometric_layers(fb
) == 0)
1291 clip
.ForceZeroRTAIndexEnable
= true;
1295 static const struct brw_tracked_state
genX(clip_state
) = {
1297 .mesa
= _NEW_BUFFERS
|
1301 .brw
= BRW_NEW_BLORP
|
1303 BRW_NEW_FS_PROG_DATA
|
1304 BRW_NEW_GS_PROG_DATA
|
1305 BRW_NEW_VS_PROG_DATA
|
1306 BRW_NEW_META_IN_PROGRESS
|
1308 BRW_NEW_RASTERIZER_DISCARD
|
1309 BRW_NEW_TES_PROG_DATA
|
1310 BRW_NEW_VIEWPORT_COUNT
,
1312 .emit
= genX(upload_clip_state
),
1315 /* ---------------------------------------------------------------------- */
1318 genX(upload_sf
)(struct brw_context
*brw
)
1320 struct gl_context
*ctx
= &brw
->ctx
;
1325 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1326 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1329 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1330 sf
.StatisticsEnable
= true;
1331 sf
.ViewportTransformEnable
= brw
->sf
.viewport_transform_enable
;
1335 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1340 sf
.FrontWinding
= ctx
->Polygon
._FrontBit
== render_to_fbo
;
1341 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1342 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1343 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1345 switch (ctx
->Polygon
.FrontMode
) {
1347 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1350 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1353 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1356 unreachable("not reached");
1359 switch (ctx
->Polygon
.BackMode
) {
1361 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1364 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1367 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1370 unreachable("not reached");
1373 sf
.ScissorRectangleEnable
= true;
1375 if (ctx
->Polygon
.CullFlag
) {
1376 switch (ctx
->Polygon
.CullFaceMode
) {
1378 sf
.CullMode
= CULLMODE_FRONT
;
1381 sf
.CullMode
= CULLMODE_BACK
;
1383 case GL_FRONT_AND_BACK
:
1384 sf
.CullMode
= CULLMODE_BOTH
;
1387 unreachable("not reached");
1390 sf
.CullMode
= CULLMODE_NONE
;
1394 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1397 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1398 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1400 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1401 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1402 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1407 if (brw
->is_cherryview
)
1408 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1410 sf
.LineWidth
= brw_get_line_width(brw
);
1412 sf
.LineWidth
= brw_get_line_width(brw
);
1415 if (ctx
->Line
.SmoothFlag
) {
1416 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1418 sf
.AntiAliasingEnable
= true;
1422 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1423 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1424 /* Clamp to the hardware limits */
1425 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1427 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1428 if (use_state_point_size(brw
))
1429 sf
.PointWidthSource
= State
;
1432 /* _NEW_POINT | _NEW_MULTISAMPLE */
1433 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1434 !ctx
->Point
.PointSprite
)
1435 sf
.SmoothPointEnable
= true;
1438 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1441 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1442 sf
.TriangleStripListProvokingVertexSelect
= 2;
1443 sf
.TriangleFanProvokingVertexSelect
= 2;
1444 sf
.LineStripListProvokingVertexSelect
= 1;
1446 sf
.TriangleFanProvokingVertexSelect
= 1;
1450 /* BRW_NEW_FS_PROG_DATA */
1451 const struct brw_wm_prog_data
*wm_prog_data
=
1452 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1454 sf
.AttributeSwizzleEnable
= true;
1455 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1458 * Window coordinates in an FBO are inverted, which means point
1459 * sprite origin must be inverted, too.
1461 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1462 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1464 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1467 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1468 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1470 uint32_t urb_entry_read_length
;
1471 uint32_t urb_entry_read_offset
;
1472 uint32_t point_sprite_enables
;
1473 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1474 &urb_entry_read_length
,
1475 &urb_entry_read_offset
);
1476 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1477 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1478 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1479 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1484 static const struct brw_tracked_state
genX(sf_state
) = {
1486 .mesa
= _NEW_LIGHT
|
1491 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1492 .brw
= BRW_NEW_BLORP
|
1494 BRW_NEW_VUE_MAP_GEOM_OUT
|
1495 (GEN_GEN
<= 7 ? BRW_NEW_GS_PROG_DATA
|
1497 BRW_NEW_TES_PROG_DATA
1499 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1500 BRW_NEW_FRAGMENT_PROGRAM
1503 .emit
= genX(upload_sf
),
1506 /* ---------------------------------------------------------------------- */
1509 genX(upload_wm
)(struct brw_context
*brw
)
1511 struct gl_context
*ctx
= &brw
->ctx
;
1513 /* BRW_NEW_FS_PROG_DATA */
1514 const struct brw_wm_prog_data
*wm_prog_data
=
1515 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1517 UNUSED
bool writes_depth
=
1518 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1521 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1522 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1524 /* We can't fold this into gen6_upload_wm_push_constants(), because
1525 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1526 * (3DSTATE_CONSTANT_PS [DevSNB]):
1528 * "[DevSNB]: This packet must be followed by WM_STATE."
1530 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1531 if (wm_prog_data
->base
.nr_params
!= 0) {
1532 wmcp
.Buffer0Valid
= true;
1533 /* Pointer to the WM constant buffer. Covered by the set of
1534 * state flags from gen6_upload_wm_push_constants.
1536 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1537 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1542 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1543 wm
.StatisticsEnable
= true;
1544 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1545 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1548 if (wm_prog_data
->base
.use_alt_mode
)
1549 wm
.FloatingPointMode
= Alternate
;
1551 wm
.SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1552 wm
.BindingTableEntryCount
= wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1553 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1554 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1555 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1556 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1557 wm_prog_data
->base
.dispatch_grf_start_reg
;
1558 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1559 wm_prog_data
->dispatch_grf_start_reg_2
;
1560 wm
.KernelStartPointer0
= stage_state
->prog_offset
;
1561 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1562 wm_prog_data
->prog_offset_2
;
1563 wm
.DualSourceBlendEnable
=
1564 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1565 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1566 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1567 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1569 /* From the SNB PRM, volume 2 part 1, page 281:
1570 * "If the PS kernel does not need the Position XY Offsets
1571 * to compute a Position XY value, then this field should be
1572 * programmed to POSOFFSET_NONE."
1574 * "SW Recommendation: If the PS kernel needs the Position Offsets
1575 * to compute a Position XY value, this field should match Position
1576 * ZW Interpolation Mode to ensure a consistent position.xyzw
1578 * We only require XY sample offsets. So, this recommendation doesn't
1579 * look useful at the moment. We might need this in future.
1581 if (wm_prog_data
->uses_pos_offset
)
1582 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1584 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1586 if (wm_prog_data
->base
.total_scratch
) {
1587 wm
.ScratchSpaceBasePointer
=
1588 render_bo(stage_state
->scratch_bo
,
1589 ffs(stage_state
->per_thread_scratch
) - 11);
1592 wm
.PixelShaderComputedDepth
= writes_depth
;
1595 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1598 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1601 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1602 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1606 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1608 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1609 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1610 if (wm_prog_data
->uses_kill
||
1611 _mesa_is_alpha_test_enabled(ctx
) ||
1612 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1613 wm_prog_data
->uses_omask
) {
1614 wm
.PixelShaderKillsPixel
= true;
1617 /* _NEW_BUFFERS | _NEW_COLOR */
1618 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1619 wm_prog_data
->has_side_effects
|| wm
.PixelShaderKillsPixel
) {
1620 wm
.ThreadDispatchEnable
= true;
1622 if (multisampled_fbo
) {
1623 /* _NEW_MULTISAMPLE */
1624 if (ctx
->Multisample
.Enabled
)
1625 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1627 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1629 if (wm_prog_data
->persample_dispatch
)
1630 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1632 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1634 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1635 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1639 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1640 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1643 /* The "UAV access enable" bits are unnecessary on HSW because they only
1644 * seem to have an effect on the HW-assisted coherency mechanism which we
1645 * don't need, and the rasterization-related UAV_ONLY flag and the
1646 * DISPATCH_ENABLE bit can be set independently from it.
1647 * C.f. gen8_upload_ps_extra().
1649 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1653 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1654 wm_prog_data
->has_side_effects
)
1660 /* BRW_NEW_FS_PROG_DATA */
1661 if (wm_prog_data
->early_fragment_tests
)
1662 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1663 else if (wm_prog_data
->has_side_effects
)
1664 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1669 static const struct brw_tracked_state
genX(wm_state
) = {
1673 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1677 (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
1678 .brw
= BRW_NEW_BLORP
|
1679 BRW_NEW_FS_PROG_DATA
|
1680 (GEN_GEN
< 7 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1684 .emit
= genX(upload_wm
),
1687 /* ---------------------------------------------------------------------- */
1689 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1690 pkt.KernelStartPointer = stage_state->prog_offset; \
1691 pkt.SamplerCount = \
1692 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1693 pkt.BindingTableEntryCount = \
1694 stage_prog_data->binding_table.size_bytes / 4; \
1695 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
1697 if (stage_prog_data->total_scratch) { \
1698 pkt.ScratchSpaceBasePointer = \
1699 render_bo(stage_state->scratch_bo, 0); \
1700 pkt.PerThreadScratchSpace = \
1701 ffs(stage_state->per_thread_scratch) - 11; \
1704 pkt.DispatchGRFStartRegisterForURBData = \
1705 stage_prog_data->dispatch_grf_start_reg; \
1706 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1707 pkt.prefix##URBEntryReadOffset = 0; \
1709 pkt.StatisticsEnable = true; \
1714 genX(upload_vs_state
)(struct brw_context
*brw
)
1716 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1717 const struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
1719 /* BRW_NEW_VS_PROG_DATA */
1720 const struct brw_vue_prog_data
*vue_prog_data
=
1721 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
1722 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
1724 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
1725 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
1727 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1728 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1730 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
1731 * command that causes the VS Function Enable to toggle. Pipeline
1732 * flush can be executed by sending a PIPE_CONTROL command with CS
1733 * stall bit set and a post sync operation.
1735 * We've already done such a flush at the start of state upload, so we
1736 * don't need to do another one here.
1740 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
1741 if (stage_state
->push_const_size
!= 0) {
1742 cvs
.Buffer0Valid
= true;
1743 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
1744 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1749 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
1750 gen7_emit_vs_workaround_flush(brw
);
1752 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
1753 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1755 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1758 vs
.SIMD8DispatchEnable
=
1759 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
1761 vs
.UserClipDistanceCullTestEnableBitmask
=
1762 vue_prog_data
->cull_distance_mask
;
1767 /* Based on my reading of the simulator, the VS constants don't get
1768 * pulled into the VS FF unit until an appropriate pipeline flush
1769 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
1770 * references to them into a little FIFO. The flushes are common,
1771 * but don't reliably happen between this and a 3DPRIMITIVE, causing
1772 * the primitive to use the wrong constants. Then the FIFO
1773 * containing the constant setup gets added to again on the next
1774 * constants change, and eventually when a flush does happen the
1775 * unit is overwhelmed by constant changes and dies.
1777 * To avoid this, send a PIPE_CONTROL down the line that will
1778 * update the unit immediately loading the constants. The flush
1779 * type bits here were those set by the STATE_BASE_ADDRESS whose
1780 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
1781 * bug reports that led to this workaround, and may be more than
1782 * what is strictly required to avoid the issue.
1784 brw_emit_pipe_control_flush(brw
,
1785 PIPE_CONTROL_DEPTH_STALL
|
1786 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1787 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
1791 static const struct brw_tracked_state
genX(vs_state
) = {
1793 .mesa
= (GEN_GEN
< 7 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
1794 .brw
= BRW_NEW_BATCH
|
1797 BRW_NEW_VS_PROG_DATA
|
1798 (GEN_GEN
< 7 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1799 BRW_NEW_VERTEX_PROGRAM
1802 .emit
= genX(upload_vs_state
),
1805 /* ---------------------------------------------------------------------- */
1808 brw_calculate_guardband_size(const struct gen_device_info
*devinfo
,
1809 uint32_t fb_width
, uint32_t fb_height
,
1810 float m00
, float m11
, float m30
, float m31
,
1811 float *xmin
, float *xmax
,
1812 float *ymin
, float *ymax
)
1814 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1815 * Strips and Fans documentation:
1817 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1818 * fixed-point "guardband" range supported by the rasterization hardware"
1822 * "In almost all circumstances, if an object’s vertices are actually
1823 * modified by this clamping (i.e., had X or Y coordinates outside of
1824 * the guardband extent the rendered object will not match the intended
1825 * result. Therefore software should take steps to ensure that this does
1826 * not happen - e.g., by clipping objects such that they do not exceed
1827 * these limits after the Drawing Rectangle is applied."
1829 * I believe the fundamental restriction is that the rasterizer (in
1830 * the SF/WM stages) have a limit on the number of pixels that can be
1831 * rasterized. We need to ensure any coordinates beyond the rasterizer
1832 * limit are handled by the clipper. So effectively that limit becomes
1833 * the clipper's guardband size.
1835 * It goes on to say:
1837 * "In addition, in order to be correctly rendered, objects must have a
1838 * screenspace bounding box not exceeding 8K in the X or Y direction.
1839 * This additional restriction must also be comprehended by software,
1840 * i.e., enforced by use of clipping."
1842 * This makes no sense. Gen7+ hardware supports 16K render targets,
1843 * and you definitely need to be able to draw polygons that fill the
1844 * surface. Our assumption is that the rasterizer was limited to 8K
1845 * on Sandybridge, which only supports 8K surfaces, and it was actually
1846 * increased to 16K on Ivybridge and later.
1848 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1850 const float gb_size
= devinfo
->gen
>= 7 ? 16384.0f
: 8192.0f
;
1852 if (m00
!= 0 && m11
!= 0) {
1853 /* First, we compute the screen-space render area */
1854 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1855 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1856 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1857 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1859 /* We want the guardband to be centered on that */
1860 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1861 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1862 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1863 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1865 /* Now we need it in native device coordinates */
1866 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1867 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1868 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1869 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1871 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1872 * flipped upside-down. X should be fine though.
1874 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1875 *xmin
= ndc_gb_xmin
;
1876 *xmax
= ndc_gb_xmax
;
1877 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1878 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1880 /* The viewport scales to 0, so nothing will be rendered. */
1889 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
1891 struct gl_context
*ctx
= &brw
->ctx
;
1892 float y_scale
, y_bias
;
1893 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1895 /* BRW_NEW_VIEWPORT_COUNT */
1896 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1899 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1900 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
1901 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
1905 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
1906 uint32_t sf_clip_vp_offset
;
1907 uint32_t *sf_clip_map
= brw_state_batch(brw
, 16 * 4 * viewport_count
,
1908 64, &sf_clip_vp_offset
);
1910 struct GENX(SF_VIEWPORT
) sfv
;
1911 struct GENX(CLIP_VIEWPORT
) clv
;
1912 uint32_t *sf_map
= brw_state_batch(brw
, 8 * 4 * viewport_count
,
1913 32, &brw
->sf
.vp_offset
);
1914 uint32_t *clip_map
= brw_state_batch(brw
, 4 * 4 * viewport_count
,
1915 32, &brw
->clip
.vp_offset
);
1919 if (render_to_fbo
) {
1924 y_bias
= (float)fb_height
;
1927 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
1928 /* _NEW_VIEWPORT: Guardband Clipping */
1929 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
1930 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
1932 sfv
.ViewportMatrixElementm00
= scale
[0];
1933 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
1934 sfv
.ViewportMatrixElementm22
= scale
[2],
1935 sfv
.ViewportMatrixElementm30
= translate
[0],
1936 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
1937 sfv
.ViewportMatrixElementm32
= translate
[2],
1938 brw_calculate_guardband_size(devinfo
, fb_width
, fb_height
,
1939 sfv
.ViewportMatrixElementm00
,
1940 sfv
.ViewportMatrixElementm11
,
1941 sfv
.ViewportMatrixElementm30
,
1942 sfv
.ViewportMatrixElementm31
,
1943 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
1946 clv
.XMinClipGuardband
= gb_xmin
;
1947 clv
.XMaxClipGuardband
= gb_xmax
;
1948 clv
.YMinClipGuardband
= gb_ymin
;
1949 clv
.YMaxClipGuardband
= gb_ymax
;
1952 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
1953 * The hardware will take the intersection of the drawing rectangle,
1954 * scissor rectangle, and the viewport extents. We don't need to be
1955 * smart, and can therefore just program the viewport extents.
1957 const float viewport_Xmax
=
1958 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
1959 const float viewport_Ymax
=
1960 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
1962 if (render_to_fbo
) {
1963 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
1964 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
1965 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
1966 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
1968 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
1969 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
1970 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
1971 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
1976 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
1979 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
1980 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
1987 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
1988 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
1991 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
1995 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
1997 .mesa
= _NEW_BUFFERS
|
1999 .brw
= BRW_NEW_BATCH
|
2001 BRW_NEW_VIEWPORT_COUNT
,
2003 .emit
= genX(upload_sf_clip_viewport
),
2007 genX(upload_gs_state
)(struct brw_context
*brw
)
2009 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2010 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2011 /* BRW_NEW_GEOMETRY_PROGRAM */
2012 bool active
= brw
->geometry_program
;
2014 /* BRW_NEW_GS_PROG_DATA */
2015 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2016 const struct brw_vue_prog_data
*vue_prog_data
=
2017 brw_vue_prog_data(stage_prog_data
);
2019 const struct brw_gs_prog_data
*gs_prog_data
=
2020 brw_gs_prog_data(stage_prog_data
);
2024 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2025 if (active
&& stage_state
->push_const_size
!= 0) {
2026 cgs
.Buffer0Valid
= true;
2027 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2028 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2033 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2035 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2036 * Geometry > Geometry Shader > State:
2038 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2039 * whole fixed function pipeline when the GS enable changes value in
2042 * The hardware architects have clarified that in this context "flush the
2043 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2046 if (brw
->gt
== 2 && brw
->gs
.enabled
!= active
)
2047 gen7_emit_cs_stall_flush(brw
);
2051 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2052 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2055 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2056 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2057 gs
.ControlDataHeaderSize
=
2058 gs_prog_data
->control_data_header_size_hwords
;
2060 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2061 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2063 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2065 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2068 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2069 * Ivy Bridge and Haswell.
2071 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2072 * strip to be delivered to the geometry shader in an order that does
2073 * not strictly follow the OpenGL spec, but preserves triangle
2074 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2075 * the geometry shader sees triangles:
2077 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2079 * (Clearing the bit is even worse, because it fails to preserve
2082 * Triangle strips with adjacency always ordered in a way that preserves
2083 * triangle orientation but does not strictly follow the OpenGL spec,
2084 * regardless of the setting of this bit.
2086 * On Haswell, both triangle strips and triangle strips with adjacency
2087 * are always ordered in a way that preserves triangle orientation.
2088 * Setting this bit causes the ordering to strictly follow the OpenGL
2091 * So in either case we want to set the bit. Unfortunately on Ivy
2092 * Bridge this will get the order close to correct but not perfect.
2094 gs
.ReorderMode
= TRAILING
;
2095 gs
.MaximumNumberofThreads
=
2096 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2097 : (devinfo
->max_gs_threads
- 1);
2100 gs
.SOStatisticsEnable
= true;
2101 gs
.RenderingEnabled
= 1;
2102 if (brw
->geometry_program
->info
.has_transform_feedback_varyings
)
2103 gs
.SVBIPayloadEnable
= true;
2105 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2106 * was previously done for gen6.
2108 * TODO: test with both disabled to see if the HW is behaving
2109 * as expected, like in gen7.
2111 gs
.SingleProgramFlow
= true;
2112 gs
.VectorMaskEnable
= true;
2116 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2118 if (gs_prog_data
->static_vertex_count
!= -1) {
2119 gs
.StaticOutput
= true;
2120 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2122 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2124 gs
.UserClipDistanceCullTestEnableBitmask
=
2125 vue_prog_data
->cull_distance_mask
;
2127 const int urb_entry_write_offset
= 1;
2128 const uint32_t urb_entry_output_length
=
2129 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2130 urb_entry_write_offset
;
2132 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2133 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2137 } else if (brw
->ff_gs
.prog_active
) {
2138 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
2139 * program. This function provides the needed 3DSTATE_GS for this.
2141 upload_gs_state_for_tf(brw
);
2144 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2145 gs
.StatisticsEnable
= true;
2147 gs
.RenderingEnabled
= true;
2151 gs
.DispatchGRFStartRegisterForURBData
= 1;
2153 gs
.IncludeVertexHandles
= true;
2159 brw
->gs
.enabled
= active
;
2163 static const struct brw_tracked_state
genX(gs_state
) = {
2165 .mesa
= (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
2166 .brw
= BRW_NEW_BATCH
|
2169 BRW_NEW_GEOMETRY_PROGRAM
|
2170 BRW_NEW_GS_PROG_DATA
|
2171 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
|
2172 BRW_NEW_PUSH_CONSTANT_ALLOCATION
2175 .emit
= genX(upload_gs_state
),
2178 /* ---------------------------------------------------------------------- */
2180 #define blend_factor(x) brw_translate_blend_factor(x)
2181 #define blend_eqn(x) brw_translate_blend_equation(x)
2184 genX(upload_blend_state
)(struct brw_context
*brw
)
2186 struct gl_context
*ctx
= &brw
->ctx
;
2189 /* We need at least one BLEND_STATE written, because we might do
2190 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2191 * for computed depth or alpha test), which will do an FB write
2192 * with render target 0, which will reference BLEND_STATE[0] for
2193 * alpha test enable.
2195 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2196 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2197 nr_draw_buffers
= 1;
2199 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2201 size
+= GENX(BLEND_STATE_length
) * 4;
2204 uint32_t *blend_map
;
2205 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2208 struct GENX(BLEND_STATE
) blend
= { 0 };
2211 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2212 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2215 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2216 * "If drawbuffer zero is not NONE and the buffer it references has an
2217 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2218 * operations are skipped."
2220 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2221 /* _NEW_MULTISAMPLE */
2222 if (_mesa_is_multisample_enabled(ctx
)) {
2223 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2224 blend
.AlphaToCoverageEnable
= true;
2225 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2227 if (ctx
->Multisample
.SampleAlphaToOne
)
2228 blend
.AlphaToOneEnable
= true;
2232 if (ctx
->Color
.AlphaEnabled
) {
2233 blend
.AlphaTestEnable
= true;
2234 blend
.AlphaTestFunction
=
2235 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2238 if (ctx
->Color
.DitherFlag
) {
2239 blend
.ColorDitherEnable
= true;
2244 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2245 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2251 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2253 /* Used for implementing the following bit of GL_EXT_texture_integer:
2254 * "Per-fragment operations that require floating-point color
2255 * components, including multisample alpha operations, alpha test,
2256 * blending, and dithering, have no effect when the corresponding
2257 * colors are written to an integer color buffer."
2259 bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2262 if (ctx
->Color
.ColorLogicOpEnabled
) {
2263 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2264 : GL_UNSIGNED_NORMALIZED
;
2265 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2266 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2267 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2269 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2270 _mesa_enum_to_string(rb_type
));
2271 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2272 entry
.LogicOpEnable
= true;
2273 entry
.LogicOpFunction
=
2274 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2276 } else if (ctx
->Color
.BlendEnabled
& (1 << i
) && !integer
&&
2277 !ctx
->Color
._AdvancedBlendMode
) {
2278 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2279 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2280 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2281 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2282 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2283 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2285 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2286 srcRGB
= dstRGB
= GL_ONE
;
2288 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2289 srcA
= dstA
= GL_ONE
;
2291 /* Due to hardware limitations, the destination may have information
2292 * in an alpha channel even when the format specifies no alpha
2293 * channel. In order to avoid getting any incorrect blending due to
2294 * that alpha channel, coerce the blend factors to values that will
2295 * not read the alpha channel, but will instead use the correct
2296 * implicit value for alpha.
2298 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2299 GL_TEXTURE_ALPHA_TYPE
)) {
2300 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2301 srcA
= brw_fix_xRGB_alpha(srcA
);
2302 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2303 dstA
= brw_fix_xRGB_alpha(dstA
);
2306 entry
.ColorBufferBlendEnable
= true;
2307 entry
.DestinationBlendFactor
= blend_factor(dstRGB
);
2308 entry
.SourceBlendFactor
= blend_factor(srcRGB
);
2309 entry
.DestinationAlphaBlendFactor
= blend_factor(dstA
);
2310 entry
.SourceAlphaBlendFactor
= blend_factor(srcA
);
2311 entry
.ColorBlendFunction
= blend_eqn(eqRGB
);
2312 entry
.AlphaBlendFunction
= blend_eqn(eqA
);
2314 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2315 blend
.IndependentAlphaBlendEnable
= true;
2318 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2319 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2321 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2322 * clamping in the fragment shader. For its clamping of
2323 * blending, the spec says:
2325 * "RESOLVED: For fixed-point color buffers, the inputs and
2326 * the result of the blending equation are clamped. For
2327 * floating-point color buffers, no clamping occurs."
2329 * So, generally, we want clamping to the render target's range.
2330 * And, good news, the hardware tables for both pre- and
2331 * post-blend color clamping are either ignored, or any are
2332 * allowed, or clamping is required but RT range clamping is a
2335 entry
.PreBlendColorClampEnable
= true;
2336 entry
.PostBlendColorClampEnable
= true;
2337 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2339 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2340 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2341 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2342 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2344 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2345 * "If Dual Source Blending is enabled, this bit must be disabled."
2347 WARN_ONCE(ctx
->Color
.Blend
[i
]._UsesDualSrc
&&
2348 _mesa_is_multisample_enabled(ctx
) &&
2349 ctx
->Multisample
.SampleAlphaToOne
,
2350 "HW workaround: disabling alpha to one with dual src "
2352 if (ctx
->Color
.Blend
[i
]._UsesDualSrc
)
2353 blend
.AlphaToOneEnable
= false;
2355 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2357 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2363 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2367 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2368 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2369 ptr
.BLEND_STATEChange
= true;
2372 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2373 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2375 ptr
.BlendStatePointerValid
= true;
2381 static const struct brw_tracked_state
genX(blend_state
) = {
2383 .mesa
= _NEW_BUFFERS
|
2386 .brw
= BRW_NEW_BATCH
|
2388 BRW_NEW_STATE_BASE_ADDRESS
,
2390 .emit
= genX(upload_blend_state
),
2393 /* ---------------------------------------------------------------------- */
2396 genX(upload_scissor_state
)(struct brw_context
*brw
)
2398 struct gl_context
*ctx
= &brw
->ctx
;
2399 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2400 struct GENX(SCISSOR_RECT
) scissor
;
2401 uint32_t scissor_state_offset
;
2402 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2403 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2404 uint32_t *scissor_map
;
2406 /* BRW_NEW_VIEWPORT_COUNT */
2407 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2409 scissor_map
= brw_state_batch(
2410 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2411 32, &scissor_state_offset
);
2413 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2415 /* The scissor only needs to handle the intersection of drawable and
2416 * scissor rect. Clipping to the boundaries of static shared buffers
2417 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2419 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2420 * inclusive but max is exclusive.
2422 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2425 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2426 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2427 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2428 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2429 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2431 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2432 /* If the scissor was out of bounds and got clamped to 0 width/height
2433 * at the bounds, the subtraction of 1 from maximums could produce a
2434 * negative number and thus not clip anything. Instead, just provide
2435 * a min > max scissor inside the bounds, which produces the expected
2438 scissor
.ScissorRectangleXMin
= 1;
2439 scissor
.ScissorRectangleXMax
= 0;
2440 scissor
.ScissorRectangleYMin
= 1;
2441 scissor
.ScissorRectangleYMax
= 0;
2442 } else if (render_to_fbo
) {
2443 /* texmemory: Y=0=bottom */
2444 scissor
.ScissorRectangleXMin
= bbox
[0];
2445 scissor
.ScissorRectangleXMax
= bbox
[1] - 1;
2446 scissor
.ScissorRectangleYMin
= bbox
[2];
2447 scissor
.ScissorRectangleYMax
= bbox
[3] - 1;
2449 /* memory: Y=0=top */
2450 scissor
.ScissorRectangleXMin
= bbox
[0];
2451 scissor
.ScissorRectangleXMax
= bbox
[1] - 1;
2452 scissor
.ScissorRectangleYMin
= fb_height
- bbox
[3];
2453 scissor
.ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2456 GENX(SCISSOR_RECT_pack
)(
2457 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2460 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2461 ptr
.ScissorRectPointer
= scissor_state_offset
;
2465 static const struct brw_tracked_state
genX(scissor_state
) = {
2467 .mesa
= _NEW_BUFFERS
|
2470 .brw
= BRW_NEW_BATCH
|
2472 BRW_NEW_VIEWPORT_COUNT
,
2474 .emit
= genX(upload_scissor_state
),
2478 UNUSED
static const uint32_t push_constant_opcodes
[] = {
2479 [MESA_SHADER_VERTEX
] = 21,
2480 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2481 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2482 [MESA_SHADER_GEOMETRY
] = 22,
2483 [MESA_SHADER_FRAGMENT
] = 23,
2484 [MESA_SHADER_COMPUTE
] = 0,
2488 upload_constant_state(struct brw_context
*brw
,
2489 struct brw_stage_state
*stage_state
,
2490 bool active
, uint32_t stage
)
2492 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
2493 active
= active
&& stage_state
->push_const_size
!= 0;
2495 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2496 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2499 pkt
.ConstantBody
.ConstantBuffer2ReadLength
=
2500 stage_state
->push_const_size
;
2501 pkt
.ConstantBody
.PointerToConstantBuffer2
=
2502 render_ro_bo(brw
->batch
.bo
, stage_state
->push_const_offset
);
2504 pkt
.ConstantBody
.ConstantBuffer0ReadLength
=
2505 stage_state
->push_const_size
;
2506 pkt
.ConstantBody
.PointerToConstantBuffer0
.offset
=
2507 stage_state
->push_const_offset
| mocs
;
2512 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
2517 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
2519 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2521 /* _BRW_NEW_VERTEX_PROGRAM */
2522 const struct brw_program
*vp
= brw_program_const(brw
->vertex_program
);
2523 /* BRW_NEW_VS_PROG_DATA */
2524 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
2526 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
2527 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
2530 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !brw
->is_baytrail
)
2531 gen7_emit_vs_workaround_flush(brw
);
2533 upload_constant_state(brw
, stage_state
, true /* active */,
2534 MESA_SHADER_VERTEX
);
2538 static const struct brw_tracked_state
genX(vs_push_constants
) = {
2540 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2542 .brw
= BRW_NEW_BATCH
|
2544 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2545 BRW_NEW_VERTEX_PROGRAM
|
2546 BRW_NEW_VS_PROG_DATA
,
2548 .emit
= genX(upload_vs_push_constants
),
2552 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
2554 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2556 /* BRW_NEW_GEOMETRY_PROGRAM */
2557 const struct brw_program
*gp
= brw_program_const(brw
->geometry_program
);
2560 /* BRW_NEW_GS_PROG_DATA */
2561 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
2563 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
2564 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
2568 upload_constant_state(brw
, stage_state
, gp
, MESA_SHADER_GEOMETRY
);
2572 static const struct brw_tracked_state
genX(gs_push_constants
) = {
2574 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2576 .brw
= BRW_NEW_BATCH
|
2578 BRW_NEW_GEOMETRY_PROGRAM
|
2579 BRW_NEW_GS_PROG_DATA
|
2580 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2582 .emit
= genX(upload_gs_push_constants
),
2586 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
2588 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
2589 /* BRW_NEW_FRAGMENT_PROGRAM */
2590 const struct brw_program
*fp
= brw_program_const(brw
->fragment_program
);
2591 /* BRW_NEW_FS_PROG_DATA */
2592 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
2594 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
2596 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
2599 upload_constant_state(brw
, stage_state
, true, MESA_SHADER_FRAGMENT
);
2603 static const struct brw_tracked_state
genX(wm_push_constants
) = {
2605 .mesa
= _NEW_PROGRAM_CONSTANTS
,
2606 .brw
= BRW_NEW_BATCH
|
2608 BRW_NEW_FRAGMENT_PROGRAM
|
2609 BRW_NEW_FS_PROG_DATA
|
2610 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2612 .emit
= genX(upload_wm_push_constants
),
2615 /* ---------------------------------------------------------------------- */
2618 genX(determine_sample_mask
)(struct brw_context
*brw
)
2620 struct gl_context
*ctx
= &brw
->ctx
;
2621 float coverage
= 1.0f
;
2622 float coverage_invert
= false;
2623 unsigned sample_mask
= ~0u;
2625 /* BRW_NEW_NUM_SAMPLES */
2626 unsigned num_samples
= brw
->num_samples
;
2628 if (_mesa_is_multisample_enabled(ctx
)) {
2629 if (ctx
->Multisample
.SampleCoverage
) {
2630 coverage
= ctx
->Multisample
.SampleCoverageValue
;
2631 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
2633 if (ctx
->Multisample
.SampleMask
) {
2634 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
2638 if (num_samples
> 1) {
2639 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
2640 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
2641 if (coverage_invert
)
2642 coverage_bits
^= (1 << num_samples
) - 1;
2643 return coverage_bits
& sample_mask
;
2649 /* ---------------------------------------------------------------------- */
2652 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
2653 unsigned num_samples
)
2655 assert(brw
->num_samples
<= 16);
2657 unsigned log2_samples
= ffs(MAX2(num_samples
, 1)) - 1;
2659 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
2660 multi
.PixelLocation
= CENTER
;
2661 multi
.NumberofMultisamples
= log2_samples
;
2663 GEN_SAMPLE_POS_4X(multi
.Sample
);
2665 switch (num_samples
) {
2667 GEN_SAMPLE_POS_1X(multi
.Sample
);
2670 GEN_SAMPLE_POS_2X(multi
.Sample
);
2673 GEN_SAMPLE_POS_4X(multi
.Sample
);
2676 GEN_SAMPLE_POS_8X(multi
.Sample
);
2686 genX(upload_multisample_state
)(struct brw_context
*brw
)
2688 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
2690 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
2691 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
2695 static const struct brw_tracked_state
genX(multisample_state
) = {
2697 .mesa
= _NEW_MULTISAMPLE
,
2698 .brw
= BRW_NEW_BLORP
|
2700 BRW_NEW_NUM_SAMPLES
,
2702 .emit
= genX(upload_multisample_state
)
2705 /* ---------------------------------------------------------------------- */
2708 genX(upload_color_calc_state
)(struct brw_context
*brw
)
2710 struct gl_context
*ctx
= &brw
->ctx
;
2712 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
2714 cc
.AlphaTestFormat
= ALPHATEST_UNORM8
;
2715 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
2716 ctx
->Color
.AlphaRef
);
2720 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
2721 cc
.BackfaceStencilReferenceValue
=
2722 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
2726 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
2727 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
2728 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
2729 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
2732 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2733 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
2735 ptr
.ColorCalcStatePointerValid
= true;
2740 static const struct brw_tracked_state
genX(color_calc_state
) = {
2742 .mesa
= _NEW_COLOR
|
2744 .brw
= BRW_NEW_BATCH
|
2747 BRW_NEW_STATE_BASE_ADDRESS
,
2749 .emit
= genX(upload_color_calc_state
),
2754 /* ---------------------------------------------------------------------- */
2758 genX(upload_sbe
)(struct brw_context
*brw
)
2760 struct gl_context
*ctx
= &brw
->ctx
;
2761 /* BRW_NEW_FS_PROG_DATA */
2762 const struct brw_wm_prog_data
*wm_prog_data
=
2763 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
2765 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
2767 #define attr_overrides sbe.Attribute
2769 uint32_t urb_entry_read_length
;
2770 uint32_t urb_entry_read_offset
;
2771 uint32_t point_sprite_enables
;
2773 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
2774 sbe
.AttributeSwizzleEnable
= true;
2775 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2778 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2782 * Window coordinates in an FBO are inverted, which means point
2783 * sprite origin must be inverted.
2785 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
2786 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
2788 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
2790 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
2791 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
2792 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
2793 * BRW_NEW_VUE_MAP_GEOM_OUT
2795 genX(calculate_attr_overrides
)(brw
,
2797 &point_sprite_enables
,
2798 &urb_entry_read_length
,
2799 &urb_entry_read_offset
);
2801 /* Typically, the URB entry read length and offset should be programmed
2802 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
2803 * stage which produces geometry. However, we don't know the proper
2804 * value until we call calculate_attr_overrides().
2806 * To fit with our existing code, we override the inherited values and
2807 * specify it here directly, as we did on previous generations.
2809 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
2810 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
2811 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
2812 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2815 sbe
.ForceVertexURBEntryReadLength
= true;
2816 sbe
.ForceVertexURBEntryReadOffset
= true;
2820 /* prepare the active component dwords */
2821 int input_index
= 0;
2822 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
2823 if (!(brw
->fragment_program
->info
.inputs_read
&
2824 BITFIELD64_BIT(attr
))) {
2828 assert(input_index
< 32);
2830 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
2837 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2838 for (int i
= 0; i
< 16; i
++)
2839 sbes
.Attribute
[i
] = attr_overrides
[i
];
2843 #undef attr_overrides
2846 static const struct brw_tracked_state
genX(sbe_state
) = {
2848 .mesa
= _NEW_BUFFERS
|
2853 .brw
= BRW_NEW_BLORP
|
2855 BRW_NEW_FRAGMENT_PROGRAM
|
2856 BRW_NEW_FS_PROG_DATA
|
2857 BRW_NEW_GS_PROG_DATA
|
2858 BRW_NEW_TES_PROG_DATA
|
2859 BRW_NEW_VUE_MAP_GEOM_OUT
|
2860 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
2863 .emit
= genX(upload_sbe
),
2866 /* ---------------------------------------------------------------------- */
2869 * Outputs the 3DSTATE_SO_DECL_LIST command.
2871 * The data output is a series of 64-bit entries containing a SO_DECL per
2872 * stream. We only have one stream of rendering coming out of the GS unit, so
2873 * we only emit stream 0 (low 16 bits) SO_DECLs.
2876 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
2877 const struct brw_vue_map
*vue_map
)
2879 struct gl_context
*ctx
= &brw
->ctx
;
2880 /* BRW_NEW_TRANSFORM_FEEDBACK */
2881 struct gl_transform_feedback_object
*xfb_obj
=
2882 ctx
->TransformFeedback
.CurrentObject
;
2883 const struct gl_transform_feedback_info
*linked_xfb_info
=
2884 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
2885 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2886 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2887 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2888 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2890 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2892 memset(so_decl
, 0, sizeof(so_decl
));
2894 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2895 * command feels strange -- each dword pair contains a SO_DECL per stream.
2897 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
2898 int buffer
= linked_xfb_info
->Outputs
[i
].OutputBuffer
;
2899 struct GENX(SO_DECL
) decl
= {0};
2900 int varying
= linked_xfb_info
->Outputs
[i
].OutputRegister
;
2901 const unsigned components
= linked_xfb_info
->Outputs
[i
].NumComponents
;
2902 unsigned component_mask
= (1 << components
) - 1;
2903 unsigned stream_id
= linked_xfb_info
->Outputs
[i
].StreamId
;
2904 unsigned decl_buffer_slot
= buffer
;
2905 assert(stream_id
< MAX_VERTEX_STREAMS
);
2907 /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w
2908 * gl_Layer is stored in VARYING_SLOT_PSIZ.y
2909 * gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
2911 if (varying
== VARYING_SLOT_PSIZ
) {
2912 assert(components
== 1);
2913 component_mask
<<= 3;
2914 } else if (varying
== VARYING_SLOT_LAYER
) {
2915 assert(components
== 1);
2916 component_mask
<<= 1;
2917 } else if (varying
== VARYING_SLOT_VIEWPORT
) {
2918 assert(components
== 1);
2919 component_mask
<<= 2;
2921 component_mask
<<= linked_xfb_info
->Outputs
[i
].ComponentOffset
;
2924 buffer_mask
[stream_id
] |= 1 << buffer
;
2926 decl
.OutputBufferSlot
= decl_buffer_slot
;
2927 if (varying
== VARYING_SLOT_LAYER
|| varying
== VARYING_SLOT_VIEWPORT
) {
2928 decl
.RegisterIndex
= vue_map
->varying_to_slot
[VARYING_SLOT_PSIZ
];
2930 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2931 decl
.RegisterIndex
= vue_map
->varying_to_slot
[varying
];
2933 decl
.ComponentMask
= component_mask
;
2935 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2936 * array. Instead, it simply increments DstOffset for the following
2937 * input by the number of components that should be skipped.
2939 * Our hardware is unusual in that it requires us to program SO_DECLs
2940 * for fake "hole" components, rather than simply taking the offset
2941 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2942 * program as many size = 4 holes as we can, then a final hole to
2943 * accommodate the final 1, 2, or 3 remaining.
2945 int skip_components
=
2946 linked_xfb_info
->Outputs
[i
].DstOffset
- next_offset
[buffer
];
2948 next_offset
[buffer
] += skip_components
;
2950 while (skip_components
>= 4) {
2951 struct GENX(SO_DECL
) *d
= &so_decl
[stream_id
][decls
[stream_id
]++];
2953 d
->OutputBufferSlot
= decl_buffer_slot
;
2954 d
->ComponentMask
= 0xf;
2955 skip_components
-= 4;
2958 if (skip_components
> 0) {
2959 struct GENX(SO_DECL
) *d
= &so_decl
[stream_id
][decls
[stream_id
]++];
2961 d
->OutputBufferSlot
= decl_buffer_slot
;
2962 d
->ComponentMask
= (1 << skip_components
) - 1;
2965 assert(linked_xfb_info
->Outputs
[i
].DstOffset
== next_offset
[buffer
]);
2967 next_offset
[buffer
] += components
;
2969 so_decl
[stream_id
][decls
[stream_id
]++] = decl
;
2971 if (decls
[stream_id
] > max_decls
)
2972 max_decls
= decls
[stream_id
];
2976 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
2977 .StreamtoBufferSelects0
= buffer_mask
[0],
2978 .StreamtoBufferSelects1
= buffer_mask
[1],
2979 .StreamtoBufferSelects2
= buffer_mask
[2],
2980 .StreamtoBufferSelects3
= buffer_mask
[3],
2981 .NumEntries0
= decls
[0],
2982 .NumEntries1
= decls
[1],
2983 .NumEntries2
= decls
[2],
2984 .NumEntries3
= decls
[3]);
2986 for (int i
= 0; i
< max_decls
; i
++) {
2987 GENX(SO_DECL_ENTRY_pack
)(
2988 brw
, dw
+ 2 + i
* 2,
2989 &(struct GENX(SO_DECL_ENTRY
)) {
2990 .Stream0Decl
= so_decl
[0][i
],
2991 .Stream1Decl
= so_decl
[1][i
],
2992 .Stream2Decl
= so_decl
[2][i
],
2993 .Stream3Decl
= so_decl
[3][i
],
2999 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3001 struct gl_context
*ctx
= &brw
->ctx
;
3002 /* BRW_NEW_TRANSFORM_FEEDBACK */
3003 struct gl_transform_feedback_object
*xfb_obj
=
3004 ctx
->TransformFeedback
.CurrentObject
;
3006 const struct gl_transform_feedback_info
*linked_xfb_info
=
3007 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3009 struct brw_transform_feedback_object
*brw_obj
=
3010 (struct brw_transform_feedback_object
*) xfb_obj
;
3011 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3014 /* Set up the up to 4 output buffers. These are the ranges defined in the
3015 * gl_transform_feedback_object.
3017 for (int i
= 0; i
< 4; i
++) {
3018 struct intel_buffer_object
*bufferobj
=
3019 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3022 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3023 sob
.SOBufferIndex
= i
;
3028 uint32_t start
= xfb_obj
->Offset
[i
];
3029 assert(start
% 4 == 0);
3030 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3032 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
);
3033 assert(end
<= bo
->size
);
3035 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3036 sob
.SOBufferIndex
= i
;
3038 sob
.SurfaceBaseAddress
= render_bo(bo
, start
);
3040 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3041 sob
.SurfaceEndAddress
= render_bo(bo
, end
);
3043 sob
.SOBufferEnable
= true;
3044 sob
.StreamOffsetWriteEnable
= true;
3045 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3046 sob
.SOBufferMOCS
= mocs_wb
;
3048 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3049 sob
.StreamOutputBufferOffsetAddress
=
3050 instruction_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3052 if (brw_obj
->zero_offsets
) {
3053 /* Zero out the offset and write that to offset_bo */
3054 sob
.StreamOffset
= 0;
3056 /* Use offset_bo as the "Stream Offset." */
3057 sob
.StreamOffset
= 0xFFFFFFFF;
3064 brw_obj
->zero_offsets
= false;
3069 query_active(struct gl_query_object
*q
)
3071 return q
&& q
->Active
;
3075 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3076 const struct brw_vue_map
*vue_map
)
3078 struct gl_context
*ctx
= &brw
->ctx
;
3079 /* BRW_NEW_TRANSFORM_FEEDBACK */
3080 struct gl_transform_feedback_object
*xfb_obj
=
3081 ctx
->TransformFeedback
.CurrentObject
;
3083 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3085 int urb_entry_read_offset
= 0;
3086 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3087 urb_entry_read_offset
;
3089 sos
.SOFunctionEnable
= true;
3090 sos
.SOStatisticsEnable
= true;
3092 /* BRW_NEW_RASTERIZER_DISCARD */
3093 if (ctx
->RasterDiscard
) {
3094 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3095 sos
.RenderingDisable
= true;
3097 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3098 "query active relies on the clipper.");
3103 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3104 sos
.ReorderMode
= TRAILING
;
3107 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3108 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3109 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3110 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3112 const struct gl_transform_feedback_info
*linked_xfb_info
=
3113 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3114 /* Set buffer pitches; 0 means unbound. */
3115 if (xfb_obj
->Buffers
[0])
3116 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3117 if (xfb_obj
->Buffers
[1])
3118 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3119 if (xfb_obj
->Buffers
[2])
3120 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3121 if (xfb_obj
->Buffers
[3])
3122 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3125 /* We always read the whole vertex. This could be reduced at some
3126 * point by reading less and offsetting the register index in the
3129 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3130 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3131 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3132 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3133 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3134 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3135 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3136 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3142 genX(upload_sol
)(struct brw_context
*brw
)
3144 struct gl_context
*ctx
= &brw
->ctx
;
3145 /* BRW_NEW_TRANSFORM_FEEDBACK */
3146 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3149 genX(upload_3dstate_so_buffers
)(brw
);
3151 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3152 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3155 /* Finally, set up the SOL stage. This command must always follow updates to
3156 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3157 * MMIO register updates (current performed by the kernel at each batch
3160 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3163 static const struct brw_tracked_state
genX(sol_state
) = {
3166 .brw
= BRW_NEW_BATCH
|
3168 BRW_NEW_RASTERIZER_DISCARD
|
3169 BRW_NEW_VUE_MAP_GEOM_OUT
|
3170 BRW_NEW_TRANSFORM_FEEDBACK
,
3172 .emit
= genX(upload_sol
),
3175 /* ---------------------------------------------------------------------- */
3178 genX(upload_ps
)(struct brw_context
*brw
)
3180 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3181 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3183 /* BRW_NEW_FS_PROG_DATA */
3184 const struct brw_wm_prog_data
*prog_data
=
3185 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3186 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3191 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3192 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3193 * incorrect for subspans where some of the pixels are unlit. We believe
3194 * the bit just didn't take effect in previous generations.
3196 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3199 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3201 /* BRW_NEW_FS_PROG_DATA */
3202 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3204 if (prog_data
->base
.use_alt_mode
)
3205 ps
.FloatingPointMode
= Alternate
;
3207 /* Haswell requires the sample mask to be set in this packet as well as
3208 * in 3DSTATE_SAMPLE_MASK; the values should match.
3211 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3213 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3216 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3217 * it implicitly scales for different GT levels (which have some # of
3220 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3223 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3225 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3227 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3230 if (prog_data
->base
.nr_params
> 0)
3231 ps
.PushConstantEnable
= true;
3234 /* From the IVB PRM, volume 2 part 1, page 287:
3235 * "This bit is inserted in the PS payload header and made available to
3236 * the DataPort (either via the message header or via header bypass) to
3237 * indicate that oMask data (one or two phases) is included in Render
3238 * Target Write messages. If present, the oMask data is used to mask off
3241 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3243 /* The hardware wedges if you have this bit set but don't turn on any
3244 * dual source blend factors.
3246 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3248 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3249 (ctx
->Color
.BlendEnabled
& 1) &&
3250 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3252 /* BRW_NEW_FS_PROG_DATA */
3253 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3256 /* From the documentation for this packet:
3257 * "If the PS kernel does not need the Position XY Offsets to
3258 * compute a Position Value, then this field should be programmed
3259 * to POSOFFSET_NONE."
3261 * "SW Recommendation: If the PS kernel needs the Position Offsets
3262 * to compute a Position XY value, this field should match Position
3263 * ZW Interpolation Mode to ensure a consistent position.xyzw
3266 * We only require XY sample offsets. So, this recommendation doesn't
3267 * look useful at the moment. We might need this in future.
3269 if (prog_data
->uses_pos_offset
)
3270 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3272 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3274 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3275 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3276 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3277 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3278 prog_data
->base
.dispatch_grf_start_reg
;
3279 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3280 prog_data
->dispatch_grf_start_reg_2
;
3282 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3283 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3284 prog_data
->prog_offset_2
;
3286 if (prog_data
->base
.total_scratch
) {
3287 ps
.ScratchSpaceBasePointer
=
3288 render_bo(stage_state
->scratch_bo
,
3289 ffs(stage_state
->per_thread_scratch
) - 11);
3294 static const struct brw_tracked_state
genX(ps_state
) = {
3296 .mesa
= _NEW_MULTISAMPLE
|
3297 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3300 .brw
= BRW_NEW_BATCH
|
3302 BRW_NEW_FS_PROG_DATA
,
3304 .emit
= genX(upload_ps
),
3307 /* ---------------------------------------------------------------------- */
3310 genX(upload_hs_state
)(struct brw_context
*brw
)
3312 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3313 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3314 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3315 const struct brw_vue_prog_data
*vue_prog_data
=
3316 brw_vue_prog_data(stage_prog_data
);
3318 /* BRW_NEW_TES_PROG_DATA */
3319 struct brw_tcs_prog_data
*tcs_prog_data
=
3320 brw_tcs_prog_data(stage_prog_data
);
3322 if (!tcs_prog_data
) {
3323 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3325 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3326 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3328 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3329 hs
.IncludeVertexHandles
= true;
3331 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3336 static const struct brw_tracked_state
genX(hs_state
) = {
3339 .brw
= BRW_NEW_BATCH
|
3341 BRW_NEW_TCS_PROG_DATA
|
3342 BRW_NEW_TESS_PROGRAMS
,
3344 .emit
= genX(upload_hs_state
),
3348 genX(upload_ds_state
)(struct brw_context
*brw
)
3350 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3351 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3352 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3354 /* BRW_NEW_TES_PROG_DATA */
3355 const struct brw_tes_prog_data
*tes_prog_data
=
3356 brw_tes_prog_data(stage_prog_data
);
3357 const struct brw_vue_prog_data
*vue_prog_data
=
3358 brw_vue_prog_data(stage_prog_data
);
3360 if (!tes_prog_data
) {
3361 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3363 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3364 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3366 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3367 ds
.ComputeWCoordinateEnable
=
3368 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3371 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3372 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3373 ds
.UserClipDistanceCullTestEnableBitmask
=
3374 vue_prog_data
->cull_distance_mask
;
3380 static const struct brw_tracked_state
genX(ds_state
) = {
3383 .brw
= BRW_NEW_BATCH
|
3385 BRW_NEW_TESS_PROGRAMS
|
3386 BRW_NEW_TES_PROG_DATA
,
3388 .emit
= genX(upload_ds_state
),
3391 /* ---------------------------------------------------------------------- */
3394 upload_te_state(struct brw_context
*brw
)
3396 /* BRW_NEW_TESS_PROGRAMS */
3397 bool active
= brw
->tess_eval_program
;
3399 /* BRW_NEW_TES_PROG_DATA */
3400 const struct brw_tes_prog_data
*tes_prog_data
=
3401 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
3404 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
3405 te
.Partitioning
= tes_prog_data
->partitioning
;
3406 te
.OutputTopology
= tes_prog_data
->output_topology
;
3407 te
.TEDomain
= tes_prog_data
->domain
;
3409 te
.MaximumTessellationFactorOdd
= 63.0;
3410 te
.MaximumTessellationFactorNotOdd
= 64.0;
3413 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
3417 static const struct brw_tracked_state
genX(te_state
) = {
3420 .brw
= BRW_NEW_BLORP
|
3422 BRW_NEW_TES_PROG_DATA
|
3423 BRW_NEW_TESS_PROGRAMS
,
3425 .emit
= upload_te_state
,
3428 /* ---------------------------------------------------------------------- */
3431 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
3433 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3434 /* BRW_NEW_TESS_PROGRAMS */
3435 const struct brw_program
*tep
= brw_program_const(brw
->tess_eval_program
);
3438 /* BRW_NEW_TES_PROG_DATA */
3439 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
3440 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
3441 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
3444 upload_constant_state(brw
, stage_state
, tep
, MESA_SHADER_TESS_EVAL
);
3447 static const struct brw_tracked_state
genX(tes_push_constants
) = {
3449 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3450 .brw
= BRW_NEW_BATCH
|
3452 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3453 BRW_NEW_TESS_PROGRAMS
|
3454 BRW_NEW_TES_PROG_DATA
,
3456 .emit
= genX(upload_tes_push_constants
),
3460 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
3462 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3463 /* BRW_NEW_TESS_PROGRAMS */
3464 const struct brw_program
*tcp
= brw_program_const(brw
->tess_ctrl_program
);
3465 bool active
= brw
->tess_eval_program
;
3468 /* BRW_NEW_TCS_PROG_DATA */
3469 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
3471 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
3472 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
3475 upload_constant_state(brw
, stage_state
, active
, MESA_SHADER_TESS_CTRL
);
3478 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
3480 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3481 .brw
= BRW_NEW_BATCH
|
3483 BRW_NEW_DEFAULT_TESS_LEVELS
|
3484 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3485 BRW_NEW_TESS_PROGRAMS
|
3486 BRW_NEW_TCS_PROG_DATA
,
3488 .emit
= genX(upload_tcs_push_constants
),
3492 /* ---------------------------------------------------------------------- */
3496 genX(upload_raster
)(struct brw_context
*brw
)
3498 struct gl_context
*ctx
= &brw
->ctx
;
3501 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3504 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
3507 struct gl_point_attrib
*point
= &ctx
->Point
;
3509 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
3510 if (polygon
->_FrontBit
== render_to_fbo
)
3511 raster
.FrontWinding
= CounterClockwise
;
3513 if (polygon
->CullFlag
) {
3514 switch (polygon
->CullFaceMode
) {
3516 raster
.CullMode
= CULLMODE_FRONT
;
3519 raster
.CullMode
= CULLMODE_BACK
;
3521 case GL_FRONT_AND_BACK
:
3522 raster
.CullMode
= CULLMODE_BOTH
;
3525 unreachable("not reached");
3528 raster
.CullMode
= CULLMODE_NONE
;
3531 point
->SmoothFlag
= raster
.SmoothPointEnable
;
3533 raster
.DXMultisampleRasterizationEnable
=
3534 _mesa_is_multisample_enabled(ctx
);
3536 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
3537 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
3538 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
3540 switch (polygon
->FrontMode
) {
3542 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
3545 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
3548 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
3551 unreachable("not reached");
3554 switch (polygon
->BackMode
) {
3556 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
3559 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
3562 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
3565 unreachable("not reached");
3569 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
3572 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
3574 /* _NEW_TRANSFORM */
3575 if (!ctx
->Transform
.DepthClamp
) {
3577 raster
.ViewportZFarClipTestEnable
= true;
3578 raster
.ViewportZNearClipTestEnable
= true;
3580 raster
.ViewportZClipTestEnable
= true;
3584 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
3586 raster
.ConservativeRasterizationEnable
=
3587 ctx
->IntelConservativeRasterization
;
3590 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
3591 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
3593 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
3597 static const struct brw_tracked_state
genX(raster_state
) = {
3599 .mesa
= _NEW_BUFFERS
|
3606 .brw
= BRW_NEW_BLORP
|
3608 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3610 .emit
= genX(upload_raster
),
3613 /* ---------------------------------------------------------------------- */
3616 genX(upload_ps_extra
)(struct brw_context
*brw
)
3618 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
3620 const struct brw_wm_prog_data
*prog_data
=
3621 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3623 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
3624 psx
.PixelShaderValid
= true;
3625 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
3626 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
3627 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
3628 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
3629 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
3630 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
3632 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
3633 if (prog_data
->uses_sample_mask
) {
3635 if (prog_data
->post_depth_coverage
)
3636 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3637 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
3638 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
3640 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3642 psx
.PixelShaderUsesInputCoverageMask
= true;
3646 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3648 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
3649 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
3652 /* The stricter cross-primitive coherency guarantees that the hardware
3653 * gives us with the "Accesses UAV" bit set for at least one shader stage
3654 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
3655 * are redundant within the current image, atomic counter and SSBO GL
3656 * APIs, which all have very loose ordering and coherency requirements
3657 * and generally rely on the application to insert explicit barriers when
3658 * a shader invocation is expected to see the memory writes performed by
3659 * the invocations of some previous primitive. Regardless of the value
3660 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
3661 * cause an in most cases useless DC flush when the lowermost stage with
3662 * the bit set finishes execution.
3664 * It would be nice to disable it, but in some cases we can't because on
3665 * Gen8+ it also has an influence on rasterization via the PS UAV-only
3666 * signal (which could be set independently from the coherency mechanism
3667 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
3668 * determine whether the hardware skips execution of the fragment shader
3669 * or not via the ThreadDispatchEnable signal. However if we know that
3670 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
3671 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
3672 * difference so we may just disable it here.
3674 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
3675 * take into account KillPixels when no depth or stencil writes are
3676 * enabled. In order for occlusion queries to work correctly with no
3677 * attachments, we need to force-enable here.
3679 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
3682 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
3683 !brw_color_buffer_write_enabled(brw
))
3684 psx
.PixelShaderHasUAV
= true;
3688 const struct brw_tracked_state
genX(ps_extra
) = {
3690 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
3691 .brw
= BRW_NEW_BLORP
|
3693 BRW_NEW_FRAGMENT_PROGRAM
|
3694 BRW_NEW_FS_PROG_DATA
|
3695 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3697 .emit
= genX(upload_ps_extra
),
3700 /* ---------------------------------------------------------------------- */
3703 genX(upload_ps_blend
)(struct brw_context
*brw
)
3705 struct gl_context
*ctx
= &brw
->ctx
;
3708 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
3709 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
3712 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
3714 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
3715 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
3716 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
3718 if (!buffer0_is_integer
) {
3719 /* _NEW_MULTISAMPLE */
3720 pb
.AlphaToCoverageEnable
=
3721 _mesa_is_multisample_enabled(ctx
) &&
3722 ctx
->Multisample
.SampleAlphaToCoverage
;
3724 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
3727 /* Used for implementing the following bit of GL_EXT_texture_integer:
3728 * "Per-fragment operations that require floating-point color
3729 * components, including multisample alpha operations, alpha test,
3730 * blending, and dithering, have no effect when the corresponding
3731 * colors are written to an integer color buffer."
3733 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
3734 * "If drawbuffer zero is not NONE and the buffer it references has an
3735 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
3736 * operations are skipped."
3738 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
3739 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
3740 GLenum eqA
= color
->Blend
[0].EquationA
;
3741 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
3742 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
3743 GLenum srcA
= color
->Blend
[0].SrcA
;
3744 GLenum dstA
= color
->Blend
[0].DstA
;
3746 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
3747 srcRGB
= dstRGB
= GL_ONE
;
3749 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
3750 srcA
= dstA
= GL_ONE
;
3752 /* Due to hardware limitations, the destination may have information
3753 * in an alpha channel even when the format specifies no alpha
3754 * channel. In order to avoid getting any incorrect blending due to
3755 * that alpha channel, coerce the blend factors to values that will
3756 * not read the alpha channel, but will instead use the correct
3757 * implicit value for alpha.
3759 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
3760 GL_TEXTURE_ALPHA_TYPE
)) {
3761 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
3762 srcA
= brw_fix_xRGB_alpha(srcA
);
3763 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
3764 dstA
= brw_fix_xRGB_alpha(dstA
);
3767 pb
.ColorBufferBlendEnable
= true;
3768 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
3769 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
3770 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
3771 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
3773 pb
.IndependentAlphaBlendEnable
=
3774 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
3779 static const struct brw_tracked_state
genX(ps_blend
) = {
3781 .mesa
= _NEW_BUFFERS
|
3784 .brw
= BRW_NEW_BLORP
|
3786 BRW_NEW_FRAGMENT_PROGRAM
,
3788 .emit
= genX(upload_ps_blend
)
3793 /* ---------------------------------------------------------------------- */
3797 genX(upload_viewport_state_pointers
)(struct brw_context
*brw
)
3799 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
3800 vp
.CCViewportStateChange
= 1;
3801 vp
.SFViewportStateChange
= 1;
3802 vp
.CLIPViewportStateChange
= 1;
3803 vp
.PointertoCLIP_VIEWPORT
= brw
->clip
.vp_offset
;
3804 vp
.PointertoSF_VIEWPORT
= brw
->sf
.vp_offset
;
3805 vp
.PointertoCC_VIEWPORT
= brw
->cc
.vp_offset
;
3809 static const struct brw_tracked_state
genX(viewport_state
) = {
3812 .brw
= BRW_NEW_BATCH
|
3817 BRW_NEW_STATE_BASE_ADDRESS
,
3819 .emit
= genX(upload_viewport_state_pointers
),
3823 /* ---------------------------------------------------------------------- */
3826 genX(init_atoms
)(struct brw_context
*brw
)
3829 static const struct brw_tracked_state
*render_atoms
[] =
3831 /* Once all the programs are done, we know how large urb entry
3832 * sizes need to be and can decide if we need to change the urb
3836 &brw_recalculate_urb_fence
,
3841 /* Surface state setup. Must come before the VS/WM unit. The binding
3842 * table upload must be last.
3844 &brw_vs_pull_constants
,
3845 &brw_wm_pull_constants
,
3846 &brw_renderbuffer_surfaces
,
3847 &brw_renderbuffer_read_surfaces
,
3848 &brw_texture_surfaces
,
3849 &brw_vs_binding_table
,
3850 &brw_wm_binding_table
,
3855 /* These set up state for brw_psp_urb_cbs */
3859 &brw_vs_unit
, /* always required, enabled or not */
3865 &brw_invariant_state
,
3867 &brw_binding_table_pointers
,
3868 &brw_blend_constant_color
,
3872 &genX(polygon_stipple
),
3873 &genX(polygon_stipple_offset
),
3875 &genX(line_stipple
),
3879 &genX(drawing_rect
),
3880 &brw_indices
, /* must come before brw_vertices */
3884 &brw_constant_buffer
3887 static const struct brw_tracked_state
*render_atoms
[] =
3889 &genX(sf_clip_viewport
),
3891 /* Command packets: */
3894 &genX(viewport_state
), /* must do after *_vp stages */
3897 &genX(blend_state
), /* must do before cc unit */
3898 &genX(color_calc_state
), /* must do before cc unit */
3899 &genX(depth_stencil_state
), /* must do before cc unit */
3901 &genX(vs_push_constants
), /* Before vs_state */
3902 &genX(gs_push_constants
), /* Before gs_state */
3903 &genX(wm_push_constants
), /* Before wm_state */
3905 /* Surface state setup. Must come before the VS/WM unit. The binding
3906 * table upload must be last.
3908 &brw_vs_pull_constants
,
3909 &brw_vs_ubo_surfaces
,
3910 &brw_gs_pull_constants
,
3911 &brw_gs_ubo_surfaces
,
3912 &brw_wm_pull_constants
,
3913 &brw_wm_ubo_surfaces
,
3914 &gen6_renderbuffer_surfaces
,
3915 &brw_renderbuffer_read_surfaces
,
3916 &brw_texture_surfaces
,
3918 &brw_vs_binding_table
,
3919 &gen6_gs_binding_table
,
3920 &brw_wm_binding_table
,
3925 &gen6_sampler_state
,
3926 &genX(multisample_state
),
3934 &genX(scissor_state
),
3936 &gen6_binding_table_pointers
,
3940 &genX(polygon_stipple
),
3941 &genX(polygon_stipple_offset
),
3943 &genX(line_stipple
),
3945 &genX(drawing_rect
),
3947 &brw_indices
, /* must come before brw_vertices */
3952 static const struct brw_tracked_state
*render_atoms
[] =
3954 /* Command packets: */
3957 &genX(sf_clip_viewport
),
3960 &gen7_push_constant_space
,
3962 &genX(blend_state
), /* must do before cc unit */
3963 &genX(color_calc_state
), /* must do before cc unit */
3964 &genX(depth_stencil_state
), /* must do before cc unit */
3966 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
3967 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
3968 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
3969 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
3970 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
3972 &genX(vs_push_constants
), /* Before vs_state */
3973 &genX(tcs_push_constants
),
3974 &genX(tes_push_constants
),
3975 &genX(gs_push_constants
), /* Before gs_state */
3976 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
3978 /* Surface state setup. Must come before the VS/WM unit. The binding
3979 * table upload must be last.
3981 &brw_vs_pull_constants
,
3982 &brw_vs_ubo_surfaces
,
3983 &brw_vs_abo_surfaces
,
3984 &brw_tcs_pull_constants
,
3985 &brw_tcs_ubo_surfaces
,
3986 &brw_tcs_abo_surfaces
,
3987 &brw_tes_pull_constants
,
3988 &brw_tes_ubo_surfaces
,
3989 &brw_tes_abo_surfaces
,
3990 &brw_gs_pull_constants
,
3991 &brw_gs_ubo_surfaces
,
3992 &brw_gs_abo_surfaces
,
3993 &brw_wm_pull_constants
,
3994 &brw_wm_ubo_surfaces
,
3995 &brw_wm_abo_surfaces
,
3996 &gen6_renderbuffer_surfaces
,
3997 &brw_renderbuffer_read_surfaces
,
3998 &brw_texture_surfaces
,
3999 &brw_vs_binding_table
,
4000 &brw_tcs_binding_table
,
4001 &brw_tes_binding_table
,
4002 &brw_gs_binding_table
,
4003 &brw_wm_binding_table
,
4010 &genX(multisample_state
),
4024 &genX(scissor_state
),
4028 &genX(polygon_stipple
),
4029 &genX(polygon_stipple_offset
),
4031 &genX(line_stipple
),
4033 &genX(drawing_rect
),
4035 &brw_indices
, /* must come before brw_vertices */
4044 static const struct brw_tracked_state
*render_atoms
[] =
4047 &genX(sf_clip_viewport
),
4050 &gen7_push_constant_space
,
4053 &genX(color_calc_state
),
4055 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4056 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4057 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4058 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4059 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4061 &genX(vs_push_constants
), /* Before vs_state */
4062 &genX(tcs_push_constants
),
4063 &genX(tes_push_constants
),
4064 &genX(gs_push_constants
), /* Before gs_state */
4065 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4067 /* Surface state setup. Must come before the VS/WM unit. The binding
4068 * table upload must be last.
4070 &brw_vs_pull_constants
,
4071 &brw_vs_ubo_surfaces
,
4072 &brw_vs_abo_surfaces
,
4073 &brw_tcs_pull_constants
,
4074 &brw_tcs_ubo_surfaces
,
4075 &brw_tcs_abo_surfaces
,
4076 &brw_tes_pull_constants
,
4077 &brw_tes_ubo_surfaces
,
4078 &brw_tes_abo_surfaces
,
4079 &brw_gs_pull_constants
,
4080 &brw_gs_ubo_surfaces
,
4081 &brw_gs_abo_surfaces
,
4082 &brw_wm_pull_constants
,
4083 &brw_wm_ubo_surfaces
,
4084 &brw_wm_abo_surfaces
,
4085 &gen6_renderbuffer_surfaces
,
4086 &brw_renderbuffer_read_surfaces
,
4087 &brw_texture_surfaces
,
4088 &brw_vs_binding_table
,
4089 &brw_tcs_binding_table
,
4090 &brw_tes_binding_table
,
4091 &brw_gs_binding_table
,
4092 &brw_wm_binding_table
,
4099 &genX(multisample_state
),
4108 &genX(raster_state
),
4114 &genX(depth_stencil_state
),
4117 &genX(scissor_state
),
4121 &genX(polygon_stipple
),
4122 &genX(polygon_stipple_offset
),
4124 &genX(line_stipple
),
4126 &genX(drawing_rect
),
4139 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
4140 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
4141 render_atoms
, ARRAY_SIZE(render_atoms
));
4144 static const struct brw_tracked_state
*compute_atoms
[] =
4147 &brw_cs_image_surfaces
,
4148 &gen7_cs_push_constants
,
4149 &brw_cs_pull_constants
,
4150 &brw_cs_ubo_surfaces
,
4151 &brw_cs_abo_surfaces
,
4152 &brw_cs_texture_surfaces
,
4153 &brw_cs_work_groups_surface
,
4158 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
4159 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
4160 compute_atoms
, ARRAY_SIZE(compute_atoms
));