2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
35 #include "brw_context.h"
37 #include "brw_defines.h"
40 #include "brw_multisample_state.h"
41 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
46 #include "intel_buffer_objects.h"
47 #include "intel_fbo.h"
49 #include "main/enums.h"
50 #include "main/fbobject.h"
51 #include "main/framebuffer.h"
52 #include "main/glformats.h"
53 #include "main/shaderapi.h"
54 #include "main/stencil.h"
55 #include "main/transformfeedback.h"
56 #include "main/varray.h"
57 #include "main/viewport.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
71 uint32_t read_domains
;
72 uint32_t write_domain
;
77 emit_reloc(struct brw_context
*brw
,
78 void *location
, struct brw_address address
, uint32_t delta
)
80 uint32_t offset
= (char *) location
- (char *) brw
->batch
.map
;
82 return brw_emit_reloc(&brw
->batch
, offset
, address
.bo
,
83 address
.offset
+ delta
,
85 address
.write_domain
);
88 #define __gen_address_type struct brw_address
89 #define __gen_user_data struct brw_context
92 __gen_combine_address(struct brw_context
*brw
, void *location
,
93 struct brw_address address
, uint32_t delta
)
95 if (address
.bo
== NULL
) {
96 return address
.offset
+ delta
;
98 return emit_reloc(brw
, location
, address
, delta
);
102 static inline struct brw_address
103 render_bo(struct brw_bo
*bo
, uint32_t offset
)
105 return (struct brw_address
) {
108 .read_domains
= I915_GEM_DOMAIN_RENDER
,
109 .write_domain
= I915_GEM_DOMAIN_RENDER
,
113 static inline struct brw_address
114 render_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
116 return (struct brw_address
) {
119 .read_domains
= I915_GEM_DOMAIN_RENDER
,
124 static inline struct brw_address
125 instruction_bo(struct brw_bo
*bo
, uint32_t offset
)
127 return (struct brw_address
) {
130 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
131 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
135 static inline struct brw_address
136 instruction_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
138 return (struct brw_address
) {
141 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
146 static inline struct brw_address
147 vertex_bo(struct brw_bo
*bo
, uint32_t offset
)
149 return (struct brw_address
) {
152 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
157 #include "genxml/genX_pack.h"
159 #define _brw_cmd_length(cmd) cmd ## _length
160 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
161 #define _brw_cmd_header(cmd) cmd ## _header
162 #define _brw_cmd_pack(cmd) cmd ## _pack
164 #define brw_batch_emit(brw, cmd, name) \
165 for (struct cmd name = { _brw_cmd_header(cmd) }, \
166 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
167 __builtin_expect(_dst != NULL, 1); \
168 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
171 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
172 uint32_t *_dw = emit_dwords(brw, n); \
173 struct cmd template = { \
174 _brw_cmd_header(cmd), \
175 .DWordLength = n - _brw_cmd_length_bias(cmd), \
178 _brw_cmd_pack(cmd)(brw, _dw, &template); \
179 _dw + 1; /* Array starts at dw[1] */ \
182 #define brw_state_emit(brw, cmd, align, offset, name) \
183 for (struct cmd name = { 0, }, \
184 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
186 __builtin_expect(_dst != NULL, 1); \
187 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
191 * Polygon stipple packet
194 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
196 struct gl_context
*ctx
= &brw
->ctx
;
199 if (!ctx
->Polygon
.StippleFlag
)
202 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
203 /* Polygon stipple is provided in OpenGL order, i.e. bottom
204 * row first. If we're rendering to a window (i.e. the
205 * default frame buffer object, 0), then we need to invert
206 * it to match our pixel layout. But if we're rendering
207 * to a FBO (i.e. any named frame buffer object), we *don't*
208 * need to invert - we already match the layout.
210 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
211 for (unsigned i
= 0; i
< 32; i
++)
212 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
214 for (unsigned i
= 0; i
< 32; i
++)
215 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
220 static const struct brw_tracked_state
genX(polygon_stipple
) = {
222 .mesa
= _NEW_POLYGON
|
224 .brw
= BRW_NEW_CONTEXT
,
226 .emit
= genX(upload_polygon_stipple
),
230 * Polygon stipple offset packet
233 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
235 struct gl_context
*ctx
= &brw
->ctx
;
238 if (!ctx
->Polygon
.StippleFlag
)
241 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
244 * If we're drawing to a system window we have to invert the Y axis
245 * in order to match the OpenGL pixel coordinate system, and our
246 * offset must be matched to the window position. If we're drawing
247 * to a user-created FBO then our native pixel coordinate system
248 * works just fine, and there's no window system to worry about.
250 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
251 poly
.PolygonStippleYOffset
=
252 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
257 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
259 .mesa
= _NEW_BUFFERS
|
261 .brw
= BRW_NEW_CONTEXT
,
263 .emit
= genX(upload_polygon_stipple_offset
),
267 * Line stipple packet
270 genX(upload_line_stipple
)(struct brw_context
*brw
)
272 struct gl_context
*ctx
= &brw
->ctx
;
274 if (!ctx
->Line
.StippleFlag
)
277 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
278 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
280 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
281 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
285 static const struct brw_tracked_state
genX(line_stipple
) = {
288 .brw
= BRW_NEW_CONTEXT
,
290 .emit
= genX(upload_line_stipple
),
293 /* Constant single cliprect for framebuffer object or DRI2 drawing */
295 genX(upload_drawing_rect
)(struct brw_context
*brw
)
297 struct gl_context
*ctx
= &brw
->ctx
;
298 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
299 const unsigned int fb_width
= _mesa_geometric_width(fb
);
300 const unsigned int fb_height
= _mesa_geometric_height(fb
);
302 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
303 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
304 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
308 static const struct brw_tracked_state
genX(drawing_rect
) = {
310 .mesa
= _NEW_BUFFERS
,
311 .brw
= BRW_NEW_BLORP
|
314 .emit
= genX(upload_drawing_rect
),
318 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
322 unsigned start_offset
,
327 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
328 .VertexBufferIndex
= buffer_nr
,
329 .BufferPitch
= stride
,
330 .BufferStartingAddress
= vertex_bo(bo
, start_offset
),
332 .BufferSize
= end_offset
- start_offset
,
336 .AddressModifyEnable
= true,
340 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
341 .InstanceDataStepRate
= step_rate
,
343 .EndAddress
= vertex_bo(bo
, end_offset
- 1),
348 .VertexBufferMOCS
= SKL_MOCS_WB
,
350 .VertexBufferMOCS
= BDW_MOCS_WB
,
352 .VertexBufferMOCS
= GEN7_MOCS_L3
,
356 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
357 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
361 is_passthru_format(uint32_t format
)
364 case ISL_FORMAT_R64_PASSTHRU
:
365 case ISL_FORMAT_R64G64_PASSTHRU
:
366 case ISL_FORMAT_R64G64B64_PASSTHRU
:
367 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
375 genX(uploads_needed
)(uint32_t format
)
377 if (!is_passthru_format(format
))
381 case ISL_FORMAT_R64_PASSTHRU
:
382 case ISL_FORMAT_R64G64_PASSTHRU
:
384 case ISL_FORMAT_R64G64B64_PASSTHRU
:
385 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
388 unreachable("not reached");
393 * Returns the format that we are finally going to use when upload a vertex
394 * element. It will only change if we are using *64*PASSTHRU formats, as for
395 * gen < 8 they need to be splitted on two *32*FLOAT formats.
397 * @upload points in which upload we are. Valid values are [0,1]
400 downsize_format_if_needed(uint32_t format
,
403 assert(upload
== 0 || upload
== 1);
405 if (!is_passthru_format(format
))
409 case ISL_FORMAT_R64_PASSTHRU
:
410 return ISL_FORMAT_R32G32_FLOAT
;
411 case ISL_FORMAT_R64G64_PASSTHRU
:
412 return ISL_FORMAT_R32G32B32A32_FLOAT
;
413 case ISL_FORMAT_R64G64B64_PASSTHRU
:
414 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
415 : ISL_FORMAT_R32G32_FLOAT
;
416 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
417 return ISL_FORMAT_R32G32B32A32_FLOAT
;
419 unreachable("not reached");
424 * Returns the number of componentes associated with a format that is used on
425 * a 64 to 32 format split. See downsize_format()
428 upload_format_size(uint32_t upload_format
)
430 switch (upload_format
) {
431 case ISL_FORMAT_R32G32_FLOAT
:
433 case ISL_FORMAT_R32G32B32A32_FLOAT
:
436 unreachable("not reached");
441 genX(emit_vertices
)(struct brw_context
*brw
)
445 brw_prepare_vertices(brw
);
446 brw_prepare_shader_draw_parameters(brw
);
449 brw_emit_query_begin(brw
);
452 const struct brw_vs_prog_data
*vs_prog_data
=
453 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
456 struct gl_context
*ctx
= &brw
->ctx
;
457 bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
458 ctx
->Polygon
.BackMode
!= GL_FILL
);
460 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
461 unsigned vue
= brw
->vb
.nr_enabled
;
463 /* The element for the edge flags must always be last, so we have to
464 * insert the SGVS before it in that case.
466 if (uses_edge_flag
) {
472 "Trying to insert VID/IID past 33rd vertex element, "
473 "need to reorder the vertex attrbutes.");
475 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
476 if (vs_prog_data
->uses_vertexid
) {
477 vfs
.VertexIDEnable
= true;
478 vfs
.VertexIDComponentNumber
= 2;
479 vfs
.VertexIDElementOffset
= vue
;
482 if (vs_prog_data
->uses_instanceid
) {
483 vfs
.InstanceIDEnable
= true;
484 vfs
.InstanceIDComponentNumber
= 3;
485 vfs
.InstanceIDElementOffset
= vue
;
489 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
490 vfi
.InstancingEnable
= true;
491 vfi
.VertexElementIndex
= vue
;
494 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
497 /* Normally we don't need an element for the SGVS attribute because the
498 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
499 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
500 * we're using draw parameters then we need an element for the those
501 * values. Additionally if there is an edge flag element then the SGVS
502 * can't be inserted past that so we need a dummy element to ensure that
503 * the edge flag is the last one.
505 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
506 vs_prog_data
->uses_baseinstance
||
507 ((vs_prog_data
->uses_instanceid
||
508 vs_prog_data
->uses_vertexid
)
511 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
512 vs_prog_data
->uses_baseinstance
||
513 vs_prog_data
->uses_instanceid
||
514 vs_prog_data
->uses_vertexid
);
516 unsigned nr_elements
=
517 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
520 /* If any of the formats of vb.enabled needs more that one upload, we need
521 * to add it to nr_elements
523 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
524 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
525 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
527 if (genX(uploads_needed(format
)) > 1)
532 /* If the VS doesn't read any inputs (calculating vertex position from
533 * a state variable for some reason, for example), emit a single pad
534 * VERTEX_ELEMENT struct and bail.
536 * The stale VB state stays in place, but they don't do anything unless
537 * a VE loads from them.
539 if (nr_elements
== 0) {
540 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
), 1 + GENX(VERTEX_ELEMENT_STATE_length
));
541 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
543 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
544 .Component0Control
= VFCOMP_STORE_0
,
545 .Component1Control
= VFCOMP_STORE_0
,
546 .Component2Control
= VFCOMP_STORE_0
,
547 .Component3Control
= VFCOMP_STORE_1_FP
,
549 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
553 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
554 const bool uses_draw_params
=
555 vs_prog_data
->uses_basevertex
||
556 vs_prog_data
->uses_baseinstance
;
557 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
558 uses_draw_params
+ vs_prog_data
->uses_drawid
;
562 assert(nr_buffers
<= 33);
564 assert(nr_buffers
<= 17);
566 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
568 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
569 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
571 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
572 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
573 /* Prior to Haswell and Bay Trail we have to use 4-component formats
574 * to fake 3-component ones. In particular, we do this for
575 * half-float and 8 and 16-bit integer formats. This means that the
576 * vertex element may poke over the end of the buffer by 2 bytes.
579 (GEN_GEN
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
580 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
582 buffer
->offset
+ buffer
->size
+ padding
,
587 if (uses_draw_params
) {
588 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
589 brw
->draw
.draw_params_bo
,
590 brw
->draw
.draw_params_offset
,
591 brw
->draw
.draw_params_bo
->size
,
596 if (vs_prog_data
->uses_drawid
) {
597 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
598 brw
->draw
.draw_id_bo
,
599 brw
->draw
.draw_id_offset
,
600 brw
->draw
.draw_id_bo
->size
,
606 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
607 * presumably for VertexID/InstanceID.
610 assert(nr_elements
<= 34);
611 struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
613 assert(nr_elements
<= 18);
616 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
617 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
619 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
620 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
621 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
622 uint32_t comp0
= VFCOMP_STORE_SRC
;
623 uint32_t comp1
= VFCOMP_STORE_SRC
;
624 uint32_t comp2
= VFCOMP_STORE_SRC
;
625 uint32_t comp3
= VFCOMP_STORE_SRC
;
626 unsigned num_uploads
= 1;
629 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
630 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
631 * element which has edge flag enabled."
633 assert(!(is_passthru_format(format
) && uses_edge_flag
));
636 /* The gen4 driver expects edgeflag to come in as a float, and passes
637 * that float on to the tests in the clipper. Mesa's current vertex
638 * attribute value for EdgeFlag is stored as a float, which works out.
639 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
640 * integer ubyte. Just rewrite that to convert to a float.
642 * Gen6+ passes edgeflag as sideband along with the vertex, instead
643 * of in the VUE. We have to upload it sideband as the last vertex
644 * element according to the B-Spec.
647 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
648 gen6_edgeflag_input
= input
;
654 num_uploads
= genX(uploads_needed(format
));
657 for (unsigned c
= 0; c
< num_uploads
; c
++) {
658 uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
659 downsize_format_if_needed(format
, c
);
660 /* If we need more that one upload, the offset stride would be 128
661 * bits (16 bytes), as for previous uploads we are using the full
663 unsigned int offset
= input
->offset
+ c
* 16;
664 int size
= input
->glarray
->Size
;
666 if (GEN_GEN
< 8 && is_passthru_format(format
))
667 size
= upload_format_size(upload_format
);
670 case 0: comp0
= VFCOMP_STORE_0
;
671 case 1: comp1
= VFCOMP_STORE_0
;
672 case 2: comp2
= VFCOMP_STORE_0
;
674 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
675 comp3
= VFCOMP_STORE_0
;
676 } else if (input
->glarray
->Integer
) {
677 comp3
= VFCOMP_STORE_1_INT
;
679 comp3
= VFCOMP_STORE_1_FP
;
686 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
688 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
689 * formats, 64-bit components are stored in the URB without any
690 * conversion. In this case, vertex elements must be written as 128
691 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
692 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
693 * component into the URB, Component 1 must be specified as
694 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
695 * order to output a 128-bit vertex element, or Components 1-3 must
696 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
697 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
698 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
701 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
702 /* Store vertex elements which correspond to double and dvec2 vertex
703 * shader inputs as 128-bit vertex elements, instead of 256-bits.
705 comp2
= VFCOMP_NOSTORE
;
706 comp3
= VFCOMP_NOSTORE
;
710 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
711 .VertexBufferIndex
= input
->buffer
,
713 .SourceElementFormat
= upload_format
,
714 .SourceElementOffset
= offset
,
715 .Component0Control
= comp0
,
716 .Component1Control
= comp1
,
717 .Component2Control
= comp2
,
718 .Component3Control
= comp3
,
720 .DestinationElementOffset
= i
* 4,
724 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
725 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
729 if (needs_sgvs_element
) {
730 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
732 .Component0Control
= VFCOMP_STORE_0
,
733 .Component1Control
= VFCOMP_STORE_0
,
734 .Component2Control
= VFCOMP_STORE_0
,
735 .Component3Control
= VFCOMP_STORE_0
,
737 .DestinationElementOffset
= i
* 4,
742 if (vs_prog_data
->uses_basevertex
||
743 vs_prog_data
->uses_baseinstance
) {
744 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
745 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
746 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
747 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
750 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
751 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
752 if (vs_prog_data
->uses_basevertex
)
753 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
755 if (vs_prog_data
->uses_baseinstance
)
756 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
758 if (vs_prog_data
->uses_vertexid
)
759 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
761 if (vs_prog_data
->uses_instanceid
)
762 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
765 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
766 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
769 if (vs_prog_data
->uses_drawid
) {
770 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
772 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
773 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
774 .Component0Control
= VFCOMP_STORE_SRC
,
775 .Component1Control
= VFCOMP_STORE_0
,
776 .Component2Control
= VFCOMP_STORE_0
,
777 .Component3Control
= VFCOMP_STORE_0
,
779 .DestinationElementOffset
= i
* 4,
783 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
784 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
788 if (gen6_edgeflag_input
) {
790 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
792 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
794 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
795 .EdgeFlagEnable
= true,
796 .SourceElementFormat
= format
,
797 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
798 .Component0Control
= VFCOMP_STORE_SRC
,
799 .Component1Control
= VFCOMP_STORE_0
,
800 .Component2Control
= VFCOMP_STORE_0
,
801 .Component3Control
= VFCOMP_STORE_0
,
804 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
805 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
810 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
811 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
812 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
813 unsigned element_index
;
815 /* The edge flag element is reordered to be the last one in the code
816 * above so we need to compensate for that in the element indices used
819 if (input
== gen6_edgeflag_input
)
820 element_index
= nr_elements
- 1;
824 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
825 vfi
.VertexElementIndex
= element_index
;
826 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
827 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
831 if (vs_prog_data
->uses_drawid
) {
832 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
834 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
835 vfi
.VertexElementIndex
= element
;
841 static const struct brw_tracked_state
genX(vertices
) = {
843 .mesa
= _NEW_POLYGON
,
844 .brw
= BRW_NEW_BATCH
|
847 BRW_NEW_VS_PROG_DATA
,
849 .emit
= genX(emit_vertices
),
852 #if GEN_IS_HASWELL || GEN_GEN >= 8
854 genX(upload_cut_index
)(struct brw_context
*brw
)
856 const struct gl_context
*ctx
= &brw
->ctx
;
858 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
859 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
860 vf
.IndexedDrawCutIndexEnable
= true;
861 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
866 const struct brw_tracked_state
genX(cut_index
) = {
868 .mesa
= _NEW_TRANSFORM
,
869 .brw
= BRW_NEW_INDEX_BUFFER
,
871 .emit
= genX(upload_cut_index
),
877 * Determine the appropriate attribute override value to store into the
878 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
879 * override value contains two pieces of information: the location of the
880 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
881 * flag indicating whether to "swizzle" the attribute based on the direction
882 * the triangle is facing.
884 * If an attribute is "swizzled", then the given VUE location is used for
885 * front-facing triangles, and the VUE location that immediately follows is
886 * used for back-facing triangles. We use this to implement the mapping from
887 * gl_FrontColor/gl_BackColor to gl_Color.
889 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
890 * being instructed to begin reading attribute data. It can be set to a
891 * nonzero value to prevent the SF unit from wasting time reading elements of
892 * the VUE that are not needed by the fragment shader. It is measured in
893 * 256-bit increments.
896 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
897 const struct brw_vue_map
*vue_map
,
898 int urb_entry_read_offset
, int fs_attr
,
899 bool two_side_color
, uint32_t *max_source_attr
)
901 /* Find the VUE slot for this attribute. */
902 int slot
= vue_map
->varying_to_slot
[fs_attr
];
904 /* Viewport and Layer are stored in the VUE header. We need to override
905 * them to zero if earlier stages didn't write them, as GL requires that
906 * they read back as zero when not explicitly set.
908 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
909 attr
->ComponentOverrideX
= true;
910 attr
->ComponentOverrideW
= true;
911 attr
->ConstantSource
= CONST_0000
;
913 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
914 attr
->ComponentOverrideY
= true;
915 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
916 attr
->ComponentOverrideZ
= true;
921 /* If there was only a back color written but not front, use back
922 * as the color instead of undefined
924 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
925 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
926 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
927 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
930 /* This attribute does not exist in the VUE--that means that the vertex
931 * shader did not write to it. This means that either:
933 * (a) This attribute is a texture coordinate, and it is going to be
934 * replaced with point coordinates (as a consequence of a call to
935 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
936 * hardware will ignore whatever attribute override we supply.
938 * (b) This attribute is read by the fragment shader but not written by
939 * the vertex shader, so its value is undefined. Therefore the
940 * attribute override we supply doesn't matter.
942 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
943 * previous shader stage.
945 * Note that we don't have to worry about the cases where the attribute
946 * is gl_PointCoord or is undergoing point sprite coordinate
947 * replacement, because in those cases, this function isn't called.
949 * In case (c), we need to program the attribute overrides so that the
950 * primitive ID will be stored in this slot. In every other case, the
951 * attribute override we supply doesn't matter. So just go ahead and
952 * program primitive ID in every case.
954 attr
->ComponentOverrideW
= true;
955 attr
->ComponentOverrideX
= true;
956 attr
->ComponentOverrideY
= true;
957 attr
->ComponentOverrideZ
= true;
958 attr
->ConstantSource
= PRIM_ID
;
962 /* Compute the location of the attribute relative to urb_entry_read_offset.
963 * Each increment of urb_entry_read_offset represents a 256-bit value, so
964 * it counts for two 128-bit VUE slots.
966 int source_attr
= slot
- 2 * urb_entry_read_offset
;
967 assert(source_attr
>= 0 && source_attr
< 32);
969 /* If we are doing two-sided color, and the VUE slot following this one
970 * represents a back-facing color, then we need to instruct the SF unit to
971 * do back-facing swizzling.
973 bool swizzling
= two_side_color
&&
974 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
975 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
976 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
977 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
979 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
980 if (*max_source_attr
< source_attr
+ swizzling
)
981 *max_source_attr
= source_attr
+ swizzling
;
983 attr
->SourceAttribute
= source_attr
;
985 attr
->SwizzleSelect
= INPUTATTR_FACING
;
990 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
991 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
992 uint32_t *point_sprite_enables
,
993 uint32_t *urb_entry_read_length
,
994 uint32_t *urb_entry_read_offset
)
996 const struct gl_context
*ctx
= &brw
->ctx
;
999 const struct gl_point_attrib
*point
= &ctx
->Point
;
1001 /* BRW_NEW_FS_PROG_DATA */
1002 const struct brw_wm_prog_data
*wm_prog_data
=
1003 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1004 uint32_t max_source_attr
= 0;
1006 *point_sprite_enables
= 0;
1008 /* BRW_NEW_FRAGMENT_PROGRAM
1010 * If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
1011 * the full vertex header. Otherwise, we can program the SF to start
1012 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
1013 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1014 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
1017 bool fs_needs_vue_header
= brw
->fragment_program
->info
.inputs_read
&
1018 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1020 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
1022 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1023 * description of dw10 Point Sprite Texture Coordinate Enable:
1025 * "This field must be programmed to zero when non-point primitives
1028 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1029 * must be programmed to zero when rendering non-point primitives, but
1030 * the IvyBridge PRM does, and if we don't, we get garbage.
1032 * This is not required on Haswell, as the hardware ignores this state
1033 * when drawing non-points -- although we do still need to be careful to
1034 * correctly set the attr overrides.
1037 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1039 bool drawing_points
= brw_is_drawing_points(brw
);
1041 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1042 int input_index
= wm_prog_data
->urb_setup
[attr
];
1044 if (input_index
< 0)
1048 bool point_sprite
= false;
1049 if (drawing_points
) {
1050 if (point
->PointSprite
&&
1051 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1052 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1053 point_sprite
= true;
1056 if (attr
== VARYING_SLOT_PNTC
)
1057 point_sprite
= true;
1060 *point_sprite_enables
|= (1 << input_index
);
1063 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1064 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1066 if (!point_sprite
) {
1067 genX(get_attr_override
)(&attribute
,
1068 &brw
->vue_map_geom_out
,
1069 *urb_entry_read_offset
, attr
,
1070 brw
->ctx
.VertexProgram
._TwoSideEnabled
,
1074 /* The hardware can only do the overrides on 16 overrides at a
1075 * time, and the other up to 16 have to be lined up so that the
1076 * input index = the output index. We'll need to do some
1077 * tweaking to make sure that's the case.
1079 if (input_index
< 16)
1080 attr_overrides
[input_index
] = attribute
;
1082 assert(attribute
.SourceAttribute
== input_index
);
1085 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1086 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1088 * "This field should be set to the minimum length required to read the
1089 * maximum source attribute. The maximum source attribute is indicated
1090 * by the maximum value of the enabled Attribute # Source Attribute if
1091 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1092 * enable is not set.
1093 * read_length = ceiling((max_source_attr + 1) / 2)
1095 * [errata] Corruption/Hang possible if length programmed larger than
1098 * Similar text exists for Ivy Bridge.
1100 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1104 /* ---------------------------------------------------------------------- */
1108 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1110 struct gl_context
*ctx
= &brw
->ctx
;
1113 struct intel_renderbuffer
*depth_irb
=
1114 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1117 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1120 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1121 const int b
= stencil
->_BackFace
;
1124 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1127 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, wmds
) {
1129 if (depth
->Test
&& depth_irb
) {
1130 wmds
.DepthTestEnable
= true;
1131 wmds
.DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1132 wmds
.DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1135 if (stencil
->_Enabled
) {
1136 wmds
.StencilTestEnable
= true;
1137 wmds
.StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1138 wmds
.StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1140 wmds
.StencilTestFunction
=
1141 intel_translate_compare_func(stencil
->Function
[0]);
1142 wmds
.StencilFailOp
=
1143 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1144 wmds
.StencilPassDepthPassOp
=
1145 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1146 wmds
.StencilPassDepthFailOp
=
1147 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1149 wmds
.StencilBufferWriteEnable
= stencil
->_WriteEnabled
;
1151 if (stencil
->_TestTwoSide
) {
1152 wmds
.DoubleSidedStencilEnable
= true;
1153 wmds
.BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1154 wmds
.BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1156 wmds
.BackfaceStencilTestFunction
=
1157 intel_translate_compare_func(stencil
->Function
[b
]);
1158 wmds
.BackfaceStencilFailOp
=
1159 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1160 wmds
.BackfaceStencilPassDepthPassOp
=
1161 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1162 wmds
.BackfaceStencilPassDepthFailOp
=
1163 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1167 wmds
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1168 wmds
.BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1174 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1175 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1176 ptr
.DEPTH_STENCIL_STATEChange
= true;
1179 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1180 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1185 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1187 .mesa
= _NEW_BUFFERS
|
1190 .brw
= BRW_NEW_BLORP
|
1191 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1193 BRW_NEW_STATE_BASE_ADDRESS
),
1195 .emit
= genX(upload_depth_stencil_state
),
1199 /* ---------------------------------------------------------------------- */
1203 genX(upload_clip_state
)(struct brw_context
*brw
)
1205 struct gl_context
*ctx
= &brw
->ctx
;
1208 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1210 /* BRW_NEW_FS_PROG_DATA */
1211 struct brw_wm_prog_data
*wm_prog_data
=
1212 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1214 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1215 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1217 if (wm_prog_data
->barycentric_interp_modes
&
1218 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1219 clip
.NonPerspectiveBarycentricEnable
= true;
1222 clip
.EarlyCullEnable
= true;
1226 clip
.FrontWinding
= ctx
->Polygon
._FrontBit
== _mesa_is_user_fbo(fb
);
1228 if (ctx
->Polygon
.CullFlag
) {
1229 switch (ctx
->Polygon
.CullFaceMode
) {
1231 clip
.CullMode
= CULLMODE_FRONT
;
1234 clip
.CullMode
= CULLMODE_BACK
;
1236 case GL_FRONT_AND_BACK
:
1237 clip
.CullMode
= CULLMODE_BOTH
;
1240 unreachable("Should not get here: invalid CullFlag");
1243 clip
.CullMode
= CULLMODE_NONE
;
1248 clip
.UserClipDistanceCullTestEnableBitmask
=
1249 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1251 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1255 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1256 clip
.TriangleStripListProvokingVertexSelect
= 0;
1257 clip
.TriangleFanProvokingVertexSelect
= 1;
1258 clip
.LineStripListProvokingVertexSelect
= 0;
1260 clip
.TriangleStripListProvokingVertexSelect
= 2;
1261 clip
.TriangleFanProvokingVertexSelect
= 2;
1262 clip
.LineStripListProvokingVertexSelect
= 1;
1265 /* _NEW_TRANSFORM */
1266 clip
.UserClipDistanceClipTestEnableBitmask
=
1267 ctx
->Transform
.ClipPlanesEnabled
;
1270 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1273 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1274 clip
.APIMode
= APIMODE_D3D
;
1276 clip
.APIMode
= APIMODE_OGL
;
1278 clip
.GuardbandClipTestEnable
= true;
1280 /* BRW_NEW_VIEWPORT_COUNT */
1281 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1283 if (ctx
->RasterDiscard
) {
1284 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1286 perf_debug("Rasterizer discard is currently implemented via the "
1287 "clipper; having the GS not write primitives would "
1288 "likely be faster.\n");
1291 clip
.ClipMode
= CLIPMODE_NORMAL
;
1294 clip
.ClipEnable
= brw
->primitive
!= _3DPRIM_RECTLIST
;
1297 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1299 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1300 clip
.ViewportXYClipTestEnable
= true;
1302 clip
.MinimumPointWidth
= 0.125;
1303 clip
.MaximumPointWidth
= 255.875;
1304 clip
.MaximumVPIndex
= viewport_count
- 1;
1305 if (_mesa_geometric_layers(fb
) == 0)
1306 clip
.ForceZeroRTAIndexEnable
= true;
1310 static const struct brw_tracked_state
genX(clip_state
) = {
1312 .mesa
= _NEW_BUFFERS
|
1316 .brw
= BRW_NEW_BLORP
|
1318 BRW_NEW_FS_PROG_DATA
|
1319 BRW_NEW_GS_PROG_DATA
|
1320 BRW_NEW_VS_PROG_DATA
|
1321 BRW_NEW_META_IN_PROGRESS
|
1323 BRW_NEW_RASTERIZER_DISCARD
|
1324 BRW_NEW_TES_PROG_DATA
|
1325 BRW_NEW_VIEWPORT_COUNT
,
1327 .emit
= genX(upload_clip_state
),
1331 /* ---------------------------------------------------------------------- */
1335 genX(upload_sf
)(struct brw_context
*brw
)
1337 struct gl_context
*ctx
= &brw
->ctx
;
1342 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1343 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1346 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1347 sf
.StatisticsEnable
= true;
1348 sf
.ViewportTransformEnable
= true;
1352 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1357 sf
.FrontWinding
= ctx
->Polygon
._FrontBit
== render_to_fbo
;
1358 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1359 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1360 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1362 switch (ctx
->Polygon
.FrontMode
) {
1364 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1367 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1370 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1373 unreachable("not reached");
1376 switch (ctx
->Polygon
.BackMode
) {
1378 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1381 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1384 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1387 unreachable("not reached");
1390 sf
.ScissorRectangleEnable
= true;
1392 if (ctx
->Polygon
.CullFlag
) {
1393 switch (ctx
->Polygon
.CullFaceMode
) {
1395 sf
.CullMode
= CULLMODE_FRONT
;
1398 sf
.CullMode
= CULLMODE_BACK
;
1400 case GL_FRONT_AND_BACK
:
1401 sf
.CullMode
= CULLMODE_BOTH
;
1404 unreachable("not reached");
1407 sf
.CullMode
= CULLMODE_NONE
;
1411 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1414 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1415 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1417 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1418 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1419 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1424 if (brw
->is_cherryview
)
1425 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1427 sf
.LineWidth
= brw_get_line_width(brw
);
1429 sf
.LineWidth
= brw_get_line_width(brw
);
1432 if (ctx
->Line
.SmoothFlag
) {
1433 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1435 sf
.AntiAliasingEnable
= true;
1439 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1440 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1441 /* Clamp to the hardware limits */
1442 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1444 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1445 if (use_state_point_size(brw
))
1446 sf
.PointWidthSource
= State
;
1449 /* _NEW_POINT | _NEW_MULTISAMPLE */
1450 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1451 !ctx
->Point
.PointSprite
)
1452 sf
.SmoothPointEnable
= true;
1455 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1458 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1459 sf
.TriangleStripListProvokingVertexSelect
= 2;
1460 sf
.TriangleFanProvokingVertexSelect
= 2;
1461 sf
.LineStripListProvokingVertexSelect
= 1;
1463 sf
.TriangleFanProvokingVertexSelect
= 1;
1467 /* BRW_NEW_FS_PROG_DATA */
1468 const struct brw_wm_prog_data
*wm_prog_data
=
1469 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1471 sf
.AttributeSwizzleEnable
= true;
1472 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1475 * Window coordinates in an FBO are inverted, which means point
1476 * sprite origin must be inverted, too.
1478 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1479 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1481 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1484 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1485 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1487 uint32_t urb_entry_read_length
;
1488 uint32_t urb_entry_read_offset
;
1489 uint32_t point_sprite_enables
;
1490 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1491 &urb_entry_read_length
,
1492 &urb_entry_read_offset
);
1493 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1494 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1495 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1496 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1501 static const struct brw_tracked_state
genX(sf_state
) = {
1503 .mesa
= _NEW_LIGHT
|
1508 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1509 .brw
= BRW_NEW_BLORP
|
1511 BRW_NEW_VUE_MAP_GEOM_OUT
|
1512 (GEN_GEN
<= 7 ? BRW_NEW_GS_PROG_DATA
|
1514 BRW_NEW_TES_PROG_DATA
1516 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1517 BRW_NEW_FRAGMENT_PROGRAM
1520 .emit
= genX(upload_sf
),
1524 /* ---------------------------------------------------------------------- */
1528 genX(upload_wm
)(struct brw_context
*brw
)
1530 struct gl_context
*ctx
= &brw
->ctx
;
1532 /* BRW_NEW_FS_PROG_DATA */
1533 const struct brw_wm_prog_data
*wm_prog_data
=
1534 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1536 UNUSED
bool writes_depth
=
1537 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1540 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1541 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1543 /* We can't fold this into gen6_upload_wm_push_constants(), because
1544 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1545 * (3DSTATE_CONSTANT_PS [DevSNB]):
1547 * "[DevSNB]: This packet must be followed by WM_STATE."
1549 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1550 if (wm_prog_data
->base
.nr_params
!= 0) {
1551 wmcp
.Buffer0Valid
= true;
1552 /* Pointer to the WM constant buffer. Covered by the set of
1553 * state flags from gen6_upload_wm_push_constants.
1555 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1556 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1561 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1562 wm
.StatisticsEnable
= true;
1563 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1564 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1567 if (wm_prog_data
->base
.use_alt_mode
)
1568 wm
.FloatingPointMode
= Alternate
;
1570 wm
.SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1571 wm
.BindingTableEntryCount
= wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1572 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1573 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1574 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1575 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1576 wm_prog_data
->base
.dispatch_grf_start_reg
;
1577 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1578 wm_prog_data
->dispatch_grf_start_reg_2
;
1579 wm
.KernelStartPointer0
= stage_state
->prog_offset
;
1580 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1581 wm_prog_data
->prog_offset_2
;
1582 wm
.DualSourceBlendEnable
=
1583 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1584 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1585 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1586 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1588 /* From the SNB PRM, volume 2 part 1, page 281:
1589 * "If the PS kernel does not need the Position XY Offsets
1590 * to compute a Position XY value, then this field should be
1591 * programmed to POSOFFSET_NONE."
1593 * "SW Recommendation: If the PS kernel needs the Position Offsets
1594 * to compute a Position XY value, this field should match Position
1595 * ZW Interpolation Mode to ensure a consistent position.xyzw
1597 * We only require XY sample offsets. So, this recommendation doesn't
1598 * look useful at the moment. We might need this in future.
1600 if (wm_prog_data
->uses_pos_offset
)
1601 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1603 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1605 if (wm_prog_data
->base
.total_scratch
) {
1606 wm
.ScratchSpaceBasePointer
=
1607 render_bo(stage_state
->scratch_bo
,
1608 ffs(stage_state
->per_thread_scratch
) - 11);
1611 wm
.PixelShaderComputedDepth
= writes_depth
;
1614 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1617 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1620 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1621 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1625 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1627 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1628 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1629 if (wm_prog_data
->uses_kill
||
1630 _mesa_is_alpha_test_enabled(ctx
) ||
1631 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1632 wm_prog_data
->uses_omask
) {
1633 wm
.PixelShaderKillsPixel
= true;
1636 /* _NEW_BUFFERS | _NEW_COLOR */
1637 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1638 wm_prog_data
->has_side_effects
|| wm
.PixelShaderKillsPixel
) {
1639 wm
.ThreadDispatchEnable
= true;
1641 if (multisampled_fbo
) {
1642 /* _NEW_MULTISAMPLE */
1643 if (ctx
->Multisample
.Enabled
)
1644 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1646 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1648 if (wm_prog_data
->persample_dispatch
)
1649 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1651 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1653 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1654 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1658 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1659 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1662 /* The "UAV access enable" bits are unnecessary on HSW because they only
1663 * seem to have an effect on the HW-assisted coherency mechanism which we
1664 * don't need, and the rasterization-related UAV_ONLY flag and the
1665 * DISPATCH_ENABLE bit can be set independently from it.
1666 * C.f. gen8_upload_ps_extra().
1668 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1672 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1673 wm_prog_data
->has_side_effects
)
1679 /* BRW_NEW_FS_PROG_DATA */
1680 if (wm_prog_data
->early_fragment_tests
)
1681 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1682 else if (wm_prog_data
->has_side_effects
)
1683 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1688 static const struct brw_tracked_state
genX(wm_state
) = {
1692 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1696 (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
1697 .brw
= BRW_NEW_BLORP
|
1698 BRW_NEW_FS_PROG_DATA
|
1699 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
1701 .emit
= genX(upload_wm
),
1705 /* ---------------------------------------------------------------------- */
1708 static inline struct brw_address
1709 KSP(struct brw_context
*brw
, uint32_t offset
)
1711 return instruction_bo(brw
->cache
.bo
, offset
);
1714 static inline uint32_t
1715 KSP(struct brw_context
*brw
, uint32_t offset
)
1721 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1722 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
1723 pkt.SamplerCount = \
1724 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1725 pkt.BindingTableEntryCount = \
1726 stage_prog_data->binding_table.size_bytes / 4; \
1727 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
1729 if (stage_prog_data->total_scratch) { \
1730 pkt.ScratchSpaceBasePointer = \
1731 render_bo(stage_state->scratch_bo, 0); \
1732 pkt.PerThreadScratchSpace = \
1733 ffs(stage_state->per_thread_scratch) - 11; \
1736 pkt.DispatchGRFStartRegisterForURBData = \
1737 stage_prog_data->dispatch_grf_start_reg; \
1738 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1739 pkt.prefix##URBEntryReadOffset = 0; \
1741 pkt.StatisticsEnable = true; \
1745 genX(upload_vs_state
)(struct brw_context
*brw
)
1747 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
1748 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1749 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
1751 /* BRW_NEW_VS_PROG_DATA */
1752 const struct brw_vue_prog_data
*vue_prog_data
=
1753 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
1754 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
1756 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
1757 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
1760 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1761 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1763 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
1764 * command that causes the VS Function Enable to toggle. Pipeline
1765 * flush can be executed by sending a PIPE_CONTROL command with CS
1766 * stall bit set and a post sync operation.
1768 * We've already done such a flush at the start of state upload, so we
1769 * don't need to do another one here.
1771 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
1772 if (stage_state
->push_const_size
!= 0) {
1773 cvs
.Buffer0Valid
= true;
1774 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
1775 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1780 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
1781 gen7_emit_vs_workaround_flush(brw
);
1784 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
1786 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1787 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
1789 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1791 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1794 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
1795 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
1796 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
1798 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
1799 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1801 vs
.MaximumNumberofThreads
=
1802 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
1804 vs
.StatisticsEnable
= false;
1805 vs
.SamplerStateOffset
=
1806 instruction_ro_bo(brw
->batch
.bo
, stage_state
->sampler_offset
);
1810 /* Force single program flow on Ironlake. We cannot reliably get
1811 * all applications working without it. See:
1812 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
1814 * The most notable and reliably failing application is the Humus
1817 vs
.SingleProgramFlow
= true;
1818 vs
.SamplerCount
= 0; /* hardware requirement */
1822 vs
.SIMD8DispatchEnable
=
1823 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
1825 vs
.UserClipDistanceCullTestEnableBitmask
=
1826 vue_prog_data
->cull_distance_mask
;
1831 /* Based on my reading of the simulator, the VS constants don't get
1832 * pulled into the VS FF unit until an appropriate pipeline flush
1833 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
1834 * references to them into a little FIFO. The flushes are common,
1835 * but don't reliably happen between this and a 3DPRIMITIVE, causing
1836 * the primitive to use the wrong constants. Then the FIFO
1837 * containing the constant setup gets added to again on the next
1838 * constants change, and eventually when a flush does happen the
1839 * unit is overwhelmed by constant changes and dies.
1841 * To avoid this, send a PIPE_CONTROL down the line that will
1842 * update the unit immediately loading the constants. The flush
1843 * type bits here were those set by the STATE_BASE_ADDRESS whose
1844 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
1845 * bug reports that led to this workaround, and may be more than
1846 * what is strictly required to avoid the issue.
1848 brw_emit_pipe_control_flush(brw
,
1849 PIPE_CONTROL_DEPTH_STALL
|
1850 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1851 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
1855 static const struct brw_tracked_state
genX(vs_state
) = {
1857 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
1858 .brw
= BRW_NEW_BATCH
|
1861 BRW_NEW_VS_PROG_DATA
|
1862 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
1863 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1864 BRW_NEW_PROGRAM_CACHE
|
1865 BRW_NEW_SAMPLER_STATE_TABLE
|
1869 .emit
= genX(upload_vs_state
),
1872 /* ---------------------------------------------------------------------- */
1876 brw_calculate_guardband_size(const struct gen_device_info
*devinfo
,
1877 uint32_t fb_width
, uint32_t fb_height
,
1878 float m00
, float m11
, float m30
, float m31
,
1879 float *xmin
, float *xmax
,
1880 float *ymin
, float *ymax
)
1882 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1883 * Strips and Fans documentation:
1885 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1886 * fixed-point "guardband" range supported by the rasterization hardware"
1890 * "In almost all circumstances, if an object’s vertices are actually
1891 * modified by this clamping (i.e., had X or Y coordinates outside of
1892 * the guardband extent the rendered object will not match the intended
1893 * result. Therefore software should take steps to ensure that this does
1894 * not happen - e.g., by clipping objects such that they do not exceed
1895 * these limits after the Drawing Rectangle is applied."
1897 * I believe the fundamental restriction is that the rasterizer (in
1898 * the SF/WM stages) have a limit on the number of pixels that can be
1899 * rasterized. We need to ensure any coordinates beyond the rasterizer
1900 * limit are handled by the clipper. So effectively that limit becomes
1901 * the clipper's guardband size.
1903 * It goes on to say:
1905 * "In addition, in order to be correctly rendered, objects must have a
1906 * screenspace bounding box not exceeding 8K in the X or Y direction.
1907 * This additional restriction must also be comprehended by software,
1908 * i.e., enforced by use of clipping."
1910 * This makes no sense. Gen7+ hardware supports 16K render targets,
1911 * and you definitely need to be able to draw polygons that fill the
1912 * surface. Our assumption is that the rasterizer was limited to 8K
1913 * on Sandybridge, which only supports 8K surfaces, and it was actually
1914 * increased to 16K on Ivybridge and later.
1916 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1918 const float gb_size
= devinfo
->gen
>= 7 ? 16384.0f
: 8192.0f
;
1920 if (m00
!= 0 && m11
!= 0) {
1921 /* First, we compute the screen-space render area */
1922 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1923 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1924 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1925 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1927 /* We want the guardband to be centered on that */
1928 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1929 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1930 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1931 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1933 /* Now we need it in native device coordinates */
1934 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1935 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1936 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1937 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1939 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1940 * flipped upside-down. X should be fine though.
1942 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1943 *xmin
= ndc_gb_xmin
;
1944 *xmax
= ndc_gb_xmax
;
1945 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1946 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1948 /* The viewport scales to 0, so nothing will be rendered. */
1957 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
1959 struct gl_context
*ctx
= &brw
->ctx
;
1960 float y_scale
, y_bias
;
1961 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1963 /* BRW_NEW_VIEWPORT_COUNT */
1964 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1967 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1968 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
1969 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
1973 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
1974 uint32_t sf_clip_vp_offset
;
1975 uint32_t *sf_clip_map
= brw_state_batch(brw
, 16 * 4 * viewport_count
,
1976 64, &sf_clip_vp_offset
);
1978 struct GENX(SF_VIEWPORT
) sfv
;
1979 struct GENX(CLIP_VIEWPORT
) clv
;
1980 uint32_t *sf_map
= brw_state_batch(brw
, 8 * 4 * viewport_count
,
1981 32, &brw
->sf
.vp_offset
);
1982 uint32_t *clip_map
= brw_state_batch(brw
, 4 * 4 * viewport_count
,
1983 32, &brw
->clip
.vp_offset
);
1987 if (render_to_fbo
) {
1992 y_bias
= (float)fb_height
;
1995 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
1996 /* _NEW_VIEWPORT: Guardband Clipping */
1997 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
1998 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2000 sfv
.ViewportMatrixElementm00
= scale
[0];
2001 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2002 sfv
.ViewportMatrixElementm22
= scale
[2],
2003 sfv
.ViewportMatrixElementm30
= translate
[0],
2004 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2005 sfv
.ViewportMatrixElementm32
= translate
[2],
2006 brw_calculate_guardband_size(devinfo
, fb_width
, fb_height
,
2007 sfv
.ViewportMatrixElementm00
,
2008 sfv
.ViewportMatrixElementm11
,
2009 sfv
.ViewportMatrixElementm30
,
2010 sfv
.ViewportMatrixElementm31
,
2011 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2014 clv
.XMinClipGuardband
= gb_xmin
;
2015 clv
.XMaxClipGuardband
= gb_xmax
;
2016 clv
.YMinClipGuardband
= gb_ymin
;
2017 clv
.YMaxClipGuardband
= gb_ymax
;
2020 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2021 * The hardware will take the intersection of the drawing rectangle,
2022 * scissor rectangle, and the viewport extents. We don't need to be
2023 * smart, and can therefore just program the viewport extents.
2025 const float viewport_Xmax
=
2026 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2027 const float viewport_Ymax
=
2028 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2030 if (render_to_fbo
) {
2031 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2032 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2033 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2034 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2036 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2037 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2038 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2039 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2044 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2047 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2048 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2055 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2056 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2059 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2063 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2065 .mesa
= _NEW_BUFFERS
|
2067 .brw
= BRW_NEW_BATCH
|
2069 BRW_NEW_VIEWPORT_COUNT
,
2071 .emit
= genX(upload_sf_clip_viewport
),
2075 /* ---------------------------------------------------------------------- */
2079 genX(upload_gs_state
)(struct brw_context
*brw
)
2081 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2082 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2083 /* BRW_NEW_GEOMETRY_PROGRAM */
2084 bool active
= brw
->geometry_program
;
2086 /* BRW_NEW_GS_PROG_DATA */
2087 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2088 const struct brw_vue_prog_data
*vue_prog_data
=
2089 brw_vue_prog_data(stage_prog_data
);
2091 const struct brw_gs_prog_data
*gs_prog_data
=
2092 brw_gs_prog_data(stage_prog_data
);
2096 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2097 if (active
&& stage_state
->push_const_size
!= 0) {
2098 cgs
.Buffer0Valid
= true;
2099 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2100 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2105 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2107 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2108 * Geometry > Geometry Shader > State:
2110 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2111 * whole fixed function pipeline when the GS enable changes value in
2114 * The hardware architects have clarified that in this context "flush the
2115 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2118 if (brw
->gt
== 2 && brw
->gs
.enabled
!= active
)
2119 gen7_emit_cs_stall_flush(brw
);
2123 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2124 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2127 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2128 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2129 gs
.ControlDataHeaderSize
=
2130 gs_prog_data
->control_data_header_size_hwords
;
2132 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2133 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2135 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2137 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2140 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2141 * Ivy Bridge and Haswell.
2143 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2144 * strip to be delivered to the geometry shader in an order that does
2145 * not strictly follow the OpenGL spec, but preserves triangle
2146 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2147 * the geometry shader sees triangles:
2149 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2151 * (Clearing the bit is even worse, because it fails to preserve
2154 * Triangle strips with adjacency always ordered in a way that preserves
2155 * triangle orientation but does not strictly follow the OpenGL spec,
2156 * regardless of the setting of this bit.
2158 * On Haswell, both triangle strips and triangle strips with adjacency
2159 * are always ordered in a way that preserves triangle orientation.
2160 * Setting this bit causes the ordering to strictly follow the OpenGL
2163 * So in either case we want to set the bit. Unfortunately on Ivy
2164 * Bridge this will get the order close to correct but not perfect.
2166 gs
.ReorderMode
= TRAILING
;
2167 gs
.MaximumNumberofThreads
=
2168 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2169 : (devinfo
->max_gs_threads
- 1);
2172 gs
.SOStatisticsEnable
= true;
2173 gs
.RenderingEnabled
= 1;
2174 if (brw
->geometry_program
->info
.has_transform_feedback_varyings
)
2175 gs
.SVBIPayloadEnable
= true;
2177 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2178 * was previously done for gen6.
2180 * TODO: test with both disabled to see if the HW is behaving
2181 * as expected, like in gen7.
2183 gs
.SingleProgramFlow
= true;
2184 gs
.VectorMaskEnable
= true;
2188 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2190 if (gs_prog_data
->static_vertex_count
!= -1) {
2191 gs
.StaticOutput
= true;
2192 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2194 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2196 gs
.UserClipDistanceCullTestEnableBitmask
=
2197 vue_prog_data
->cull_distance_mask
;
2199 const int urb_entry_write_offset
= 1;
2200 const uint32_t urb_entry_output_length
=
2201 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2202 urb_entry_write_offset
;
2204 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2205 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2209 } else if (brw
->ff_gs
.prog_active
) {
2210 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
2211 * program. This function provides the needed 3DSTATE_GS for this.
2213 upload_gs_state_for_tf(brw
);
2216 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2217 gs
.StatisticsEnable
= true;
2219 gs
.RenderingEnabled
= true;
2223 gs
.DispatchGRFStartRegisterForURBData
= 1;
2225 gs
.IncludeVertexHandles
= true;
2231 brw
->gs
.enabled
= active
;
2235 static const struct brw_tracked_state
genX(gs_state
) = {
2237 .mesa
= (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
2238 .brw
= BRW_NEW_BATCH
|
2241 BRW_NEW_GEOMETRY_PROGRAM
|
2242 BRW_NEW_GS_PROG_DATA
|
2243 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2245 .emit
= genX(upload_gs_state
),
2249 /* ---------------------------------------------------------------------- */
2251 #define blend_factor(x) brw_translate_blend_factor(x)
2252 #define blend_eqn(x) brw_translate_blend_equation(x)
2256 genX(upload_blend_state
)(struct brw_context
*brw
)
2258 struct gl_context
*ctx
= &brw
->ctx
;
2261 /* We need at least one BLEND_STATE written, because we might do
2262 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2263 * for computed depth or alpha test), which will do an FB write
2264 * with render target 0, which will reference BLEND_STATE[0] for
2265 * alpha test enable.
2267 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2268 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2269 nr_draw_buffers
= 1;
2271 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2273 size
+= GENX(BLEND_STATE_length
) * 4;
2276 uint32_t *blend_map
;
2277 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2280 struct GENX(BLEND_STATE
) blend
= { 0 };
2283 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2284 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2287 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2288 * "If drawbuffer zero is not NONE and the buffer it references has an
2289 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2290 * operations are skipped."
2292 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2293 /* _NEW_MULTISAMPLE */
2294 if (_mesa_is_multisample_enabled(ctx
)) {
2295 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2296 blend
.AlphaToCoverageEnable
= true;
2297 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2299 if (ctx
->Multisample
.SampleAlphaToOne
)
2300 blend
.AlphaToOneEnable
= true;
2304 if (ctx
->Color
.AlphaEnabled
) {
2305 blend
.AlphaTestEnable
= true;
2306 blend
.AlphaTestFunction
=
2307 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2310 if (ctx
->Color
.DitherFlag
) {
2311 blend
.ColorDitherEnable
= true;
2316 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2317 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2323 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2325 /* Used for implementing the following bit of GL_EXT_texture_integer:
2326 * "Per-fragment operations that require floating-point color
2327 * components, including multisample alpha operations, alpha test,
2328 * blending, and dithering, have no effect when the corresponding
2329 * colors are written to an integer color buffer."
2331 bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2334 if (ctx
->Color
.ColorLogicOpEnabled
) {
2335 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2336 : GL_UNSIGNED_NORMALIZED
;
2337 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2338 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2339 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2341 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2342 _mesa_enum_to_string(rb_type
));
2343 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2344 entry
.LogicOpEnable
= true;
2345 entry
.LogicOpFunction
=
2346 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2348 } else if (ctx
->Color
.BlendEnabled
& (1 << i
) && !integer
&&
2349 !ctx
->Color
._AdvancedBlendMode
) {
2350 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2351 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2352 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2353 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2354 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2355 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2357 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2358 srcRGB
= dstRGB
= GL_ONE
;
2360 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2361 srcA
= dstA
= GL_ONE
;
2363 /* Due to hardware limitations, the destination may have information
2364 * in an alpha channel even when the format specifies no alpha
2365 * channel. In order to avoid getting any incorrect blending due to
2366 * that alpha channel, coerce the blend factors to values that will
2367 * not read the alpha channel, but will instead use the correct
2368 * implicit value for alpha.
2370 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2371 GL_TEXTURE_ALPHA_TYPE
)) {
2372 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2373 srcA
= brw_fix_xRGB_alpha(srcA
);
2374 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2375 dstA
= brw_fix_xRGB_alpha(dstA
);
2378 entry
.ColorBufferBlendEnable
= true;
2379 entry
.DestinationBlendFactor
= blend_factor(dstRGB
);
2380 entry
.SourceBlendFactor
= blend_factor(srcRGB
);
2381 entry
.DestinationAlphaBlendFactor
= blend_factor(dstA
);
2382 entry
.SourceAlphaBlendFactor
= blend_factor(srcA
);
2383 entry
.ColorBlendFunction
= blend_eqn(eqRGB
);
2384 entry
.AlphaBlendFunction
= blend_eqn(eqA
);
2386 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2387 blend
.IndependentAlphaBlendEnable
= true;
2390 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2391 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2393 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2394 * clamping in the fragment shader. For its clamping of
2395 * blending, the spec says:
2397 * "RESOLVED: For fixed-point color buffers, the inputs and
2398 * the result of the blending equation are clamped. For
2399 * floating-point color buffers, no clamping occurs."
2401 * So, generally, we want clamping to the render target's range.
2402 * And, good news, the hardware tables for both pre- and
2403 * post-blend color clamping are either ignored, or any are
2404 * allowed, or clamping is required but RT range clamping is a
2407 entry
.PreBlendColorClampEnable
= true;
2408 entry
.PostBlendColorClampEnable
= true;
2409 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2411 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2412 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2413 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2414 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2416 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2417 * "If Dual Source Blending is enabled, this bit must be disabled."
2419 WARN_ONCE(ctx
->Color
.Blend
[i
]._UsesDualSrc
&&
2420 _mesa_is_multisample_enabled(ctx
) &&
2421 ctx
->Multisample
.SampleAlphaToOne
,
2422 "HW workaround: disabling alpha to one with dual src "
2424 if (ctx
->Color
.Blend
[i
]._UsesDualSrc
)
2425 blend
.AlphaToOneEnable
= false;
2427 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2429 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2435 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2439 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2440 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2441 ptr
.BLEND_STATEChange
= true;
2444 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2445 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2447 ptr
.BlendStatePointerValid
= true;
2453 static const struct brw_tracked_state
genX(blend_state
) = {
2455 .mesa
= _NEW_BUFFERS
|
2458 .brw
= BRW_NEW_BATCH
|
2460 BRW_NEW_STATE_BASE_ADDRESS
,
2462 .emit
= genX(upload_blend_state
),
2466 /* ---------------------------------------------------------------------- */
2470 genX(upload_scissor_state
)(struct brw_context
*brw
)
2472 struct gl_context
*ctx
= &brw
->ctx
;
2473 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2474 struct GENX(SCISSOR_RECT
) scissor
;
2475 uint32_t scissor_state_offset
;
2476 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2477 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2478 uint32_t *scissor_map
;
2480 /* BRW_NEW_VIEWPORT_COUNT */
2481 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2483 scissor_map
= brw_state_batch(
2484 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2485 32, &scissor_state_offset
);
2487 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2489 /* The scissor only needs to handle the intersection of drawable and
2490 * scissor rect. Clipping to the boundaries of static shared buffers
2491 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2493 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2494 * inclusive but max is exclusive.
2496 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2499 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2500 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2501 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2502 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2503 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2505 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2506 /* If the scissor was out of bounds and got clamped to 0 width/height
2507 * at the bounds, the subtraction of 1 from maximums could produce a
2508 * negative number and thus not clip anything. Instead, just provide
2509 * a min > max scissor inside the bounds, which produces the expected
2512 scissor
.ScissorRectangleXMin
= 1;
2513 scissor
.ScissorRectangleXMax
= 0;
2514 scissor
.ScissorRectangleYMin
= 1;
2515 scissor
.ScissorRectangleYMax
= 0;
2516 } else if (render_to_fbo
) {
2517 /* texmemory: Y=0=bottom */
2518 scissor
.ScissorRectangleXMin
= bbox
[0];
2519 scissor
.ScissorRectangleXMax
= bbox
[1] - 1;
2520 scissor
.ScissorRectangleYMin
= bbox
[2];
2521 scissor
.ScissorRectangleYMax
= bbox
[3] - 1;
2523 /* memory: Y=0=top */
2524 scissor
.ScissorRectangleXMin
= bbox
[0];
2525 scissor
.ScissorRectangleXMax
= bbox
[1] - 1;
2526 scissor
.ScissorRectangleYMin
= fb_height
- bbox
[3];
2527 scissor
.ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2530 GENX(SCISSOR_RECT_pack
)(
2531 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2534 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2535 ptr
.ScissorRectPointer
= scissor_state_offset
;
2539 static const struct brw_tracked_state
genX(scissor_state
) = {
2541 .mesa
= _NEW_BUFFERS
|
2544 .brw
= BRW_NEW_BATCH
|
2546 BRW_NEW_VIEWPORT_COUNT
,
2548 .emit
= genX(upload_scissor_state
),
2552 /* ---------------------------------------------------------------------- */
2555 UNUSED
static const uint32_t push_constant_opcodes
[] = {
2556 [MESA_SHADER_VERTEX
] = 21,
2557 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2558 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2559 [MESA_SHADER_GEOMETRY
] = 22,
2560 [MESA_SHADER_FRAGMENT
] = 23,
2561 [MESA_SHADER_COMPUTE
] = 0,
2565 upload_constant_state(struct brw_context
*brw
,
2566 struct brw_stage_state
*stage_state
,
2567 bool active
, uint32_t stage
)
2569 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
2570 active
= active
&& stage_state
->push_const_size
!= 0;
2572 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2573 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2576 pkt
.ConstantBody
.ConstantBuffer2ReadLength
=
2577 stage_state
->push_const_size
;
2578 pkt
.ConstantBody
.PointerToConstantBuffer2
=
2579 render_ro_bo(brw
->batch
.bo
, stage_state
->push_const_offset
);
2581 pkt
.ConstantBody
.ConstantBuffer0ReadLength
=
2582 stage_state
->push_const_size
;
2583 pkt
.ConstantBody
.PointerToConstantBuffer0
.offset
=
2584 stage_state
->push_const_offset
| mocs
;
2589 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
2595 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
2597 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2599 /* _BRW_NEW_VERTEX_PROGRAM */
2600 const struct brw_program
*vp
= brw_program_const(brw
->vertex_program
);
2601 /* BRW_NEW_VS_PROG_DATA */
2602 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
2604 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
2605 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
2608 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !brw
->is_baytrail
)
2609 gen7_emit_vs_workaround_flush(brw
);
2611 upload_constant_state(brw
, stage_state
, true /* active */,
2612 MESA_SHADER_VERTEX
);
2616 static const struct brw_tracked_state
genX(vs_push_constants
) = {
2618 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2620 .brw
= BRW_NEW_BATCH
|
2622 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2623 BRW_NEW_VERTEX_PROGRAM
|
2624 BRW_NEW_VS_PROG_DATA
,
2626 .emit
= genX(upload_vs_push_constants
),
2630 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
2632 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2634 /* BRW_NEW_GEOMETRY_PROGRAM */
2635 const struct brw_program
*gp
= brw_program_const(brw
->geometry_program
);
2638 /* BRW_NEW_GS_PROG_DATA */
2639 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
2641 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
2642 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
2646 upload_constant_state(brw
, stage_state
, gp
, MESA_SHADER_GEOMETRY
);
2650 static const struct brw_tracked_state
genX(gs_push_constants
) = {
2652 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2654 .brw
= BRW_NEW_BATCH
|
2656 BRW_NEW_GEOMETRY_PROGRAM
|
2657 BRW_NEW_GS_PROG_DATA
|
2658 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2660 .emit
= genX(upload_gs_push_constants
),
2664 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
2666 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
2667 /* BRW_NEW_FRAGMENT_PROGRAM */
2668 const struct brw_program
*fp
= brw_program_const(brw
->fragment_program
);
2669 /* BRW_NEW_FS_PROG_DATA */
2670 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
2672 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
2674 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
2677 upload_constant_state(brw
, stage_state
, true, MESA_SHADER_FRAGMENT
);
2681 static const struct brw_tracked_state
genX(wm_push_constants
) = {
2683 .mesa
= _NEW_PROGRAM_CONSTANTS
,
2684 .brw
= BRW_NEW_BATCH
|
2686 BRW_NEW_FRAGMENT_PROGRAM
|
2687 BRW_NEW_FS_PROG_DATA
|
2688 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2690 .emit
= genX(upload_wm_push_constants
),
2694 /* ---------------------------------------------------------------------- */
2698 genX(determine_sample_mask
)(struct brw_context
*brw
)
2700 struct gl_context
*ctx
= &brw
->ctx
;
2701 float coverage
= 1.0f
;
2702 float coverage_invert
= false;
2703 unsigned sample_mask
= ~0u;
2705 /* BRW_NEW_NUM_SAMPLES */
2706 unsigned num_samples
= brw
->num_samples
;
2708 if (_mesa_is_multisample_enabled(ctx
)) {
2709 if (ctx
->Multisample
.SampleCoverage
) {
2710 coverage
= ctx
->Multisample
.SampleCoverageValue
;
2711 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
2713 if (ctx
->Multisample
.SampleMask
) {
2714 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
2718 if (num_samples
> 1) {
2719 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
2720 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
2721 if (coverage_invert
)
2722 coverage_bits
^= (1 << num_samples
) - 1;
2723 return coverage_bits
& sample_mask
;
2730 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
2731 unsigned num_samples
)
2733 assert(brw
->num_samples
<= 16);
2735 unsigned log2_samples
= ffs(MAX2(num_samples
, 1)) - 1;
2737 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
2738 multi
.PixelLocation
= CENTER
;
2739 multi
.NumberofMultisamples
= log2_samples
;
2741 GEN_SAMPLE_POS_4X(multi
.Sample
);
2743 switch (num_samples
) {
2745 GEN_SAMPLE_POS_1X(multi
.Sample
);
2748 GEN_SAMPLE_POS_2X(multi
.Sample
);
2751 GEN_SAMPLE_POS_4X(multi
.Sample
);
2754 GEN_SAMPLE_POS_8X(multi
.Sample
);
2764 genX(upload_multisample_state
)(struct brw_context
*brw
)
2766 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
2768 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
2769 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
2773 static const struct brw_tracked_state
genX(multisample_state
) = {
2775 .mesa
= _NEW_MULTISAMPLE
,
2776 .brw
= BRW_NEW_BLORP
|
2778 BRW_NEW_NUM_SAMPLES
,
2780 .emit
= genX(upload_multisample_state
)
2784 /* ---------------------------------------------------------------------- */
2788 genX(upload_color_calc_state
)(struct brw_context
*brw
)
2790 struct gl_context
*ctx
= &brw
->ctx
;
2792 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
2794 cc
.AlphaTestFormat
= ALPHATEST_UNORM8
;
2795 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
2796 ctx
->Color
.AlphaRef
);
2800 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
2801 cc
.BackfaceStencilReferenceValue
=
2802 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
2806 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
2807 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
2808 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
2809 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
2812 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2813 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
2815 ptr
.ColorCalcStatePointerValid
= true;
2820 static const struct brw_tracked_state
genX(color_calc_state
) = {
2822 .mesa
= _NEW_COLOR
|
2824 .brw
= BRW_NEW_BATCH
|
2827 BRW_NEW_STATE_BASE_ADDRESS
,
2829 .emit
= genX(upload_color_calc_state
),
2834 /* ---------------------------------------------------------------------- */
2838 genX(upload_sbe
)(struct brw_context
*brw
)
2840 struct gl_context
*ctx
= &brw
->ctx
;
2841 /* BRW_NEW_FS_PROG_DATA */
2842 const struct brw_wm_prog_data
*wm_prog_data
=
2843 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
2845 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
2847 #define attr_overrides sbe.Attribute
2849 uint32_t urb_entry_read_length
;
2850 uint32_t urb_entry_read_offset
;
2851 uint32_t point_sprite_enables
;
2853 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
2854 sbe
.AttributeSwizzleEnable
= true;
2855 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2858 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2862 * Window coordinates in an FBO are inverted, which means point
2863 * sprite origin must be inverted.
2865 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
2866 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
2868 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
2870 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
2871 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
2872 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
2873 * BRW_NEW_VUE_MAP_GEOM_OUT
2875 genX(calculate_attr_overrides
)(brw
,
2877 &point_sprite_enables
,
2878 &urb_entry_read_length
,
2879 &urb_entry_read_offset
);
2881 /* Typically, the URB entry read length and offset should be programmed
2882 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
2883 * stage which produces geometry. However, we don't know the proper
2884 * value until we call calculate_attr_overrides().
2886 * To fit with our existing code, we override the inherited values and
2887 * specify it here directly, as we did on previous generations.
2889 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
2890 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
2891 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
2892 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2895 sbe
.ForceVertexURBEntryReadLength
= true;
2896 sbe
.ForceVertexURBEntryReadOffset
= true;
2900 /* prepare the active component dwords */
2901 int input_index
= 0;
2902 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
2903 if (!(brw
->fragment_program
->info
.inputs_read
&
2904 BITFIELD64_BIT(attr
))) {
2908 assert(input_index
< 32);
2910 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
2917 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2918 for (int i
= 0; i
< 16; i
++)
2919 sbes
.Attribute
[i
] = attr_overrides
[i
];
2923 #undef attr_overrides
2926 static const struct brw_tracked_state
genX(sbe_state
) = {
2928 .mesa
= _NEW_BUFFERS
|
2933 .brw
= BRW_NEW_BLORP
|
2935 BRW_NEW_FRAGMENT_PROGRAM
|
2936 BRW_NEW_FS_PROG_DATA
|
2937 BRW_NEW_GS_PROG_DATA
|
2938 BRW_NEW_TES_PROG_DATA
|
2939 BRW_NEW_VUE_MAP_GEOM_OUT
|
2940 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
2943 .emit
= genX(upload_sbe
),
2947 /* ---------------------------------------------------------------------- */
2951 * Outputs the 3DSTATE_SO_DECL_LIST command.
2953 * The data output is a series of 64-bit entries containing a SO_DECL per
2954 * stream. We only have one stream of rendering coming out of the GS unit, so
2955 * we only emit stream 0 (low 16 bits) SO_DECLs.
2958 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
2959 const struct brw_vue_map
*vue_map
)
2961 struct gl_context
*ctx
= &brw
->ctx
;
2962 /* BRW_NEW_TRANSFORM_FEEDBACK */
2963 struct gl_transform_feedback_object
*xfb_obj
=
2964 ctx
->TransformFeedback
.CurrentObject
;
2965 const struct gl_transform_feedback_info
*linked_xfb_info
=
2966 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
2967 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2968 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2969 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2970 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2972 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2974 memset(so_decl
, 0, sizeof(so_decl
));
2976 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2977 * command feels strange -- each dword pair contains a SO_DECL per stream.
2979 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
2980 int buffer
= linked_xfb_info
->Outputs
[i
].OutputBuffer
;
2981 struct GENX(SO_DECL
) decl
= {0};
2982 int varying
= linked_xfb_info
->Outputs
[i
].OutputRegister
;
2983 const unsigned components
= linked_xfb_info
->Outputs
[i
].NumComponents
;
2984 unsigned component_mask
= (1 << components
) - 1;
2985 unsigned stream_id
= linked_xfb_info
->Outputs
[i
].StreamId
;
2986 unsigned decl_buffer_slot
= buffer
;
2987 assert(stream_id
< MAX_VERTEX_STREAMS
);
2989 /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w
2990 * gl_Layer is stored in VARYING_SLOT_PSIZ.y
2991 * gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
2993 if (varying
== VARYING_SLOT_PSIZ
) {
2994 assert(components
== 1);
2995 component_mask
<<= 3;
2996 } else if (varying
== VARYING_SLOT_LAYER
) {
2997 assert(components
== 1);
2998 component_mask
<<= 1;
2999 } else if (varying
== VARYING_SLOT_VIEWPORT
) {
3000 assert(components
== 1);
3001 component_mask
<<= 2;
3003 component_mask
<<= linked_xfb_info
->Outputs
[i
].ComponentOffset
;
3006 buffer_mask
[stream_id
] |= 1 << buffer
;
3008 decl
.OutputBufferSlot
= decl_buffer_slot
;
3009 if (varying
== VARYING_SLOT_LAYER
|| varying
== VARYING_SLOT_VIEWPORT
) {
3010 decl
.RegisterIndex
= vue_map
->varying_to_slot
[VARYING_SLOT_PSIZ
];
3012 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3013 decl
.RegisterIndex
= vue_map
->varying_to_slot
[varying
];
3015 decl
.ComponentMask
= component_mask
;
3017 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3018 * array. Instead, it simply increments DstOffset for the following
3019 * input by the number of components that should be skipped.
3021 * Our hardware is unusual in that it requires us to program SO_DECLs
3022 * for fake "hole" components, rather than simply taking the offset
3023 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3024 * program as many size = 4 holes as we can, then a final hole to
3025 * accommodate the final 1, 2, or 3 remaining.
3027 int skip_components
=
3028 linked_xfb_info
->Outputs
[i
].DstOffset
- next_offset
[buffer
];
3030 next_offset
[buffer
] += skip_components
;
3032 while (skip_components
>= 4) {
3033 struct GENX(SO_DECL
) *d
= &so_decl
[stream_id
][decls
[stream_id
]++];
3035 d
->OutputBufferSlot
= decl_buffer_slot
;
3036 d
->ComponentMask
= 0xf;
3037 skip_components
-= 4;
3040 if (skip_components
> 0) {
3041 struct GENX(SO_DECL
) *d
= &so_decl
[stream_id
][decls
[stream_id
]++];
3043 d
->OutputBufferSlot
= decl_buffer_slot
;
3044 d
->ComponentMask
= (1 << skip_components
) - 1;
3047 assert(linked_xfb_info
->Outputs
[i
].DstOffset
== next_offset
[buffer
]);
3049 next_offset
[buffer
] += components
;
3051 so_decl
[stream_id
][decls
[stream_id
]++] = decl
;
3053 if (decls
[stream_id
] > max_decls
)
3054 max_decls
= decls
[stream_id
];
3058 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3059 .StreamtoBufferSelects0
= buffer_mask
[0],
3060 .StreamtoBufferSelects1
= buffer_mask
[1],
3061 .StreamtoBufferSelects2
= buffer_mask
[2],
3062 .StreamtoBufferSelects3
= buffer_mask
[3],
3063 .NumEntries0
= decls
[0],
3064 .NumEntries1
= decls
[1],
3065 .NumEntries2
= decls
[2],
3066 .NumEntries3
= decls
[3]);
3068 for (int i
= 0; i
< max_decls
; i
++) {
3069 GENX(SO_DECL_ENTRY_pack
)(
3070 brw
, dw
+ 2 + i
* 2,
3071 &(struct GENX(SO_DECL_ENTRY
)) {
3072 .Stream0Decl
= so_decl
[0][i
],
3073 .Stream1Decl
= so_decl
[1][i
],
3074 .Stream2Decl
= so_decl
[2][i
],
3075 .Stream3Decl
= so_decl
[3][i
],
3081 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3083 struct gl_context
*ctx
= &brw
->ctx
;
3084 /* BRW_NEW_TRANSFORM_FEEDBACK */
3085 struct gl_transform_feedback_object
*xfb_obj
=
3086 ctx
->TransformFeedback
.CurrentObject
;
3088 const struct gl_transform_feedback_info
*linked_xfb_info
=
3089 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3091 struct brw_transform_feedback_object
*brw_obj
=
3092 (struct brw_transform_feedback_object
*) xfb_obj
;
3093 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3096 /* Set up the up to 4 output buffers. These are the ranges defined in the
3097 * gl_transform_feedback_object.
3099 for (int i
= 0; i
< 4; i
++) {
3100 struct intel_buffer_object
*bufferobj
=
3101 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3104 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3105 sob
.SOBufferIndex
= i
;
3110 uint32_t start
= xfb_obj
->Offset
[i
];
3111 assert(start
% 4 == 0);
3112 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3114 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
);
3115 assert(end
<= bo
->size
);
3117 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3118 sob
.SOBufferIndex
= i
;
3120 sob
.SurfaceBaseAddress
= render_bo(bo
, start
);
3122 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3123 sob
.SurfaceEndAddress
= render_bo(bo
, end
);
3125 sob
.SOBufferEnable
= true;
3126 sob
.StreamOffsetWriteEnable
= true;
3127 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3128 sob
.SOBufferMOCS
= mocs_wb
;
3130 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3131 sob
.StreamOutputBufferOffsetAddress
=
3132 instruction_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3134 if (brw_obj
->zero_offsets
) {
3135 /* Zero out the offset and write that to offset_bo */
3136 sob
.StreamOffset
= 0;
3138 /* Use offset_bo as the "Stream Offset." */
3139 sob
.StreamOffset
= 0xFFFFFFFF;
3146 brw_obj
->zero_offsets
= false;
3151 query_active(struct gl_query_object
*q
)
3153 return q
&& q
->Active
;
3157 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3158 const struct brw_vue_map
*vue_map
)
3160 struct gl_context
*ctx
= &brw
->ctx
;
3161 /* BRW_NEW_TRANSFORM_FEEDBACK */
3162 struct gl_transform_feedback_object
*xfb_obj
=
3163 ctx
->TransformFeedback
.CurrentObject
;
3165 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3167 int urb_entry_read_offset
= 0;
3168 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3169 urb_entry_read_offset
;
3171 sos
.SOFunctionEnable
= true;
3172 sos
.SOStatisticsEnable
= true;
3174 /* BRW_NEW_RASTERIZER_DISCARD */
3175 if (ctx
->RasterDiscard
) {
3176 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3177 sos
.RenderingDisable
= true;
3179 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3180 "query active relies on the clipper.");
3185 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3186 sos
.ReorderMode
= TRAILING
;
3189 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3190 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3191 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3192 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3194 const struct gl_transform_feedback_info
*linked_xfb_info
=
3195 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3196 /* Set buffer pitches; 0 means unbound. */
3197 if (xfb_obj
->Buffers
[0])
3198 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3199 if (xfb_obj
->Buffers
[1])
3200 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3201 if (xfb_obj
->Buffers
[2])
3202 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3203 if (xfb_obj
->Buffers
[3])
3204 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3207 /* We always read the whole vertex. This could be reduced at some
3208 * point by reading less and offsetting the register index in the
3211 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3212 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3213 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3214 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3215 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3216 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3217 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3218 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3224 genX(upload_sol
)(struct brw_context
*brw
)
3226 struct gl_context
*ctx
= &brw
->ctx
;
3227 /* BRW_NEW_TRANSFORM_FEEDBACK */
3228 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3231 genX(upload_3dstate_so_buffers
)(brw
);
3233 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3234 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3237 /* Finally, set up the SOL stage. This command must always follow updates to
3238 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3239 * MMIO register updates (current performed by the kernel at each batch
3242 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3245 static const struct brw_tracked_state
genX(sol_state
) = {
3248 .brw
= BRW_NEW_BATCH
|
3250 BRW_NEW_RASTERIZER_DISCARD
|
3251 BRW_NEW_VUE_MAP_GEOM_OUT
|
3252 BRW_NEW_TRANSFORM_FEEDBACK
,
3254 .emit
= genX(upload_sol
),
3258 /* ---------------------------------------------------------------------- */
3262 genX(upload_ps
)(struct brw_context
*brw
)
3264 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3265 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3267 /* BRW_NEW_FS_PROG_DATA */
3268 const struct brw_wm_prog_data
*prog_data
=
3269 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3270 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3275 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3276 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3277 * incorrect for subspans where some of the pixels are unlit. We believe
3278 * the bit just didn't take effect in previous generations.
3280 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3283 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3285 /* BRW_NEW_FS_PROG_DATA */
3286 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3288 if (prog_data
->base
.use_alt_mode
)
3289 ps
.FloatingPointMode
= Alternate
;
3291 /* Haswell requires the sample mask to be set in this packet as well as
3292 * in 3DSTATE_SAMPLE_MASK; the values should match.
3295 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3297 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3300 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3301 * it implicitly scales for different GT levels (which have some # of
3304 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3307 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3309 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3311 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3314 if (prog_data
->base
.nr_params
> 0)
3315 ps
.PushConstantEnable
= true;
3318 /* From the IVB PRM, volume 2 part 1, page 287:
3319 * "This bit is inserted in the PS payload header and made available to
3320 * the DataPort (either via the message header or via header bypass) to
3321 * indicate that oMask data (one or two phases) is included in Render
3322 * Target Write messages. If present, the oMask data is used to mask off
3325 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3327 /* The hardware wedges if you have this bit set but don't turn on any
3328 * dual source blend factors.
3330 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3332 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3333 (ctx
->Color
.BlendEnabled
& 1) &&
3334 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3336 /* BRW_NEW_FS_PROG_DATA */
3337 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3340 /* From the documentation for this packet:
3341 * "If the PS kernel does not need the Position XY Offsets to
3342 * compute a Position Value, then this field should be programmed
3343 * to POSOFFSET_NONE."
3345 * "SW Recommendation: If the PS kernel needs the Position Offsets
3346 * to compute a Position XY value, this field should match Position
3347 * ZW Interpolation Mode to ensure a consistent position.xyzw
3350 * We only require XY sample offsets. So, this recommendation doesn't
3351 * look useful at the moment. We might need this in future.
3353 if (prog_data
->uses_pos_offset
)
3354 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3356 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3358 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3359 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3360 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3361 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3362 prog_data
->base
.dispatch_grf_start_reg
;
3363 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3364 prog_data
->dispatch_grf_start_reg_2
;
3366 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3367 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3368 prog_data
->prog_offset_2
;
3370 if (prog_data
->base
.total_scratch
) {
3371 ps
.ScratchSpaceBasePointer
=
3372 render_bo(stage_state
->scratch_bo
,
3373 ffs(stage_state
->per_thread_scratch
) - 11);
3378 static const struct brw_tracked_state
genX(ps_state
) = {
3380 .mesa
= _NEW_MULTISAMPLE
|
3381 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3384 .brw
= BRW_NEW_BATCH
|
3386 BRW_NEW_FS_PROG_DATA
,
3388 .emit
= genX(upload_ps
),
3392 /* ---------------------------------------------------------------------- */
3396 genX(upload_hs_state
)(struct brw_context
*brw
)
3398 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3399 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3400 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3401 const struct brw_vue_prog_data
*vue_prog_data
=
3402 brw_vue_prog_data(stage_prog_data
);
3404 /* BRW_NEW_TES_PROG_DATA */
3405 struct brw_tcs_prog_data
*tcs_prog_data
=
3406 brw_tcs_prog_data(stage_prog_data
);
3408 if (!tcs_prog_data
) {
3409 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3411 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3412 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3414 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3415 hs
.IncludeVertexHandles
= true;
3417 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3422 static const struct brw_tracked_state
genX(hs_state
) = {
3425 .brw
= BRW_NEW_BATCH
|
3427 BRW_NEW_TCS_PROG_DATA
|
3428 BRW_NEW_TESS_PROGRAMS
,
3430 .emit
= genX(upload_hs_state
),
3434 genX(upload_ds_state
)(struct brw_context
*brw
)
3436 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3437 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3438 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3440 /* BRW_NEW_TES_PROG_DATA */
3441 const struct brw_tes_prog_data
*tes_prog_data
=
3442 brw_tes_prog_data(stage_prog_data
);
3443 const struct brw_vue_prog_data
*vue_prog_data
=
3444 brw_vue_prog_data(stage_prog_data
);
3446 if (!tes_prog_data
) {
3447 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3449 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3450 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3452 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3453 ds
.ComputeWCoordinateEnable
=
3454 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3457 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3458 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3459 ds
.UserClipDistanceCullTestEnableBitmask
=
3460 vue_prog_data
->cull_distance_mask
;
3466 static const struct brw_tracked_state
genX(ds_state
) = {
3469 .brw
= BRW_NEW_BATCH
|
3471 BRW_NEW_TESS_PROGRAMS
|
3472 BRW_NEW_TES_PROG_DATA
,
3474 .emit
= genX(upload_ds_state
),
3477 /* ---------------------------------------------------------------------- */
3480 upload_te_state(struct brw_context
*brw
)
3482 /* BRW_NEW_TESS_PROGRAMS */
3483 bool active
= brw
->tess_eval_program
;
3485 /* BRW_NEW_TES_PROG_DATA */
3486 const struct brw_tes_prog_data
*tes_prog_data
=
3487 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
3490 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
3491 te
.Partitioning
= tes_prog_data
->partitioning
;
3492 te
.OutputTopology
= tes_prog_data
->output_topology
;
3493 te
.TEDomain
= tes_prog_data
->domain
;
3495 te
.MaximumTessellationFactorOdd
= 63.0;
3496 te
.MaximumTessellationFactorNotOdd
= 64.0;
3499 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
3503 static const struct brw_tracked_state
genX(te_state
) = {
3506 .brw
= BRW_NEW_BLORP
|
3508 BRW_NEW_TES_PROG_DATA
|
3509 BRW_NEW_TESS_PROGRAMS
,
3511 .emit
= upload_te_state
,
3514 /* ---------------------------------------------------------------------- */
3517 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
3519 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3520 /* BRW_NEW_TESS_PROGRAMS */
3521 const struct brw_program
*tep
= brw_program_const(brw
->tess_eval_program
);
3524 /* BRW_NEW_TES_PROG_DATA */
3525 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
3526 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
3527 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
3530 upload_constant_state(brw
, stage_state
, tep
, MESA_SHADER_TESS_EVAL
);
3533 static const struct brw_tracked_state
genX(tes_push_constants
) = {
3535 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3536 .brw
= BRW_NEW_BATCH
|
3538 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3539 BRW_NEW_TESS_PROGRAMS
|
3540 BRW_NEW_TES_PROG_DATA
,
3542 .emit
= genX(upload_tes_push_constants
),
3546 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
3548 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3549 /* BRW_NEW_TESS_PROGRAMS */
3550 const struct brw_program
*tcp
= brw_program_const(brw
->tess_ctrl_program
);
3551 bool active
= brw
->tess_eval_program
;
3554 /* BRW_NEW_TCS_PROG_DATA */
3555 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
3557 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
3558 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
3561 upload_constant_state(brw
, stage_state
, active
, MESA_SHADER_TESS_CTRL
);
3564 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
3566 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3567 .brw
= BRW_NEW_BATCH
|
3569 BRW_NEW_DEFAULT_TESS_LEVELS
|
3570 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3571 BRW_NEW_TESS_PROGRAMS
|
3572 BRW_NEW_TCS_PROG_DATA
,
3574 .emit
= genX(upload_tcs_push_constants
),
3578 /* ---------------------------------------------------------------------- */
3582 genX(upload_raster
)(struct brw_context
*brw
)
3584 struct gl_context
*ctx
= &brw
->ctx
;
3587 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3590 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
3593 struct gl_point_attrib
*point
= &ctx
->Point
;
3595 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
3596 if (polygon
->_FrontBit
== render_to_fbo
)
3597 raster
.FrontWinding
= CounterClockwise
;
3599 if (polygon
->CullFlag
) {
3600 switch (polygon
->CullFaceMode
) {
3602 raster
.CullMode
= CULLMODE_FRONT
;
3605 raster
.CullMode
= CULLMODE_BACK
;
3607 case GL_FRONT_AND_BACK
:
3608 raster
.CullMode
= CULLMODE_BOTH
;
3611 unreachable("not reached");
3614 raster
.CullMode
= CULLMODE_NONE
;
3617 point
->SmoothFlag
= raster
.SmoothPointEnable
;
3619 raster
.DXMultisampleRasterizationEnable
=
3620 _mesa_is_multisample_enabled(ctx
);
3622 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
3623 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
3624 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
3626 switch (polygon
->FrontMode
) {
3628 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
3631 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
3634 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
3637 unreachable("not reached");
3640 switch (polygon
->BackMode
) {
3642 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
3645 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
3648 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
3651 unreachable("not reached");
3655 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
3658 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
3660 /* _NEW_TRANSFORM */
3661 if (!ctx
->Transform
.DepthClamp
) {
3663 raster
.ViewportZFarClipTestEnable
= true;
3664 raster
.ViewportZNearClipTestEnable
= true;
3666 raster
.ViewportZClipTestEnable
= true;
3670 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
3672 raster
.ConservativeRasterizationEnable
=
3673 ctx
->IntelConservativeRasterization
;
3676 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
3677 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
3679 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
3683 static const struct brw_tracked_state
genX(raster_state
) = {
3685 .mesa
= _NEW_BUFFERS
|
3692 .brw
= BRW_NEW_BLORP
|
3694 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3696 .emit
= genX(upload_raster
),
3700 /* ---------------------------------------------------------------------- */
3704 genX(upload_ps_extra
)(struct brw_context
*brw
)
3706 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
3708 const struct brw_wm_prog_data
*prog_data
=
3709 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3711 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
3712 psx
.PixelShaderValid
= true;
3713 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
3714 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
3715 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
3716 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
3717 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
3718 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
3720 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
3721 if (prog_data
->uses_sample_mask
) {
3723 if (prog_data
->post_depth_coverage
)
3724 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3725 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
3726 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
3728 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3730 psx
.PixelShaderUsesInputCoverageMask
= true;
3734 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3736 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
3737 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
3740 /* The stricter cross-primitive coherency guarantees that the hardware
3741 * gives us with the "Accesses UAV" bit set for at least one shader stage
3742 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
3743 * are redundant within the current image, atomic counter and SSBO GL
3744 * APIs, which all have very loose ordering and coherency requirements
3745 * and generally rely on the application to insert explicit barriers when
3746 * a shader invocation is expected to see the memory writes performed by
3747 * the invocations of some previous primitive. Regardless of the value
3748 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
3749 * cause an in most cases useless DC flush when the lowermost stage with
3750 * the bit set finishes execution.
3752 * It would be nice to disable it, but in some cases we can't because on
3753 * Gen8+ it also has an influence on rasterization via the PS UAV-only
3754 * signal (which could be set independently from the coherency mechanism
3755 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
3756 * determine whether the hardware skips execution of the fragment shader
3757 * or not via the ThreadDispatchEnable signal. However if we know that
3758 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
3759 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
3760 * difference so we may just disable it here.
3762 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
3763 * take into account KillPixels when no depth or stencil writes are
3764 * enabled. In order for occlusion queries to work correctly with no
3765 * attachments, we need to force-enable here.
3767 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
3770 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
3771 !brw_color_buffer_write_enabled(brw
))
3772 psx
.PixelShaderHasUAV
= true;
3776 const struct brw_tracked_state
genX(ps_extra
) = {
3778 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
3779 .brw
= BRW_NEW_BLORP
|
3781 BRW_NEW_FRAGMENT_PROGRAM
|
3782 BRW_NEW_FS_PROG_DATA
|
3783 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3785 .emit
= genX(upload_ps_extra
),
3789 /* ---------------------------------------------------------------------- */
3793 genX(upload_ps_blend
)(struct brw_context
*brw
)
3795 struct gl_context
*ctx
= &brw
->ctx
;
3798 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
3799 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
3802 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
3804 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
3805 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
3806 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
3808 if (!buffer0_is_integer
) {
3809 /* _NEW_MULTISAMPLE */
3810 pb
.AlphaToCoverageEnable
=
3811 _mesa_is_multisample_enabled(ctx
) &&
3812 ctx
->Multisample
.SampleAlphaToCoverage
;
3814 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
3817 /* Used for implementing the following bit of GL_EXT_texture_integer:
3818 * "Per-fragment operations that require floating-point color
3819 * components, including multisample alpha operations, alpha test,
3820 * blending, and dithering, have no effect when the corresponding
3821 * colors are written to an integer color buffer."
3823 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
3824 * "If drawbuffer zero is not NONE and the buffer it references has an
3825 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
3826 * operations are skipped."
3828 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
3829 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
3830 GLenum eqA
= color
->Blend
[0].EquationA
;
3831 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
3832 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
3833 GLenum srcA
= color
->Blend
[0].SrcA
;
3834 GLenum dstA
= color
->Blend
[0].DstA
;
3836 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
3837 srcRGB
= dstRGB
= GL_ONE
;
3839 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
3840 srcA
= dstA
= GL_ONE
;
3842 /* Due to hardware limitations, the destination may have information
3843 * in an alpha channel even when the format specifies no alpha
3844 * channel. In order to avoid getting any incorrect blending due to
3845 * that alpha channel, coerce the blend factors to values that will
3846 * not read the alpha channel, but will instead use the correct
3847 * implicit value for alpha.
3849 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
3850 GL_TEXTURE_ALPHA_TYPE
)) {
3851 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
3852 srcA
= brw_fix_xRGB_alpha(srcA
);
3853 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
3854 dstA
= brw_fix_xRGB_alpha(dstA
);
3857 pb
.ColorBufferBlendEnable
= true;
3858 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
3859 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
3860 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
3861 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
3863 pb
.IndependentAlphaBlendEnable
=
3864 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
3869 static const struct brw_tracked_state
genX(ps_blend
) = {
3871 .mesa
= _NEW_BUFFERS
|
3874 .brw
= BRW_NEW_BLORP
|
3876 BRW_NEW_FRAGMENT_PROGRAM
,
3878 .emit
= genX(upload_ps_blend
)
3883 /* ---------------------------------------------------------------------- */
3887 genX(upload_viewport_state_pointers
)(struct brw_context
*brw
)
3889 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
3890 vp
.CCViewportStateChange
= 1;
3891 vp
.SFViewportStateChange
= 1;
3892 vp
.CLIPViewportStateChange
= 1;
3893 vp
.PointertoCLIP_VIEWPORT
= brw
->clip
.vp_offset
;
3894 vp
.PointertoSF_VIEWPORT
= brw
->sf
.vp_offset
;
3895 vp
.PointertoCC_VIEWPORT
= brw
->cc
.vp_offset
;
3899 static const struct brw_tracked_state
genX(viewport_state
) = {
3902 .brw
= BRW_NEW_BATCH
|
3907 BRW_NEW_STATE_BASE_ADDRESS
,
3909 .emit
= genX(upload_viewport_state_pointers
),
3913 /* ---------------------------------------------------------------------- */
3916 genX(init_atoms
)(struct brw_context
*brw
)
3919 static const struct brw_tracked_state
*render_atoms
[] =
3921 /* Once all the programs are done, we know how large urb entry
3922 * sizes need to be and can decide if we need to change the urb
3926 &brw_recalculate_urb_fence
,
3931 /* Surface state setup. Must come before the VS/WM unit. The binding
3932 * table upload must be last.
3934 &brw_vs_pull_constants
,
3935 &brw_wm_pull_constants
,
3936 &brw_renderbuffer_surfaces
,
3937 &brw_renderbuffer_read_surfaces
,
3938 &brw_texture_surfaces
,
3939 &brw_vs_binding_table
,
3940 &brw_wm_binding_table
,
3945 /* These set up state for brw_psp_urb_cbs */
3949 &genX(vs_state
), /* always required, enabled or not */
3955 &brw_invariant_state
,
3957 &brw_binding_table_pointers
,
3958 &brw_blend_constant_color
,
3962 &genX(polygon_stipple
),
3963 &genX(polygon_stipple_offset
),
3965 &genX(line_stipple
),
3969 &genX(drawing_rect
),
3970 &brw_indices
, /* must come before brw_vertices */
3974 &brw_constant_buffer
3977 static const struct brw_tracked_state
*render_atoms
[] =
3979 &genX(sf_clip_viewport
),
3981 /* Command packets: */
3984 &genX(viewport_state
), /* must do after *_vp stages */
3987 &genX(blend_state
), /* must do before cc unit */
3988 &genX(color_calc_state
), /* must do before cc unit */
3989 &genX(depth_stencil_state
), /* must do before cc unit */
3991 &genX(vs_push_constants
), /* Before vs_state */
3992 &genX(gs_push_constants
), /* Before gs_state */
3993 &genX(wm_push_constants
), /* Before wm_state */
3995 /* Surface state setup. Must come before the VS/WM unit. The binding
3996 * table upload must be last.
3998 &brw_vs_pull_constants
,
3999 &brw_vs_ubo_surfaces
,
4000 &brw_gs_pull_constants
,
4001 &brw_gs_ubo_surfaces
,
4002 &brw_wm_pull_constants
,
4003 &brw_wm_ubo_surfaces
,
4004 &gen6_renderbuffer_surfaces
,
4005 &brw_renderbuffer_read_surfaces
,
4006 &brw_texture_surfaces
,
4008 &brw_vs_binding_table
,
4009 &gen6_gs_binding_table
,
4010 &brw_wm_binding_table
,
4015 &gen6_sampler_state
,
4016 &genX(multisample_state
),
4024 &genX(scissor_state
),
4026 &gen6_binding_table_pointers
,
4030 &genX(polygon_stipple
),
4031 &genX(polygon_stipple_offset
),
4033 &genX(line_stipple
),
4035 &genX(drawing_rect
),
4037 &brw_indices
, /* must come before brw_vertices */
4042 static const struct brw_tracked_state
*render_atoms
[] =
4044 /* Command packets: */
4047 &genX(sf_clip_viewport
),
4050 &gen7_push_constant_space
,
4052 &genX(blend_state
), /* must do before cc unit */
4053 &genX(color_calc_state
), /* must do before cc unit */
4054 &genX(depth_stencil_state
), /* must do before cc unit */
4056 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4057 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4058 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4059 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4060 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4062 &genX(vs_push_constants
), /* Before vs_state */
4063 &genX(tcs_push_constants
),
4064 &genX(tes_push_constants
),
4065 &genX(gs_push_constants
), /* Before gs_state */
4066 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4068 /* Surface state setup. Must come before the VS/WM unit. The binding
4069 * table upload must be last.
4071 &brw_vs_pull_constants
,
4072 &brw_vs_ubo_surfaces
,
4073 &brw_vs_abo_surfaces
,
4074 &brw_tcs_pull_constants
,
4075 &brw_tcs_ubo_surfaces
,
4076 &brw_tcs_abo_surfaces
,
4077 &brw_tes_pull_constants
,
4078 &brw_tes_ubo_surfaces
,
4079 &brw_tes_abo_surfaces
,
4080 &brw_gs_pull_constants
,
4081 &brw_gs_ubo_surfaces
,
4082 &brw_gs_abo_surfaces
,
4083 &brw_wm_pull_constants
,
4084 &brw_wm_ubo_surfaces
,
4085 &brw_wm_abo_surfaces
,
4086 &gen6_renderbuffer_surfaces
,
4087 &brw_renderbuffer_read_surfaces
,
4088 &brw_texture_surfaces
,
4089 &brw_vs_binding_table
,
4090 &brw_tcs_binding_table
,
4091 &brw_tes_binding_table
,
4092 &brw_gs_binding_table
,
4093 &brw_wm_binding_table
,
4100 &genX(multisample_state
),
4114 &genX(scissor_state
),
4118 &genX(polygon_stipple
),
4119 &genX(polygon_stipple_offset
),
4121 &genX(line_stipple
),
4123 &genX(drawing_rect
),
4125 &brw_indices
, /* must come before brw_vertices */
4134 static const struct brw_tracked_state
*render_atoms
[] =
4137 &genX(sf_clip_viewport
),
4140 &gen7_push_constant_space
,
4143 &genX(color_calc_state
),
4145 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4146 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4147 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4148 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4149 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4151 &genX(vs_push_constants
), /* Before vs_state */
4152 &genX(tcs_push_constants
),
4153 &genX(tes_push_constants
),
4154 &genX(gs_push_constants
), /* Before gs_state */
4155 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4157 /* Surface state setup. Must come before the VS/WM unit. The binding
4158 * table upload must be last.
4160 &brw_vs_pull_constants
,
4161 &brw_vs_ubo_surfaces
,
4162 &brw_vs_abo_surfaces
,
4163 &brw_tcs_pull_constants
,
4164 &brw_tcs_ubo_surfaces
,
4165 &brw_tcs_abo_surfaces
,
4166 &brw_tes_pull_constants
,
4167 &brw_tes_ubo_surfaces
,
4168 &brw_tes_abo_surfaces
,
4169 &brw_gs_pull_constants
,
4170 &brw_gs_ubo_surfaces
,
4171 &brw_gs_abo_surfaces
,
4172 &brw_wm_pull_constants
,
4173 &brw_wm_ubo_surfaces
,
4174 &brw_wm_abo_surfaces
,
4175 &gen6_renderbuffer_surfaces
,
4176 &brw_renderbuffer_read_surfaces
,
4177 &brw_texture_surfaces
,
4178 &brw_vs_binding_table
,
4179 &brw_tcs_binding_table
,
4180 &brw_tes_binding_table
,
4181 &brw_gs_binding_table
,
4182 &brw_wm_binding_table
,
4189 &genX(multisample_state
),
4198 &genX(raster_state
),
4204 &genX(depth_stencil_state
),
4207 &genX(scissor_state
),
4211 &genX(polygon_stipple
),
4212 &genX(polygon_stipple_offset
),
4214 &genX(line_stipple
),
4216 &genX(drawing_rect
),
4229 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
4230 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
4231 render_atoms
, ARRAY_SIZE(render_atoms
));
4234 static const struct brw_tracked_state
*compute_atoms
[] =
4237 &brw_cs_image_surfaces
,
4238 &gen7_cs_push_constants
,
4239 &brw_cs_pull_constants
,
4240 &brw_cs_ubo_surfaces
,
4241 &brw_cs_abo_surfaces
,
4242 &brw_cs_texture_surfaces
,
4243 &brw_cs_work_groups_surface
,
4248 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
4249 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
4250 compute_atoms
, ARRAY_SIZE(compute_atoms
));