2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
35 #include "brw_context.h"
37 #include "brw_defines.h"
40 #include "brw_multisample_state.h"
41 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
46 #include "intel_buffer_objects.h"
47 #include "intel_fbo.h"
49 #include "main/enums.h"
50 #include "main/fbobject.h"
51 #include "main/framebuffer.h"
52 #include "main/glformats.h"
53 #include "main/shaderapi.h"
54 #include "main/stencil.h"
55 #include "main/transformfeedback.h"
56 #include "main/varray.h"
57 #include "main/viewport.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
71 uint32_t read_domains
;
72 uint32_t write_domain
;
77 emit_reloc(struct brw_context
*brw
,
78 void *location
, struct brw_address address
, uint32_t delta
)
80 uint32_t offset
= (char *) location
- (char *) brw
->batch
.map
;
82 return brw_emit_reloc(&brw
->batch
, offset
, address
.bo
,
83 address
.offset
+ delta
,
85 address
.write_domain
);
88 #define __gen_address_type struct brw_address
89 #define __gen_user_data struct brw_context
92 __gen_combine_address(struct brw_context
*brw
, void *location
,
93 struct brw_address address
, uint32_t delta
)
95 if (address
.bo
== NULL
) {
96 return address
.offset
+ delta
;
98 return emit_reloc(brw
, location
, address
, delta
);
102 static inline struct brw_address
103 render_bo(struct brw_bo
*bo
, uint32_t offset
)
105 return (struct brw_address
) {
108 .read_domains
= I915_GEM_DOMAIN_RENDER
,
109 .write_domain
= I915_GEM_DOMAIN_RENDER
,
113 static inline struct brw_address
114 render_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
116 return (struct brw_address
) {
119 .read_domains
= I915_GEM_DOMAIN_RENDER
,
124 static inline struct brw_address
125 instruction_bo(struct brw_bo
*bo
, uint32_t offset
)
127 return (struct brw_address
) {
130 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
131 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
135 static inline struct brw_address
136 instruction_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
138 return (struct brw_address
) {
141 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
146 static inline struct brw_address
147 vertex_bo(struct brw_bo
*bo
, uint32_t offset
)
149 return (struct brw_address
) {
152 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
158 static inline struct brw_address
159 KSP(struct brw_context
*brw
, uint32_t offset
)
161 return instruction_bo(brw
->cache
.bo
, offset
);
164 static inline struct brw_address
165 KSP_ro(struct brw_context
*brw
, uint32_t offset
)
167 return instruction_ro_bo(brw
->cache
.bo
, offset
);
170 static inline uint32_t
171 KSP(struct brw_context
*brw
, uint32_t offset
)
180 #include "genxml/genX_pack.h"
182 #define _brw_cmd_length(cmd) cmd ## _length
183 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
184 #define _brw_cmd_header(cmd) cmd ## _header
185 #define _brw_cmd_pack(cmd) cmd ## _pack
187 #define brw_batch_emit(brw, cmd, name) \
188 for (struct cmd name = { _brw_cmd_header(cmd) }, \
189 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
190 __builtin_expect(_dst != NULL, 1); \
191 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
194 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
195 uint32_t *_dw = emit_dwords(brw, n); \
196 struct cmd template = { \
197 _brw_cmd_header(cmd), \
198 .DWordLength = n - _brw_cmd_length_bias(cmd), \
201 _brw_cmd_pack(cmd)(brw, _dw, &template); \
202 _dw + 1; /* Array starts at dw[1] */ \
205 #define brw_state_emit(brw, cmd, align, offset, name) \
206 for (struct cmd name = { 0, }, \
207 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
209 __builtin_expect(_dst != NULL, 1); \
210 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
214 * Polygon stipple packet
217 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
219 struct gl_context
*ctx
= &brw
->ctx
;
222 if (!ctx
->Polygon
.StippleFlag
)
225 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
226 /* Polygon stipple is provided in OpenGL order, i.e. bottom
227 * row first. If we're rendering to a window (i.e. the
228 * default frame buffer object, 0), then we need to invert
229 * it to match our pixel layout. But if we're rendering
230 * to a FBO (i.e. any named frame buffer object), we *don't*
231 * need to invert - we already match the layout.
233 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
234 for (unsigned i
= 0; i
< 32; i
++)
235 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
237 for (unsigned i
= 0; i
< 32; i
++)
238 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
243 static const struct brw_tracked_state
genX(polygon_stipple
) = {
245 .mesa
= _NEW_POLYGON
|
247 .brw
= BRW_NEW_CONTEXT
,
249 .emit
= genX(upload_polygon_stipple
),
253 * Polygon stipple offset packet
256 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
258 struct gl_context
*ctx
= &brw
->ctx
;
261 if (!ctx
->Polygon
.StippleFlag
)
264 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
267 * If we're drawing to a system window we have to invert the Y axis
268 * in order to match the OpenGL pixel coordinate system, and our
269 * offset must be matched to the window position. If we're drawing
270 * to a user-created FBO then our native pixel coordinate system
271 * works just fine, and there's no window system to worry about.
273 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
274 poly
.PolygonStippleYOffset
=
275 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
280 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
282 .mesa
= _NEW_BUFFERS
|
284 .brw
= BRW_NEW_CONTEXT
,
286 .emit
= genX(upload_polygon_stipple_offset
),
290 * Line stipple packet
293 genX(upload_line_stipple
)(struct brw_context
*brw
)
295 struct gl_context
*ctx
= &brw
->ctx
;
297 if (!ctx
->Line
.StippleFlag
)
300 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
301 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
303 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
304 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
308 static const struct brw_tracked_state
genX(line_stipple
) = {
311 .brw
= BRW_NEW_CONTEXT
,
313 .emit
= genX(upload_line_stipple
),
316 /* Constant single cliprect for framebuffer object or DRI2 drawing */
318 genX(upload_drawing_rect
)(struct brw_context
*brw
)
320 struct gl_context
*ctx
= &brw
->ctx
;
321 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
322 const unsigned int fb_width
= _mesa_geometric_width(fb
);
323 const unsigned int fb_height
= _mesa_geometric_height(fb
);
325 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
326 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
327 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
331 static const struct brw_tracked_state
genX(drawing_rect
) = {
333 .mesa
= _NEW_BUFFERS
,
334 .brw
= BRW_NEW_BLORP
|
337 .emit
= genX(upload_drawing_rect
),
341 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
345 unsigned start_offset
,
350 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
351 .VertexBufferIndex
= buffer_nr
,
352 .BufferPitch
= stride
,
353 .BufferStartingAddress
= vertex_bo(bo
, start_offset
),
355 .BufferSize
= end_offset
- start_offset
,
359 .AddressModifyEnable
= true,
363 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
364 .InstanceDataStepRate
= step_rate
,
366 .EndAddress
= vertex_bo(bo
, end_offset
- 1),
371 .VertexBufferMOCS
= CNL_MOCS_WB
,
373 .VertexBufferMOCS
= SKL_MOCS_WB
,
375 .VertexBufferMOCS
= BDW_MOCS_WB
,
377 .VertexBufferMOCS
= GEN7_MOCS_L3
,
381 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
382 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
386 is_passthru_format(uint32_t format
)
389 case ISL_FORMAT_R64_PASSTHRU
:
390 case ISL_FORMAT_R64G64_PASSTHRU
:
391 case ISL_FORMAT_R64G64B64_PASSTHRU
:
392 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
400 uploads_needed(uint32_t format
)
402 if (!is_passthru_format(format
))
406 case ISL_FORMAT_R64_PASSTHRU
:
407 case ISL_FORMAT_R64G64_PASSTHRU
:
409 case ISL_FORMAT_R64G64B64_PASSTHRU
:
410 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
413 unreachable("not reached");
418 * Returns the format that we are finally going to use when upload a vertex
419 * element. It will only change if we are using *64*PASSTHRU formats, as for
420 * gen < 8 they need to be splitted on two *32*FLOAT formats.
422 * @upload points in which upload we are. Valid values are [0,1]
425 downsize_format_if_needed(uint32_t format
,
428 assert(upload
== 0 || upload
== 1);
430 if (!is_passthru_format(format
))
434 case ISL_FORMAT_R64_PASSTHRU
:
435 return ISL_FORMAT_R32G32_FLOAT
;
436 case ISL_FORMAT_R64G64_PASSTHRU
:
437 return ISL_FORMAT_R32G32B32A32_FLOAT
;
438 case ISL_FORMAT_R64G64B64_PASSTHRU
:
439 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
440 : ISL_FORMAT_R32G32_FLOAT
;
441 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
442 return ISL_FORMAT_R32G32B32A32_FLOAT
;
444 unreachable("not reached");
449 * Returns the number of componentes associated with a format that is used on
450 * a 64 to 32 format split. See downsize_format()
453 upload_format_size(uint32_t upload_format
)
455 switch (upload_format
) {
456 case ISL_FORMAT_R32G32_FLOAT
:
458 case ISL_FORMAT_R32G32B32A32_FLOAT
:
461 unreachable("not reached");
466 genX(emit_vertices
)(struct brw_context
*brw
)
470 brw_prepare_vertices(brw
);
471 brw_prepare_shader_draw_parameters(brw
);
474 brw_emit_query_begin(brw
);
477 const struct brw_vs_prog_data
*vs_prog_data
=
478 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
481 struct gl_context
*ctx
= &brw
->ctx
;
482 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
483 ctx
->Polygon
.BackMode
!= GL_FILL
);
485 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
486 unsigned vue
= brw
->vb
.nr_enabled
;
488 /* The element for the edge flags must always be last, so we have to
489 * insert the SGVS before it in that case.
491 if (uses_edge_flag
) {
497 "Trying to insert VID/IID past 33rd vertex element, "
498 "need to reorder the vertex attrbutes.");
500 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
501 if (vs_prog_data
->uses_vertexid
) {
502 vfs
.VertexIDEnable
= true;
503 vfs
.VertexIDComponentNumber
= 2;
504 vfs
.VertexIDElementOffset
= vue
;
507 if (vs_prog_data
->uses_instanceid
) {
508 vfs
.InstanceIDEnable
= true;
509 vfs
.InstanceIDComponentNumber
= 3;
510 vfs
.InstanceIDElementOffset
= vue
;
514 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
515 vfi
.InstancingEnable
= true;
516 vfi
.VertexElementIndex
= vue
;
519 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
522 /* Normally we don't need an element for the SGVS attribute because the
523 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
524 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
525 * we're using draw parameters then we need an element for the those
526 * values. Additionally if there is an edge flag element then the SGVS
527 * can't be inserted past that so we need a dummy element to ensure that
528 * the edge flag is the last one.
530 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
531 vs_prog_data
->uses_baseinstance
||
532 ((vs_prog_data
->uses_instanceid
||
533 vs_prog_data
->uses_vertexid
)
536 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
537 vs_prog_data
->uses_baseinstance
||
538 vs_prog_data
->uses_instanceid
||
539 vs_prog_data
->uses_vertexid
);
541 unsigned nr_elements
=
542 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
545 /* If any of the formats of vb.enabled needs more that one upload, we need
546 * to add it to nr_elements
548 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
549 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
550 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
552 if (uploads_needed(format
) > 1)
557 /* If the VS doesn't read any inputs (calculating vertex position from
558 * a state variable for some reason, for example), emit a single pad
559 * VERTEX_ELEMENT struct and bail.
561 * The stale VB state stays in place, but they don't do anything unless
562 * a VE loads from them.
564 if (nr_elements
== 0) {
565 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
566 1 + GENX(VERTEX_ELEMENT_STATE_length
));
567 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
569 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
570 .Component0Control
= VFCOMP_STORE_0
,
571 .Component1Control
= VFCOMP_STORE_0
,
572 .Component2Control
= VFCOMP_STORE_0
,
573 .Component3Control
= VFCOMP_STORE_1_FP
,
575 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
579 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
580 const bool uses_draw_params
=
581 vs_prog_data
->uses_basevertex
||
582 vs_prog_data
->uses_baseinstance
;
583 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
584 uses_draw_params
+ vs_prog_data
->uses_drawid
;
587 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
589 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
590 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
592 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
593 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
594 /* Prior to Haswell and Bay Trail we have to use 4-component formats
595 * to fake 3-component ones. In particular, we do this for
596 * half-float and 8 and 16-bit integer formats. This means that the
597 * vertex element may poke over the end of the buffer by 2 bytes.
599 const unsigned padding
=
600 (GEN_GEN
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
601 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
602 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
609 if (uses_draw_params
) {
610 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
611 brw
->draw
.draw_params_bo
,
612 brw
->draw
.draw_params_offset
,
613 brw
->draw
.draw_params_bo
->size
,
618 if (vs_prog_data
->uses_drawid
) {
619 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
620 brw
->draw
.draw_id_bo
,
621 brw
->draw
.draw_id_offset
,
622 brw
->draw
.draw_id_bo
->size
,
628 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
629 * presumably for VertexID/InstanceID.
632 assert(nr_elements
<= 34);
633 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
635 assert(nr_elements
<= 18);
638 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
639 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
641 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
642 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
643 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
644 uint32_t comp0
= VFCOMP_STORE_SRC
;
645 uint32_t comp1
= VFCOMP_STORE_SRC
;
646 uint32_t comp2
= VFCOMP_STORE_SRC
;
647 uint32_t comp3
= VFCOMP_STORE_SRC
;
648 const unsigned num_uploads
= GEN_GEN
< 8 ? uploads_needed(format
) : 1;
651 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
652 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
653 * element which has edge flag enabled."
655 assert(!(is_passthru_format(format
) && uses_edge_flag
));
658 /* The gen4 driver expects edgeflag to come in as a float, and passes
659 * that float on to the tests in the clipper. Mesa's current vertex
660 * attribute value for EdgeFlag is stored as a float, which works out.
661 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
662 * integer ubyte. Just rewrite that to convert to a float.
664 * Gen6+ passes edgeflag as sideband along with the vertex, instead
665 * of in the VUE. We have to upload it sideband as the last vertex
666 * element according to the B-Spec.
669 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
670 gen6_edgeflag_input
= input
;
675 for (unsigned c
= 0; c
< num_uploads
; c
++) {
676 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
677 downsize_format_if_needed(format
, c
);
678 /* If we need more that one upload, the offset stride would be 128
679 * bits (16 bytes), as for previous uploads we are using the full
681 const unsigned offset
= input
->offset
+ c
* 16;
683 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
684 upload_format_size(upload_format
) : input
->glarray
->Size
;
687 case 0: comp0
= VFCOMP_STORE_0
;
688 case 1: comp1
= VFCOMP_STORE_0
;
689 case 2: comp2
= VFCOMP_STORE_0
;
691 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
692 comp3
= VFCOMP_STORE_0
;
693 } else if (input
->glarray
->Integer
) {
694 comp3
= VFCOMP_STORE_1_INT
;
696 comp3
= VFCOMP_STORE_1_FP
;
703 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
705 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
706 * formats, 64-bit components are stored in the URB without any
707 * conversion. In this case, vertex elements must be written as 128
708 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
709 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
710 * component into the URB, Component 1 must be specified as
711 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
712 * order to output a 128-bit vertex element, or Components 1-3 must
713 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
714 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
715 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
718 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
719 /* Store vertex elements which correspond to double and dvec2 vertex
720 * shader inputs as 128-bit vertex elements, instead of 256-bits.
722 comp2
= VFCOMP_NOSTORE
;
723 comp3
= VFCOMP_NOSTORE
;
727 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
728 .VertexBufferIndex
= input
->buffer
,
730 .SourceElementFormat
= upload_format
,
731 .SourceElementOffset
= offset
,
732 .Component0Control
= comp0
,
733 .Component1Control
= comp1
,
734 .Component2Control
= comp2
,
735 .Component3Control
= comp3
,
737 .DestinationElementOffset
= i
* 4,
741 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
742 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
746 if (needs_sgvs_element
) {
747 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
749 .Component0Control
= VFCOMP_STORE_0
,
750 .Component1Control
= VFCOMP_STORE_0
,
751 .Component2Control
= VFCOMP_STORE_0
,
752 .Component3Control
= VFCOMP_STORE_0
,
754 .DestinationElementOffset
= i
* 4,
759 if (vs_prog_data
->uses_basevertex
||
760 vs_prog_data
->uses_baseinstance
) {
761 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
762 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
763 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
764 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
767 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
768 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
769 if (vs_prog_data
->uses_basevertex
)
770 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
772 if (vs_prog_data
->uses_baseinstance
)
773 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
775 if (vs_prog_data
->uses_vertexid
)
776 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
778 if (vs_prog_data
->uses_instanceid
)
779 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
782 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
783 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
786 if (vs_prog_data
->uses_drawid
) {
787 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
789 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
790 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
791 .Component0Control
= VFCOMP_STORE_SRC
,
792 .Component1Control
= VFCOMP_STORE_0
,
793 .Component2Control
= VFCOMP_STORE_0
,
794 .Component3Control
= VFCOMP_STORE_0
,
796 .DestinationElementOffset
= i
* 4,
800 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
801 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
805 if (gen6_edgeflag_input
) {
806 const uint32_t format
=
807 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
809 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
811 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
812 .EdgeFlagEnable
= true,
813 .SourceElementFormat
= format
,
814 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
815 .Component0Control
= VFCOMP_STORE_SRC
,
816 .Component1Control
= VFCOMP_STORE_0
,
817 .Component2Control
= VFCOMP_STORE_0
,
818 .Component3Control
= VFCOMP_STORE_0
,
821 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
822 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
827 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
828 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
829 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
830 unsigned element_index
;
832 /* The edge flag element is reordered to be the last one in the code
833 * above so we need to compensate for that in the element indices used
836 if (input
== gen6_edgeflag_input
)
837 element_index
= nr_elements
- 1;
841 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
842 vfi
.VertexElementIndex
= element_index
;
843 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
844 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
848 if (vs_prog_data
->uses_drawid
) {
849 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
851 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
852 vfi
.VertexElementIndex
= element
;
858 static const struct brw_tracked_state
genX(vertices
) = {
860 .mesa
= _NEW_POLYGON
,
861 .brw
= BRW_NEW_BATCH
|
864 BRW_NEW_VS_PROG_DATA
,
866 .emit
= genX(emit_vertices
),
870 genX(emit_index_buffer
)(struct brw_context
*brw
)
872 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
874 if (index_buffer
== NULL
)
877 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
878 #if GEN_GEN < 8 && !GEN_IS_HASWELL
879 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
881 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
882 ib
.BufferStartingAddress
= vertex_bo(brw
->ib
.bo
, 0);
884 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
885 ib
.BufferSize
= brw
->ib
.size
;
887 ib
.BufferEndingAddress
= vertex_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
892 static const struct brw_tracked_state
genX(index_buffer
) = {
895 .brw
= BRW_NEW_BATCH
|
897 BRW_NEW_INDEX_BUFFER
,
899 .emit
= genX(emit_index_buffer
),
902 #if GEN_IS_HASWELL || GEN_GEN >= 8
904 genX(upload_cut_index
)(struct brw_context
*brw
)
906 const struct gl_context
*ctx
= &brw
->ctx
;
908 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
909 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
910 vf
.IndexedDrawCutIndexEnable
= true;
911 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
916 const struct brw_tracked_state
genX(cut_index
) = {
918 .mesa
= _NEW_TRANSFORM
,
919 .brw
= BRW_NEW_INDEX_BUFFER
,
921 .emit
= genX(upload_cut_index
),
927 * Determine the appropriate attribute override value to store into the
928 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
929 * override value contains two pieces of information: the location of the
930 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
931 * flag indicating whether to "swizzle" the attribute based on the direction
932 * the triangle is facing.
934 * If an attribute is "swizzled", then the given VUE location is used for
935 * front-facing triangles, and the VUE location that immediately follows is
936 * used for back-facing triangles. We use this to implement the mapping from
937 * gl_FrontColor/gl_BackColor to gl_Color.
939 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
940 * being instructed to begin reading attribute data. It can be set to a
941 * nonzero value to prevent the SF unit from wasting time reading elements of
942 * the VUE that are not needed by the fragment shader. It is measured in
943 * 256-bit increments.
946 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
947 const struct brw_vue_map
*vue_map
,
948 int urb_entry_read_offset
, int fs_attr
,
949 bool two_side_color
, uint32_t *max_source_attr
)
951 /* Find the VUE slot for this attribute. */
952 int slot
= vue_map
->varying_to_slot
[fs_attr
];
954 /* Viewport and Layer are stored in the VUE header. We need to override
955 * them to zero if earlier stages didn't write them, as GL requires that
956 * they read back as zero when not explicitly set.
958 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
959 attr
->ComponentOverrideX
= true;
960 attr
->ComponentOverrideW
= true;
961 attr
->ConstantSource
= CONST_0000
;
963 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
964 attr
->ComponentOverrideY
= true;
965 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
966 attr
->ComponentOverrideZ
= true;
971 /* If there was only a back color written but not front, use back
972 * as the color instead of undefined
974 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
975 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
976 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
977 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
980 /* This attribute does not exist in the VUE--that means that the vertex
981 * shader did not write to it. This means that either:
983 * (a) This attribute is a texture coordinate, and it is going to be
984 * replaced with point coordinates (as a consequence of a call to
985 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
986 * hardware will ignore whatever attribute override we supply.
988 * (b) This attribute is read by the fragment shader but not written by
989 * the vertex shader, so its value is undefined. Therefore the
990 * attribute override we supply doesn't matter.
992 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
993 * previous shader stage.
995 * Note that we don't have to worry about the cases where the attribute
996 * is gl_PointCoord or is undergoing point sprite coordinate
997 * replacement, because in those cases, this function isn't called.
999 * In case (c), we need to program the attribute overrides so that the
1000 * primitive ID will be stored in this slot. In every other case, the
1001 * attribute override we supply doesn't matter. So just go ahead and
1002 * program primitive ID in every case.
1004 attr
->ComponentOverrideW
= true;
1005 attr
->ComponentOverrideX
= true;
1006 attr
->ComponentOverrideY
= true;
1007 attr
->ComponentOverrideZ
= true;
1008 attr
->ConstantSource
= PRIM_ID
;
1012 /* Compute the location of the attribute relative to urb_entry_read_offset.
1013 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1014 * it counts for two 128-bit VUE slots.
1016 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1017 assert(source_attr
>= 0 && source_attr
< 32);
1019 /* If we are doing two-sided color, and the VUE slot following this one
1020 * represents a back-facing color, then we need to instruct the SF unit to
1021 * do back-facing swizzling.
1023 bool swizzling
= two_side_color
&&
1024 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1025 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1026 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1027 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1029 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1030 if (*max_source_attr
< source_attr
+ swizzling
)
1031 *max_source_attr
= source_attr
+ swizzling
;
1033 attr
->SourceAttribute
= source_attr
;
1035 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1040 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1041 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1042 uint32_t *point_sprite_enables
,
1043 uint32_t *urb_entry_read_length
,
1044 uint32_t *urb_entry_read_offset
)
1046 const struct gl_context
*ctx
= &brw
->ctx
;
1049 const struct gl_point_attrib
*point
= &ctx
->Point
;
1051 /* BRW_NEW_FS_PROG_DATA */
1052 const struct brw_wm_prog_data
*wm_prog_data
=
1053 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1054 uint32_t max_source_attr
= 0;
1056 *point_sprite_enables
= 0;
1058 /* BRW_NEW_FRAGMENT_PROGRAM
1060 * If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
1061 * the full vertex header. Otherwise, we can program the SF to start
1062 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
1063 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1064 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
1067 bool fs_needs_vue_header
= brw
->fragment_program
->info
.inputs_read
&
1068 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1070 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
1072 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1073 * description of dw10 Point Sprite Texture Coordinate Enable:
1075 * "This field must be programmed to zero when non-point primitives
1078 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1079 * must be programmed to zero when rendering non-point primitives, but
1080 * the IvyBridge PRM does, and if we don't, we get garbage.
1082 * This is not required on Haswell, as the hardware ignores this state
1083 * when drawing non-points -- although we do still need to be careful to
1084 * correctly set the attr overrides.
1087 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1089 bool drawing_points
= brw_is_drawing_points(brw
);
1091 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1092 int input_index
= wm_prog_data
->urb_setup
[attr
];
1094 if (input_index
< 0)
1098 bool point_sprite
= false;
1099 if (drawing_points
) {
1100 if (point
->PointSprite
&&
1101 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1102 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1103 point_sprite
= true;
1106 if (attr
== VARYING_SLOT_PNTC
)
1107 point_sprite
= true;
1110 *point_sprite_enables
|= (1 << input_index
);
1113 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1114 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1116 if (!point_sprite
) {
1117 genX(get_attr_override
)(&attribute
,
1118 &brw
->vue_map_geom_out
,
1119 *urb_entry_read_offset
, attr
,
1120 brw
->ctx
.VertexProgram
._TwoSideEnabled
,
1124 /* The hardware can only do the overrides on 16 overrides at a
1125 * time, and the other up to 16 have to be lined up so that the
1126 * input index = the output index. We'll need to do some
1127 * tweaking to make sure that's the case.
1129 if (input_index
< 16)
1130 attr_overrides
[input_index
] = attribute
;
1132 assert(attribute
.SourceAttribute
== input_index
);
1135 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1136 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1138 * "This field should be set to the minimum length required to read the
1139 * maximum source attribute. The maximum source attribute is indicated
1140 * by the maximum value of the enabled Attribute # Source Attribute if
1141 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1142 * enable is not set.
1143 * read_length = ceiling((max_source_attr + 1) / 2)
1145 * [errata] Corruption/Hang possible if length programmed larger than
1148 * Similar text exists for Ivy Bridge.
1150 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1154 /* ---------------------------------------------------------------------- */
1158 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1160 struct gl_context
*ctx
= &brw
->ctx
;
1163 struct intel_renderbuffer
*depth_irb
=
1164 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1167 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1170 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1171 const int b
= stencil
->_BackFace
;
1174 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1177 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, wmds
) {
1179 if (depth
->Test
&& depth_irb
) {
1180 wmds
.DepthTestEnable
= true;
1181 wmds
.DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1182 wmds
.DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1185 if (brw
->stencil_enabled
) {
1186 wmds
.StencilTestEnable
= true;
1187 wmds
.StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1188 wmds
.StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1190 wmds
.StencilTestFunction
=
1191 intel_translate_compare_func(stencil
->Function
[0]);
1192 wmds
.StencilFailOp
=
1193 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1194 wmds
.StencilPassDepthPassOp
=
1195 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1196 wmds
.StencilPassDepthFailOp
=
1197 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1199 wmds
.StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1201 if (brw
->stencil_two_sided
) {
1202 wmds
.DoubleSidedStencilEnable
= true;
1203 wmds
.BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1204 wmds
.BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1206 wmds
.BackfaceStencilTestFunction
=
1207 intel_translate_compare_func(stencil
->Function
[b
]);
1208 wmds
.BackfaceStencilFailOp
=
1209 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1210 wmds
.BackfaceStencilPassDepthPassOp
=
1211 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1212 wmds
.BackfaceStencilPassDepthFailOp
=
1213 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1217 wmds
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1218 wmds
.BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1224 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1225 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1226 ptr
.DEPTH_STENCIL_STATEChange
= true;
1229 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1230 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1235 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1237 .mesa
= _NEW_BUFFERS
|
1240 .brw
= BRW_NEW_BLORP
|
1241 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1243 BRW_NEW_STATE_BASE_ADDRESS
),
1245 .emit
= genX(upload_depth_stencil_state
),
1249 /* ---------------------------------------------------------------------- */
1253 genX(upload_clip_state
)(struct brw_context
*brw
)
1255 struct gl_context
*ctx
= &brw
->ctx
;
1258 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1260 /* BRW_NEW_FS_PROG_DATA */
1261 struct brw_wm_prog_data
*wm_prog_data
=
1262 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1264 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1265 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1267 if (wm_prog_data
->barycentric_interp_modes
&
1268 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1269 clip
.NonPerspectiveBarycentricEnable
= true;
1272 clip
.EarlyCullEnable
= true;
1276 clip
.FrontWinding
= ctx
->Polygon
._FrontBit
== _mesa_is_user_fbo(fb
);
1278 if (ctx
->Polygon
.CullFlag
) {
1279 switch (ctx
->Polygon
.CullFaceMode
) {
1281 clip
.CullMode
= CULLMODE_FRONT
;
1284 clip
.CullMode
= CULLMODE_BACK
;
1286 case GL_FRONT_AND_BACK
:
1287 clip
.CullMode
= CULLMODE_BOTH
;
1290 unreachable("Should not get here: invalid CullFlag");
1293 clip
.CullMode
= CULLMODE_NONE
;
1298 clip
.UserClipDistanceCullTestEnableBitmask
=
1299 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1301 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1305 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1306 clip
.TriangleStripListProvokingVertexSelect
= 0;
1307 clip
.TriangleFanProvokingVertexSelect
= 1;
1308 clip
.LineStripListProvokingVertexSelect
= 0;
1310 clip
.TriangleStripListProvokingVertexSelect
= 2;
1311 clip
.TriangleFanProvokingVertexSelect
= 2;
1312 clip
.LineStripListProvokingVertexSelect
= 1;
1315 /* _NEW_TRANSFORM */
1316 clip
.UserClipDistanceClipTestEnableBitmask
=
1317 ctx
->Transform
.ClipPlanesEnabled
;
1320 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1323 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1324 clip
.APIMode
= APIMODE_D3D
;
1326 clip
.APIMode
= APIMODE_OGL
;
1328 clip
.GuardbandClipTestEnable
= true;
1330 /* BRW_NEW_VIEWPORT_COUNT */
1331 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1333 if (ctx
->RasterDiscard
) {
1334 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1336 perf_debug("Rasterizer discard is currently implemented via the "
1337 "clipper; having the GS not write primitives would "
1338 "likely be faster.\n");
1341 clip
.ClipMode
= CLIPMODE_NORMAL
;
1344 clip
.ClipEnable
= true;
1347 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1349 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1350 clip
.ViewportXYClipTestEnable
= true;
1352 clip
.MinimumPointWidth
= 0.125;
1353 clip
.MaximumPointWidth
= 255.875;
1354 clip
.MaximumVPIndex
= viewport_count
- 1;
1355 if (_mesa_geometric_layers(fb
) == 0)
1356 clip
.ForceZeroRTAIndexEnable
= true;
1360 static const struct brw_tracked_state
genX(clip_state
) = {
1362 .mesa
= _NEW_BUFFERS
|
1366 .brw
= BRW_NEW_BLORP
|
1368 BRW_NEW_FS_PROG_DATA
|
1369 BRW_NEW_GS_PROG_DATA
|
1370 BRW_NEW_VS_PROG_DATA
|
1371 BRW_NEW_META_IN_PROGRESS
|
1373 BRW_NEW_RASTERIZER_DISCARD
|
1374 BRW_NEW_TES_PROG_DATA
|
1375 BRW_NEW_VIEWPORT_COUNT
,
1377 .emit
= genX(upload_clip_state
),
1381 /* ---------------------------------------------------------------------- */
1384 genX(upload_sf
)(struct brw_context
*brw
)
1386 struct gl_context
*ctx
= &brw
->ctx
;
1391 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1392 UNUSED
const bool multisampled_fbo
=
1393 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1397 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1399 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1401 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1402 sf
.KernelStartPointer
= KSP_ro(brw
, brw
->sf
.prog_offset
);
1403 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1404 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1405 sf
.DispatchGRFStartRegisterForURBData
= 3;
1406 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1407 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1408 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1409 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1411 /* STATE_PREFETCH command description describes this state as being
1412 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1415 sf
.SetupViewportStateOffset
=
1416 instruction_ro_bo(brw
->batch
.bo
, brw
->sf
.vp_offset
);
1418 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1420 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1421 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1423 sf
.MaximumNumberofThreads
=
1424 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1426 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1428 sf
.DestinationOriginHorizontalBias
= 0.5;
1429 sf
.DestinationOriginVerticalBias
= 0.5;
1431 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1432 sf
.StatisticsEnable
= true;
1434 sf
.ViewportTransformEnable
= true;
1438 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1443 sf
.FrontWinding
= ctx
->Polygon
._FrontBit
== render_to_fbo
;
1445 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1446 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1447 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1449 switch (ctx
->Polygon
.FrontMode
) {
1451 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1454 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1457 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1460 unreachable("not reached");
1463 switch (ctx
->Polygon
.BackMode
) {
1465 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1468 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1471 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1474 unreachable("not reached");
1477 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1478 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1480 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1481 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1482 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1485 sf
.ScissorRectangleEnable
= true;
1487 if (ctx
->Polygon
.CullFlag
) {
1488 switch (ctx
->Polygon
.CullFaceMode
) {
1490 sf
.CullMode
= CULLMODE_FRONT
;
1493 sf
.CullMode
= CULLMODE_BACK
;
1495 case GL_FRONT_AND_BACK
:
1496 sf
.CullMode
= CULLMODE_BOTH
;
1499 unreachable("not reached");
1502 sf
.CullMode
= CULLMODE_NONE
;
1506 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1513 if (brw
->is_cherryview
)
1514 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1516 sf
.LineWidth
= brw_get_line_width(brw
);
1518 sf
.LineWidth
= brw_get_line_width(brw
);
1521 if (ctx
->Line
.SmoothFlag
) {
1522 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1524 sf
.AntiAliasingEnable
= true;
1528 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1529 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1530 /* Clamp to the hardware limits */
1531 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1533 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1534 if (use_state_point_size(brw
))
1535 sf
.PointWidthSource
= State
;
1538 /* _NEW_POINT | _NEW_MULTISAMPLE */
1539 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1540 !ctx
->Point
.PointSprite
)
1541 sf
.SmoothPointEnable
= true;
1544 #if GEN_IS_G4X || GEN_GEN >= 5
1545 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1549 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1550 sf
.TriangleStripListProvokingVertexSelect
= 2;
1551 sf
.TriangleFanProvokingVertexSelect
= 2;
1552 sf
.LineStripListProvokingVertexSelect
= 1;
1554 sf
.TriangleFanProvokingVertexSelect
= 1;
1558 /* BRW_NEW_FS_PROG_DATA */
1559 const struct brw_wm_prog_data
*wm_prog_data
=
1560 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1562 sf
.AttributeSwizzleEnable
= true;
1563 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1566 * Window coordinates in an FBO are inverted, which means point
1567 * sprite origin must be inverted, too.
1569 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1570 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1572 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1575 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1576 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1578 uint32_t urb_entry_read_length
;
1579 uint32_t urb_entry_read_offset
;
1580 uint32_t point_sprite_enables
;
1581 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1582 &urb_entry_read_length
,
1583 &urb_entry_read_offset
);
1584 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1585 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1586 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1587 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1592 static const struct brw_tracked_state
genX(sf_state
) = {
1594 .mesa
= _NEW_LIGHT
|
1598 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1599 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1600 .brw
= BRW_NEW_BLORP
|
1601 BRW_NEW_VUE_MAP_GEOM_OUT
|
1602 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1603 BRW_NEW_PROGRAM_CACHE
|
1604 BRW_NEW_SF_PROG_DATA
|
1608 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1609 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1610 BRW_NEW_GS_PROG_DATA
|
1612 BRW_NEW_TES_PROG_DATA
1614 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1615 BRW_NEW_FRAGMENT_PROGRAM
1618 .emit
= genX(upload_sf
),
1621 /* ---------------------------------------------------------------------- */
1625 genX(upload_wm
)(struct brw_context
*brw
)
1627 struct gl_context
*ctx
= &brw
->ctx
;
1629 /* BRW_NEW_FS_PROG_DATA */
1630 const struct brw_wm_prog_data
*wm_prog_data
=
1631 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1633 UNUSED
bool writes_depth
=
1634 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1637 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1638 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1640 /* We can't fold this into gen6_upload_wm_push_constants(), because
1641 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1642 * (3DSTATE_CONSTANT_PS [DevSNB]):
1644 * "[DevSNB]: This packet must be followed by WM_STATE."
1646 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1647 if (wm_prog_data
->base
.nr_params
!= 0) {
1648 wmcp
.Buffer0Valid
= true;
1649 /* Pointer to the WM constant buffer. Covered by the set of
1650 * state flags from gen6_upload_wm_push_constants.
1652 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1653 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1658 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1659 wm
.StatisticsEnable
= true;
1660 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1661 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1664 if (wm_prog_data
->base
.use_alt_mode
)
1665 wm
.FloatingPointMode
= Alternate
;
1667 wm
.SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1668 wm
.BindingTableEntryCount
= wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1669 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1670 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1671 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1672 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1673 wm_prog_data
->base
.dispatch_grf_start_reg
;
1674 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1675 wm_prog_data
->dispatch_grf_start_reg_2
;
1676 wm
.KernelStartPointer0
= stage_state
->prog_offset
;
1677 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1678 wm_prog_data
->prog_offset_2
;
1679 wm
.DualSourceBlendEnable
=
1680 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1681 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1682 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1683 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1685 /* From the SNB PRM, volume 2 part 1, page 281:
1686 * "If the PS kernel does not need the Position XY Offsets
1687 * to compute a Position XY value, then this field should be
1688 * programmed to POSOFFSET_NONE."
1690 * "SW Recommendation: If the PS kernel needs the Position Offsets
1691 * to compute a Position XY value, this field should match Position
1692 * ZW Interpolation Mode to ensure a consistent position.xyzw
1694 * We only require XY sample offsets. So, this recommendation doesn't
1695 * look useful at the moment. We might need this in future.
1697 if (wm_prog_data
->uses_pos_offset
)
1698 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1700 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1702 if (wm_prog_data
->base
.total_scratch
) {
1703 wm
.ScratchSpaceBasePointer
=
1704 render_bo(stage_state
->scratch_bo
,
1705 ffs(stage_state
->per_thread_scratch
) - 11);
1708 wm
.PixelShaderComputedDepth
= writes_depth
;
1711 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1714 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1717 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1718 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1722 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1724 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1725 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1726 if (wm_prog_data
->uses_kill
||
1727 _mesa_is_alpha_test_enabled(ctx
) ||
1728 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1729 wm_prog_data
->uses_omask
) {
1730 wm
.PixelShaderKillsPixel
= true;
1733 /* _NEW_BUFFERS | _NEW_COLOR */
1734 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1735 wm_prog_data
->has_side_effects
|| wm
.PixelShaderKillsPixel
) {
1736 wm
.ThreadDispatchEnable
= true;
1738 if (multisampled_fbo
) {
1739 /* _NEW_MULTISAMPLE */
1740 if (ctx
->Multisample
.Enabled
)
1741 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1743 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1745 if (wm_prog_data
->persample_dispatch
)
1746 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1748 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1750 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1751 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1755 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1756 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1759 /* The "UAV access enable" bits are unnecessary on HSW because they only
1760 * seem to have an effect on the HW-assisted coherency mechanism which we
1761 * don't need, and the rasterization-related UAV_ONLY flag and the
1762 * DISPATCH_ENABLE bit can be set independently from it.
1763 * C.f. gen8_upload_ps_extra().
1765 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1769 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1770 wm_prog_data
->has_side_effects
)
1776 /* BRW_NEW_FS_PROG_DATA */
1777 if (wm_prog_data
->early_fragment_tests
)
1778 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1779 else if (wm_prog_data
->has_side_effects
)
1780 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1785 static const struct brw_tracked_state
genX(wm_state
) = {
1789 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1793 (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
1794 .brw
= BRW_NEW_BLORP
|
1795 BRW_NEW_FS_PROG_DATA
|
1796 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
1798 .emit
= genX(upload_wm
),
1802 /* ---------------------------------------------------------------------- */
1804 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1805 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
1806 pkt.SamplerCount = \
1807 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1808 pkt.BindingTableEntryCount = \
1809 stage_prog_data->binding_table.size_bytes / 4; \
1810 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
1812 if (stage_prog_data->total_scratch) { \
1813 pkt.ScratchSpaceBasePointer = \
1814 render_bo(stage_state->scratch_bo, 0); \
1815 pkt.PerThreadScratchSpace = \
1816 ffs(stage_state->per_thread_scratch) - 11; \
1819 pkt.DispatchGRFStartRegisterForURBData = \
1820 stage_prog_data->dispatch_grf_start_reg; \
1821 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1822 pkt.prefix##URBEntryReadOffset = 0; \
1824 pkt.StatisticsEnable = true; \
1828 genX(upload_vs_state
)(struct brw_context
*brw
)
1830 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
1831 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1832 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
1834 /* BRW_NEW_VS_PROG_DATA */
1835 const struct brw_vue_prog_data
*vue_prog_data
=
1836 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
1837 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
1839 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
1840 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
1843 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1844 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1846 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
1847 * command that causes the VS Function Enable to toggle. Pipeline
1848 * flush can be executed by sending a PIPE_CONTROL command with CS
1849 * stall bit set and a post sync operation.
1851 * We've already done such a flush at the start of state upload, so we
1852 * don't need to do another one here.
1854 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
1855 if (stage_state
->push_const_size
!= 0) {
1856 cvs
.Buffer0Valid
= true;
1857 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
1858 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1863 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
1864 gen7_emit_vs_workaround_flush(brw
);
1867 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
1869 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1870 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
1872 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1874 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1877 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
1878 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
1879 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
1881 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
1882 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1884 vs
.MaximumNumberofThreads
=
1885 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
1887 vs
.StatisticsEnable
= false;
1888 vs
.SamplerStatePointer
=
1889 instruction_ro_bo(brw
->batch
.bo
, stage_state
->sampler_offset
);
1893 /* Force single program flow on Ironlake. We cannot reliably get
1894 * all applications working without it. See:
1895 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
1897 * The most notable and reliably failing application is the Humus
1900 vs
.SingleProgramFlow
= true;
1901 vs
.SamplerCount
= 0; /* hardware requirement */
1905 vs
.SIMD8DispatchEnable
=
1906 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
1908 vs
.UserClipDistanceCullTestEnableBitmask
=
1909 vue_prog_data
->cull_distance_mask
;
1914 /* Based on my reading of the simulator, the VS constants don't get
1915 * pulled into the VS FF unit until an appropriate pipeline flush
1916 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
1917 * references to them into a little FIFO. The flushes are common,
1918 * but don't reliably happen between this and a 3DPRIMITIVE, causing
1919 * the primitive to use the wrong constants. Then the FIFO
1920 * containing the constant setup gets added to again on the next
1921 * constants change, and eventually when a flush does happen the
1922 * unit is overwhelmed by constant changes and dies.
1924 * To avoid this, send a PIPE_CONTROL down the line that will
1925 * update the unit immediately loading the constants. The flush
1926 * type bits here were those set by the STATE_BASE_ADDRESS whose
1927 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
1928 * bug reports that led to this workaround, and may be more than
1929 * what is strictly required to avoid the issue.
1931 brw_emit_pipe_control_flush(brw
,
1932 PIPE_CONTROL_DEPTH_STALL
|
1933 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1934 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
1938 static const struct brw_tracked_state
genX(vs_state
) = {
1940 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
1941 .brw
= BRW_NEW_BATCH
|
1944 BRW_NEW_VS_PROG_DATA
|
1945 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
1946 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1947 BRW_NEW_PROGRAM_CACHE
|
1948 BRW_NEW_SAMPLER_STATE_TABLE
|
1952 .emit
= genX(upload_vs_state
),
1955 /* ---------------------------------------------------------------------- */
1958 genX(upload_cc_viewport
)(struct brw_context
*brw
)
1960 struct gl_context
*ctx
= &brw
->ctx
;
1962 /* BRW_NEW_VIEWPORT_COUNT */
1963 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1965 struct GENX(CC_VIEWPORT
) ccv
;
1966 uint32_t cc_vp_offset
;
1968 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
1971 for (unsigned i
= 0; i
< viewport_count
; i
++) {
1972 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
1973 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
1974 if (ctx
->Transform
.DepthClamp
) {
1975 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
1976 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
1978 ccv
.MinimumDepth
= 0.0;
1979 ccv
.MaximumDepth
= 1.0;
1981 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
1982 cc_map
+= GENX(CC_VIEWPORT_length
);
1986 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1987 ptr
.CCViewportPointer
= cc_vp_offset
;
1990 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
1991 vp
.CCViewportStateChange
= 1;
1992 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1995 brw
->cc
.vp_offset
= cc_vp_offset
;
1996 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2000 const struct brw_tracked_state
genX(cc_vp
) = {
2002 .mesa
= _NEW_TRANSFORM
|
2004 .brw
= BRW_NEW_BATCH
|
2006 BRW_NEW_VIEWPORT_COUNT
,
2008 .emit
= genX(upload_cc_viewport
)
2011 /* ---------------------------------------------------------------------- */
2014 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2015 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2016 struct GENX(SCISSOR_RECT
) *sc
)
2020 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2021 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2022 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2023 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2024 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2026 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2027 /* If the scissor was out of bounds and got clamped to 0 width/height
2028 * at the bounds, the subtraction of 1 from maximums could produce a
2029 * negative number and thus not clip anything. Instead, just provide
2030 * a min > max scissor inside the bounds, which produces the expected
2033 sc
->ScissorRectangleXMin
= 1;
2034 sc
->ScissorRectangleXMax
= 0;
2035 sc
->ScissorRectangleYMin
= 1;
2036 sc
->ScissorRectangleYMax
= 0;
2037 } else if (render_to_fbo
) {
2038 /* texmemory: Y=0=bottom */
2039 sc
->ScissorRectangleXMin
= bbox
[0];
2040 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2041 sc
->ScissorRectangleYMin
= bbox
[2];
2042 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2044 /* memory: Y=0=top */
2045 sc
->ScissorRectangleXMin
= bbox
[0];
2046 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2047 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2048 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2054 genX(upload_scissor_state
)(struct brw_context
*brw
)
2056 struct gl_context
*ctx
= &brw
->ctx
;
2057 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2058 struct GENX(SCISSOR_RECT
) scissor
;
2059 uint32_t scissor_state_offset
;
2060 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2061 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2062 uint32_t *scissor_map
;
2064 /* BRW_NEW_VIEWPORT_COUNT */
2065 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2067 scissor_map
= brw_state_batch(
2068 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2069 32, &scissor_state_offset
);
2071 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2073 /* The scissor only needs to handle the intersection of drawable and
2074 * scissor rect. Clipping to the boundaries of static shared buffers
2075 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2077 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2078 * inclusive but max is exclusive.
2080 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2081 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2082 GENX(SCISSOR_RECT_pack
)(
2083 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2086 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2087 ptr
.ScissorRectPointer
= scissor_state_offset
;
2091 static const struct brw_tracked_state
genX(scissor_state
) = {
2093 .mesa
= _NEW_BUFFERS
|
2096 .brw
= BRW_NEW_BATCH
|
2098 BRW_NEW_VIEWPORT_COUNT
,
2100 .emit
= genX(upload_scissor_state
),
2104 /* ---------------------------------------------------------------------- */
2107 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2108 float m00
, float m11
, float m30
, float m31
,
2109 float *xmin
, float *xmax
,
2110 float *ymin
, float *ymax
)
2112 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2113 * Strips and Fans documentation:
2115 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2116 * fixed-point "guardband" range supported by the rasterization hardware"
2120 * "In almost all circumstances, if an object’s vertices are actually
2121 * modified by this clamping (i.e., had X or Y coordinates outside of
2122 * the guardband extent the rendered object will not match the intended
2123 * result. Therefore software should take steps to ensure that this does
2124 * not happen - e.g., by clipping objects such that they do not exceed
2125 * these limits after the Drawing Rectangle is applied."
2127 * I believe the fundamental restriction is that the rasterizer (in
2128 * the SF/WM stages) have a limit on the number of pixels that can be
2129 * rasterized. We need to ensure any coordinates beyond the rasterizer
2130 * limit are handled by the clipper. So effectively that limit becomes
2131 * the clipper's guardband size.
2133 * It goes on to say:
2135 * "In addition, in order to be correctly rendered, objects must have a
2136 * screenspace bounding box not exceeding 8K in the X or Y direction.
2137 * This additional restriction must also be comprehended by software,
2138 * i.e., enforced by use of clipping."
2140 * This makes no sense. Gen7+ hardware supports 16K render targets,
2141 * and you definitely need to be able to draw polygons that fill the
2142 * surface. Our assumption is that the rasterizer was limited to 8K
2143 * on Sandybridge, which only supports 8K surfaces, and it was actually
2144 * increased to 16K on Ivybridge and later.
2146 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2148 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2150 if (m00
!= 0 && m11
!= 0) {
2151 /* First, we compute the screen-space render area */
2152 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2153 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2154 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2155 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2157 /* We want the guardband to be centered on that */
2158 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2159 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2160 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2161 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2163 /* Now we need it in native device coordinates */
2164 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2165 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2166 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2167 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2169 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2170 * flipped upside-down. X should be fine though.
2172 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2173 *xmin
= ndc_gb_xmin
;
2174 *xmax
= ndc_gb_xmax
;
2175 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2176 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2178 /* The viewport scales to 0, so nothing will be rendered. */
2187 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2189 struct gl_context
*ctx
= &brw
->ctx
;
2190 float y_scale
, y_bias
;
2192 /* BRW_NEW_VIEWPORT_COUNT */
2193 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2196 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2197 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2198 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2202 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2203 uint32_t sf_clip_vp_offset
;
2204 uint32_t *sf_clip_map
=
2205 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2206 64, &sf_clip_vp_offset
);
2208 struct GENX(SF_VIEWPORT
) sfv
;
2209 struct GENX(CLIP_VIEWPORT
) clv
;
2210 uint32_t sf_vp_offset
, clip_vp_offset
;
2212 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2214 uint32_t *clip_map
=
2215 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2216 32, &clip_vp_offset
);
2220 if (render_to_fbo
) {
2225 y_bias
= (float)fb_height
;
2228 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2229 /* _NEW_VIEWPORT: Guardband Clipping */
2230 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2231 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2233 sfv
.ViewportMatrixElementm00
= scale
[0];
2234 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2235 sfv
.ViewportMatrixElementm22
= scale
[2],
2236 sfv
.ViewportMatrixElementm30
= translate
[0],
2237 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2238 sfv
.ViewportMatrixElementm32
= translate
[2],
2239 brw_calculate_guardband_size(fb_width
, fb_height
,
2240 sfv
.ViewportMatrixElementm00
,
2241 sfv
.ViewportMatrixElementm11
,
2242 sfv
.ViewportMatrixElementm30
,
2243 sfv
.ViewportMatrixElementm31
,
2244 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2247 clv
.XMinClipGuardband
= gb_xmin
;
2248 clv
.XMaxClipGuardband
= gb_xmax
;
2249 clv
.YMinClipGuardband
= gb_ymin
;
2250 clv
.YMaxClipGuardband
= gb_ymax
;
2253 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2254 &sfv
.ScissorRectangle
);
2256 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2257 * The hardware will take the intersection of the drawing rectangle,
2258 * scissor rectangle, and the viewport extents. We don't need to be
2259 * smart, and can therefore just program the viewport extents.
2261 const float viewport_Xmax
=
2262 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2263 const float viewport_Ymax
=
2264 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2266 if (render_to_fbo
) {
2267 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2268 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2269 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2270 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2272 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2273 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2274 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2275 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2280 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2281 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2283 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2284 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2285 sf_map
+= GENX(SF_VIEWPORT_length
);
2286 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2291 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2292 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2295 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2296 vp
.SFViewportStateChange
= 1;
2297 vp
.CLIPViewportStateChange
= 1;
2298 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2299 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2302 brw
->sf
.vp_offset
= sf_vp_offset
;
2303 brw
->clip
.vp_offset
= clip_vp_offset
;
2304 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2308 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2310 .mesa
= _NEW_BUFFERS
|
2312 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2313 .brw
= BRW_NEW_BATCH
|
2315 BRW_NEW_VIEWPORT_COUNT
,
2317 .emit
= genX(upload_sf_clip_viewport
),
2320 /* ---------------------------------------------------------------------- */
2324 genX(upload_gs_state
)(struct brw_context
*brw
)
2326 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2327 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2328 /* BRW_NEW_GEOMETRY_PROGRAM */
2329 bool active
= brw
->geometry_program
;
2331 /* BRW_NEW_GS_PROG_DATA */
2332 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2333 const struct brw_vue_prog_data
*vue_prog_data
=
2334 brw_vue_prog_data(stage_prog_data
);
2336 const struct brw_gs_prog_data
*gs_prog_data
=
2337 brw_gs_prog_data(stage_prog_data
);
2341 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2342 if (active
&& stage_state
->push_const_size
!= 0) {
2343 cgs
.Buffer0Valid
= true;
2344 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2345 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2350 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2352 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2353 * Geometry > Geometry Shader > State:
2355 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2356 * whole fixed function pipeline when the GS enable changes value in
2359 * The hardware architects have clarified that in this context "flush the
2360 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2363 if (brw
->gt
== 2 && brw
->gs
.enabled
!= active
)
2364 gen7_emit_cs_stall_flush(brw
);
2368 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2369 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2372 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2373 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2374 gs
.ControlDataHeaderSize
=
2375 gs_prog_data
->control_data_header_size_hwords
;
2377 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2378 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2380 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2382 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2385 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2386 * Ivy Bridge and Haswell.
2388 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2389 * strip to be delivered to the geometry shader in an order that does
2390 * not strictly follow the OpenGL spec, but preserves triangle
2391 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2392 * the geometry shader sees triangles:
2394 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2396 * (Clearing the bit is even worse, because it fails to preserve
2399 * Triangle strips with adjacency always ordered in a way that preserves
2400 * triangle orientation but does not strictly follow the OpenGL spec,
2401 * regardless of the setting of this bit.
2403 * On Haswell, both triangle strips and triangle strips with adjacency
2404 * are always ordered in a way that preserves triangle orientation.
2405 * Setting this bit causes the ordering to strictly follow the OpenGL
2408 * So in either case we want to set the bit. Unfortunately on Ivy
2409 * Bridge this will get the order close to correct but not perfect.
2411 gs
.ReorderMode
= TRAILING
;
2412 gs
.MaximumNumberofThreads
=
2413 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2414 : (devinfo
->max_gs_threads
- 1);
2417 gs
.SOStatisticsEnable
= true;
2418 gs
.RenderingEnabled
= 1;
2419 if (brw
->geometry_program
->info
.has_transform_feedback_varyings
)
2420 gs
.SVBIPayloadEnable
= true;
2422 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2423 * was previously done for gen6.
2425 * TODO: test with both disabled to see if the HW is behaving
2426 * as expected, like in gen7.
2428 gs
.SingleProgramFlow
= true;
2429 gs
.VectorMaskEnable
= true;
2433 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2435 if (gs_prog_data
->static_vertex_count
!= -1) {
2436 gs
.StaticOutput
= true;
2437 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2439 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2441 gs
.UserClipDistanceCullTestEnableBitmask
=
2442 vue_prog_data
->cull_distance_mask
;
2444 const int urb_entry_write_offset
= 1;
2445 const uint32_t urb_entry_output_length
=
2446 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2447 urb_entry_write_offset
;
2449 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2450 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2454 } else if (brw
->ff_gs
.prog_active
) {
2455 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
2456 * program. This function provides the needed 3DSTATE_GS for this.
2458 upload_gs_state_for_tf(brw
);
2461 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2462 gs
.StatisticsEnable
= true;
2464 gs
.RenderingEnabled
= true;
2468 gs
.DispatchGRFStartRegisterForURBData
= 1;
2470 gs
.IncludeVertexHandles
= true;
2476 brw
->gs
.enabled
= active
;
2480 static const struct brw_tracked_state
genX(gs_state
) = {
2482 .mesa
= (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
2483 .brw
= BRW_NEW_BATCH
|
2486 BRW_NEW_GEOMETRY_PROGRAM
|
2487 BRW_NEW_GS_PROG_DATA
|
2488 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2490 .emit
= genX(upload_gs_state
),
2494 /* ---------------------------------------------------------------------- */
2496 UNUSED
static GLenum
2497 fix_dual_blend_alpha_to_one(GLenum function
)
2503 case GL_ONE_MINUS_SRC1_ALPHA
:
2510 #define blend_factor(x) brw_translate_blend_factor(x)
2511 #define blend_eqn(x) brw_translate_blend_equation(x)
2515 genX(upload_blend_state
)(struct brw_context
*brw
)
2517 struct gl_context
*ctx
= &brw
->ctx
;
2520 /* We need at least one BLEND_STATE written, because we might do
2521 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2522 * for computed depth or alpha test), which will do an FB write
2523 * with render target 0, which will reference BLEND_STATE[0] for
2524 * alpha test enable.
2526 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2527 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2528 nr_draw_buffers
= 1;
2530 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2532 size
+= GENX(BLEND_STATE_length
) * 4;
2535 uint32_t *blend_map
;
2536 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2539 struct GENX(BLEND_STATE
) blend
= { 0 };
2542 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2543 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2546 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2547 * "If drawbuffer zero is not NONE and the buffer it references has an
2548 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2549 * operations are skipped."
2551 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2552 /* _NEW_MULTISAMPLE */
2553 if (_mesa_is_multisample_enabled(ctx
)) {
2554 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2555 blend
.AlphaToCoverageEnable
= true;
2556 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2558 if (ctx
->Multisample
.SampleAlphaToOne
)
2559 blend
.AlphaToOneEnable
= true;
2563 if (ctx
->Color
.AlphaEnabled
) {
2564 blend
.AlphaTestEnable
= true;
2565 blend
.AlphaTestFunction
=
2566 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2569 if (ctx
->Color
.DitherFlag
) {
2570 blend
.ColorDitherEnable
= true;
2575 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2576 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2582 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2584 /* Used for implementing the following bit of GL_EXT_texture_integer:
2585 * "Per-fragment operations that require floating-point color
2586 * components, including multisample alpha operations, alpha test,
2587 * blending, and dithering, have no effect when the corresponding
2588 * colors are written to an integer color buffer."
2590 bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2593 if (ctx
->Color
.ColorLogicOpEnabled
) {
2594 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2595 : GL_UNSIGNED_NORMALIZED
;
2596 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2597 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2598 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2600 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2601 _mesa_enum_to_string(rb_type
));
2602 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2603 entry
.LogicOpEnable
= true;
2604 entry
.LogicOpFunction
=
2605 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2607 } else if (ctx
->Color
.BlendEnabled
& (1 << i
) && !integer
&&
2608 !ctx
->Color
._AdvancedBlendMode
) {
2609 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2610 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2611 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2612 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2613 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2614 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2616 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2617 srcRGB
= dstRGB
= GL_ONE
;
2619 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2620 srcA
= dstA
= GL_ONE
;
2622 /* Due to hardware limitations, the destination may have information
2623 * in an alpha channel even when the format specifies no alpha
2624 * channel. In order to avoid getting any incorrect blending due to
2625 * that alpha channel, coerce the blend factors to values that will
2626 * not read the alpha channel, but will instead use the correct
2627 * implicit value for alpha.
2629 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2630 GL_TEXTURE_ALPHA_TYPE
)) {
2631 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2632 srcA
= brw_fix_xRGB_alpha(srcA
);
2633 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2634 dstA
= brw_fix_xRGB_alpha(dstA
);
2637 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2638 * "If Dual Source Blending is enabled, this bit must be disabled."
2640 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2641 * and leave it enabled anyway.
2643 if (ctx
->Color
.Blend
[i
]._UsesDualSrc
&& blend
.AlphaToOneEnable
) {
2644 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2645 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2646 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2647 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2650 entry
.ColorBufferBlendEnable
= true;
2651 entry
.DestinationBlendFactor
= blend_factor(dstRGB
);
2652 entry
.SourceBlendFactor
= blend_factor(srcRGB
);
2653 entry
.DestinationAlphaBlendFactor
= blend_factor(dstA
);
2654 entry
.SourceAlphaBlendFactor
= blend_factor(srcA
);
2655 entry
.ColorBlendFunction
= blend_eqn(eqRGB
);
2656 entry
.AlphaBlendFunction
= blend_eqn(eqA
);
2658 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2659 blend
.IndependentAlphaBlendEnable
= true;
2662 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2663 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2665 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2666 * clamping in the fragment shader. For its clamping of
2667 * blending, the spec says:
2669 * "RESOLVED: For fixed-point color buffers, the inputs and
2670 * the result of the blending equation are clamped. For
2671 * floating-point color buffers, no clamping occurs."
2673 * So, generally, we want clamping to the render target's range.
2674 * And, good news, the hardware tables for both pre- and
2675 * post-blend color clamping are either ignored, or any are
2676 * allowed, or clamping is required but RT range clamping is a
2679 entry
.PreBlendColorClampEnable
= true;
2680 entry
.PostBlendColorClampEnable
= true;
2681 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2683 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2684 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2685 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2686 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2689 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2691 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2697 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2701 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2702 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2703 ptr
.BLEND_STATEChange
= true;
2706 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2707 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2709 ptr
.BlendStatePointerValid
= true;
2715 static const struct brw_tracked_state
genX(blend_state
) = {
2717 .mesa
= _NEW_BUFFERS
|
2720 .brw
= BRW_NEW_BATCH
|
2722 BRW_NEW_STATE_BASE_ADDRESS
,
2724 .emit
= genX(upload_blend_state
),
2728 /* ---------------------------------------------------------------------- */
2731 UNUSED
static const uint32_t push_constant_opcodes
[] = {
2732 [MESA_SHADER_VERTEX
] = 21,
2733 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2734 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2735 [MESA_SHADER_GEOMETRY
] = 22,
2736 [MESA_SHADER_FRAGMENT
] = 23,
2737 [MESA_SHADER_COMPUTE
] = 0,
2741 upload_constant_state(struct brw_context
*brw
,
2742 struct brw_stage_state
*stage_state
,
2743 bool active
, uint32_t stage
)
2745 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
2746 active
= active
&& stage_state
->push_const_size
!= 0;
2748 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2749 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2751 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2752 pkt
.ConstantBody
.ReadLength
[2] = stage_state
->push_const_size
;
2753 pkt
.ConstantBody
.Buffer
[2] =
2754 render_ro_bo(brw
->curbe
.curbe_bo
, stage_state
->push_const_offset
);
2756 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
2757 pkt
.ConstantBody
.Buffer
[0].offset
=
2758 stage_state
->push_const_offset
| mocs
;
2763 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
2769 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
2771 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2773 /* _BRW_NEW_VERTEX_PROGRAM */
2774 const struct brw_program
*vp
= brw_program_const(brw
->vertex_program
);
2775 /* BRW_NEW_VS_PROG_DATA */
2776 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
2778 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
2779 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
2782 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !brw
->is_baytrail
)
2783 gen7_emit_vs_workaround_flush(brw
);
2785 upload_constant_state(brw
, stage_state
, true /* active */,
2786 MESA_SHADER_VERTEX
);
2790 static const struct brw_tracked_state
genX(vs_push_constants
) = {
2792 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2794 .brw
= BRW_NEW_BATCH
|
2796 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2797 BRW_NEW_VERTEX_PROGRAM
|
2798 BRW_NEW_VS_PROG_DATA
,
2800 .emit
= genX(upload_vs_push_constants
),
2804 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
2806 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2808 /* BRW_NEW_GEOMETRY_PROGRAM */
2809 const struct brw_program
*gp
= brw_program_const(brw
->geometry_program
);
2812 /* BRW_NEW_GS_PROG_DATA */
2813 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
2815 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
2816 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
2820 upload_constant_state(brw
, stage_state
, gp
, MESA_SHADER_GEOMETRY
);
2824 static const struct brw_tracked_state
genX(gs_push_constants
) = {
2826 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2828 .brw
= BRW_NEW_BATCH
|
2830 BRW_NEW_GEOMETRY_PROGRAM
|
2831 BRW_NEW_GS_PROG_DATA
|
2832 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2834 .emit
= genX(upload_gs_push_constants
),
2838 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
2840 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
2841 /* BRW_NEW_FRAGMENT_PROGRAM */
2842 const struct brw_program
*fp
= brw_program_const(brw
->fragment_program
);
2843 /* BRW_NEW_FS_PROG_DATA */
2844 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
2846 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
2848 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
2851 upload_constant_state(brw
, stage_state
, true, MESA_SHADER_FRAGMENT
);
2855 static const struct brw_tracked_state
genX(wm_push_constants
) = {
2857 .mesa
= _NEW_PROGRAM_CONSTANTS
,
2858 .brw
= BRW_NEW_BATCH
|
2860 BRW_NEW_FRAGMENT_PROGRAM
|
2861 BRW_NEW_FS_PROG_DATA
|
2862 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2864 .emit
= genX(upload_wm_push_constants
),
2868 /* ---------------------------------------------------------------------- */
2872 genX(determine_sample_mask
)(struct brw_context
*brw
)
2874 struct gl_context
*ctx
= &brw
->ctx
;
2875 float coverage
= 1.0f
;
2876 float coverage_invert
= false;
2877 unsigned sample_mask
= ~0u;
2879 /* BRW_NEW_NUM_SAMPLES */
2880 unsigned num_samples
= brw
->num_samples
;
2882 if (_mesa_is_multisample_enabled(ctx
)) {
2883 if (ctx
->Multisample
.SampleCoverage
) {
2884 coverage
= ctx
->Multisample
.SampleCoverageValue
;
2885 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
2887 if (ctx
->Multisample
.SampleMask
) {
2888 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
2892 if (num_samples
> 1) {
2893 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
2894 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
2895 if (coverage_invert
)
2896 coverage_bits
^= (1 << num_samples
) - 1;
2897 return coverage_bits
& sample_mask
;
2904 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
2905 unsigned num_samples
)
2907 assert(brw
->num_samples
<= 16);
2909 unsigned log2_samples
= ffs(MAX2(num_samples
, 1)) - 1;
2911 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
2912 multi
.PixelLocation
= CENTER
;
2913 multi
.NumberofMultisamples
= log2_samples
;
2915 GEN_SAMPLE_POS_4X(multi
.Sample
);
2917 switch (num_samples
) {
2919 GEN_SAMPLE_POS_1X(multi
.Sample
);
2922 GEN_SAMPLE_POS_2X(multi
.Sample
);
2925 GEN_SAMPLE_POS_4X(multi
.Sample
);
2928 GEN_SAMPLE_POS_8X(multi
.Sample
);
2938 genX(upload_multisample_state
)(struct brw_context
*brw
)
2940 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
2942 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
2943 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
2947 static const struct brw_tracked_state
genX(multisample_state
) = {
2949 .mesa
= _NEW_MULTISAMPLE
,
2950 .brw
= BRW_NEW_BLORP
|
2952 BRW_NEW_NUM_SAMPLES
,
2954 .emit
= genX(upload_multisample_state
)
2958 /* ---------------------------------------------------------------------- */
2962 genX(upload_color_calc_state
)(struct brw_context
*brw
)
2964 struct gl_context
*ctx
= &brw
->ctx
;
2966 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
2968 cc
.AlphaTestFormat
= ALPHATEST_UNORM8
;
2969 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
2970 ctx
->Color
.AlphaRef
);
2974 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
2975 cc
.BackfaceStencilReferenceValue
=
2976 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
2980 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
2981 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
2982 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
2983 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
2986 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2987 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
2989 ptr
.ColorCalcStatePointerValid
= true;
2994 static const struct brw_tracked_state
genX(color_calc_state
) = {
2996 .mesa
= _NEW_COLOR
|
2998 .brw
= BRW_NEW_BATCH
|
3001 BRW_NEW_STATE_BASE_ADDRESS
,
3003 .emit
= genX(upload_color_calc_state
),
3008 /* ---------------------------------------------------------------------- */
3012 genX(upload_sbe
)(struct brw_context
*brw
)
3014 struct gl_context
*ctx
= &brw
->ctx
;
3015 /* BRW_NEW_FS_PROG_DATA */
3016 const struct brw_wm_prog_data
*wm_prog_data
=
3017 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3019 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3021 #define attr_overrides sbe.Attribute
3023 uint32_t urb_entry_read_length
;
3024 uint32_t urb_entry_read_offset
;
3025 uint32_t point_sprite_enables
;
3027 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3028 sbe
.AttributeSwizzleEnable
= true;
3029 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3032 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3036 * Window coordinates in an FBO are inverted, which means point
3037 * sprite origin must be inverted.
3039 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3040 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3042 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3044 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3045 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3046 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3047 * BRW_NEW_VUE_MAP_GEOM_OUT
3049 genX(calculate_attr_overrides
)(brw
,
3051 &point_sprite_enables
,
3052 &urb_entry_read_length
,
3053 &urb_entry_read_offset
);
3055 /* Typically, the URB entry read length and offset should be programmed
3056 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3057 * stage which produces geometry. However, we don't know the proper
3058 * value until we call calculate_attr_overrides().
3060 * To fit with our existing code, we override the inherited values and
3061 * specify it here directly, as we did on previous generations.
3063 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3064 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3065 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3066 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3069 sbe
.ForceVertexURBEntryReadLength
= true;
3070 sbe
.ForceVertexURBEntryReadOffset
= true;
3074 /* prepare the active component dwords */
3075 int input_index
= 0;
3076 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
3077 if (!(brw
->fragment_program
->info
.inputs_read
&
3078 BITFIELD64_BIT(attr
))) {
3082 assert(input_index
< 32);
3084 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3091 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3092 for (int i
= 0; i
< 16; i
++)
3093 sbes
.Attribute
[i
] = attr_overrides
[i
];
3097 #undef attr_overrides
3100 static const struct brw_tracked_state
genX(sbe_state
) = {
3102 .mesa
= _NEW_BUFFERS
|
3107 .brw
= BRW_NEW_BLORP
|
3109 BRW_NEW_FRAGMENT_PROGRAM
|
3110 BRW_NEW_FS_PROG_DATA
|
3111 BRW_NEW_GS_PROG_DATA
|
3112 BRW_NEW_TES_PROG_DATA
|
3113 BRW_NEW_VUE_MAP_GEOM_OUT
|
3114 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3117 .emit
= genX(upload_sbe
),
3121 /* ---------------------------------------------------------------------- */
3125 * Outputs the 3DSTATE_SO_DECL_LIST command.
3127 * The data output is a series of 64-bit entries containing a SO_DECL per
3128 * stream. We only have one stream of rendering coming out of the GS unit, so
3129 * we only emit stream 0 (low 16 bits) SO_DECLs.
3132 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3133 const struct brw_vue_map
*vue_map
)
3135 struct gl_context
*ctx
= &brw
->ctx
;
3136 /* BRW_NEW_TRANSFORM_FEEDBACK */
3137 struct gl_transform_feedback_object
*xfb_obj
=
3138 ctx
->TransformFeedback
.CurrentObject
;
3139 const struct gl_transform_feedback_info
*linked_xfb_info
=
3140 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3141 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3142 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3143 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3144 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3146 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3148 memset(so_decl
, 0, sizeof(so_decl
));
3150 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3151 * command feels strange -- each dword pair contains a SO_DECL per stream.
3153 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3154 const struct gl_transform_feedback_output
*output
=
3155 &linked_xfb_info
->Outputs
[i
];
3156 const int buffer
= output
->OutputBuffer
;
3157 const int varying
= output
->OutputRegister
;
3158 const unsigned stream_id
= output
->StreamId
;
3159 assert(stream_id
< MAX_VERTEX_STREAMS
);
3161 buffer_mask
[stream_id
] |= 1 << buffer
;
3163 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3165 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3166 * array. Instead, it simply increments DstOffset for the following
3167 * input by the number of components that should be skipped.
3169 * Our hardware is unusual in that it requires us to program SO_DECLs
3170 * for fake "hole" components, rather than simply taking the offset
3171 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3172 * program as many size = 4 holes as we can, then a final hole to
3173 * accommodate the final 1, 2, or 3 remaining.
3175 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3177 while (skip_components
> 0) {
3178 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3180 .OutputBufferSlot
= output
->OutputBuffer
,
3181 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3183 skip_components
-= 4;
3186 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3188 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3189 .OutputBufferSlot
= output
->OutputBuffer
,
3190 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3192 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3195 if (decls
[stream_id
] > max_decls
)
3196 max_decls
= decls
[stream_id
];
3200 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3201 .StreamtoBufferSelects0
= buffer_mask
[0],
3202 .StreamtoBufferSelects1
= buffer_mask
[1],
3203 .StreamtoBufferSelects2
= buffer_mask
[2],
3204 .StreamtoBufferSelects3
= buffer_mask
[3],
3205 .NumEntries0
= decls
[0],
3206 .NumEntries1
= decls
[1],
3207 .NumEntries2
= decls
[2],
3208 .NumEntries3
= decls
[3]);
3210 for (int i
= 0; i
< max_decls
; i
++) {
3211 GENX(SO_DECL_ENTRY_pack
)(
3212 brw
, dw
+ 2 + i
* 2,
3213 &(struct GENX(SO_DECL_ENTRY
)) {
3214 .Stream0Decl
= so_decl
[0][i
],
3215 .Stream1Decl
= so_decl
[1][i
],
3216 .Stream2Decl
= so_decl
[2][i
],
3217 .Stream3Decl
= so_decl
[3][i
],
3223 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3225 struct gl_context
*ctx
= &brw
->ctx
;
3226 /* BRW_NEW_TRANSFORM_FEEDBACK */
3227 struct gl_transform_feedback_object
*xfb_obj
=
3228 ctx
->TransformFeedback
.CurrentObject
;
3230 const struct gl_transform_feedback_info
*linked_xfb_info
=
3231 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3233 struct brw_transform_feedback_object
*brw_obj
=
3234 (struct brw_transform_feedback_object
*) xfb_obj
;
3235 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3238 /* Set up the up to 4 output buffers. These are the ranges defined in the
3239 * gl_transform_feedback_object.
3241 for (int i
= 0; i
< 4; i
++) {
3242 struct intel_buffer_object
*bufferobj
=
3243 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3246 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3247 sob
.SOBufferIndex
= i
;
3252 uint32_t start
= xfb_obj
->Offset
[i
];
3253 assert(start
% 4 == 0);
3254 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3256 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
);
3257 assert(end
<= bo
->size
);
3259 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3260 sob
.SOBufferIndex
= i
;
3262 sob
.SurfaceBaseAddress
= render_bo(bo
, start
);
3264 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3265 sob
.SurfaceEndAddress
= render_bo(bo
, end
);
3267 sob
.SOBufferEnable
= true;
3268 sob
.StreamOffsetWriteEnable
= true;
3269 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3270 sob
.SOBufferMOCS
= mocs_wb
;
3272 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3273 sob
.StreamOutputBufferOffsetAddress
=
3274 instruction_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3276 if (brw_obj
->zero_offsets
) {
3277 /* Zero out the offset and write that to offset_bo */
3278 sob
.StreamOffset
= 0;
3280 /* Use offset_bo as the "Stream Offset." */
3281 sob
.StreamOffset
= 0xFFFFFFFF;
3288 brw_obj
->zero_offsets
= false;
3293 query_active(struct gl_query_object
*q
)
3295 return q
&& q
->Active
;
3299 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3300 const struct brw_vue_map
*vue_map
)
3302 struct gl_context
*ctx
= &brw
->ctx
;
3303 /* BRW_NEW_TRANSFORM_FEEDBACK */
3304 struct gl_transform_feedback_object
*xfb_obj
=
3305 ctx
->TransformFeedback
.CurrentObject
;
3307 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3309 int urb_entry_read_offset
= 0;
3310 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3311 urb_entry_read_offset
;
3313 sos
.SOFunctionEnable
= true;
3314 sos
.SOStatisticsEnable
= true;
3316 /* BRW_NEW_RASTERIZER_DISCARD */
3317 if (ctx
->RasterDiscard
) {
3318 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3319 sos
.RenderingDisable
= true;
3321 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3322 "query active relies on the clipper.");
3327 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3328 sos
.ReorderMode
= TRAILING
;
3331 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3332 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3333 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3334 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3336 const struct gl_transform_feedback_info
*linked_xfb_info
=
3337 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3338 /* Set buffer pitches; 0 means unbound. */
3339 if (xfb_obj
->Buffers
[0])
3340 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3341 if (xfb_obj
->Buffers
[1])
3342 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3343 if (xfb_obj
->Buffers
[2])
3344 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3345 if (xfb_obj
->Buffers
[3])
3346 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3349 /* We always read the whole vertex. This could be reduced at some
3350 * point by reading less and offsetting the register index in the
3353 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3354 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3355 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3356 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3357 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3358 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3359 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3360 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3366 genX(upload_sol
)(struct brw_context
*brw
)
3368 struct gl_context
*ctx
= &brw
->ctx
;
3369 /* BRW_NEW_TRANSFORM_FEEDBACK */
3370 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3373 genX(upload_3dstate_so_buffers
)(brw
);
3375 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3376 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3379 /* Finally, set up the SOL stage. This command must always follow updates to
3380 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3381 * MMIO register updates (current performed by the kernel at each batch
3384 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3387 static const struct brw_tracked_state
genX(sol_state
) = {
3390 .brw
= BRW_NEW_BATCH
|
3392 BRW_NEW_RASTERIZER_DISCARD
|
3393 BRW_NEW_VUE_MAP_GEOM_OUT
|
3394 BRW_NEW_TRANSFORM_FEEDBACK
,
3396 .emit
= genX(upload_sol
),
3400 /* ---------------------------------------------------------------------- */
3404 genX(upload_ps
)(struct brw_context
*brw
)
3406 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3407 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3409 /* BRW_NEW_FS_PROG_DATA */
3410 const struct brw_wm_prog_data
*prog_data
=
3411 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3412 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3417 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3418 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3419 * incorrect for subspans where some of the pixels are unlit. We believe
3420 * the bit just didn't take effect in previous generations.
3422 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3425 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3427 /* BRW_NEW_FS_PROG_DATA */
3428 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3430 if (prog_data
->base
.use_alt_mode
)
3431 ps
.FloatingPointMode
= Alternate
;
3433 /* Haswell requires the sample mask to be set in this packet as well as
3434 * in 3DSTATE_SAMPLE_MASK; the values should match.
3437 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3439 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3442 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3443 * it implicitly scales for different GT levels (which have some # of
3446 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3449 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3451 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3453 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3456 if (prog_data
->base
.nr_params
> 0)
3457 ps
.PushConstantEnable
= true;
3460 /* From the IVB PRM, volume 2 part 1, page 287:
3461 * "This bit is inserted in the PS payload header and made available to
3462 * the DataPort (either via the message header or via header bypass) to
3463 * indicate that oMask data (one or two phases) is included in Render
3464 * Target Write messages. If present, the oMask data is used to mask off
3467 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3469 /* The hardware wedges if you have this bit set but don't turn on any
3470 * dual source blend factors.
3472 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3474 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3475 (ctx
->Color
.BlendEnabled
& 1) &&
3476 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3478 /* BRW_NEW_FS_PROG_DATA */
3479 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3482 /* From the documentation for this packet:
3483 * "If the PS kernel does not need the Position XY Offsets to
3484 * compute a Position Value, then this field should be programmed
3485 * to POSOFFSET_NONE."
3487 * "SW Recommendation: If the PS kernel needs the Position Offsets
3488 * to compute a Position XY value, this field should match Position
3489 * ZW Interpolation Mode to ensure a consistent position.xyzw
3492 * We only require XY sample offsets. So, this recommendation doesn't
3493 * look useful at the moment. We might need this in future.
3495 if (prog_data
->uses_pos_offset
)
3496 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3498 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3500 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3501 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3502 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3503 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3504 prog_data
->base
.dispatch_grf_start_reg
;
3505 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3506 prog_data
->dispatch_grf_start_reg_2
;
3508 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3509 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3510 prog_data
->prog_offset_2
;
3512 if (prog_data
->base
.total_scratch
) {
3513 ps
.ScratchSpaceBasePointer
=
3514 render_bo(stage_state
->scratch_bo
,
3515 ffs(stage_state
->per_thread_scratch
) - 11);
3520 static const struct brw_tracked_state
genX(ps_state
) = {
3522 .mesa
= _NEW_MULTISAMPLE
|
3523 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3526 .brw
= BRW_NEW_BATCH
|
3528 BRW_NEW_FS_PROG_DATA
,
3530 .emit
= genX(upload_ps
),
3534 /* ---------------------------------------------------------------------- */
3538 genX(upload_hs_state
)(struct brw_context
*brw
)
3540 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3541 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3542 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3543 const struct brw_vue_prog_data
*vue_prog_data
=
3544 brw_vue_prog_data(stage_prog_data
);
3546 /* BRW_NEW_TES_PROG_DATA */
3547 struct brw_tcs_prog_data
*tcs_prog_data
=
3548 brw_tcs_prog_data(stage_prog_data
);
3550 if (!tcs_prog_data
) {
3551 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3553 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3554 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3556 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3557 hs
.IncludeVertexHandles
= true;
3559 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3564 static const struct brw_tracked_state
genX(hs_state
) = {
3567 .brw
= BRW_NEW_BATCH
|
3569 BRW_NEW_TCS_PROG_DATA
|
3570 BRW_NEW_TESS_PROGRAMS
,
3572 .emit
= genX(upload_hs_state
),
3576 genX(upload_ds_state
)(struct brw_context
*brw
)
3578 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3579 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3580 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3582 /* BRW_NEW_TES_PROG_DATA */
3583 const struct brw_tes_prog_data
*tes_prog_data
=
3584 brw_tes_prog_data(stage_prog_data
);
3585 const struct brw_vue_prog_data
*vue_prog_data
=
3586 brw_vue_prog_data(stage_prog_data
);
3588 if (!tes_prog_data
) {
3589 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3591 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3592 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3594 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3595 ds
.ComputeWCoordinateEnable
=
3596 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3599 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3600 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3601 ds
.UserClipDistanceCullTestEnableBitmask
=
3602 vue_prog_data
->cull_distance_mask
;
3608 static const struct brw_tracked_state
genX(ds_state
) = {
3611 .brw
= BRW_NEW_BATCH
|
3613 BRW_NEW_TESS_PROGRAMS
|
3614 BRW_NEW_TES_PROG_DATA
,
3616 .emit
= genX(upload_ds_state
),
3619 /* ---------------------------------------------------------------------- */
3622 upload_te_state(struct brw_context
*brw
)
3624 /* BRW_NEW_TESS_PROGRAMS */
3625 bool active
= brw
->tess_eval_program
;
3627 /* BRW_NEW_TES_PROG_DATA */
3628 const struct brw_tes_prog_data
*tes_prog_data
=
3629 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
3632 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
3633 te
.Partitioning
= tes_prog_data
->partitioning
;
3634 te
.OutputTopology
= tes_prog_data
->output_topology
;
3635 te
.TEDomain
= tes_prog_data
->domain
;
3637 te
.MaximumTessellationFactorOdd
= 63.0;
3638 te
.MaximumTessellationFactorNotOdd
= 64.0;
3641 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
3645 static const struct brw_tracked_state
genX(te_state
) = {
3648 .brw
= BRW_NEW_BLORP
|
3650 BRW_NEW_TES_PROG_DATA
|
3651 BRW_NEW_TESS_PROGRAMS
,
3653 .emit
= upload_te_state
,
3656 /* ---------------------------------------------------------------------- */
3659 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
3661 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3662 /* BRW_NEW_TESS_PROGRAMS */
3663 const struct brw_program
*tep
= brw_program_const(brw
->tess_eval_program
);
3666 /* BRW_NEW_TES_PROG_DATA */
3667 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
3668 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
3669 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
3672 upload_constant_state(brw
, stage_state
, tep
, MESA_SHADER_TESS_EVAL
);
3675 static const struct brw_tracked_state
genX(tes_push_constants
) = {
3677 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3678 .brw
= BRW_NEW_BATCH
|
3680 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3681 BRW_NEW_TESS_PROGRAMS
|
3682 BRW_NEW_TES_PROG_DATA
,
3684 .emit
= genX(upload_tes_push_constants
),
3688 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
3690 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3691 /* BRW_NEW_TESS_PROGRAMS */
3692 const struct brw_program
*tcp
= brw_program_const(brw
->tess_ctrl_program
);
3693 bool active
= brw
->tess_eval_program
;
3696 /* BRW_NEW_TCS_PROG_DATA */
3697 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
3699 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
3700 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
3703 upload_constant_state(brw
, stage_state
, active
, MESA_SHADER_TESS_CTRL
);
3706 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
3708 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3709 .brw
= BRW_NEW_BATCH
|
3711 BRW_NEW_DEFAULT_TESS_LEVELS
|
3712 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3713 BRW_NEW_TESS_PROGRAMS
|
3714 BRW_NEW_TCS_PROG_DATA
,
3716 .emit
= genX(upload_tcs_push_constants
),
3721 /* ---------------------------------------------------------------------- */
3725 genX(upload_cs_state
)(struct brw_context
*brw
)
3727 if (!brw
->cs
.base
.prog_data
)
3731 uint32_t *desc
= (uint32_t*) brw_state_batch(
3732 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
3735 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
3736 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
3737 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3738 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3740 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
3741 brw_emit_buffer_surface_state(
3742 brw
, &stage_state
->surf_offset
[
3743 prog_data
->binding_table
.shader_time_start
],
3744 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
3745 brw
->shader_time
.bo
->size
, 1, true);
3748 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
3749 32, &stage_state
->bind_bo_offset
);
3751 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
3752 if (prog_data
->total_scratch
) {
3756 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
3757 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
3759 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 11;
3760 } else if (GEN_IS_HASWELL
) {
3761 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
3762 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
3764 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 12;
3766 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
3767 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
3769 bo_offset
= stage_state
->per_thread_scratch
/ 1024 - 1;
3771 vfe
.ScratchSpaceBasePointer
=
3772 render_bo(stage_state
->scratch_bo
, bo_offset
);
3775 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
3776 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
3777 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
3778 vfe
.ResetGatewayTimer
=
3779 Resettingrelativetimerandlatchingtheglobaltimestamp
;
3781 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
3787 /* We are uploading duplicated copies of push constant uniforms for each
3788 * thread. Although the local id data needs to vary per thread, it won't
3789 * change for other uniform data. Unfortunately this duplication is
3790 * required for gen7. As of Haswell, this duplication can be avoided,
3791 * but this older mechanism with duplicated data continues to work.
3793 * FINISHME: As of Haswell, we could make use of the
3794 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
3795 * field to only store one copy of uniform data.
3797 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
3798 * which is described in the GPGPU_WALKER command and in the Broadwell
3799 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
3800 * Operations => GPGPU Mode => Indirect Payload Storage.
3802 * Note: The constant data is built in brw_upload_cs_push_constants
3805 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
3807 const uint32_t vfe_curbe_allocation
=
3808 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
3809 cs_prog_data
->push
.cross_thread
.regs
, 2);
3810 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
3813 if (cs_prog_data
->push
.total
.size
> 0) {
3814 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3815 curbe
.CURBETotalDataLength
=
3816 ALIGN(cs_prog_data
->push
.total
.size
, 64);
3817 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
3821 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
3822 memcpy(bind
, stage_state
->surf_offset
,
3823 prog_data
->binding_table
.size_bytes
);
3824 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
3825 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
3826 .SamplerStatePointer
= stage_state
->sampler_offset
,
3827 .SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4) >> 2,
3828 .BindingTablePointer
= stage_state
->bind_bo_offset
,
3829 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
3830 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
3831 .SharedLocalMemorySize
= encode_slm_size(devinfo
->gen
,
3832 prog_data
->total_shared
),
3833 .BarrierEnable
= cs_prog_data
->uses_barrier
,
3834 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3835 .CrossThreadConstantDataReadLength
=
3836 cs_prog_data
->push
.cross_thread
.regs
,
3840 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
3842 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
3843 load
.InterfaceDescriptorTotalLength
=
3844 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3845 load
.InterfaceDescriptorDataStartAddress
= offset
;
3849 static const struct brw_tracked_state
genX(cs_state
) = {
3851 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3852 .brw
= BRW_NEW_BATCH
|
3854 BRW_NEW_CS_PROG_DATA
|
3855 BRW_NEW_SAMPLER_STATE_TABLE
|
3858 .emit
= genX(upload_cs_state
)
3863 /* ---------------------------------------------------------------------- */
3867 genX(upload_raster
)(struct brw_context
*brw
)
3869 struct gl_context
*ctx
= &brw
->ctx
;
3872 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3875 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
3878 struct gl_point_attrib
*point
= &ctx
->Point
;
3880 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
3881 if (polygon
->_FrontBit
== render_to_fbo
)
3882 raster
.FrontWinding
= CounterClockwise
;
3884 if (polygon
->CullFlag
) {
3885 switch (polygon
->CullFaceMode
) {
3887 raster
.CullMode
= CULLMODE_FRONT
;
3890 raster
.CullMode
= CULLMODE_BACK
;
3892 case GL_FRONT_AND_BACK
:
3893 raster
.CullMode
= CULLMODE_BOTH
;
3896 unreachable("not reached");
3899 raster
.CullMode
= CULLMODE_NONE
;
3902 point
->SmoothFlag
= raster
.SmoothPointEnable
;
3904 raster
.DXMultisampleRasterizationEnable
=
3905 _mesa_is_multisample_enabled(ctx
);
3907 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
3908 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
3909 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
3911 switch (polygon
->FrontMode
) {
3913 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
3916 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
3919 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
3922 unreachable("not reached");
3925 switch (polygon
->BackMode
) {
3927 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
3930 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
3933 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
3936 unreachable("not reached");
3940 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
3943 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
3945 /* _NEW_TRANSFORM */
3946 if (!ctx
->Transform
.DepthClamp
) {
3948 raster
.ViewportZFarClipTestEnable
= true;
3949 raster
.ViewportZNearClipTestEnable
= true;
3951 raster
.ViewportZClipTestEnable
= true;
3955 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
3957 raster
.ConservativeRasterizationEnable
=
3958 ctx
->IntelConservativeRasterization
;
3961 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
3962 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
3964 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
3968 static const struct brw_tracked_state
genX(raster_state
) = {
3970 .mesa
= _NEW_BUFFERS
|
3977 .brw
= BRW_NEW_BLORP
|
3979 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3981 .emit
= genX(upload_raster
),
3985 /* ---------------------------------------------------------------------- */
3989 genX(upload_ps_extra
)(struct brw_context
*brw
)
3991 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
3993 const struct brw_wm_prog_data
*prog_data
=
3994 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3996 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
3997 psx
.PixelShaderValid
= true;
3998 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
3999 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4000 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4001 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4002 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4003 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4005 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4006 if (prog_data
->uses_sample_mask
) {
4008 if (prog_data
->post_depth_coverage
)
4009 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4010 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4011 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4013 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4015 psx
.PixelShaderUsesInputCoverageMask
= true;
4019 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4021 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4022 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4025 /* The stricter cross-primitive coherency guarantees that the hardware
4026 * gives us with the "Accesses UAV" bit set for at least one shader stage
4027 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4028 * are redundant within the current image, atomic counter and SSBO GL
4029 * APIs, which all have very loose ordering and coherency requirements
4030 * and generally rely on the application to insert explicit barriers when
4031 * a shader invocation is expected to see the memory writes performed by
4032 * the invocations of some previous primitive. Regardless of the value
4033 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4034 * cause an in most cases useless DC flush when the lowermost stage with
4035 * the bit set finishes execution.
4037 * It would be nice to disable it, but in some cases we can't because on
4038 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4039 * signal (which could be set independently from the coherency mechanism
4040 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4041 * determine whether the hardware skips execution of the fragment shader
4042 * or not via the ThreadDispatchEnable signal. However if we know that
4043 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4044 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4045 * difference so we may just disable it here.
4047 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4048 * take into account KillPixels when no depth or stencil writes are
4049 * enabled. In order for occlusion queries to work correctly with no
4050 * attachments, we need to force-enable here.
4052 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4055 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4056 !brw_color_buffer_write_enabled(brw
))
4057 psx
.PixelShaderHasUAV
= true;
4061 const struct brw_tracked_state
genX(ps_extra
) = {
4063 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4064 .brw
= BRW_NEW_BLORP
|
4066 BRW_NEW_FRAGMENT_PROGRAM
|
4067 BRW_NEW_FS_PROG_DATA
|
4068 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4070 .emit
= genX(upload_ps_extra
),
4074 /* ---------------------------------------------------------------------- */
4078 genX(upload_ps_blend
)(struct brw_context
*brw
)
4080 struct gl_context
*ctx
= &brw
->ctx
;
4083 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4084 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4087 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4089 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4090 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4091 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4093 bool alpha_to_one
= false;
4095 if (!buffer0_is_integer
) {
4096 /* _NEW_MULTISAMPLE */
4098 if (_mesa_is_multisample_enabled(ctx
)) {
4099 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4100 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4103 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4106 /* Used for implementing the following bit of GL_EXT_texture_integer:
4107 * "Per-fragment operations that require floating-point color
4108 * components, including multisample alpha operations, alpha test,
4109 * blending, and dithering, have no effect when the corresponding
4110 * colors are written to an integer color buffer."
4112 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4113 * "If drawbuffer zero is not NONE and the buffer it references has an
4114 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4115 * operations are skipped."
4117 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4118 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4119 GLenum eqA
= color
->Blend
[0].EquationA
;
4120 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4121 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4122 GLenum srcA
= color
->Blend
[0].SrcA
;
4123 GLenum dstA
= color
->Blend
[0].DstA
;
4125 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4126 srcRGB
= dstRGB
= GL_ONE
;
4128 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4129 srcA
= dstA
= GL_ONE
;
4131 /* Due to hardware limitations, the destination may have information
4132 * in an alpha channel even when the format specifies no alpha
4133 * channel. In order to avoid getting any incorrect blending due to
4134 * that alpha channel, coerce the blend factors to values that will
4135 * not read the alpha channel, but will instead use the correct
4136 * implicit value for alpha.
4138 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4139 GL_TEXTURE_ALPHA_TYPE
)) {
4140 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4141 srcA
= brw_fix_xRGB_alpha(srcA
);
4142 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4143 dstA
= brw_fix_xRGB_alpha(dstA
);
4146 /* Alpha to One doesn't work with Dual Color Blending. Override
4147 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4149 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4150 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4151 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4152 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4153 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4156 pb
.ColorBufferBlendEnable
= true;
4157 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4158 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4159 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4160 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4162 pb
.IndependentAlphaBlendEnable
=
4163 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4168 static const struct brw_tracked_state
genX(ps_blend
) = {
4170 .mesa
= _NEW_BUFFERS
|
4173 .brw
= BRW_NEW_BLORP
|
4175 BRW_NEW_FRAGMENT_PROGRAM
,
4177 .emit
= genX(upload_ps_blend
)
4181 /* ---------------------------------------------------------------------- */
4185 genX(emit_vf_topology
)(struct brw_context
*brw
)
4187 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4188 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4192 static const struct brw_tracked_state
genX(vf_topology
) = {
4195 .brw
= BRW_NEW_BLORP
|
4198 .emit
= genX(emit_vf_topology
),
4202 /* ---------------------------------------------------------------------- */
4206 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4208 uint32_t offset_in_bytes
,
4211 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4212 mi_rpc
.MemoryAddress
= instruction_bo(bo
, offset_in_bytes
);
4213 mi_rpc
.ReportID
= report_id
;
4218 /* ---------------------------------------------------------------------- */
4221 genX(init_atoms
)(struct brw_context
*brw
)
4224 static const struct brw_tracked_state
*render_atoms
[] =
4226 /* Once all the programs are done, we know how large urb entry
4227 * sizes need to be and can decide if we need to change the urb
4231 &brw_recalculate_urb_fence
,
4236 /* Surface state setup. Must come before the VS/WM unit. The binding
4237 * table upload must be last.
4239 &brw_vs_pull_constants
,
4240 &brw_wm_pull_constants
,
4241 &brw_renderbuffer_surfaces
,
4242 &brw_renderbuffer_read_surfaces
,
4243 &brw_texture_surfaces
,
4244 &brw_vs_binding_table
,
4245 &brw_wm_binding_table
,
4250 /* These set up state for brw_psp_urb_cbs */
4252 &genX(sf_clip_viewport
),
4254 &genX(vs_state
), /* always required, enabled or not */
4260 &brw_invariant_state
,
4262 &brw_binding_table_pointers
,
4263 &brw_blend_constant_color
,
4267 &genX(polygon_stipple
),
4268 &genX(polygon_stipple_offset
),
4270 &genX(line_stipple
),
4274 &genX(drawing_rect
),
4275 &brw_indices
, /* must come before brw_vertices */
4276 &genX(index_buffer
),
4279 &brw_constant_buffer
4282 static const struct brw_tracked_state
*render_atoms
[] =
4284 &genX(sf_clip_viewport
),
4286 /* Command packets: */
4291 &genX(blend_state
), /* must do before cc unit */
4292 &genX(color_calc_state
), /* must do before cc unit */
4293 &genX(depth_stencil_state
), /* must do before cc unit */
4295 &genX(vs_push_constants
), /* Before vs_state */
4296 &genX(gs_push_constants
), /* Before gs_state */
4297 &genX(wm_push_constants
), /* Before wm_state */
4299 /* Surface state setup. Must come before the VS/WM unit. The binding
4300 * table upload must be last.
4302 &brw_vs_pull_constants
,
4303 &brw_vs_ubo_surfaces
,
4304 &brw_gs_pull_constants
,
4305 &brw_gs_ubo_surfaces
,
4306 &brw_wm_pull_constants
,
4307 &brw_wm_ubo_surfaces
,
4308 &gen6_renderbuffer_surfaces
,
4309 &brw_renderbuffer_read_surfaces
,
4310 &brw_texture_surfaces
,
4312 &brw_vs_binding_table
,
4313 &gen6_gs_binding_table
,
4314 &brw_wm_binding_table
,
4319 &gen6_sampler_state
,
4320 &genX(multisample_state
),
4328 &genX(scissor_state
),
4330 &gen6_binding_table_pointers
,
4334 &genX(polygon_stipple
),
4335 &genX(polygon_stipple_offset
),
4337 &genX(line_stipple
),
4339 &genX(drawing_rect
),
4341 &brw_indices
, /* must come before brw_vertices */
4342 &genX(index_buffer
),
4346 static const struct brw_tracked_state
*render_atoms
[] =
4348 /* Command packets: */
4351 &genX(sf_clip_viewport
),
4354 &gen7_push_constant_space
,
4356 &genX(blend_state
), /* must do before cc unit */
4357 &genX(color_calc_state
), /* must do before cc unit */
4358 &genX(depth_stencil_state
), /* must do before cc unit */
4360 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4361 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4362 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4363 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4364 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4366 &genX(vs_push_constants
), /* Before vs_state */
4367 &genX(tcs_push_constants
),
4368 &genX(tes_push_constants
),
4369 &genX(gs_push_constants
), /* Before gs_state */
4370 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4372 /* Surface state setup. Must come before the VS/WM unit. The binding
4373 * table upload must be last.
4375 &brw_vs_pull_constants
,
4376 &brw_vs_ubo_surfaces
,
4377 &brw_vs_abo_surfaces
,
4378 &brw_tcs_pull_constants
,
4379 &brw_tcs_ubo_surfaces
,
4380 &brw_tcs_abo_surfaces
,
4381 &brw_tes_pull_constants
,
4382 &brw_tes_ubo_surfaces
,
4383 &brw_tes_abo_surfaces
,
4384 &brw_gs_pull_constants
,
4385 &brw_gs_ubo_surfaces
,
4386 &brw_gs_abo_surfaces
,
4387 &brw_wm_pull_constants
,
4388 &brw_wm_ubo_surfaces
,
4389 &brw_wm_abo_surfaces
,
4390 &gen6_renderbuffer_surfaces
,
4391 &brw_renderbuffer_read_surfaces
,
4392 &brw_texture_surfaces
,
4393 &brw_vs_binding_table
,
4394 &brw_tcs_binding_table
,
4395 &brw_tes_binding_table
,
4396 &brw_gs_binding_table
,
4397 &brw_wm_binding_table
,
4404 &genX(multisample_state
),
4418 &genX(scissor_state
),
4422 &genX(polygon_stipple
),
4423 &genX(polygon_stipple_offset
),
4425 &genX(line_stipple
),
4427 &genX(drawing_rect
),
4429 &brw_indices
, /* must come before brw_vertices */
4430 &genX(index_buffer
),
4438 static const struct brw_tracked_state
*render_atoms
[] =
4441 &genX(sf_clip_viewport
),
4444 &gen7_push_constant_space
,
4447 &genX(color_calc_state
),
4449 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4450 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4451 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4452 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4453 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4455 &genX(vs_push_constants
), /* Before vs_state */
4456 &genX(tcs_push_constants
),
4457 &genX(tes_push_constants
),
4458 &genX(gs_push_constants
), /* Before gs_state */
4459 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4461 /* Surface state setup. Must come before the VS/WM unit. The binding
4462 * table upload must be last.
4464 &brw_vs_pull_constants
,
4465 &brw_vs_ubo_surfaces
,
4466 &brw_vs_abo_surfaces
,
4467 &brw_tcs_pull_constants
,
4468 &brw_tcs_ubo_surfaces
,
4469 &brw_tcs_abo_surfaces
,
4470 &brw_tes_pull_constants
,
4471 &brw_tes_ubo_surfaces
,
4472 &brw_tes_abo_surfaces
,
4473 &brw_gs_pull_constants
,
4474 &brw_gs_ubo_surfaces
,
4475 &brw_gs_abo_surfaces
,
4476 &brw_wm_pull_constants
,
4477 &brw_wm_ubo_surfaces
,
4478 &brw_wm_abo_surfaces
,
4479 &gen6_renderbuffer_surfaces
,
4480 &brw_renderbuffer_read_surfaces
,
4481 &brw_texture_surfaces
,
4482 &brw_vs_binding_table
,
4483 &brw_tcs_binding_table
,
4484 &brw_tes_binding_table
,
4485 &brw_gs_binding_table
,
4486 &brw_wm_binding_table
,
4493 &genX(multisample_state
),
4502 &genX(raster_state
),
4508 &genX(depth_stencil_state
),
4511 &genX(scissor_state
),
4515 &genX(polygon_stipple
),
4516 &genX(polygon_stipple_offset
),
4518 &genX(line_stipple
),
4520 &genX(drawing_rect
),
4525 &genX(index_buffer
),
4533 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
4534 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
4535 render_atoms
, ARRAY_SIZE(render_atoms
));
4538 static const struct brw_tracked_state
*compute_atoms
[] =
4541 &brw_cs_image_surfaces
,
4542 &gen7_cs_push_constants
,
4543 &brw_cs_pull_constants
,
4544 &brw_cs_ubo_surfaces
,
4545 &brw_cs_abo_surfaces
,
4546 &brw_cs_texture_surfaces
,
4547 &brw_cs_work_groups_surface
,
4552 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
4553 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
4554 compute_atoms
, ARRAY_SIZE(compute_atoms
));
4556 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);