2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_multisample_state.h"
39 #include "brw_state.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffer_objects.h"
45 #include "intel_fbo.h"
47 #include "main/enums.h"
48 #include "main/fbobject.h"
49 #include "main/framebuffer.h"
50 #include "main/glformats.h"
51 #include "main/samplerobj.h"
52 #include "main/shaderapi.h"
53 #include "main/stencil.h"
54 #include "main/transformfeedback.h"
55 #include "main/varray.h"
56 #include "main/viewport.h"
57 #include "util/half_float.h"
60 emit_dwords(struct brw_context
*brw
, unsigned n
)
62 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
63 uint32_t *map
= brw
->batch
.map_next
;
64 brw
->batch
.map_next
+= n
;
65 intel_batchbuffer_advance(brw
);
75 #define __gen_address_type struct brw_address
76 #define __gen_user_data struct brw_context
79 __gen_combine_address(struct brw_context
*brw
, void *location
,
80 struct brw_address address
, uint32_t delta
)
82 struct intel_batchbuffer
*batch
= &brw
->batch
;
85 if (address
.bo
== NULL
) {
86 return address
.offset
+ delta
;
88 if (GEN_GEN
< 6 && brw_ptr_in_state_buffer(batch
, location
)) {
89 offset
= (char *) location
- (char *) brw
->batch
.state
.map
;
90 return brw_state_reloc(batch
, offset
, address
.bo
,
91 address
.offset
+ delta
,
95 assert(!brw_ptr_in_state_buffer(batch
, location
));
97 offset
= (char *) location
- (char *) brw
->batch
.batch
.map
;
98 return brw_batch_reloc(batch
, offset
, address
.bo
,
99 address
.offset
+ delta
,
100 address
.reloc_flags
);
104 UNUSED
static struct brw_address
105 rw_bo(struct brw_bo
*bo
, uint32_t offset
)
107 return (struct brw_address
) {
110 .reloc_flags
= RELOC_WRITE
,
114 static struct brw_address
115 ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
123 static struct brw_address
124 rw_32_bo(struct brw_bo
*bo
, uint32_t offset
)
126 return (struct brw_address
) {
129 .reloc_flags
= RELOC_WRITE
| RELOC_32BIT
,
133 static struct brw_address
134 ro_32_bo(struct brw_bo
*bo
, uint32_t offset
)
136 return (struct brw_address
) {
139 .reloc_flags
= RELOC_32BIT
,
143 UNUSED
static struct brw_address
144 ggtt_bo(struct brw_bo
*bo
, uint32_t offset
)
146 return (struct brw_address
) {
149 .reloc_flags
= RELOC_WRITE
| RELOC_NEEDS_GGTT
,
154 static struct brw_address
155 KSP(struct brw_context
*brw
, uint32_t offset
)
157 return ro_bo(brw
->cache
.bo
, offset
);
161 KSP(struct brw_context
*brw
, uint32_t offset
)
167 #include "genxml/genX_pack.h"
169 #define _brw_cmd_length(cmd) cmd ## _length
170 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
171 #define _brw_cmd_header(cmd) cmd ## _header
172 #define _brw_cmd_pack(cmd) cmd ## _pack
174 #define brw_batch_emit(brw, cmd, name) \
175 for (struct cmd name = { _brw_cmd_header(cmd) }, \
176 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
177 __builtin_expect(_dst != NULL, 1); \
178 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
181 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
182 uint32_t *_dw = emit_dwords(brw, n); \
183 struct cmd template = { \
184 _brw_cmd_header(cmd), \
185 .DWordLength = n - _brw_cmd_length_bias(cmd), \
188 _brw_cmd_pack(cmd)(brw, _dw, &template); \
189 _dw + 1; /* Array starts at dw[1] */ \
192 #define brw_state_emit(brw, cmd, align, offset, name) \
193 for (struct cmd name = {}, \
194 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
196 __builtin_expect(_dst != NULL, 1); \
197 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
201 * Polygon stipple packet
204 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
206 struct gl_context
*ctx
= &brw
->ctx
;
209 if (!ctx
->Polygon
.StippleFlag
)
212 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
213 /* Polygon stipple is provided in OpenGL order, i.e. bottom
214 * row first. If we're rendering to a window (i.e. the
215 * default frame buffer object, 0), then we need to invert
216 * it to match our pixel layout. But if we're rendering
217 * to a FBO (i.e. any named frame buffer object), we *don't*
218 * need to invert - we already match the layout.
220 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
221 for (unsigned i
= 0; i
< 32; i
++)
222 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
224 for (unsigned i
= 0; i
< 32; i
++)
225 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
230 static const struct brw_tracked_state
genX(polygon_stipple
) = {
232 .mesa
= _NEW_POLYGON
|
234 .brw
= BRW_NEW_CONTEXT
,
236 .emit
= genX(upload_polygon_stipple
),
240 * Polygon stipple offset packet
243 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
245 struct gl_context
*ctx
= &brw
->ctx
;
248 if (!ctx
->Polygon
.StippleFlag
)
251 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
254 * If we're drawing to a system window we have to invert the Y axis
255 * in order to match the OpenGL pixel coordinate system, and our
256 * offset must be matched to the window position. If we're drawing
257 * to a user-created FBO then our native pixel coordinate system
258 * works just fine, and there's no window system to worry about.
260 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
261 poly
.PolygonStippleYOffset
=
262 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
267 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
269 .mesa
= _NEW_BUFFERS
|
271 .brw
= BRW_NEW_CONTEXT
,
273 .emit
= genX(upload_polygon_stipple_offset
),
277 * Line stipple packet
280 genX(upload_line_stipple
)(struct brw_context
*brw
)
282 struct gl_context
*ctx
= &brw
->ctx
;
284 if (!ctx
->Line
.StippleFlag
)
287 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
288 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
290 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
291 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
295 static const struct brw_tracked_state
genX(line_stipple
) = {
298 .brw
= BRW_NEW_CONTEXT
,
300 .emit
= genX(upload_line_stipple
),
303 /* Constant single cliprect for framebuffer object or DRI2 drawing */
305 genX(upload_drawing_rect
)(struct brw_context
*brw
)
307 struct gl_context
*ctx
= &brw
->ctx
;
308 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
309 const unsigned int fb_width
= _mesa_geometric_width(fb
);
310 const unsigned int fb_height
= _mesa_geometric_height(fb
);
312 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
313 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
314 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
318 static const struct brw_tracked_state
genX(drawing_rect
) = {
320 .mesa
= _NEW_BUFFERS
,
321 .brw
= BRW_NEW_BLORP
|
324 .emit
= genX(upload_drawing_rect
),
328 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
332 unsigned start_offset
,
337 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
338 .VertexBufferIndex
= buffer_nr
,
339 .BufferPitch
= stride
,
341 /* The VF cache designers apparently cut corners, and made the cache
342 * only consider the bottom 32 bits of memory addresses. If you happen
343 * to have two vertex buffers which get placed exactly 4 GiB apart and
344 * use them in back-to-back draw calls, you can get collisions. To work
345 * around this problem, we restrict vertex buffers to the low 32 bits of
348 .BufferStartingAddress
= ro_32_bo(bo
, start_offset
),
350 .BufferSize
= end_offset
- start_offset
,
354 .AddressModifyEnable
= true,
358 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
359 .InstanceDataStepRate
= step_rate
,
361 .EndAddress
= ro_bo(bo
, end_offset
- 1),
366 .VertexBufferMOCS
= ICL_MOCS_WB
,
368 .VertexBufferMOCS
= CNL_MOCS_WB
,
370 .VertexBufferMOCS
= SKL_MOCS_WB
,
372 .VertexBufferMOCS
= BDW_MOCS_WB
,
374 .VertexBufferMOCS
= GEN7_MOCS_L3
,
378 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
379 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
383 is_passthru_format(uint32_t format
)
386 case ISL_FORMAT_R64_PASSTHRU
:
387 case ISL_FORMAT_R64G64_PASSTHRU
:
388 case ISL_FORMAT_R64G64B64_PASSTHRU
:
389 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
397 uploads_needed(uint32_t format
,
400 if (!is_passthru_format(format
))
407 case ISL_FORMAT_R64_PASSTHRU
:
408 case ISL_FORMAT_R64G64_PASSTHRU
:
410 case ISL_FORMAT_R64G64B64_PASSTHRU
:
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
414 unreachable("not reached");
419 * Returns the format that we are finally going to use when upload a vertex
420 * element. It will only change if we are using *64*PASSTHRU formats, as for
421 * gen < 8 they need to be splitted on two *32*FLOAT formats.
423 * @upload points in which upload we are. Valid values are [0,1]
426 downsize_format_if_needed(uint32_t format
,
429 assert(upload
== 0 || upload
== 1);
431 if (!is_passthru_format(format
))
434 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
435 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
436 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
437 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
438 * flagging that we want to fill with zeroes this second forced upload.
441 case ISL_FORMAT_R64_PASSTHRU
:
442 return upload
== 0 ? ISL_FORMAT_R32G32_FLOAT
443 : ISL_FORMAT_R32_FLOAT
;
444 case ISL_FORMAT_R64G64_PASSTHRU
:
445 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
446 : ISL_FORMAT_R32_FLOAT
;
447 case ISL_FORMAT_R64G64B64_PASSTHRU
:
448 return upload
== 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
449 : ISL_FORMAT_R32G32_FLOAT
;
450 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
451 return ISL_FORMAT_R32G32B32A32_FLOAT
;
453 unreachable("not reached");
458 * Returns the number of componentes associated with a format that is used on
459 * a 64 to 32 format split. See downsize_format()
462 upload_format_size(uint32_t upload_format
)
464 switch (upload_format
) {
465 case ISL_FORMAT_R32_FLOAT
:
467 /* downsized_format has returned this one in order to flag that we are
468 * performing a second upload which we want to have filled with
469 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
470 * vertex shader input variables.
474 case ISL_FORMAT_R32G32_FLOAT
:
476 case ISL_FORMAT_R32G32B32A32_FLOAT
:
479 unreachable("not reached");
484 genX(emit_vertices
)(struct brw_context
*brw
)
486 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
489 brw_prepare_vertices(brw
);
490 brw_prepare_shader_draw_parameters(brw
);
493 brw_emit_query_begin(brw
);
496 const struct brw_vs_prog_data
*vs_prog_data
=
497 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
500 struct gl_context
*ctx
= &brw
->ctx
;
501 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
502 ctx
->Polygon
.BackMode
!= GL_FILL
);
504 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
505 unsigned vue
= brw
->vb
.nr_enabled
;
507 /* The element for the edge flags must always be last, so we have to
508 * insert the SGVS before it in that case.
510 if (uses_edge_flag
) {
516 "Trying to insert VID/IID past 33rd vertex element, "
517 "need to reorder the vertex attrbutes.");
519 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
520 if (vs_prog_data
->uses_vertexid
) {
521 vfs
.VertexIDEnable
= true;
522 vfs
.VertexIDComponentNumber
= 2;
523 vfs
.VertexIDElementOffset
= vue
;
526 if (vs_prog_data
->uses_instanceid
) {
527 vfs
.InstanceIDEnable
= true;
528 vfs
.InstanceIDComponentNumber
= 3;
529 vfs
.InstanceIDElementOffset
= vue
;
533 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
534 vfi
.InstancingEnable
= true;
535 vfi
.VertexElementIndex
= vue
;
538 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
542 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
543 vs_prog_data
->uses_baseinstance
||
544 vs_prog_data
->uses_instanceid
||
545 vs_prog_data
->uses_vertexid
);
547 unsigned nr_elements
=
548 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
551 /* If any of the formats of vb.enabled needs more that one upload, we need
552 * to add it to nr_elements
554 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
555 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
556 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
558 if (uploads_needed(format
, input
->is_dual_slot
) > 1)
563 /* If the VS doesn't read any inputs (calculating vertex position from
564 * a state variable for some reason, for example), emit a single pad
565 * VERTEX_ELEMENT struct and bail.
567 * The stale VB state stays in place, but they don't do anything unless
568 * a VE loads from them.
570 if (nr_elements
== 0) {
571 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
572 1 + GENX(VERTEX_ELEMENT_STATE_length
));
573 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
575 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
576 .Component0Control
= VFCOMP_STORE_0
,
577 .Component1Control
= VFCOMP_STORE_0
,
578 .Component2Control
= VFCOMP_STORE_0
,
579 .Component3Control
= VFCOMP_STORE_1_FP
,
581 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
585 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
586 const bool uses_draw_params
=
587 vs_prog_data
->uses_basevertex
||
588 vs_prog_data
->uses_baseinstance
;
589 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
590 uses_draw_params
+ vs_prog_data
->uses_drawid
;
593 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
595 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
596 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
598 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
599 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
600 /* Prior to Haswell and Bay Trail we have to use 4-component formats
601 * to fake 3-component ones. In particular, we do this for
602 * half-float and 8 and 16-bit integer formats. This means that the
603 * vertex element may poke over the end of the buffer by 2 bytes.
605 const unsigned padding
=
606 (GEN_GEN
<= 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
) * 2;
607 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
608 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
615 if (uses_draw_params
) {
616 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
617 brw
->draw
.draw_params_bo
,
618 brw
->draw
.draw_params_offset
,
619 brw
->draw
.draw_params_bo
->size
,
624 if (vs_prog_data
->uses_drawid
) {
625 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
626 brw
->draw
.draw_id_bo
,
627 brw
->draw
.draw_id_offset
,
628 brw
->draw
.draw_id_bo
->size
,
634 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
635 * presumably for VertexID/InstanceID.
638 assert(nr_elements
<= 34);
639 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
641 assert(nr_elements
<= 18);
644 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
645 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
647 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
648 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
649 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
650 uint32_t comp0
= VFCOMP_STORE_SRC
;
651 uint32_t comp1
= VFCOMP_STORE_SRC
;
652 uint32_t comp2
= VFCOMP_STORE_SRC
;
653 uint32_t comp3
= VFCOMP_STORE_SRC
;
654 const unsigned num_uploads
= GEN_GEN
< 8 ?
655 uploads_needed(format
, input
->is_dual_slot
) : 1;
658 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
659 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
660 * element which has edge flag enabled."
662 assert(!(is_passthru_format(format
) && uses_edge_flag
));
665 /* The gen4 driver expects edgeflag to come in as a float, and passes
666 * that float on to the tests in the clipper. Mesa's current vertex
667 * attribute value for EdgeFlag is stored as a float, which works out.
668 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
669 * integer ubyte. Just rewrite that to convert to a float.
671 * Gen6+ passes edgeflag as sideband along with the vertex, instead
672 * of in the VUE. We have to upload it sideband as the last vertex
673 * element according to the B-Spec.
676 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
677 gen6_edgeflag_input
= input
;
682 for (unsigned c
= 0; c
< num_uploads
; c
++) {
683 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
684 downsize_format_if_needed(format
, c
);
685 /* If we need more that one upload, the offset stride would be 128
686 * bits (16 bytes), as for previous uploads we are using the full
688 const unsigned offset
= input
->offset
+ c
* 16;
690 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
691 upload_format_size(upload_format
) : input
->glarray
->Size
;
694 case 0: comp0
= VFCOMP_STORE_0
;
695 case 1: comp1
= VFCOMP_STORE_0
;
696 case 2: comp2
= VFCOMP_STORE_0
;
698 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
699 comp3
= VFCOMP_STORE_0
;
700 } else if (input
->glarray
->Integer
) {
701 comp3
= VFCOMP_STORE_1_INT
;
703 comp3
= VFCOMP_STORE_1_FP
;
710 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
712 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
713 * formats, 64-bit components are stored in the URB without any
714 * conversion. In this case, vertex elements must be written as 128
715 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
716 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
717 * component into the URB, Component 1 must be specified as
718 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
719 * order to output a 128-bit vertex element, or Components 1-3 must
720 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
721 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
722 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
725 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
726 /* Store vertex elements which correspond to double and dvec2 vertex
727 * shader inputs as 128-bit vertex elements, instead of 256-bits.
729 comp2
= VFCOMP_NOSTORE
;
730 comp3
= VFCOMP_NOSTORE
;
734 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
735 .VertexBufferIndex
= input
->buffer
,
737 .SourceElementFormat
= upload_format
,
738 .SourceElementOffset
= offset
,
739 .Component0Control
= comp0
,
740 .Component1Control
= comp1
,
741 .Component2Control
= comp2
,
742 .Component3Control
= comp3
,
744 .DestinationElementOffset
= i
* 4,
748 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
749 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
753 if (needs_sgvs_element
) {
754 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
756 .Component0Control
= VFCOMP_STORE_0
,
757 .Component1Control
= VFCOMP_STORE_0
,
758 .Component2Control
= VFCOMP_STORE_0
,
759 .Component3Control
= VFCOMP_STORE_0
,
761 .DestinationElementOffset
= i
* 4,
766 if (vs_prog_data
->uses_basevertex
||
767 vs_prog_data
->uses_baseinstance
) {
768 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
769 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
770 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
771 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
774 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
775 elem_state
.SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32_UINT
;
776 if (vs_prog_data
->uses_basevertex
)
777 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
779 if (vs_prog_data
->uses_baseinstance
)
780 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
782 if (vs_prog_data
->uses_vertexid
)
783 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
785 if (vs_prog_data
->uses_instanceid
)
786 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
789 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
790 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
793 if (vs_prog_data
->uses_drawid
) {
794 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
796 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
797 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32_UINT
,
798 .Component0Control
= VFCOMP_STORE_SRC
,
799 .Component1Control
= VFCOMP_STORE_0
,
800 .Component2Control
= VFCOMP_STORE_0
,
801 .Component3Control
= VFCOMP_STORE_0
,
803 .DestinationElementOffset
= i
* 4,
807 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
808 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
812 if (gen6_edgeflag_input
) {
813 const uint32_t format
=
814 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
816 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
818 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
819 .EdgeFlagEnable
= true,
820 .SourceElementFormat
= format
,
821 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
822 .Component0Control
= VFCOMP_STORE_SRC
,
823 .Component1Control
= VFCOMP_STORE_0
,
824 .Component2Control
= VFCOMP_STORE_0
,
825 .Component3Control
= VFCOMP_STORE_0
,
828 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
829 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
834 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
835 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
836 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
837 unsigned element_index
;
839 /* The edge flag element is reordered to be the last one in the code
840 * above so we need to compensate for that in the element indices used
843 if (input
== gen6_edgeflag_input
)
844 element_index
= nr_elements
- 1;
848 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
849 vfi
.VertexElementIndex
= element_index
;
850 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
851 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
855 if (vs_prog_data
->uses_drawid
) {
856 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
858 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
859 vfi
.VertexElementIndex
= element
;
865 static const struct brw_tracked_state
genX(vertices
) = {
867 .mesa
= _NEW_POLYGON
,
868 .brw
= BRW_NEW_BATCH
|
871 BRW_NEW_VS_PROG_DATA
,
873 .emit
= genX(emit_vertices
),
877 genX(emit_index_buffer
)(struct brw_context
*brw
)
879 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
881 if (index_buffer
== NULL
)
884 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
885 #if GEN_GEN < 8 && !GEN_IS_HASWELL
886 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
888 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
890 /* The VF cache designers apparently cut corners, and made the cache
891 * only consider the bottom 32 bits of memory addresses. If you happen
892 * to have two index buffers which get placed exactly 4 GiB apart and
893 * use them in back-to-back draw calls, you can get collisions. To work
894 * around this problem, we restrict index buffers to the low 32 bits of
897 ib
.BufferStartingAddress
= ro_32_bo(brw
->ib
.bo
, 0);
899 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
900 ib
.BufferSize
= brw
->ib
.size
;
902 ib
.BufferEndingAddress
= ro_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
907 static const struct brw_tracked_state
genX(index_buffer
) = {
910 .brw
= BRW_NEW_BATCH
|
912 BRW_NEW_INDEX_BUFFER
,
914 .emit
= genX(emit_index_buffer
),
917 #if GEN_IS_HASWELL || GEN_GEN >= 8
919 genX(upload_cut_index
)(struct brw_context
*brw
)
921 const struct gl_context
*ctx
= &brw
->ctx
;
923 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
924 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
925 vf
.IndexedDrawCutIndexEnable
= true;
926 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
931 const struct brw_tracked_state
genX(cut_index
) = {
933 .mesa
= _NEW_TRANSFORM
,
934 .brw
= BRW_NEW_INDEX_BUFFER
,
936 .emit
= genX(upload_cut_index
),
942 * Determine the appropriate attribute override value to store into the
943 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
944 * override value contains two pieces of information: the location of the
945 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
946 * flag indicating whether to "swizzle" the attribute based on the direction
947 * the triangle is facing.
949 * If an attribute is "swizzled", then the given VUE location is used for
950 * front-facing triangles, and the VUE location that immediately follows is
951 * used for back-facing triangles. We use this to implement the mapping from
952 * gl_FrontColor/gl_BackColor to gl_Color.
954 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
955 * being instructed to begin reading attribute data. It can be set to a
956 * nonzero value to prevent the SF unit from wasting time reading elements of
957 * the VUE that are not needed by the fragment shader. It is measured in
958 * 256-bit increments.
961 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
962 const struct brw_vue_map
*vue_map
,
963 int urb_entry_read_offset
, int fs_attr
,
964 bool two_side_color
, uint32_t *max_source_attr
)
966 /* Find the VUE slot for this attribute. */
967 int slot
= vue_map
->varying_to_slot
[fs_attr
];
969 /* Viewport and Layer are stored in the VUE header. We need to override
970 * them to zero if earlier stages didn't write them, as GL requires that
971 * they read back as zero when not explicitly set.
973 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
974 attr
->ComponentOverrideX
= true;
975 attr
->ComponentOverrideW
= true;
976 attr
->ConstantSource
= CONST_0000
;
978 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
979 attr
->ComponentOverrideY
= true;
980 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
981 attr
->ComponentOverrideZ
= true;
986 /* If there was only a back color written but not front, use back
987 * as the color instead of undefined
989 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
990 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
991 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
992 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
995 /* This attribute does not exist in the VUE--that means that the vertex
996 * shader did not write to it. This means that either:
998 * (a) This attribute is a texture coordinate, and it is going to be
999 * replaced with point coordinates (as a consequence of a call to
1000 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
1001 * hardware will ignore whatever attribute override we supply.
1003 * (b) This attribute is read by the fragment shader but not written by
1004 * the vertex shader, so its value is undefined. Therefore the
1005 * attribute override we supply doesn't matter.
1007 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
1008 * previous shader stage.
1010 * Note that we don't have to worry about the cases where the attribute
1011 * is gl_PointCoord or is undergoing point sprite coordinate
1012 * replacement, because in those cases, this function isn't called.
1014 * In case (c), we need to program the attribute overrides so that the
1015 * primitive ID will be stored in this slot. In every other case, the
1016 * attribute override we supply doesn't matter. So just go ahead and
1017 * program primitive ID in every case.
1019 attr
->ComponentOverrideW
= true;
1020 attr
->ComponentOverrideX
= true;
1021 attr
->ComponentOverrideY
= true;
1022 attr
->ComponentOverrideZ
= true;
1023 attr
->ConstantSource
= PRIM_ID
;
1027 /* Compute the location of the attribute relative to urb_entry_read_offset.
1028 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1029 * it counts for two 128-bit VUE slots.
1031 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1032 assert(source_attr
>= 0 && source_attr
< 32);
1034 /* If we are doing two-sided color, and the VUE slot following this one
1035 * represents a back-facing color, then we need to instruct the SF unit to
1036 * do back-facing swizzling.
1038 bool swizzling
= two_side_color
&&
1039 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1040 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1041 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1042 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1044 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1045 if (*max_source_attr
< source_attr
+ swizzling
)
1046 *max_source_attr
= source_attr
+ swizzling
;
1048 attr
->SourceAttribute
= source_attr
;
1050 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1055 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1056 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1057 uint32_t *point_sprite_enables
,
1058 uint32_t *urb_entry_read_length
,
1059 uint32_t *urb_entry_read_offset
)
1061 const struct gl_context
*ctx
= &brw
->ctx
;
1064 const struct gl_point_attrib
*point
= &ctx
->Point
;
1066 /* BRW_NEW_FRAGMENT_PROGRAM */
1067 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1069 /* BRW_NEW_FS_PROG_DATA */
1070 const struct brw_wm_prog_data
*wm_prog_data
=
1071 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1072 uint32_t max_source_attr
= 0;
1074 *point_sprite_enables
= 0;
1077 brw_compute_first_urb_slot_required(fp
->info
.inputs_read
,
1078 &brw
->vue_map_geom_out
);
1080 /* Each URB offset packs two varying slots */
1081 assert(first_slot
% 2 == 0);
1082 *urb_entry_read_offset
= first_slot
/ 2;
1084 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1085 * description of dw10 Point Sprite Texture Coordinate Enable:
1087 * "This field must be programmed to zero when non-point primitives
1090 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1091 * must be programmed to zero when rendering non-point primitives, but
1092 * the IvyBridge PRM does, and if we don't, we get garbage.
1094 * This is not required on Haswell, as the hardware ignores this state
1095 * when drawing non-points -- although we do still need to be careful to
1096 * correctly set the attr overrides.
1099 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1101 bool drawing_points
= brw_is_drawing_points(brw
);
1103 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1104 int input_index
= wm_prog_data
->urb_setup
[attr
];
1106 if (input_index
< 0)
1110 bool point_sprite
= false;
1111 if (drawing_points
) {
1112 if (point
->PointSprite
&&
1113 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1114 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1115 point_sprite
= true;
1118 if (attr
== VARYING_SLOT_PNTC
)
1119 point_sprite
= true;
1122 *point_sprite_enables
|= (1 << input_index
);
1125 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1126 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1128 if (!point_sprite
) {
1129 genX(get_attr_override
)(&attribute
,
1130 &brw
->vue_map_geom_out
,
1131 *urb_entry_read_offset
, attr
,
1132 _mesa_vertex_program_two_side_enabled(ctx
),
1136 /* The hardware can only do the overrides on 16 overrides at a
1137 * time, and the other up to 16 have to be lined up so that the
1138 * input index = the output index. We'll need to do some
1139 * tweaking to make sure that's the case.
1141 if (input_index
< 16)
1142 attr_overrides
[input_index
] = attribute
;
1144 assert(attribute
.SourceAttribute
== input_index
);
1147 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1148 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1150 * "This field should be set to the minimum length required to read the
1151 * maximum source attribute. The maximum source attribute is indicated
1152 * by the maximum value of the enabled Attribute # Source Attribute if
1153 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1154 * enable is not set.
1155 * read_length = ceiling((max_source_attr + 1) / 2)
1157 * [errata] Corruption/Hang possible if length programmed larger than
1160 * Similar text exists for Ivy Bridge.
1162 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1166 /* ---------------------------------------------------------------------- */
1169 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL
) DEPTH_STENCIL_GENXML
;
1171 typedef struct GENX(DEPTH_STENCIL_STATE
) DEPTH_STENCIL_GENXML
;
1173 typedef struct GENX(COLOR_CALC_STATE
) DEPTH_STENCIL_GENXML
;
1177 set_depth_stencil_bits(struct brw_context
*brw
, DEPTH_STENCIL_GENXML
*ds
)
1179 struct gl_context
*ctx
= &brw
->ctx
;
1182 struct intel_renderbuffer
*depth_irb
=
1183 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1186 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1189 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1190 const int b
= stencil
->_BackFace
;
1192 if (depth
->Test
&& depth_irb
) {
1193 ds
->DepthTestEnable
= true;
1194 ds
->DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1195 ds
->DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1198 if (brw
->stencil_enabled
) {
1199 ds
->StencilTestEnable
= true;
1200 ds
->StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1201 ds
->StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1203 ds
->StencilTestFunction
=
1204 intel_translate_compare_func(stencil
->Function
[0]);
1206 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1207 ds
->StencilPassDepthPassOp
=
1208 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1209 ds
->StencilPassDepthFailOp
=
1210 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1212 ds
->StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1214 if (brw
->stencil_two_sided
) {
1215 ds
->DoubleSidedStencilEnable
= true;
1216 ds
->BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1217 ds
->BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1219 ds
->BackfaceStencilTestFunction
=
1220 intel_translate_compare_func(stencil
->Function
[b
]);
1221 ds
->BackfaceStencilFailOp
=
1222 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1223 ds
->BackfaceStencilPassDepthPassOp
=
1224 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1225 ds
->BackfaceStencilPassDepthFailOp
=
1226 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1229 #if GEN_GEN <= 5 || GEN_GEN >= 9
1230 ds
->StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1231 ds
->BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1238 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1241 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1242 set_depth_stencil_bits(brw
, &wmds
);
1246 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, ds
) {
1247 set_depth_stencil_bits(brw
, &ds
);
1250 /* Now upload a pointer to the indirect state */
1252 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1253 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1254 ptr
.DEPTH_STENCIL_STATEChange
= true;
1257 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1258 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1264 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1266 .mesa
= _NEW_BUFFERS
|
1269 .brw
= BRW_NEW_BLORP
|
1270 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1272 BRW_NEW_STATE_BASE_ADDRESS
),
1274 .emit
= genX(upload_depth_stencil_state
),
1278 /* ---------------------------------------------------------------------- */
1283 genX(upload_clip_state
)(struct brw_context
*brw
)
1285 struct gl_context
*ctx
= &brw
->ctx
;
1287 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1288 brw_state_emit(brw
, GENX(CLIP_STATE
), 32, &brw
->clip
.state_offset
, clip
) {
1289 clip
.KernelStartPointer
= KSP(brw
, brw
->clip
.prog_offset
);
1290 clip
.GRFRegisterCount
=
1291 DIV_ROUND_UP(brw
->clip
.prog_data
->total_grf
, 16) - 1;
1292 clip
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1293 clip
.SingleProgramFlow
= true;
1294 clip
.VertexURBEntryReadLength
= brw
->clip
.prog_data
->urb_read_length
;
1295 clip
.ConstantURBEntryReadLength
= brw
->clip
.prog_data
->curb_read_length
;
1297 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1298 clip
.ConstantURBEntryReadOffset
= brw
->curbe
.clip_start
* 2;
1299 clip
.DispatchGRFStartRegisterForURBData
= 1;
1300 clip
.VertexURBEntryReadOffset
= 0;
1302 /* BRW_NEW_URB_FENCE */
1303 clip
.NumberofURBEntries
= brw
->urb
.nr_clip_entries
;
1304 clip
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1306 if (brw
->urb
.nr_clip_entries
>= 10) {
1307 /* Half of the URB entries go to each thread, and it has to be an
1310 assert(brw
->urb
.nr_clip_entries
% 2 == 0);
1312 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1313 * only 2 threads can output VUEs at a time.
1315 clip
.MaximumNumberofThreads
= (GEN_GEN
== 5 ? 16 : 2) - 1;
1317 assert(brw
->urb
.nr_clip_entries
>= 5);
1318 clip
.MaximumNumberofThreads
= 1 - 1;
1321 clip
.VertexPositionSpace
= VPOS_NDCSPACE
;
1322 clip
.UserClipFlagsMustClipEnable
= true;
1323 clip
.GuardbandClipTestEnable
= true;
1325 clip
.ClipperViewportStatePointer
=
1326 ro_bo(brw
->batch
.state
.bo
, brw
->clip
.vp_offset
);
1328 clip
.ScreenSpaceViewportXMin
= -1;
1329 clip
.ScreenSpaceViewportXMax
= 1;
1330 clip
.ScreenSpaceViewportYMin
= -1;
1331 clip
.ScreenSpaceViewportYMax
= 1;
1333 clip
.ViewportXYClipTestEnable
= true;
1334 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1336 /* _NEW_TRANSFORM */
1337 if (GEN_GEN
== 5 || GEN_IS_G4X
) {
1338 clip
.UserClipDistanceClipTestEnableBitmask
=
1339 ctx
->Transform
.ClipPlanesEnabled
;
1341 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1344 clip
.UserClipDistanceClipTestEnableBitmask
=
1345 (ctx
->Transform
.ClipPlanesEnabled
& 0x3f) | 0x40;
1348 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1349 clip
.APIMode
= APIMODE_D3D
;
1351 clip
.APIMode
= APIMODE_OGL
;
1353 clip
.GuardbandClipTestEnable
= true;
1355 clip
.ClipMode
= brw
->clip
.prog_data
->clip_mode
;
1358 clip
.NegativeWClipTestEnable
= true;
1363 const struct brw_tracked_state
genX(clip_state
) = {
1365 .mesa
= _NEW_TRANSFORM
|
1367 .brw
= BRW_NEW_BATCH
|
1369 BRW_NEW_CLIP_PROG_DATA
|
1370 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1371 BRW_NEW_PROGRAM_CACHE
|
1374 .emit
= genX(upload_clip_state
),
1380 genX(upload_clip_state
)(struct brw_context
*brw
)
1382 struct gl_context
*ctx
= &brw
->ctx
;
1385 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1387 /* BRW_NEW_FS_PROG_DATA */
1388 struct brw_wm_prog_data
*wm_prog_data
=
1389 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1391 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1392 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1394 if (wm_prog_data
->barycentric_interp_modes
&
1395 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1396 clip
.NonPerspectiveBarycentricEnable
= true;
1399 clip
.EarlyCullEnable
= true;
1403 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1405 if (ctx
->Polygon
.CullFlag
) {
1406 switch (ctx
->Polygon
.CullFaceMode
) {
1408 clip
.CullMode
= CULLMODE_FRONT
;
1411 clip
.CullMode
= CULLMODE_BACK
;
1413 case GL_FRONT_AND_BACK
:
1414 clip
.CullMode
= CULLMODE_BOTH
;
1417 unreachable("Should not get here: invalid CullFlag");
1420 clip
.CullMode
= CULLMODE_NONE
;
1425 clip
.UserClipDistanceCullTestEnableBitmask
=
1426 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1428 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1432 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1433 clip
.TriangleStripListProvokingVertexSelect
= 0;
1434 clip
.TriangleFanProvokingVertexSelect
= 1;
1435 clip
.LineStripListProvokingVertexSelect
= 0;
1437 clip
.TriangleStripListProvokingVertexSelect
= 2;
1438 clip
.TriangleFanProvokingVertexSelect
= 2;
1439 clip
.LineStripListProvokingVertexSelect
= 1;
1442 /* _NEW_TRANSFORM */
1443 clip
.UserClipDistanceClipTestEnableBitmask
=
1444 ctx
->Transform
.ClipPlanesEnabled
;
1447 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1450 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1451 clip
.APIMode
= APIMODE_D3D
;
1453 clip
.APIMode
= APIMODE_OGL
;
1455 clip
.GuardbandClipTestEnable
= true;
1457 /* BRW_NEW_VIEWPORT_COUNT */
1458 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1460 if (ctx
->RasterDiscard
) {
1461 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1463 perf_debug("Rasterizer discard is currently implemented via the "
1464 "clipper; having the GS not write primitives would "
1465 "likely be faster.\n");
1468 clip
.ClipMode
= CLIPMODE_NORMAL
;
1471 clip
.ClipEnable
= true;
1474 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1476 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1477 clip
.ViewportXYClipTestEnable
= true;
1479 clip
.MinimumPointWidth
= 0.125;
1480 clip
.MaximumPointWidth
= 255.875;
1481 clip
.MaximumVPIndex
= viewport_count
- 1;
1482 if (_mesa_geometric_layers(fb
) == 0)
1483 clip
.ForceZeroRTAIndexEnable
= true;
1487 static const struct brw_tracked_state
genX(clip_state
) = {
1489 .mesa
= _NEW_BUFFERS
|
1493 .brw
= BRW_NEW_BLORP
|
1495 BRW_NEW_FS_PROG_DATA
|
1496 BRW_NEW_GS_PROG_DATA
|
1497 BRW_NEW_VS_PROG_DATA
|
1498 BRW_NEW_META_IN_PROGRESS
|
1500 BRW_NEW_RASTERIZER_DISCARD
|
1501 BRW_NEW_TES_PROG_DATA
|
1502 BRW_NEW_VIEWPORT_COUNT
,
1504 .emit
= genX(upload_clip_state
),
1508 /* ---------------------------------------------------------------------- */
1511 genX(upload_sf
)(struct brw_context
*brw
)
1513 struct gl_context
*ctx
= &brw
->ctx
;
1518 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1519 UNUSED
const bool multisampled_fbo
=
1520 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1524 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1526 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1528 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1529 sf
.KernelStartPointer
= KSP(brw
, brw
->sf
.prog_offset
);
1530 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1531 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1532 sf
.DispatchGRFStartRegisterForURBData
= 3;
1533 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1534 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1535 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1536 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1538 /* STATE_PREFETCH command description describes this state as being
1539 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1542 sf
.SetupViewportStateOffset
=
1543 ro_bo(brw
->batch
.state
.bo
, brw
->sf
.vp_offset
);
1545 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1547 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1548 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1550 sf
.MaximumNumberofThreads
=
1551 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1553 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1555 sf
.DestinationOriginHorizontalBias
= 0.5;
1556 sf
.DestinationOriginVerticalBias
= 0.5;
1558 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1559 sf
.StatisticsEnable
= true;
1561 sf
.ViewportTransformEnable
= true;
1565 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1570 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1572 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1573 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1574 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1576 switch (ctx
->Polygon
.FrontMode
) {
1578 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1581 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1584 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1587 unreachable("not reached");
1590 switch (ctx
->Polygon
.BackMode
) {
1592 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1595 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1598 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1601 unreachable("not reached");
1604 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1605 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1607 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1608 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1609 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1612 sf
.ScissorRectangleEnable
= true;
1614 if (ctx
->Polygon
.CullFlag
) {
1615 switch (ctx
->Polygon
.CullFaceMode
) {
1617 sf
.CullMode
= CULLMODE_FRONT
;
1620 sf
.CullMode
= CULLMODE_BACK
;
1622 case GL_FRONT_AND_BACK
:
1623 sf
.CullMode
= CULLMODE_BOTH
;
1626 unreachable("not reached");
1629 sf
.CullMode
= CULLMODE_NONE
;
1633 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1640 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1642 if (devinfo
->is_cherryview
)
1643 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1645 sf
.LineWidth
= brw_get_line_width(brw
);
1647 sf
.LineWidth
= brw_get_line_width(brw
);
1650 if (ctx
->Line
.SmoothFlag
) {
1651 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1653 sf
.AntiAliasingEnable
= true;
1657 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1658 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1659 /* Clamp to the hardware limits */
1660 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1662 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1663 if (use_state_point_size(brw
))
1664 sf
.PointWidthSource
= State
;
1667 /* _NEW_POINT | _NEW_MULTISAMPLE */
1668 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1669 !ctx
->Point
.PointSprite
)
1670 sf
.SmoothPointEnable
= true;
1675 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1677 const bool multisampled_fbo
=
1678 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1679 if (multisampled_fbo
)
1680 sf
.SmoothPointEnable
= false;
1683 #if GEN_IS_G4X || GEN_GEN >= 5
1684 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1688 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1689 sf
.TriangleStripListProvokingVertexSelect
= 2;
1690 sf
.TriangleFanProvokingVertexSelect
= 2;
1691 sf
.LineStripListProvokingVertexSelect
= 1;
1693 sf
.TriangleFanProvokingVertexSelect
= 1;
1697 /* BRW_NEW_FS_PROG_DATA */
1698 const struct brw_wm_prog_data
*wm_prog_data
=
1699 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1701 sf
.AttributeSwizzleEnable
= true;
1702 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1705 * Window coordinates in an FBO are inverted, which means point
1706 * sprite origin must be inverted, too.
1708 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1709 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1711 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1714 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1715 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1717 uint32_t urb_entry_read_length
;
1718 uint32_t urb_entry_read_offset
;
1719 uint32_t point_sprite_enables
;
1720 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1721 &urb_entry_read_length
,
1722 &urb_entry_read_offset
);
1723 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1724 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1725 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1726 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1731 static const struct brw_tracked_state
genX(sf_state
) = {
1733 .mesa
= _NEW_LIGHT
|
1737 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1738 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0) |
1739 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
1740 .brw
= BRW_NEW_BLORP
|
1741 BRW_NEW_VUE_MAP_GEOM_OUT
|
1742 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1743 BRW_NEW_PROGRAM_CACHE
|
1744 BRW_NEW_SF_PROG_DATA
|
1748 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1749 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1750 BRW_NEW_GS_PROG_DATA
|
1752 BRW_NEW_TES_PROG_DATA
1754 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1755 BRW_NEW_FRAGMENT_PROGRAM
1758 .emit
= genX(upload_sf
),
1761 /* ---------------------------------------------------------------------- */
1764 brw_color_buffer_write_enabled(struct brw_context
*brw
)
1766 struct gl_context
*ctx
= &brw
->ctx
;
1767 /* BRW_NEW_FRAGMENT_PROGRAM */
1768 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1772 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
1773 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
1774 uint64_t outputs_written
= fp
->info
.outputs_written
;
1777 if (rb
&& (outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
1778 outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
1779 GET_COLORMASK(ctx
->Color
.ColorMask
, i
)) {
1788 genX(upload_wm
)(struct brw_context
*brw
)
1790 struct gl_context
*ctx
= &brw
->ctx
;
1792 /* BRW_NEW_FS_PROG_DATA */
1793 const struct brw_wm_prog_data
*wm_prog_data
=
1794 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1796 UNUSED
bool writes_depth
=
1797 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1798 UNUSED
struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1799 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1802 /* We can't fold this into gen6_upload_wm_push_constants(), because
1803 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1804 * (3DSTATE_CONSTANT_PS [DevSNB]):
1806 * "[DevSNB]: This packet must be followed by WM_STATE."
1808 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1809 if (wm_prog_data
->base
.nr_params
!= 0) {
1810 wmcp
.Buffer0Valid
= true;
1811 /* Pointer to the WM constant buffer. Covered by the set of
1812 * state flags from gen6_upload_wm_push_constants.
1814 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1815 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1821 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1822 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1823 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1825 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1826 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1828 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1829 brw_state_emit(brw
, GENX(WM_STATE
), 64, &stage_state
->state_offset
, wm
) {
1830 if (wm_prog_data
->dispatch_8
&& wm_prog_data
->dispatch_16
) {
1831 /* These two fields should be the same pre-gen6, which is why we
1832 * only have one hardware field to program for both dispatch
1835 assert(wm_prog_data
->base
.dispatch_grf_start_reg
==
1836 wm_prog_data
->dispatch_grf_start_reg_2
);
1839 if (wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
)
1840 wm
.GRFRegisterCount0
= wm_prog_data
->reg_blocks_0
;
1842 if (stage_state
->sampler_count
)
1843 wm
.SamplerStatePointer
=
1844 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
1846 if (wm_prog_data
->prog_offset_2
)
1847 wm
.GRFRegisterCount2
= wm_prog_data
->reg_blocks_2
;
1850 wm
.SetupURBEntryReadLength
= wm_prog_data
->num_varying_inputs
* 2;
1851 wm
.ConstantURBEntryReadLength
= wm_prog_data
->base
.curb_read_length
;
1852 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1853 wm
.ConstantURBEntryReadOffset
= brw
->curbe
.wm_start
* 2;
1854 wm
.EarlyDepthTestEnable
= true;
1855 wm
.LineAntialiasingRegionWidth
= _05pixels
;
1856 wm
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1859 if (ctx
->Polygon
.OffsetFill
) {
1860 wm
.GlobalDepthOffsetEnable
= true;
1861 /* Something weird going on with legacy_global_depth_bias,
1862 * offset_constant, scaling and MRD. This value passes glean
1863 * but gives some odd results elsewere (eg. the
1864 * quad-offset-units test).
1866 wm
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1868 /* This is the only value that passes glean:
1870 wm
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1873 wm
.DepthCoefficientURBReadOffset
= 1;
1876 /* BRW_NEW_STATS_WM */
1877 wm
.StatisticsEnable
= GEN_GEN
>= 6 || brw
->stats_wm
;
1880 if (wm_prog_data
->base
.use_alt_mode
)
1881 wm
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1883 wm
.SamplerCount
= GEN_GEN
== 5 ?
1884 0 : DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1886 wm
.BindingTableEntryCount
=
1887 wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1888 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1889 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1890 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1891 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1892 wm_prog_data
->base
.dispatch_grf_start_reg
;
1894 wm_prog_data
->dispatch_8
|| wm_prog_data
->dispatch_16
) {
1895 wm
.KernelStartPointer0
= KSP(brw
, stage_state
->prog_offset
);
1899 if (GEN_GEN
== 6 || wm_prog_data
->prog_offset_2
) {
1900 wm
.KernelStartPointer2
=
1901 KSP(brw
, stage_state
->prog_offset
+ wm_prog_data
->prog_offset_2
);
1906 wm
.DualSourceBlendEnable
=
1907 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1908 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1909 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1910 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1912 /* From the SNB PRM, volume 2 part 1, page 281:
1913 * "If the PS kernel does not need the Position XY Offsets
1914 * to compute a Position XY value, then this field should be
1915 * programmed to POSOFFSET_NONE."
1917 * "SW Recommendation: If the PS kernel needs the Position Offsets
1918 * to compute a Position XY value, this field should match Position
1919 * ZW Interpolation Mode to ensure a consistent position.xyzw
1921 * We only require XY sample offsets. So, this recommendation doesn't
1922 * look useful at the moment. We might need this in future.
1924 if (wm_prog_data
->uses_pos_offset
)
1925 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1927 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1929 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1930 wm_prog_data
->dispatch_grf_start_reg_2
;
1933 if (wm_prog_data
->base
.total_scratch
) {
1934 wm
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
1935 wm
.PerThreadScratchSpace
=
1936 ffs(stage_state
->per_thread_scratch
) - 11;
1939 wm
.PixelShaderComputedDepth
= writes_depth
;
1943 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1946 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1951 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1954 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1956 if (multisampled_fbo
) {
1957 /* _NEW_MULTISAMPLE */
1958 if (ctx
->Multisample
.Enabled
)
1959 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1961 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1963 if (wm_prog_data
->persample_dispatch
)
1964 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1966 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1968 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1969 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1972 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1973 if (wm_prog_data
->uses_kill
||
1974 _mesa_is_alpha_test_enabled(ctx
) ||
1975 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1976 (GEN_GEN
>= 6 && wm_prog_data
->uses_omask
)) {
1977 wm
.PixelShaderKillsPixel
= true;
1980 /* _NEW_BUFFERS | _NEW_COLOR */
1981 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1982 wm
.PixelShaderKillsPixel
||
1983 (GEN_GEN
>= 6 && wm_prog_data
->has_side_effects
)) {
1984 wm
.ThreadDispatchEnable
= true;
1988 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1989 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1992 /* The "UAV access enable" bits are unnecessary on HSW because they only
1993 * seem to have an effect on the HW-assisted coherency mechanism which we
1994 * don't need, and the rasterization-related UAV_ONLY flag and the
1995 * DISPATCH_ENABLE bit can be set independently from it.
1996 * C.f. gen8_upload_ps_extra().
1998 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
2002 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
2003 wm_prog_data
->has_side_effects
)
2009 /* BRW_NEW_FS_PROG_DATA */
2010 if (wm_prog_data
->early_fragment_tests
)
2011 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2012 else if (wm_prog_data
->has_side_effects
)
2013 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2018 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
2019 brw_batch_emit(brw
, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
), clamp
) {
2020 clamp
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
2023 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
2028 static const struct brw_tracked_state
genX(wm_state
) = {
2032 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
2035 (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0) |
2036 (GEN_GEN
< 6 ? _NEW_POLYGONSTIPPLE
: 0) |
2037 (GEN_GEN
< 8 && GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0),
2038 .brw
= BRW_NEW_BLORP
|
2039 BRW_NEW_FS_PROG_DATA
|
2040 (GEN_GEN
< 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2041 BRW_NEW_FRAGMENT_PROGRAM
|
2042 BRW_NEW_PROGRAM_CACHE
|
2043 BRW_NEW_SAMPLER_STATE_TABLE
|
2046 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
2048 .emit
= genX(upload_wm
),
2051 /* ---------------------------------------------------------------------- */
2053 /* We restrict scratch buffers to the bottom 32 bits of the address space
2054 * by using rw_32_bo().
2056 * General State Base Address is a bit broken. If the address + size as
2057 * seen by STATE_BASE_ADDRESS overflows 48 bits, the GPU appears to treat
2058 * all accesses to the buffer as being out of bounds and returns zero.
2061 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2062 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2063 pkt.SamplerCount = \
2064 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2065 pkt.BindingTableEntryCount = \
2066 stage_prog_data->binding_table.size_bytes / 4; \
2067 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2069 if (stage_prog_data->total_scratch) { \
2070 pkt.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0); \
2071 pkt.PerThreadScratchSpace = \
2072 ffs(stage_state->per_thread_scratch) - 11; \
2075 pkt.DispatchGRFStartRegisterForURBData = \
2076 stage_prog_data->dispatch_grf_start_reg; \
2077 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2078 pkt.prefix##URBEntryReadOffset = 0; \
2080 pkt.StatisticsEnable = true; \
2084 genX(upload_vs_state
)(struct brw_context
*brw
)
2086 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2087 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2088 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2090 /* BRW_NEW_VS_PROG_DATA */
2091 const struct brw_vue_prog_data
*vue_prog_data
=
2092 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
2093 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
2095 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
2096 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
2097 assert(GEN_GEN
< 11 ||
2098 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
2101 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2102 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2104 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2105 * command that causes the VS Function Enable to toggle. Pipeline
2106 * flush can be executed by sending a PIPE_CONTROL command with CS
2107 * stall bit set and a post sync operation.
2109 * We've already done such a flush at the start of state upload, so we
2110 * don't need to do another one here.
2112 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
2113 if (stage_state
->push_const_size
!= 0) {
2114 cvs
.Buffer0Valid
= true;
2115 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
2116 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2121 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
2122 gen7_emit_vs_workaround_flush(brw
);
2125 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
2127 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2128 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
2130 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2132 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2135 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
2136 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
2137 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
2139 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
2140 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2142 vs
.MaximumNumberofThreads
=
2143 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
2145 vs
.StatisticsEnable
= false;
2146 vs
.SamplerStatePointer
=
2147 ro_bo(brw
->batch
.state
.bo
, stage_state
->sampler_offset
);
2151 /* Force single program flow on Ironlake. We cannot reliably get
2152 * all applications working without it. See:
2153 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2155 * The most notable and reliably failing application is the Humus
2158 vs
.SingleProgramFlow
= true;
2159 vs
.SamplerCount
= 0; /* hardware requirement */
2163 vs
.SIMD8DispatchEnable
=
2164 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
2166 vs
.UserClipDistanceCullTestEnableBitmask
=
2167 vue_prog_data
->cull_distance_mask
;
2172 /* Based on my reading of the simulator, the VS constants don't get
2173 * pulled into the VS FF unit until an appropriate pipeline flush
2174 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2175 * references to them into a little FIFO. The flushes are common,
2176 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2177 * the primitive to use the wrong constants. Then the FIFO
2178 * containing the constant setup gets added to again on the next
2179 * constants change, and eventually when a flush does happen the
2180 * unit is overwhelmed by constant changes and dies.
2182 * To avoid this, send a PIPE_CONTROL down the line that will
2183 * update the unit immediately loading the constants. The flush
2184 * type bits here were those set by the STATE_BASE_ADDRESS whose
2185 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2186 * bug reports that led to this workaround, and may be more than
2187 * what is strictly required to avoid the issue.
2189 brw_emit_pipe_control_flush(brw
,
2190 PIPE_CONTROL_DEPTH_STALL
|
2191 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
2192 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
2196 static const struct brw_tracked_state
genX(vs_state
) = {
2198 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
2199 .brw
= BRW_NEW_BATCH
|
2202 BRW_NEW_VS_PROG_DATA
|
2203 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
2204 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2205 BRW_NEW_PROGRAM_CACHE
|
2206 BRW_NEW_SAMPLER_STATE_TABLE
|
2210 .emit
= genX(upload_vs_state
),
2213 /* ---------------------------------------------------------------------- */
2216 genX(upload_cc_viewport
)(struct brw_context
*brw
)
2218 struct gl_context
*ctx
= &brw
->ctx
;
2220 /* BRW_NEW_VIEWPORT_COUNT */
2221 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2223 struct GENX(CC_VIEWPORT
) ccv
;
2224 uint32_t cc_vp_offset
;
2226 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
2229 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2230 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2231 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
2232 if (ctx
->Transform
.DepthClamp
) {
2233 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
2234 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
2236 ccv
.MinimumDepth
= 0.0;
2237 ccv
.MaximumDepth
= 1.0;
2239 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
2240 cc_map
+= GENX(CC_VIEWPORT_length
);
2244 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2245 ptr
.CCViewportPointer
= cc_vp_offset
;
2248 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2249 vp
.CCViewportStateChange
= 1;
2250 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
2253 brw
->cc
.vp_offset
= cc_vp_offset
;
2254 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2258 const struct brw_tracked_state
genX(cc_vp
) = {
2260 .mesa
= _NEW_TRANSFORM
|
2262 .brw
= BRW_NEW_BATCH
|
2264 BRW_NEW_VIEWPORT_COUNT
,
2266 .emit
= genX(upload_cc_viewport
)
2269 /* ---------------------------------------------------------------------- */
2272 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2273 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2274 struct GENX(SCISSOR_RECT
) *sc
)
2278 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2279 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2280 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2281 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2282 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2284 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2285 /* If the scissor was out of bounds and got clamped to 0 width/height
2286 * at the bounds, the subtraction of 1 from maximums could produce a
2287 * negative number and thus not clip anything. Instead, just provide
2288 * a min > max scissor inside the bounds, which produces the expected
2291 sc
->ScissorRectangleXMin
= 1;
2292 sc
->ScissorRectangleXMax
= 0;
2293 sc
->ScissorRectangleYMin
= 1;
2294 sc
->ScissorRectangleYMax
= 0;
2295 } else if (render_to_fbo
) {
2296 /* texmemory: Y=0=bottom */
2297 sc
->ScissorRectangleXMin
= bbox
[0];
2298 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2299 sc
->ScissorRectangleYMin
= bbox
[2];
2300 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2302 /* memory: Y=0=top */
2303 sc
->ScissorRectangleXMin
= bbox
[0];
2304 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2305 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2306 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2312 genX(upload_scissor_state
)(struct brw_context
*brw
)
2314 struct gl_context
*ctx
= &brw
->ctx
;
2315 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2316 struct GENX(SCISSOR_RECT
) scissor
;
2317 uint32_t scissor_state_offset
;
2318 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2319 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2320 uint32_t *scissor_map
;
2322 /* BRW_NEW_VIEWPORT_COUNT */
2323 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2325 scissor_map
= brw_state_batch(
2326 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2327 32, &scissor_state_offset
);
2329 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2331 /* The scissor only needs to handle the intersection of drawable and
2332 * scissor rect. Clipping to the boundaries of static shared buffers
2333 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2335 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2336 * inclusive but max is exclusive.
2338 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2339 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2340 GENX(SCISSOR_RECT_pack
)(
2341 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2344 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2345 ptr
.ScissorRectPointer
= scissor_state_offset
;
2349 static const struct brw_tracked_state
genX(scissor_state
) = {
2351 .mesa
= _NEW_BUFFERS
|
2354 .brw
= BRW_NEW_BATCH
|
2356 BRW_NEW_VIEWPORT_COUNT
,
2358 .emit
= genX(upload_scissor_state
),
2362 /* ---------------------------------------------------------------------- */
2365 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2366 float m00
, float m11
, float m30
, float m31
,
2367 float *xmin
, float *xmax
,
2368 float *ymin
, float *ymax
)
2370 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2371 * Strips and Fans documentation:
2373 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2374 * fixed-point "guardband" range supported by the rasterization hardware"
2378 * "In almost all circumstances, if an object’s vertices are actually
2379 * modified by this clamping (i.e., had X or Y coordinates outside of
2380 * the guardband extent the rendered object will not match the intended
2381 * result. Therefore software should take steps to ensure that this does
2382 * not happen - e.g., by clipping objects such that they do not exceed
2383 * these limits after the Drawing Rectangle is applied."
2385 * I believe the fundamental restriction is that the rasterizer (in
2386 * the SF/WM stages) have a limit on the number of pixels that can be
2387 * rasterized. We need to ensure any coordinates beyond the rasterizer
2388 * limit are handled by the clipper. So effectively that limit becomes
2389 * the clipper's guardband size.
2391 * It goes on to say:
2393 * "In addition, in order to be correctly rendered, objects must have a
2394 * screenspace bounding box not exceeding 8K in the X or Y direction.
2395 * This additional restriction must also be comprehended by software,
2396 * i.e., enforced by use of clipping."
2398 * This makes no sense. Gen7+ hardware supports 16K render targets,
2399 * and you definitely need to be able to draw polygons that fill the
2400 * surface. Our assumption is that the rasterizer was limited to 8K
2401 * on Sandybridge, which only supports 8K surfaces, and it was actually
2402 * increased to 16K on Ivybridge and later.
2404 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2406 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2408 if (m00
!= 0 && m11
!= 0) {
2409 /* First, we compute the screen-space render area */
2410 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2411 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2412 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2413 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2415 /* We want the guardband to be centered on that */
2416 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2417 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2418 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2419 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2421 /* Now we need it in native device coordinates */
2422 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2423 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2424 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2425 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2427 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2428 * flipped upside-down. X should be fine though.
2430 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2431 *xmin
= ndc_gb_xmin
;
2432 *xmax
= ndc_gb_xmax
;
2433 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2434 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2436 /* The viewport scales to 0, so nothing will be rendered. */
2445 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2447 struct gl_context
*ctx
= &brw
->ctx
;
2448 float y_scale
, y_bias
;
2450 /* BRW_NEW_VIEWPORT_COUNT */
2451 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2454 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2455 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2456 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2460 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2461 uint32_t sf_clip_vp_offset
;
2462 uint32_t *sf_clip_map
=
2463 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2464 64, &sf_clip_vp_offset
);
2466 struct GENX(SF_VIEWPORT
) sfv
;
2467 struct GENX(CLIP_VIEWPORT
) clv
;
2468 uint32_t sf_vp_offset
, clip_vp_offset
;
2470 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2472 uint32_t *clip_map
=
2473 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2474 32, &clip_vp_offset
);
2478 if (render_to_fbo
) {
2483 y_bias
= (float)fb_height
;
2486 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2487 /* _NEW_VIEWPORT: Guardband Clipping */
2488 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2489 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2491 sfv
.ViewportMatrixElementm00
= scale
[0];
2492 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2493 sfv
.ViewportMatrixElementm22
= scale
[2],
2494 sfv
.ViewportMatrixElementm30
= translate
[0],
2495 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2496 sfv
.ViewportMatrixElementm32
= translate
[2],
2497 brw_calculate_guardband_size(fb_width
, fb_height
,
2498 sfv
.ViewportMatrixElementm00
,
2499 sfv
.ViewportMatrixElementm11
,
2500 sfv
.ViewportMatrixElementm30
,
2501 sfv
.ViewportMatrixElementm31
,
2502 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2505 clv
.XMinClipGuardband
= gb_xmin
;
2506 clv
.XMaxClipGuardband
= gb_xmax
;
2507 clv
.YMinClipGuardband
= gb_ymin
;
2508 clv
.YMaxClipGuardband
= gb_ymax
;
2511 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2512 &sfv
.ScissorRectangle
);
2514 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2515 * The hardware will take the intersection of the drawing rectangle,
2516 * scissor rectangle, and the viewport extents. However, emitting
2517 * 3DSTATE_DRAWING_RECTANGLE is expensive since it requires a full
2518 * pipeline stall so we're better off just being a little more clever
2519 * with our viewport so we can emit it once at context creation time.
2521 const float viewport_Xmin
= MAX2(ctx
->ViewportArray
[i
].X
, 0);
2522 const float viewport_Ymin
= MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2523 const float viewport_Xmax
=
2524 MIN2(ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
, fb_width
);
2525 const float viewport_Ymax
=
2526 MIN2(ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
, fb_height
);
2528 if (render_to_fbo
) {
2529 sfv
.XMinViewPort
= viewport_Xmin
;
2530 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2531 sfv
.YMinViewPort
= viewport_Ymin
;
2532 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2534 sfv
.XMinViewPort
= viewport_Xmin
;
2535 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2536 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2537 sfv
.YMaxViewPort
= fb_height
- viewport_Ymin
- 1;
2542 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2543 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2545 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2546 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2547 sf_map
+= GENX(SF_VIEWPORT_length
);
2548 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2553 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2554 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2557 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2558 vp
.SFViewportStateChange
= 1;
2559 vp
.CLIPViewportStateChange
= 1;
2560 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2561 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2564 brw
->sf
.vp_offset
= sf_vp_offset
;
2565 brw
->clip
.vp_offset
= clip_vp_offset
;
2566 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2570 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2572 .mesa
= _NEW_BUFFERS
|
2574 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2575 .brw
= BRW_NEW_BATCH
|
2577 BRW_NEW_VIEWPORT_COUNT
,
2579 .emit
= genX(upload_sf_clip_viewport
),
2582 /* ---------------------------------------------------------------------- */
2585 genX(upload_gs_state
)(struct brw_context
*brw
)
2587 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
2588 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2589 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2590 const struct gl_program
*gs_prog
= brw
->programs
[MESA_SHADER_GEOMETRY
];
2591 /* BRW_NEW_GEOMETRY_PROGRAM */
2592 bool active
= GEN_GEN
>= 6 && gs_prog
;
2594 /* BRW_NEW_GS_PROG_DATA */
2595 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2596 UNUSED
const struct brw_vue_prog_data
*vue_prog_data
=
2597 brw_vue_prog_data(stage_prog_data
);
2599 const struct brw_gs_prog_data
*gs_prog_data
=
2600 brw_gs_prog_data(stage_prog_data
);
2604 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2605 if (active
&& stage_state
->push_const_size
!= 0) {
2606 cgs
.Buffer0Valid
= true;
2607 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2608 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2613 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2615 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2616 * Geometry > Geometry Shader > State:
2618 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2619 * whole fixed function pipeline when the GS enable changes value in
2622 * The hardware architects have clarified that in this context "flush the
2623 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2626 if (devinfo
->gt
== 2 && brw
->gs
.enabled
!= active
)
2627 gen7_emit_cs_stall_flush(brw
);
2631 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2633 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
2634 brw_state_emit(brw
, GENX(GS_STATE
), 32, &brw
->ff_gs
.state_offset
, gs
) {
2639 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2642 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2643 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2644 gs
.ControlDataHeaderSize
=
2645 gs_prog_data
->control_data_header_size_hwords
;
2647 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2648 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2650 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2652 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2655 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2656 * Ivy Bridge and Haswell.
2658 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2659 * strip to be delivered to the geometry shader in an order that does
2660 * not strictly follow the OpenGL spec, but preserves triangle
2661 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2662 * the geometry shader sees triangles:
2664 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2666 * (Clearing the bit is even worse, because it fails to preserve
2669 * Triangle strips with adjacency always ordered in a way that preserves
2670 * triangle orientation but does not strictly follow the OpenGL spec,
2671 * regardless of the setting of this bit.
2673 * On Haswell, both triangle strips and triangle strips with adjacency
2674 * are always ordered in a way that preserves triangle orientation.
2675 * Setting this bit causes the ordering to strictly follow the OpenGL
2678 * So in either case we want to set the bit. Unfortunately on Ivy
2679 * Bridge this will get the order close to correct but not perfect.
2681 gs
.ReorderMode
= TRAILING
;
2682 gs
.MaximumNumberofThreads
=
2683 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2684 : (devinfo
->max_gs_threads
- 1);
2687 gs
.SOStatisticsEnable
= true;
2688 if (gs_prog
->info
.has_transform_feedback_varyings
)
2689 gs
.SVBIPayloadEnable
= true;
2691 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2692 * was previously done for gen6.
2694 * TODO: test with both disabled to see if the HW is behaving
2695 * as expected, like in gen7.
2697 gs
.SingleProgramFlow
= true;
2698 gs
.VectorMaskEnable
= true;
2702 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2704 if (gs_prog_data
->static_vertex_count
!= -1) {
2705 gs
.StaticOutput
= true;
2706 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2708 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2710 gs
.UserClipDistanceCullTestEnableBitmask
=
2711 vue_prog_data
->cull_distance_mask
;
2713 const int urb_entry_write_offset
= 1;
2714 const uint32_t urb_entry_output_length
=
2715 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2716 urb_entry_write_offset
;
2718 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2719 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2725 if (!active
&& brw
->ff_gs
.prog_active
) {
2726 /* In gen6, transform feedback for the VS stage is done with an
2727 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2730 gs
.KernelStartPointer
= KSP(brw
, brw
->ff_gs
.prog_offset
);
2731 gs
.SingleProgramFlow
= true;
2732 gs
.DispatchGRFStartRegisterForURBData
= GEN_GEN
== 6 ? 2 : 1;
2733 gs
.VertexURBEntryReadLength
= brw
->ff_gs
.prog_data
->urb_read_length
;
2736 gs
.GRFRegisterCount
=
2737 DIV_ROUND_UP(brw
->ff_gs
.prog_data
->total_grf
, 16) - 1;
2738 /* BRW_NEW_URB_FENCE */
2739 gs
.NumberofURBEntries
= brw
->urb
.nr_gs_entries
;
2740 gs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
2741 gs
.MaximumNumberofThreads
= brw
->urb
.nr_gs_entries
>= 8 ? 1 : 0;
2742 gs
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
2745 gs
.VectorMaskEnable
= true;
2746 gs
.SVBIPayloadEnable
= true;
2747 gs
.SVBIPostIncrementEnable
= true;
2748 gs
.SVBIPostIncrementValue
=
2749 brw
->ff_gs
.prog_data
->svbi_postincrement_value
;
2750 gs
.SOStatisticsEnable
= true;
2751 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
2755 if (!active
&& !brw
->ff_gs
.prog_active
) {
2757 gs
.DispatchGRFStartRegisterForURBData
= 1;
2759 gs
.IncludeVertexHandles
= true;
2765 gs
.StatisticsEnable
= true;
2767 #if GEN_GEN == 5 || GEN_GEN == 6
2768 gs
.RenderingEnabled
= true;
2771 gs
.MaximumVPIndex
= brw
->clip
.viewport_count
- 1;
2776 brw
->gs
.enabled
= active
;
2780 static const struct brw_tracked_state
genX(gs_state
) = {
2782 .mesa
= (GEN_GEN
== 6 ? _NEW_PROGRAM_CONSTANTS
: 0),
2783 .brw
= BRW_NEW_BATCH
|
2785 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2786 BRW_NEW_PROGRAM_CACHE
|
2788 BRW_NEW_VIEWPORT_COUNT
2790 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
|
2791 BRW_NEW_GEOMETRY_PROGRAM
|
2792 BRW_NEW_GS_PROG_DATA
2794 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2796 .emit
= genX(upload_gs_state
),
2799 /* ---------------------------------------------------------------------- */
2801 UNUSED
static GLenum
2802 fix_dual_blend_alpha_to_one(GLenum function
)
2808 case GL_ONE_MINUS_SRC1_ALPHA
:
2815 #define blend_factor(x) brw_translate_blend_factor(x)
2816 #define blend_eqn(x) brw_translate_blend_equation(x)
2819 * Modify blend function to force destination alpha to 1.0
2821 * If \c function specifies a blend function that uses destination alpha,
2822 * replace it with a function that hard-wires destination alpha to 1.0. This
2823 * is used when rendering to xRGB targets.
2826 brw_fix_xRGB_alpha(GLenum function
)
2832 case GL_ONE_MINUS_DST_ALPHA
:
2833 case GL_SRC_ALPHA_SATURATE
:
2841 typedef struct GENX(BLEND_STATE_ENTRY
) BLEND_ENTRY_GENXML
;
2843 typedef struct GENX(COLOR_CALC_STATE
) BLEND_ENTRY_GENXML
;
2847 set_blend_entry_bits(struct brw_context
*brw
, BLEND_ENTRY_GENXML
*entry
, int i
,
2850 struct gl_context
*ctx
= &brw
->ctx
;
2853 const struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2855 bool independent_alpha_blend
= false;
2857 /* Used for implementing the following bit of GL_EXT_texture_integer:
2858 * "Per-fragment operations that require floating-point color
2859 * components, including multisample alpha operations, alpha test,
2860 * blending, and dithering, have no effect when the corresponding
2861 * colors are written to an integer color buffer."
2863 const bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2865 const unsigned blend_enabled
= GEN_GEN
>= 6 ?
2866 ctx
->Color
.BlendEnabled
& (1 << i
) : ctx
->Color
.BlendEnabled
;
2869 if (ctx
->Color
.ColorLogicOpEnabled
) {
2870 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2871 : GL_UNSIGNED_NORMALIZED
;
2872 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2873 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2874 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2876 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2877 _mesa_enum_to_string(rb_type
));
2878 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2879 entry
->LogicOpEnable
= true;
2880 entry
->LogicOpFunction
= ctx
->Color
._LogicOp
;
2882 } else if (blend_enabled
&& !ctx
->Color
._AdvancedBlendMode
2883 && (GEN_GEN
<= 5 || !integer
)) {
2884 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2885 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2886 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2887 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2888 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2889 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2891 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2892 srcRGB
= dstRGB
= GL_ONE
;
2894 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2895 srcA
= dstA
= GL_ONE
;
2897 /* Due to hardware limitations, the destination may have information
2898 * in an alpha channel even when the format specifies no alpha
2899 * channel. In order to avoid getting any incorrect blending due to
2900 * that alpha channel, coerce the blend factors to values that will
2901 * not read the alpha channel, but will instead use the correct
2902 * implicit value for alpha.
2904 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2905 GL_TEXTURE_ALPHA_TYPE
)) {
2906 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2907 srcA
= brw_fix_xRGB_alpha(srcA
);
2908 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2909 dstA
= brw_fix_xRGB_alpha(dstA
);
2912 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2913 * "If Dual Source Blending is enabled, this bit must be disabled."
2915 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2916 * and leave it enabled anyway.
2918 if (GEN_GEN
>= 6 && ctx
->Color
.Blend
[i
]._UsesDualSrc
&& alpha_to_one
) {
2919 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2920 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2921 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2922 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2925 entry
->ColorBufferBlendEnable
= true;
2926 entry
->DestinationBlendFactor
= blend_factor(dstRGB
);
2927 entry
->SourceBlendFactor
= blend_factor(srcRGB
);
2928 entry
->DestinationAlphaBlendFactor
= blend_factor(dstA
);
2929 entry
->SourceAlphaBlendFactor
= blend_factor(srcA
);
2930 entry
->ColorBlendFunction
= blend_eqn(eqRGB
);
2931 entry
->AlphaBlendFunction
= blend_eqn(eqA
);
2933 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2934 independent_alpha_blend
= true;
2937 return independent_alpha_blend
;
2942 genX(upload_blend_state
)(struct brw_context
*brw
)
2944 struct gl_context
*ctx
= &brw
->ctx
;
2947 /* We need at least one BLEND_STATE written, because we might do
2948 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2949 * for computed depth or alpha test), which will do an FB write
2950 * with render target 0, which will reference BLEND_STATE[0] for
2951 * alpha test enable.
2953 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2954 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2955 nr_draw_buffers
= 1;
2957 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2959 size
+= GENX(BLEND_STATE_length
) * 4;
2962 uint32_t *blend_map
;
2963 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2966 struct GENX(BLEND_STATE
) blend
= { 0 };
2969 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2970 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2973 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2974 * "If drawbuffer zero is not NONE and the buffer it references has an
2975 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2976 * operations are skipped."
2978 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2979 /* _NEW_MULTISAMPLE */
2980 if (_mesa_is_multisample_enabled(ctx
)) {
2981 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2982 blend
.AlphaToCoverageEnable
= true;
2983 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2985 if (ctx
->Multisample
.SampleAlphaToOne
)
2986 blend
.AlphaToOneEnable
= true;
2990 if (ctx
->Color
.AlphaEnabled
) {
2991 blend
.AlphaTestEnable
= true;
2992 blend
.AlphaTestFunction
=
2993 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2996 if (ctx
->Color
.DitherFlag
) {
2997 blend
.ColorDitherEnable
= true;
3002 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
3003 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
3007 blend
.IndependentAlphaBlendEnable
=
3008 set_blend_entry_bits(brw
, &entry
, i
, blend
.AlphaToOneEnable
) ||
3009 blend
.IndependentAlphaBlendEnable
;
3011 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
3012 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
3014 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
3015 * clamping in the fragment shader. For its clamping of
3016 * blending, the spec says:
3018 * "RESOLVED: For fixed-point color buffers, the inputs and
3019 * the result of the blending equation are clamped. For
3020 * floating-point color buffers, no clamping occurs."
3022 * So, generally, we want clamping to the render target's range.
3023 * And, good news, the hardware tables for both pre- and
3024 * post-blend color clamping are either ignored, or any are
3025 * allowed, or clamping is required but RT range clamping is a
3028 entry
.PreBlendColorClampEnable
= true;
3029 entry
.PostBlendColorClampEnable
= true;
3030 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
3032 entry
.WriteDisableRed
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 0);
3033 entry
.WriteDisableGreen
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 1);
3034 entry
.WriteDisableBlue
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 2);
3035 entry
.WriteDisableAlpha
= !GET_COLORMASK_BIT(ctx
->Color
.ColorMask
, i
, 3);
3038 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
3040 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
3046 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
3050 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3051 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
3052 ptr
.BLEND_STATEChange
= true;
3055 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3056 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
3058 ptr
.BlendStatePointerValid
= true;
3064 static const struct brw_tracked_state
genX(blend_state
) = {
3066 .mesa
= _NEW_BUFFERS
|
3069 .brw
= BRW_NEW_BATCH
|
3071 BRW_NEW_STATE_BASE_ADDRESS
,
3073 .emit
= genX(upload_blend_state
),
3077 /* ---------------------------------------------------------------------- */
3080 UNUSED
static const uint32_t push_constant_opcodes
[] = {
3081 [MESA_SHADER_VERTEX
] = 21,
3082 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3083 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3084 [MESA_SHADER_GEOMETRY
] = 22,
3085 [MESA_SHADER_FRAGMENT
] = 23,
3086 [MESA_SHADER_COMPUTE
] = 0,
3090 genX(upload_push_constant_packets
)(struct brw_context
*brw
)
3092 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3093 struct gl_context
*ctx
= &brw
->ctx
;
3095 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
3097 struct brw_stage_state
*stage_states
[] = {
3105 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !devinfo
->is_baytrail
&&
3106 stage_states
[MESA_SHADER_VERTEX
]->push_constants_dirty
)
3107 gen7_emit_vs_workaround_flush(brw
);
3109 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3110 struct brw_stage_state
*stage_state
= stage_states
[stage
];
3111 UNUSED
struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[stage
];
3113 if (!stage_state
->push_constants_dirty
)
3116 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3117 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3118 if (stage_state
->prog_data
) {
3119 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3120 /* The Skylake PRM contains the following restriction:
3122 * "The driver must ensure The following case does not occur
3123 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3124 * buffer 3 read length equal to zero committed followed by a
3125 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3128 * To avoid this, we program the buffers in the highest slots.
3129 * This way, slot 0 is only used if slot 3 is also used.
3133 for (int i
= 3; i
>= 0; i
--) {
3134 const struct brw_ubo_range
*range
=
3135 &stage_state
->prog_data
->ubo_ranges
[i
];
3137 if (range
->length
== 0)
3140 const struct gl_uniform_block
*block
=
3141 prog
->sh
.UniformBlocks
[range
->block
];
3142 const struct gl_buffer_binding
*binding
=
3143 &ctx
->UniformBufferBindings
[block
->Binding
];
3145 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
3146 static unsigned msg_id
= 0;
3147 _mesa_gl_debug(ctx
, &msg_id
, MESA_DEBUG_SOURCE_API
,
3148 MESA_DEBUG_TYPE_UNDEFINED
,
3149 MESA_DEBUG_SEVERITY_HIGH
,
3150 "UBO %d unbound, %s shader uniform data "
3151 "will be undefined.",
3153 _mesa_shader_stage_to_string(stage
));
3157 assert(binding
->Offset
% 32 == 0);
3159 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
3160 intel_buffer_object(binding
->BufferObject
),
3161 binding
->Offset
, range
->length
* 32, false);
3163 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3164 pkt
.ConstantBody
.Buffer
[n
] =
3165 ro_bo(bo
, range
->start
* 32 + binding
->Offset
);
3169 if (stage_state
->push_const_size
> 0) {
3171 pkt
.ConstantBody
.ReadLength
[n
] = stage_state
->push_const_size
;
3172 pkt
.ConstantBody
.Buffer
[n
] =
3173 ro_bo(stage_state
->push_const_bo
,
3174 stage_state
->push_const_offset
);
3177 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
3178 pkt
.ConstantBody
.Buffer
[0].offset
=
3179 stage_state
->push_const_offset
| mocs
;
3184 stage_state
->push_constants_dirty
= false;
3185 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
3189 const struct brw_tracked_state
genX(push_constant_packets
) = {
3192 .brw
= BRW_NEW_DRAW_CALL
,
3194 .emit
= genX(upload_push_constant_packets
),
3200 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
3202 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
3204 /* BRW_NEW_VERTEX_PROGRAM */
3205 const struct gl_program
*vp
= brw
->programs
[MESA_SHADER_VERTEX
];
3206 /* BRW_NEW_VS_PROG_DATA */
3207 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
3209 gen6_upload_push_constants(brw
, vp
, prog_data
, stage_state
);
3212 static const struct brw_tracked_state
genX(vs_push_constants
) = {
3214 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3216 .brw
= BRW_NEW_BATCH
|
3218 BRW_NEW_VERTEX_PROGRAM
|
3219 BRW_NEW_VS_PROG_DATA
,
3221 .emit
= genX(upload_vs_push_constants
),
3225 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
3227 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
3229 /* BRW_NEW_GEOMETRY_PROGRAM */
3230 const struct gl_program
*gp
= brw
->programs
[MESA_SHADER_GEOMETRY
];
3232 /* BRW_NEW_GS_PROG_DATA */
3233 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
3235 gen6_upload_push_constants(brw
, gp
, prog_data
, stage_state
);
3238 static const struct brw_tracked_state
genX(gs_push_constants
) = {
3240 .mesa
= _NEW_PROGRAM_CONSTANTS
|
3242 .brw
= BRW_NEW_BATCH
|
3244 BRW_NEW_GEOMETRY_PROGRAM
|
3245 BRW_NEW_GS_PROG_DATA
,
3247 .emit
= genX(upload_gs_push_constants
),
3251 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
3253 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3254 /* BRW_NEW_FRAGMENT_PROGRAM */
3255 const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3256 /* BRW_NEW_FS_PROG_DATA */
3257 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
3259 gen6_upload_push_constants(brw
, fp
, prog_data
, stage_state
);
3262 static const struct brw_tracked_state
genX(wm_push_constants
) = {
3264 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3265 .brw
= BRW_NEW_BATCH
|
3267 BRW_NEW_FRAGMENT_PROGRAM
|
3268 BRW_NEW_FS_PROG_DATA
,
3270 .emit
= genX(upload_wm_push_constants
),
3274 /* ---------------------------------------------------------------------- */
3278 genX(determine_sample_mask
)(struct brw_context
*brw
)
3280 struct gl_context
*ctx
= &brw
->ctx
;
3281 float coverage
= 1.0f
;
3282 float coverage_invert
= false;
3283 unsigned sample_mask
= ~0u;
3285 /* BRW_NEW_NUM_SAMPLES */
3286 unsigned num_samples
= brw
->num_samples
;
3288 if (_mesa_is_multisample_enabled(ctx
)) {
3289 if (ctx
->Multisample
.SampleCoverage
) {
3290 coverage
= ctx
->Multisample
.SampleCoverageValue
;
3291 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
3293 if (ctx
->Multisample
.SampleMask
) {
3294 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
3298 if (num_samples
> 1) {
3299 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
3300 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
3301 if (coverage_invert
)
3302 coverage_bits
^= (1 << num_samples
) - 1;
3303 return coverage_bits
& sample_mask
;
3310 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
3311 unsigned num_samples
)
3313 unsigned log2_samples
= ffs(num_samples
) - 1;
3315 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
3316 multi
.PixelLocation
= CENTER
;
3317 multi
.NumberofMultisamples
= log2_samples
;
3319 GEN_SAMPLE_POS_4X(multi
.Sample
);
3321 switch (num_samples
) {
3323 GEN_SAMPLE_POS_1X(multi
.Sample
);
3326 GEN_SAMPLE_POS_2X(multi
.Sample
);
3329 GEN_SAMPLE_POS_4X(multi
.Sample
);
3332 GEN_SAMPLE_POS_8X(multi
.Sample
);
3342 genX(upload_multisample_state
)(struct brw_context
*brw
)
3344 assert(brw
->num_samples
> 0 && brw
->num_samples
<= 16);
3346 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
3348 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
3349 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
3353 static const struct brw_tracked_state
genX(multisample_state
) = {
3355 .mesa
= _NEW_MULTISAMPLE
|
3356 (GEN_GEN
== 10 ? _NEW_BUFFERS
: 0),
3357 .brw
= BRW_NEW_BLORP
|
3359 BRW_NEW_NUM_SAMPLES
,
3361 .emit
= genX(upload_multisample_state
)
3365 /* ---------------------------------------------------------------------- */
3368 genX(upload_color_calc_state
)(struct brw_context
*brw
)
3370 struct gl_context
*ctx
= &brw
->ctx
;
3372 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
3374 cc
.IndependentAlphaBlendEnable
=
3375 set_blend_entry_bits(brw
, &cc
, 0, false);
3376 set_depth_stencil_bits(brw
, &cc
);
3378 if (ctx
->Color
.AlphaEnabled
&&
3379 ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
3380 cc
.AlphaTestEnable
= true;
3381 cc
.AlphaTestFunction
=
3382 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
3385 cc
.ColorDitherEnable
= ctx
->Color
.DitherFlag
;
3387 cc
.StatisticsEnable
= brw
->stats_wm
;
3389 cc
.CCViewportStatePointer
=
3390 ro_bo(brw
->batch
.state
.bo
, brw
->cc
.vp_offset
);
3393 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
3394 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
3395 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
3396 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
3400 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
3401 cc
.BackfaceStencilReferenceValue
=
3402 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
3408 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
3409 ctx
->Color
.AlphaRef
);
3413 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3414 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
3416 ptr
.ColorCalcStatePointerValid
= true;
3420 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
3424 static const struct brw_tracked_state
genX(color_calc_state
) = {
3426 .mesa
= _NEW_COLOR
|
3428 (GEN_GEN
<= 5 ? _NEW_BUFFERS
|
3431 .brw
= BRW_NEW_BATCH
|
3433 (GEN_GEN
<= 5 ? BRW_NEW_CC_VP
|
3435 : BRW_NEW_CC_STATE
|
3436 BRW_NEW_STATE_BASE_ADDRESS
),
3438 .emit
= genX(upload_color_calc_state
),
3442 /* ---------------------------------------------------------------------- */
3446 genX(upload_sbe
)(struct brw_context
*brw
)
3448 struct gl_context
*ctx
= &brw
->ctx
;
3449 /* BRW_NEW_FRAGMENT_PROGRAM */
3450 UNUSED
const struct gl_program
*fp
= brw
->programs
[MESA_SHADER_FRAGMENT
];
3451 /* BRW_NEW_FS_PROG_DATA */
3452 const struct brw_wm_prog_data
*wm_prog_data
=
3453 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3455 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3457 #define attr_overrides sbe.Attribute
3459 uint32_t urb_entry_read_length
;
3460 uint32_t urb_entry_read_offset
;
3461 uint32_t point_sprite_enables
;
3463 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3464 sbe
.AttributeSwizzleEnable
= true;
3465 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3468 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3472 * Window coordinates in an FBO are inverted, which means point
3473 * sprite origin must be inverted.
3475 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3476 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3478 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3480 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3481 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3482 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3483 * BRW_NEW_VUE_MAP_GEOM_OUT
3485 genX(calculate_attr_overrides
)(brw
,
3487 &point_sprite_enables
,
3488 &urb_entry_read_length
,
3489 &urb_entry_read_offset
);
3491 /* Typically, the URB entry read length and offset should be programmed
3492 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3493 * stage which produces geometry. However, we don't know the proper
3494 * value until we call calculate_attr_overrides().
3496 * To fit with our existing code, we override the inherited values and
3497 * specify it here directly, as we did on previous generations.
3499 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3500 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3501 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3502 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3505 sbe
.ForceVertexURBEntryReadLength
= true;
3506 sbe
.ForceVertexURBEntryReadOffset
= true;
3510 /* prepare the active component dwords */
3511 for (int i
= 0; i
< 32; i
++)
3512 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3517 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3518 for (int i
= 0; i
< 16; i
++)
3519 sbes
.Attribute
[i
] = attr_overrides
[i
];
3523 #undef attr_overrides
3526 static const struct brw_tracked_state
genX(sbe_state
) = {
3528 .mesa
= _NEW_BUFFERS
|
3533 .brw
= BRW_NEW_BLORP
|
3535 BRW_NEW_FRAGMENT_PROGRAM
|
3536 BRW_NEW_FS_PROG_DATA
|
3537 BRW_NEW_GS_PROG_DATA
|
3538 BRW_NEW_TES_PROG_DATA
|
3539 BRW_NEW_VUE_MAP_GEOM_OUT
|
3540 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3543 .emit
= genX(upload_sbe
),
3547 /* ---------------------------------------------------------------------- */
3551 * Outputs the 3DSTATE_SO_DECL_LIST command.
3553 * The data output is a series of 64-bit entries containing a SO_DECL per
3554 * stream. We only have one stream of rendering coming out of the GS unit, so
3555 * we only emit stream 0 (low 16 bits) SO_DECLs.
3558 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3559 const struct brw_vue_map
*vue_map
)
3561 struct gl_context
*ctx
= &brw
->ctx
;
3562 /* BRW_NEW_TRANSFORM_FEEDBACK */
3563 struct gl_transform_feedback_object
*xfb_obj
=
3564 ctx
->TransformFeedback
.CurrentObject
;
3565 const struct gl_transform_feedback_info
*linked_xfb_info
=
3566 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3567 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3568 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3569 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3570 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3572 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3574 memset(so_decl
, 0, sizeof(so_decl
));
3576 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3577 * command feels strange -- each dword pair contains a SO_DECL per stream.
3579 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3580 const struct gl_transform_feedback_output
*output
=
3581 &linked_xfb_info
->Outputs
[i
];
3582 const int buffer
= output
->OutputBuffer
;
3583 const int varying
= output
->OutputRegister
;
3584 const unsigned stream_id
= output
->StreamId
;
3585 assert(stream_id
< MAX_VERTEX_STREAMS
);
3587 buffer_mask
[stream_id
] |= 1 << buffer
;
3589 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3591 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3592 * array. Instead, it simply increments DstOffset for the following
3593 * input by the number of components that should be skipped.
3595 * Our hardware is unusual in that it requires us to program SO_DECLs
3596 * for fake "hole" components, rather than simply taking the offset
3597 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3598 * program as many size = 4 holes as we can, then a final hole to
3599 * accommodate the final 1, 2, or 3 remaining.
3601 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3603 while (skip_components
> 0) {
3604 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3606 .OutputBufferSlot
= output
->OutputBuffer
,
3607 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3609 skip_components
-= 4;
3612 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3614 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3615 .OutputBufferSlot
= output
->OutputBuffer
,
3616 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3618 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3621 if (decls
[stream_id
] > max_decls
)
3622 max_decls
= decls
[stream_id
];
3626 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3627 .StreamtoBufferSelects0
= buffer_mask
[0],
3628 .StreamtoBufferSelects1
= buffer_mask
[1],
3629 .StreamtoBufferSelects2
= buffer_mask
[2],
3630 .StreamtoBufferSelects3
= buffer_mask
[3],
3631 .NumEntries0
= decls
[0],
3632 .NumEntries1
= decls
[1],
3633 .NumEntries2
= decls
[2],
3634 .NumEntries3
= decls
[3]);
3636 for (int i
= 0; i
< max_decls
; i
++) {
3637 GENX(SO_DECL_ENTRY_pack
)(
3638 brw
, dw
+ 2 + i
* 2,
3639 &(struct GENX(SO_DECL_ENTRY
)) {
3640 .Stream0Decl
= so_decl
[0][i
],
3641 .Stream1Decl
= so_decl
[1][i
],
3642 .Stream2Decl
= so_decl
[2][i
],
3643 .Stream3Decl
= so_decl
[3][i
],
3649 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3651 struct gl_context
*ctx
= &brw
->ctx
;
3652 /* BRW_NEW_TRANSFORM_FEEDBACK */
3653 struct gl_transform_feedback_object
*xfb_obj
=
3654 ctx
->TransformFeedback
.CurrentObject
;
3656 const struct gl_transform_feedback_info
*linked_xfb_info
=
3657 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3659 struct brw_transform_feedback_object
*brw_obj
=
3660 (struct brw_transform_feedback_object
*) xfb_obj
;
3661 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3664 /* Set up the up to 4 output buffers. These are the ranges defined in the
3665 * gl_transform_feedback_object.
3667 for (int i
= 0; i
< 4; i
++) {
3668 struct intel_buffer_object
*bufferobj
=
3669 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3672 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3673 sob
.SOBufferIndex
= i
;
3678 uint32_t start
= xfb_obj
->Offset
[i
];
3679 assert(start
% 4 == 0);
3680 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3682 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
, true);
3683 assert(end
<= bo
->size
);
3685 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3686 sob
.SOBufferIndex
= i
;
3688 sob
.SurfaceBaseAddress
= rw_bo(bo
, start
);
3690 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3691 sob
.SurfaceEndAddress
= rw_bo(bo
, end
);
3693 sob
.SOBufferEnable
= true;
3694 sob
.StreamOffsetWriteEnable
= true;
3695 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3696 sob
.SOBufferMOCS
= mocs_wb
;
3698 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3699 sob
.StreamOutputBufferOffsetAddress
=
3700 rw_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3702 if (brw_obj
->zero_offsets
) {
3703 /* Zero out the offset and write that to offset_bo */
3704 sob
.StreamOffset
= 0;
3706 /* Use offset_bo as the "Stream Offset." */
3707 sob
.StreamOffset
= 0xFFFFFFFF;
3714 brw_obj
->zero_offsets
= false;
3719 query_active(struct gl_query_object
*q
)
3721 return q
&& q
->Active
;
3725 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3726 const struct brw_vue_map
*vue_map
)
3728 struct gl_context
*ctx
= &brw
->ctx
;
3729 /* BRW_NEW_TRANSFORM_FEEDBACK */
3730 struct gl_transform_feedback_object
*xfb_obj
=
3731 ctx
->TransformFeedback
.CurrentObject
;
3733 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3735 int urb_entry_read_offset
= 0;
3736 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3737 urb_entry_read_offset
;
3739 sos
.SOFunctionEnable
= true;
3740 sos
.SOStatisticsEnable
= true;
3742 /* BRW_NEW_RASTERIZER_DISCARD */
3743 if (ctx
->RasterDiscard
) {
3744 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3745 sos
.RenderingDisable
= true;
3747 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3748 "query active relies on the clipper.\n");
3753 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3754 sos
.ReorderMode
= TRAILING
;
3757 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3758 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3759 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3760 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3762 const struct gl_transform_feedback_info
*linked_xfb_info
=
3763 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3764 /* Set buffer pitches; 0 means unbound. */
3765 if (xfb_obj
->Buffers
[0])
3766 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3767 if (xfb_obj
->Buffers
[1])
3768 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3769 if (xfb_obj
->Buffers
[2])
3770 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3771 if (xfb_obj
->Buffers
[3])
3772 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3775 /* We always read the whole vertex. This could be reduced at some
3776 * point by reading less and offsetting the register index in the
3779 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3780 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3781 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3782 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3783 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3784 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3785 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3786 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3792 genX(upload_sol
)(struct brw_context
*brw
)
3794 struct gl_context
*ctx
= &brw
->ctx
;
3795 /* BRW_NEW_TRANSFORM_FEEDBACK */
3796 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3799 genX(upload_3dstate_so_buffers
)(brw
);
3801 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3802 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3805 /* Finally, set up the SOL stage. This command must always follow updates to
3806 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3807 * MMIO register updates (current performed by the kernel at each batch
3810 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3813 static const struct brw_tracked_state
genX(sol_state
) = {
3816 .brw
= BRW_NEW_BATCH
|
3818 BRW_NEW_RASTERIZER_DISCARD
|
3819 BRW_NEW_VUE_MAP_GEOM_OUT
|
3820 BRW_NEW_TRANSFORM_FEEDBACK
,
3822 .emit
= genX(upload_sol
),
3826 /* ---------------------------------------------------------------------- */
3830 genX(upload_ps
)(struct brw_context
*brw
)
3832 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3833 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3835 /* BRW_NEW_FS_PROG_DATA */
3836 const struct brw_wm_prog_data
*prog_data
=
3837 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3838 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3843 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3844 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3845 * incorrect for subspans where some of the pixels are unlit. We believe
3846 * the bit just didn't take effect in previous generations.
3848 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3851 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3853 /* BRW_NEW_FS_PROG_DATA */
3854 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3856 if (prog_data
->base
.use_alt_mode
)
3857 ps
.FloatingPointMode
= Alternate
;
3859 /* Haswell requires the sample mask to be set in this packet as well as
3860 * in 3DSTATE_SAMPLE_MASK; the values should match.
3863 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3865 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3868 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
3869 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
3870 * k, it implies 2(k+1) threads. It implicitly scales for different GT
3871 * levels (which have some # of PSDs).
3873 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
3876 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3878 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3880 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3883 if (prog_data
->base
.nr_params
> 0 ||
3884 prog_data
->base
.ubo_ranges
[0].length
> 0)
3885 ps
.PushConstantEnable
= true;
3888 /* From the IVB PRM, volume 2 part 1, page 287:
3889 * "This bit is inserted in the PS payload header and made available to
3890 * the DataPort (either via the message header or via header bypass) to
3891 * indicate that oMask data (one or two phases) is included in Render
3892 * Target Write messages. If present, the oMask data is used to mask off
3895 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3897 /* The hardware wedges if you have this bit set but don't turn on any
3898 * dual source blend factors.
3900 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3902 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3903 (ctx
->Color
.BlendEnabled
& 1) &&
3904 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3906 /* BRW_NEW_FS_PROG_DATA */
3907 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3910 /* From the documentation for this packet:
3911 * "If the PS kernel does not need the Position XY Offsets to
3912 * compute a Position Value, then this field should be programmed
3913 * to POSOFFSET_NONE."
3915 * "SW Recommendation: If the PS kernel needs the Position Offsets
3916 * to compute a Position XY value, this field should match Position
3917 * ZW Interpolation Mode to ensure a consistent position.xyzw
3920 * We only require XY sample offsets. So, this recommendation doesn't
3921 * look useful at the moment. We might need this in future.
3923 if (prog_data
->uses_pos_offset
)
3924 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3926 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3928 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3929 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3930 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3931 prog_data
->base
.dispatch_grf_start_reg
;
3932 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3933 prog_data
->dispatch_grf_start_reg_2
;
3935 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3936 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3937 prog_data
->prog_offset_2
;
3939 if (prog_data
->base
.total_scratch
) {
3940 ps
.ScratchSpaceBasePointer
=
3941 rw_32_bo(stage_state
->scratch_bo
,
3942 ffs(stage_state
->per_thread_scratch
) - 11);
3947 static const struct brw_tracked_state
genX(ps_state
) = {
3949 .mesa
= _NEW_MULTISAMPLE
|
3950 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3953 .brw
= BRW_NEW_BATCH
|
3955 BRW_NEW_FS_PROG_DATA
,
3957 .emit
= genX(upload_ps
),
3961 /* ---------------------------------------------------------------------- */
3965 genX(upload_hs_state
)(struct brw_context
*brw
)
3967 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3968 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3969 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3970 const struct brw_vue_prog_data
*vue_prog_data
=
3971 brw_vue_prog_data(stage_prog_data
);
3973 /* BRW_NEW_TES_PROG_DATA */
3974 struct brw_tcs_prog_data
*tcs_prog_data
=
3975 brw_tcs_prog_data(stage_prog_data
);
3977 if (!tcs_prog_data
) {
3978 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3980 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3981 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3983 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3984 hs
.IncludeVertexHandles
= true;
3986 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3991 static const struct brw_tracked_state
genX(hs_state
) = {
3994 .brw
= BRW_NEW_BATCH
|
3996 BRW_NEW_TCS_PROG_DATA
|
3997 BRW_NEW_TESS_PROGRAMS
,
3999 .emit
= genX(upload_hs_state
),
4003 genX(upload_ds_state
)(struct brw_context
*brw
)
4005 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4006 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4007 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
4009 /* BRW_NEW_TES_PROG_DATA */
4010 const struct brw_tes_prog_data
*tes_prog_data
=
4011 brw_tes_prog_data(stage_prog_data
);
4012 const struct brw_vue_prog_data
*vue_prog_data
=
4013 brw_vue_prog_data(stage_prog_data
);
4015 if (!tes_prog_data
) {
4016 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
4018 assert(GEN_GEN
< 11 ||
4019 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
);
4021 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
4022 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
4024 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4025 ds
.ComputeWCoordinateEnable
=
4026 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4029 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
4030 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4031 ds
.UserClipDistanceCullTestEnableBitmask
=
4032 vue_prog_data
->cull_distance_mask
;
4038 static const struct brw_tracked_state
genX(ds_state
) = {
4041 .brw
= BRW_NEW_BATCH
|
4043 BRW_NEW_TESS_PROGRAMS
|
4044 BRW_NEW_TES_PROG_DATA
,
4046 .emit
= genX(upload_ds_state
),
4049 /* ---------------------------------------------------------------------- */
4052 upload_te_state(struct brw_context
*brw
)
4054 /* BRW_NEW_TESS_PROGRAMS */
4055 bool active
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4057 /* BRW_NEW_TES_PROG_DATA */
4058 const struct brw_tes_prog_data
*tes_prog_data
=
4059 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
4062 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
4063 te
.Partitioning
= tes_prog_data
->partitioning
;
4064 te
.OutputTopology
= tes_prog_data
->output_topology
;
4065 te
.TEDomain
= tes_prog_data
->domain
;
4067 te
.MaximumTessellationFactorOdd
= 63.0;
4068 te
.MaximumTessellationFactorNotOdd
= 64.0;
4071 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
4075 static const struct brw_tracked_state
genX(te_state
) = {
4078 .brw
= BRW_NEW_BLORP
|
4080 BRW_NEW_TES_PROG_DATA
|
4081 BRW_NEW_TESS_PROGRAMS
,
4083 .emit
= upload_te_state
,
4086 /* ---------------------------------------------------------------------- */
4089 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
4091 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
4092 /* BRW_NEW_TESS_PROGRAMS */
4093 const struct gl_program
*tep
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
4095 /* BRW_NEW_TES_PROG_DATA */
4096 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
4097 gen6_upload_push_constants(brw
, tep
, prog_data
, stage_state
);
4100 static const struct brw_tracked_state
genX(tes_push_constants
) = {
4102 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4103 .brw
= BRW_NEW_BATCH
|
4105 BRW_NEW_TESS_PROGRAMS
|
4106 BRW_NEW_TES_PROG_DATA
,
4108 .emit
= genX(upload_tes_push_constants
),
4112 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
4114 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
4115 /* BRW_NEW_TESS_PROGRAMS */
4116 const struct gl_program
*tcp
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
4118 /* BRW_NEW_TCS_PROG_DATA */
4119 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
4121 gen6_upload_push_constants(brw
, tcp
, prog_data
, stage_state
);
4124 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
4126 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4127 .brw
= BRW_NEW_BATCH
|
4129 BRW_NEW_DEFAULT_TESS_LEVELS
|
4130 BRW_NEW_TESS_PROGRAMS
|
4131 BRW_NEW_TCS_PROG_DATA
,
4133 .emit
= genX(upload_tcs_push_constants
),
4138 /* ---------------------------------------------------------------------- */
4142 genX(upload_cs_push_constants
)(struct brw_context
*brw
)
4144 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4146 /* BRW_NEW_COMPUTE_PROGRAM */
4147 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
4150 /* BRW_NEW_CS_PROG_DATA */
4151 struct brw_cs_prog_data
*cs_prog_data
=
4152 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
4154 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4155 brw_upload_cs_push_constants(brw
, cp
, cs_prog_data
, stage_state
);
4159 const struct brw_tracked_state
genX(cs_push_constants
) = {
4161 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4162 .brw
= BRW_NEW_BATCH
|
4164 BRW_NEW_COMPUTE_PROGRAM
|
4165 BRW_NEW_CS_PROG_DATA
,
4167 .emit
= genX(upload_cs_push_constants
),
4171 * Creates a new CS constant buffer reflecting the current CS program's
4172 * constants, if needed by the CS program.
4175 genX(upload_cs_pull_constants
)(struct brw_context
*brw
)
4177 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4179 /* BRW_NEW_COMPUTE_PROGRAM */
4180 struct brw_program
*cp
=
4181 (struct brw_program
*) brw
->programs
[MESA_SHADER_COMPUTE
];
4183 /* BRW_NEW_CS_PROG_DATA */
4184 const struct brw_stage_prog_data
*prog_data
= brw
->cs
.base
.prog_data
;
4186 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_COMPUTE
);
4187 /* _NEW_PROGRAM_CONSTANTS */
4188 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &cp
->program
,
4189 stage_state
, prog_data
);
4192 const struct brw_tracked_state
genX(cs_pull_constants
) = {
4194 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4195 .brw
= BRW_NEW_BATCH
|
4197 BRW_NEW_COMPUTE_PROGRAM
|
4198 BRW_NEW_CS_PROG_DATA
,
4200 .emit
= genX(upload_cs_pull_constants
),
4204 genX(upload_cs_state
)(struct brw_context
*brw
)
4206 if (!brw
->cs
.base
.prog_data
)
4210 uint32_t *desc
= (uint32_t*) brw_state_batch(
4211 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
4214 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
4215 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
4216 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
4217 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
4219 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4220 brw_emit_buffer_surface_state(
4221 brw
, &stage_state
->surf_offset
[
4222 prog_data
->binding_table
.shader_time_start
],
4223 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
4224 brw
->shader_time
.bo
->size
, 1,
4228 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
4229 32, &stage_state
->bind_bo_offset
);
4231 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4233 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4234 * the only bits that are changed are scoreboard related: Scoreboard
4235 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4236 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4238 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4239 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4241 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
4243 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
4244 if (prog_data
->total_scratch
) {
4245 uint32_t per_thread_scratch_value
;
4248 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4249 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4251 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 11;
4252 } else if (GEN_IS_HASWELL
) {
4253 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4254 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4256 per_thread_scratch_value
= ffs(stage_state
->per_thread_scratch
) - 12;
4258 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4259 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4261 per_thread_scratch_value
= stage_state
->per_thread_scratch
/ 1024 - 1;
4263 vfe
.ScratchSpaceBasePointer
= rw_32_bo(stage_state
->scratch_bo
, 0);
4264 vfe
.PerThreadScratchSpace
= per_thread_scratch_value
;
4267 /* If brw->screen->subslice_total is greater than one, then
4268 * devinfo->max_cs_threads stores number of threads per sub-slice;
4269 * thus we need to multiply by that number by subslices to get
4270 * the actual maximum number of threads; the -1 is because the HW
4271 * has a bias of 1 (would not make sense to say the maximum number
4274 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
4275 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
4276 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
4278 vfe
.ResetGatewayTimer
=
4279 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4282 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
4288 /* We are uploading duplicated copies of push constant uniforms for each
4289 * thread. Although the local id data needs to vary per thread, it won't
4290 * change for other uniform data. Unfortunately this duplication is
4291 * required for gen7. As of Haswell, this duplication can be avoided,
4292 * but this older mechanism with duplicated data continues to work.
4294 * FINISHME: As of Haswell, we could make use of the
4295 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4296 * field to only store one copy of uniform data.
4298 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4299 * which is described in the GPGPU_WALKER command and in the Broadwell
4300 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4301 * Operations => GPGPU Mode => Indirect Payload Storage.
4303 * Note: The constant data is built in brw_upload_cs_push_constants
4306 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
4308 const uint32_t vfe_curbe_allocation
=
4309 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4310 cs_prog_data
->push
.cross_thread
.regs
, 2);
4311 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
4314 if (cs_prog_data
->push
.total
.size
> 0) {
4315 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4316 curbe
.CURBETotalDataLength
=
4317 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4318 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
4322 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4323 memcpy(bind
, stage_state
->surf_offset
,
4324 prog_data
->binding_table
.size_bytes
);
4325 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
4326 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
4327 .SamplerStatePointer
= stage_state
->sampler_offset
,
4328 .SamplerCount
= DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4),
4329 .BindingTablePointer
= stage_state
->bind_bo_offset
,
4330 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
4331 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
4332 .SharedLocalMemorySize
= encode_slm_size(GEN_GEN
,
4333 prog_data
->total_shared
),
4334 .BarrierEnable
= cs_prog_data
->uses_barrier
,
4335 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4336 .CrossThreadConstantDataReadLength
=
4337 cs_prog_data
->push
.cross_thread
.regs
,
4341 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
4343 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4344 load
.InterfaceDescriptorTotalLength
=
4345 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4346 load
.InterfaceDescriptorDataStartAddress
= offset
;
4350 static const struct brw_tracked_state
genX(cs_state
) = {
4352 .mesa
= _NEW_PROGRAM_CONSTANTS
,
4353 .brw
= BRW_NEW_BATCH
|
4355 BRW_NEW_CS_PROG_DATA
|
4356 BRW_NEW_SAMPLER_STATE_TABLE
|
4359 .emit
= genX(upload_cs_state
)
4364 /* ---------------------------------------------------------------------- */
4368 genX(upload_raster
)(struct brw_context
*brw
)
4370 const struct gl_context
*ctx
= &brw
->ctx
;
4373 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
4376 const struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
4379 const struct gl_point_attrib
*point
= &ctx
->Point
;
4381 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
4382 if (brw
->polygon_front_bit
== render_to_fbo
)
4383 raster
.FrontWinding
= CounterClockwise
;
4385 if (polygon
->CullFlag
) {
4386 switch (polygon
->CullFaceMode
) {
4388 raster
.CullMode
= CULLMODE_FRONT
;
4391 raster
.CullMode
= CULLMODE_BACK
;
4393 case GL_FRONT_AND_BACK
:
4394 raster
.CullMode
= CULLMODE_BOTH
;
4397 unreachable("not reached");
4400 raster
.CullMode
= CULLMODE_NONE
;
4403 raster
.SmoothPointEnable
= point
->SmoothFlag
;
4405 raster
.DXMultisampleRasterizationEnable
=
4406 _mesa_is_multisample_enabled(ctx
);
4408 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
4409 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
4410 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
4412 switch (polygon
->FrontMode
) {
4414 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
4417 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
4420 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
4423 unreachable("not reached");
4426 switch (polygon
->BackMode
) {
4428 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
4431 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
4434 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
4437 unreachable("not reached");
4441 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
4445 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4447 const bool multisampled_fbo
=
4448 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
4449 if (multisampled_fbo
)
4450 raster
.AntialiasingEnable
= false;
4454 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
4456 /* _NEW_TRANSFORM */
4457 if (!ctx
->Transform
.DepthClamp
) {
4459 raster
.ViewportZFarClipTestEnable
= true;
4460 raster
.ViewportZNearClipTestEnable
= true;
4462 raster
.ViewportZClipTestEnable
= true;
4466 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4468 raster
.ConservativeRasterizationEnable
=
4469 ctx
->IntelConservativeRasterization
;
4472 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
4473 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
4475 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
4479 static const struct brw_tracked_state
genX(raster_state
) = {
4481 .mesa
= _NEW_BUFFERS
|
4488 .brw
= BRW_NEW_BLORP
|
4490 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4492 .emit
= genX(upload_raster
),
4496 /* ---------------------------------------------------------------------- */
4500 genX(upload_ps_extra
)(struct brw_context
*brw
)
4502 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
4504 const struct brw_wm_prog_data
*prog_data
=
4505 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
4507 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
4508 psx
.PixelShaderValid
= true;
4509 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4510 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4511 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4512 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4513 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4514 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4516 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4517 if (prog_data
->uses_sample_mask
) {
4519 if (prog_data
->post_depth_coverage
)
4520 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4521 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4522 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4524 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4526 psx
.PixelShaderUsesInputCoverageMask
= true;
4530 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4532 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4533 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4536 /* The stricter cross-primitive coherency guarantees that the hardware
4537 * gives us with the "Accesses UAV" bit set for at least one shader stage
4538 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4539 * are redundant within the current image, atomic counter and SSBO GL
4540 * APIs, which all have very loose ordering and coherency requirements
4541 * and generally rely on the application to insert explicit barriers when
4542 * a shader invocation is expected to see the memory writes performed by
4543 * the invocations of some previous primitive. Regardless of the value
4544 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4545 * cause an in most cases useless DC flush when the lowermost stage with
4546 * the bit set finishes execution.
4548 * It would be nice to disable it, but in some cases we can't because on
4549 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4550 * signal (which could be set independently from the coherency mechanism
4551 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4552 * determine whether the hardware skips execution of the fragment shader
4553 * or not via the ThreadDispatchEnable signal. However if we know that
4554 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4555 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4556 * difference so we may just disable it here.
4558 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4559 * take into account KillPixels when no depth or stencil writes are
4560 * enabled. In order for occlusion queries to work correctly with no
4561 * attachments, we need to force-enable here.
4563 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4566 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4567 !brw_color_buffer_write_enabled(brw
))
4568 psx
.PixelShaderHasUAV
= true;
4572 const struct brw_tracked_state
genX(ps_extra
) = {
4574 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4575 .brw
= BRW_NEW_BLORP
|
4577 BRW_NEW_FRAGMENT_PROGRAM
|
4578 BRW_NEW_FS_PROG_DATA
|
4579 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4581 .emit
= genX(upload_ps_extra
),
4585 /* ---------------------------------------------------------------------- */
4589 genX(upload_ps_blend
)(struct brw_context
*brw
)
4591 struct gl_context
*ctx
= &brw
->ctx
;
4594 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4595 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4598 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4600 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4601 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4602 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4604 bool alpha_to_one
= false;
4606 if (!buffer0_is_integer
) {
4607 /* _NEW_MULTISAMPLE */
4609 if (_mesa_is_multisample_enabled(ctx
)) {
4610 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4611 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4614 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4617 /* Used for implementing the following bit of GL_EXT_texture_integer:
4618 * "Per-fragment operations that require floating-point color
4619 * components, including multisample alpha operations, alpha test,
4620 * blending, and dithering, have no effect when the corresponding
4621 * colors are written to an integer color buffer."
4623 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4624 * "If drawbuffer zero is not NONE and the buffer it references has an
4625 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4626 * operations are skipped."
4628 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4629 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4630 GLenum eqA
= color
->Blend
[0].EquationA
;
4631 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4632 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4633 GLenum srcA
= color
->Blend
[0].SrcA
;
4634 GLenum dstA
= color
->Blend
[0].DstA
;
4636 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4637 srcRGB
= dstRGB
= GL_ONE
;
4639 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4640 srcA
= dstA
= GL_ONE
;
4642 /* Due to hardware limitations, the destination may have information
4643 * in an alpha channel even when the format specifies no alpha
4644 * channel. In order to avoid getting any incorrect blending due to
4645 * that alpha channel, coerce the blend factors to values that will
4646 * not read the alpha channel, but will instead use the correct
4647 * implicit value for alpha.
4649 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4650 GL_TEXTURE_ALPHA_TYPE
)) {
4651 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4652 srcA
= brw_fix_xRGB_alpha(srcA
);
4653 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4654 dstA
= brw_fix_xRGB_alpha(dstA
);
4657 /* Alpha to One doesn't work with Dual Color Blending. Override
4658 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4660 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4661 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4662 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4663 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4664 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4667 pb
.ColorBufferBlendEnable
= true;
4668 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4669 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4670 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4671 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4673 pb
.IndependentAlphaBlendEnable
=
4674 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4679 static const struct brw_tracked_state
genX(ps_blend
) = {
4681 .mesa
= _NEW_BUFFERS
|
4684 .brw
= BRW_NEW_BLORP
|
4686 BRW_NEW_FRAGMENT_PROGRAM
,
4688 .emit
= genX(upload_ps_blend
)
4692 /* ---------------------------------------------------------------------- */
4696 genX(emit_vf_topology
)(struct brw_context
*brw
)
4698 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4699 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4703 static const struct brw_tracked_state
genX(vf_topology
) = {
4706 .brw
= BRW_NEW_BLORP
|
4709 .emit
= genX(emit_vf_topology
),
4713 /* ---------------------------------------------------------------------- */
4717 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4719 uint32_t offset_in_bytes
,
4722 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4723 mi_rpc
.MemoryAddress
= ggtt_bo(bo
, offset_in_bytes
);
4724 mi_rpc
.ReportID
= report_id
;
4729 /* ---------------------------------------------------------------------- */
4732 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4735 genX(emit_sampler_state_pointers_xs
)(struct brw_context
*brw
,
4736 struct brw_stage_state
*stage_state
)
4739 static const uint16_t packet_headers
[] = {
4740 [MESA_SHADER_VERTEX
] = 43,
4741 [MESA_SHADER_TESS_CTRL
] = 44,
4742 [MESA_SHADER_TESS_EVAL
] = 45,
4743 [MESA_SHADER_GEOMETRY
] = 46,
4744 [MESA_SHADER_FRAGMENT
] = 47,
4747 /* Ivybridge requires a workaround flush before VS packets. */
4748 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&&
4749 stage_state
->stage
== MESA_SHADER_VERTEX
) {
4750 gen7_emit_vs_workaround_flush(brw
);
4753 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4754 ptr
._3DCommandSubOpcode
= packet_headers
[stage_state
->stage
];
4755 ptr
.PointertoVSSamplerState
= stage_state
->sampler_offset
;
4761 has_component(mesa_format format
, int i
)
4763 if (_mesa_is_format_color_format(format
))
4764 return _mesa_format_has_color_component(format
, i
);
4766 /* depth and stencil have only one component */
4771 * Upload SAMPLER_BORDER_COLOR_STATE.
4774 genX(upload_default_color
)(struct brw_context
*brw
,
4775 const struct gl_sampler_object
*sampler
,
4776 mesa_format format
, GLenum base_format
,
4777 bool is_integer_format
, bool is_stencil_sampling
,
4778 uint32_t *sdc_offset
)
4780 union gl_color_union color
;
4782 switch (base_format
) {
4783 case GL_DEPTH_COMPONENT
:
4784 /* GL specs that border color for depth textures is taken from the
4785 * R channel, while the hardware uses A. Spam R into all the
4786 * channels for safety.
4788 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4789 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4790 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4791 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4797 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4800 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4801 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4802 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4803 color
.ui
[3] = sampler
->BorderColor
.ui
[0];
4806 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4807 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4808 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4809 color
.ui
[3] = float_as_int(1.0);
4811 case GL_LUMINANCE_ALPHA
:
4812 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4813 color
.ui
[1] = sampler
->BorderColor
.ui
[0];
4814 color
.ui
[2] = sampler
->BorderColor
.ui
[0];
4815 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4818 color
.ui
[0] = sampler
->BorderColor
.ui
[0];
4819 color
.ui
[1] = sampler
->BorderColor
.ui
[1];
4820 color
.ui
[2] = sampler
->BorderColor
.ui
[2];
4821 color
.ui
[3] = sampler
->BorderColor
.ui
[3];
4825 /* In some cases we use an RGBA surface format for GL RGB textures,
4826 * where we've initialized the A channel to 1.0. We also have to set
4827 * the border color alpha to 1.0 in that case.
4829 if (base_format
== GL_RGB
)
4830 color
.ui
[3] = float_as_int(1.0);
4835 } else if (GEN_IS_HASWELL
&& (is_integer_format
|| is_stencil_sampling
)) {
4839 uint32_t *sdc
= brw_state_batch(
4840 brw
, GENX(SAMPLER_BORDER_COLOR_STATE_length
) * sizeof(uint32_t),
4841 alignment
, sdc_offset
);
4843 struct GENX(SAMPLER_BORDER_COLOR_STATE
) state
= { 0 };
4845 #define ASSIGN(dst, src) \
4850 #define ASSIGNu16(dst, src) \
4852 dst = (uint16_t)src; \
4855 #define ASSIGNu8(dst, src) \
4857 dst = (uint8_t)src; \
4860 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
4861 macro(state.BorderColor ## _color_type ## Red, src[0]); \
4862 macro(state.BorderColor ## _color_type ## Green, src[1]); \
4863 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
4864 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
4867 /* On Broadwell, the border color is represented as four 32-bit floats,
4868 * integers, or unsigned values, interpreted according to the surface
4869 * format. This matches the sampler->BorderColor union exactly; just
4870 * memcpy the values.
4872 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, color
.ui
);
4873 #elif GEN_IS_HASWELL
4874 if (is_integer_format
|| is_stencil_sampling
) {
4875 bool stencil
= format
== MESA_FORMAT_S_UINT8
|| is_stencil_sampling
;
4876 const int bits_per_channel
=
4877 _mesa_get_format_bits(format
, stencil
? GL_STENCIL_BITS
: GL_RED_BITS
);
4879 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
4880 * "If any color channel is missing from the surface format,
4881 * corresponding border color should be programmed as zero and if
4882 * alpha channel is missing, corresponding Alpha border color should
4883 * be programmed as 1."
4885 unsigned c
[4] = { 0, 0, 0, 1 };
4886 for (int i
= 0; i
< 4; i
++) {
4887 if (has_component(format
, i
))
4891 switch (bits_per_channel
) {
4893 /* Copy RGBA in order. */
4894 BORDER_COLOR_ATTR(ASSIGNu8
, 8bit
, c
);
4897 /* R10G10B10A2_UINT is treated like a 16-bit format. */
4899 BORDER_COLOR_ATTR(ASSIGNu16
, 16bit
, c
);
4902 if (base_format
== GL_RG
) {
4903 /* Careful inspection of the tables reveals that for RG32 formats,
4904 * the green channel needs to go where blue normally belongs.
4906 state
.BorderColor32bitRed
= c
[0];
4907 state
.BorderColor32bitBlue
= c
[1];
4908 state
.BorderColor32bitAlpha
= 1;
4910 /* Copy RGBA in order. */
4911 BORDER_COLOR_ATTR(ASSIGN
, 32bit
, c
);
4915 assert(!"Invalid number of bits per channel in integer format.");
4919 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4921 #elif GEN_GEN == 5 || GEN_GEN == 6
4922 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE
, Unorm
, color
.f
);
4923 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT
, Unorm16
, color
.f
);
4924 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT
, Snorm16
, color
.f
);
4926 #define MESA_FLOAT_TO_HALF(dst, src) \
4927 dst = _mesa_float_to_half(src);
4929 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF
, Float16
, color
.f
);
4931 #undef MESA_FLOAT_TO_HALF
4933 state
.BorderColorSnorm8Red
= state
.BorderColorSnorm16Red
>> 8;
4934 state
.BorderColorSnorm8Green
= state
.BorderColorSnorm16Green
>> 8;
4935 state
.BorderColorSnorm8Blue
= state
.BorderColorSnorm16Blue
>> 8;
4936 state
.BorderColorSnorm8Alpha
= state
.BorderColorSnorm16Alpha
>> 8;
4938 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4940 BORDER_COLOR_ATTR(ASSIGN
, , color
.f
);
4942 BORDER_COLOR_ATTR(ASSIGN
, Float
, color
.f
);
4946 #undef BORDER_COLOR_ATTR
4948 GENX(SAMPLER_BORDER_COLOR_STATE_pack
)(brw
, sdc
, &state
);
4952 translate_wrap_mode(struct brw_context
*brw
, GLenum wrap
, bool using_nearest
)
4959 /* GL_CLAMP is the weird mode where coordinates are clamped to
4960 * [0.0, 1.0], so linear filtering of coordinates outside of
4961 * [0.0, 1.0] give you half edge texel value and half border
4964 * Gen8+ supports this natively.
4966 return TCM_HALF_BORDER
;
4968 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
4969 * and set clamp_border here, which gets the result desired.
4970 * We just use clamp(_to_edge) for nearest, because for nearest
4971 * clamping to 1.0 gives border color instead of the desired
4977 return TCM_CLAMP_BORDER
;
4979 case GL_CLAMP_TO_EDGE
:
4981 case GL_CLAMP_TO_BORDER
:
4982 return TCM_CLAMP_BORDER
;
4983 case GL_MIRRORED_REPEAT
:
4985 case GL_MIRROR_CLAMP_TO_EDGE
:
4986 return TCM_MIRROR_ONCE
;
4993 * Return true if the given wrap mode requires the border color to exist.
4996 wrap_mode_needs_border_color(unsigned wrap_mode
)
4999 return wrap_mode
== TCM_CLAMP_BORDER
||
5000 wrap_mode
== TCM_HALF_BORDER
;
5002 return wrap_mode
== TCM_CLAMP_BORDER
;
5007 * Sets the sampler state for a single unit based off of the sampler key
5011 genX(update_sampler_state
)(struct brw_context
*brw
,
5012 GLenum target
, bool tex_cube_map_seamless
,
5013 GLfloat tex_unit_lod_bias
,
5014 mesa_format format
, GLenum base_format
,
5015 const struct gl_texture_object
*texObj
,
5016 const struct gl_sampler_object
*sampler
,
5017 uint32_t *sampler_state
,
5018 uint32_t batch_offset_for_sampler_state
)
5020 struct GENX(SAMPLER_STATE
) samp_st
= { 0 };
5022 /* Select min and mip filters. */
5023 switch (sampler
->MinFilter
) {
5025 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5026 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5029 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5030 samp_st
.MipModeFilter
= MIPFILTER_NONE
;
5032 case GL_NEAREST_MIPMAP_NEAREST
:
5033 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5034 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5036 case GL_LINEAR_MIPMAP_NEAREST
:
5037 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5038 samp_st
.MipModeFilter
= MIPFILTER_NEAREST
;
5040 case GL_NEAREST_MIPMAP_LINEAR
:
5041 samp_st
.MinModeFilter
= MAPFILTER_NEAREST
;
5042 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5044 case GL_LINEAR_MIPMAP_LINEAR
:
5045 samp_st
.MinModeFilter
= MAPFILTER_LINEAR
;
5046 samp_st
.MipModeFilter
= MIPFILTER_LINEAR
;
5049 unreachable("not reached");
5052 /* Select mag filter. */
5053 samp_st
.MagModeFilter
= sampler
->MagFilter
== GL_LINEAR
?
5054 MAPFILTER_LINEAR
: MAPFILTER_NEAREST
;
5056 /* Enable anisotropic filtering if desired. */
5057 samp_st
.MaximumAnisotropy
= RATIO21
;
5059 if (sampler
->MaxAnisotropy
> 1.0f
) {
5060 if (samp_st
.MinModeFilter
== MAPFILTER_LINEAR
)
5061 samp_st
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
5062 if (samp_st
.MagModeFilter
== MAPFILTER_LINEAR
)
5063 samp_st
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
5065 if (sampler
->MaxAnisotropy
> 2.0f
) {
5066 samp_st
.MaximumAnisotropy
=
5067 MIN2((sampler
->MaxAnisotropy
- 2) / 2, RATIO161
);
5071 /* Set address rounding bits if not using nearest filtering. */
5072 if (samp_st
.MinModeFilter
!= MAPFILTER_NEAREST
) {
5073 samp_st
.UAddressMinFilterRoundingEnable
= true;
5074 samp_st
.VAddressMinFilterRoundingEnable
= true;
5075 samp_st
.RAddressMinFilterRoundingEnable
= true;
5078 if (samp_st
.MagModeFilter
!= MAPFILTER_NEAREST
) {
5079 samp_st
.UAddressMagFilterRoundingEnable
= true;
5080 samp_st
.VAddressMagFilterRoundingEnable
= true;
5081 samp_st
.RAddressMagFilterRoundingEnable
= true;
5084 bool either_nearest
=
5085 sampler
->MinFilter
== GL_NEAREST
|| sampler
->MagFilter
== GL_NEAREST
;
5086 unsigned wrap_s
= translate_wrap_mode(brw
, sampler
->WrapS
, either_nearest
);
5087 unsigned wrap_t
= translate_wrap_mode(brw
, sampler
->WrapT
, either_nearest
);
5088 unsigned wrap_r
= translate_wrap_mode(brw
, sampler
->WrapR
, either_nearest
);
5090 if (target
== GL_TEXTURE_CUBE_MAP
||
5091 target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
5092 /* Cube maps must use the same wrap mode for all three coordinate
5093 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5095 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5096 * integer formats. Fall back to CLAMP for now.
5098 if ((tex_cube_map_seamless
|| sampler
->CubeMapSeamless
) &&
5099 !(GEN_GEN
== 7 && !GEN_IS_HASWELL
&& texObj
->_IsIntegerFormat
)) {
5108 } else if (target
== GL_TEXTURE_1D
) {
5109 /* There's a bug in 1D texture sampling - it actually pays
5110 * attention to the wrap_t value, though it should not.
5111 * Override the wrap_t value here to GL_REPEAT to keep
5112 * any nonexistent border pixels from floating in.
5117 samp_st
.TCXAddressControlMode
= wrap_s
;
5118 samp_st
.TCYAddressControlMode
= wrap_t
;
5119 samp_st
.TCZAddressControlMode
= wrap_r
;
5121 samp_st
.ShadowFunction
=
5122 sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
?
5123 intel_translate_shadow_compare_func(sampler
->CompareFunc
) : 0;
5126 /* Set shadow function. */
5127 samp_st
.AnisotropicAlgorithm
=
5128 samp_st
.MinModeFilter
== MAPFILTER_ANISOTROPIC
?
5129 EWAApproximation
: LEGACY
;
5133 samp_st
.NonnormalizedCoordinateEnable
= target
== GL_TEXTURE_RECTANGLE
;
5136 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
5137 samp_st
.MinLOD
= CLAMP(sampler
->MinLod
, 0, hw_max_lod
);
5138 samp_st
.MaxLOD
= CLAMP(sampler
->MaxLod
, 0, hw_max_lod
);
5139 samp_st
.TextureLODBias
=
5140 CLAMP(tex_unit_lod_bias
+ sampler
->LodBias
, -16, 15);
5143 samp_st
.BaseMipLevel
=
5144 CLAMP(texObj
->MinLevel
+ texObj
->BaseLevel
, 0, hw_max_lod
);
5145 samp_st
.MinandMagStateNotEqual
=
5146 samp_st
.MinModeFilter
!= samp_st
.MagModeFilter
;
5149 /* Upload the border color if necessary. If not, just point it at
5150 * offset 0 (the start of the batch) - the color should be ignored,
5151 * but that address won't fault in case something reads it anyway.
5153 uint32_t border_color_offset
= 0;
5154 if (wrap_mode_needs_border_color(wrap_s
) ||
5155 wrap_mode_needs_border_color(wrap_t
) ||
5156 wrap_mode_needs_border_color(wrap_r
)) {
5157 genX(upload_default_color
)(brw
, sampler
, format
, base_format
,
5158 texObj
->_IsIntegerFormat
,
5159 texObj
->StencilSampling
,
5160 &border_color_offset
);
5163 samp_st
.BorderColorPointer
=
5164 ro_bo(brw
->batch
.state
.bo
, border_color_offset
);
5166 samp_st
.BorderColorPointer
= border_color_offset
;
5170 samp_st
.LODPreClampMode
= CLAMP_MODE_OGL
;
5172 samp_st
.LODPreClampEnable
= true;
5175 GENX(SAMPLER_STATE_pack
)(brw
, sampler_state
, &samp_st
);
5179 update_sampler_state(struct brw_context
*brw
,
5181 uint32_t *sampler_state
,
5182 uint32_t batch_offset_for_sampler_state
)
5184 struct gl_context
*ctx
= &brw
->ctx
;
5185 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
5186 const struct gl_texture_object
*texObj
= texUnit
->_Current
;
5187 const struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
5189 /* These don't use samplers at all. */
5190 if (texObj
->Target
== GL_TEXTURE_BUFFER
)
5193 struct gl_texture_image
*firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
5194 genX(update_sampler_state
)(brw
, texObj
->Target
,
5195 ctx
->Texture
.CubeMapSeamless
,
5197 firstImage
->TexFormat
, firstImage
->_BaseFormat
,
5199 sampler_state
, batch_offset_for_sampler_state
);
5203 genX(upload_sampler_state_table
)(struct brw_context
*brw
,
5204 struct gl_program
*prog
,
5205 struct brw_stage_state
*stage_state
)
5207 struct gl_context
*ctx
= &brw
->ctx
;
5208 uint32_t sampler_count
= stage_state
->sampler_count
;
5210 GLbitfield SamplersUsed
= prog
->SamplersUsed
;
5212 if (sampler_count
== 0)
5215 /* SAMPLER_STATE is 4 DWords on all platforms. */
5216 const int dwords
= GENX(SAMPLER_STATE_length
);
5217 const int size_in_bytes
= dwords
* sizeof(uint32_t);
5219 uint32_t *sampler_state
= brw_state_batch(brw
,
5220 sampler_count
* size_in_bytes
,
5221 32, &stage_state
->sampler_offset
);
5222 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5224 uint32_t batch_offset_for_sampler_state
= stage_state
->sampler_offset
;
5226 for (unsigned s
= 0; s
< sampler_count
; s
++) {
5227 if (SamplersUsed
& (1 << s
)) {
5228 const unsigned unit
= prog
->SamplerUnits
[s
];
5229 if (ctx
->Texture
.Unit
[unit
]._Current
) {
5230 update_sampler_state(brw
, unit
, sampler_state
,
5231 batch_offset_for_sampler_state
);
5235 sampler_state
+= dwords
;
5236 batch_offset_for_sampler_state
+= size_in_bytes
;
5239 if (GEN_GEN
>= 7 && stage_state
->stage
!= MESA_SHADER_COMPUTE
) {
5240 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5241 genX(emit_sampler_state_pointers_xs
)(brw
, stage_state
);
5243 /* Flag that the sampler state table pointer has changed; later atoms
5246 brw
->ctx
.NewDriverState
|= BRW_NEW_SAMPLER_STATE_TABLE
;
5251 genX(upload_fs_samplers
)(struct brw_context
*brw
)
5253 /* BRW_NEW_FRAGMENT_PROGRAM */
5254 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
5255 genX(upload_sampler_state_table
)(brw
, fs
, &brw
->wm
.base
);
5258 static const struct brw_tracked_state
genX(fs_samplers
) = {
5260 .mesa
= _NEW_TEXTURE
,
5261 .brw
= BRW_NEW_BATCH
|
5263 BRW_NEW_FRAGMENT_PROGRAM
,
5265 .emit
= genX(upload_fs_samplers
),
5269 genX(upload_vs_samplers
)(struct brw_context
*brw
)
5271 /* BRW_NEW_VERTEX_PROGRAM */
5272 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
5273 genX(upload_sampler_state_table
)(brw
, vs
, &brw
->vs
.base
);
5276 static const struct brw_tracked_state
genX(vs_samplers
) = {
5278 .mesa
= _NEW_TEXTURE
,
5279 .brw
= BRW_NEW_BATCH
|
5281 BRW_NEW_VERTEX_PROGRAM
,
5283 .emit
= genX(upload_vs_samplers
),
5288 genX(upload_gs_samplers
)(struct brw_context
*brw
)
5290 /* BRW_NEW_GEOMETRY_PROGRAM */
5291 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
5295 genX(upload_sampler_state_table
)(brw
, gs
, &brw
->gs
.base
);
5299 static const struct brw_tracked_state
genX(gs_samplers
) = {
5301 .mesa
= _NEW_TEXTURE
,
5302 .brw
= BRW_NEW_BATCH
|
5304 BRW_NEW_GEOMETRY_PROGRAM
,
5306 .emit
= genX(upload_gs_samplers
),
5312 genX(upload_tcs_samplers
)(struct brw_context
*brw
)
5314 /* BRW_NEW_TESS_PROGRAMS */
5315 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
5319 genX(upload_sampler_state_table
)(brw
, tcs
, &brw
->tcs
.base
);
5322 static const struct brw_tracked_state
genX(tcs_samplers
) = {
5324 .mesa
= _NEW_TEXTURE
,
5325 .brw
= BRW_NEW_BATCH
|
5327 BRW_NEW_TESS_PROGRAMS
,
5329 .emit
= genX(upload_tcs_samplers
),
5335 genX(upload_tes_samplers
)(struct brw_context
*brw
)
5337 /* BRW_NEW_TESS_PROGRAMS */
5338 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
5342 genX(upload_sampler_state_table
)(brw
, tes
, &brw
->tes
.base
);
5345 static const struct brw_tracked_state
genX(tes_samplers
) = {
5347 .mesa
= _NEW_TEXTURE
,
5348 .brw
= BRW_NEW_BATCH
|
5350 BRW_NEW_TESS_PROGRAMS
,
5352 .emit
= genX(upload_tes_samplers
),
5358 genX(upload_cs_samplers
)(struct brw_context
*brw
)
5360 /* BRW_NEW_COMPUTE_PROGRAM */
5361 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
5365 genX(upload_sampler_state_table
)(brw
, cs
, &brw
->cs
.base
);
5368 const struct brw_tracked_state
genX(cs_samplers
) = {
5370 .mesa
= _NEW_TEXTURE
,
5371 .brw
= BRW_NEW_BATCH
|
5373 BRW_NEW_COMPUTE_PROGRAM
,
5375 .emit
= genX(upload_cs_samplers
),
5379 /* ---------------------------------------------------------------------- */
5383 static void genX(upload_blend_constant_color
)(struct brw_context
*brw
)
5385 struct gl_context
*ctx
= &brw
->ctx
;
5387 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_COLOR
), blend_cc
) {
5388 blend_cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
5389 blend_cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
5390 blend_cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
5391 blend_cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
5395 static const struct brw_tracked_state
genX(blend_constant_color
) = {
5398 .brw
= BRW_NEW_CONTEXT
|
5401 .emit
= genX(upload_blend_constant_color
)
5405 /* ---------------------------------------------------------------------- */
5408 genX(init_atoms
)(struct brw_context
*brw
)
5411 static const struct brw_tracked_state
*render_atoms
[] =
5413 /* Once all the programs are done, we know how large urb entry
5414 * sizes need to be and can decide if we need to change the urb
5418 &brw_recalculate_urb_fence
,
5421 &genX(color_calc_state
),
5423 /* Surface state setup. Must come before the VS/WM unit. The binding
5424 * table upload must be last.
5426 &brw_vs_pull_constants
,
5427 &brw_wm_pull_constants
,
5428 &brw_renderbuffer_surfaces
,
5429 &brw_renderbuffer_read_surfaces
,
5430 &brw_texture_surfaces
,
5431 &brw_vs_binding_table
,
5432 &brw_wm_binding_table
,
5437 /* These set up state for brw_psp_urb_cbs */
5439 &genX(sf_clip_viewport
),
5441 &genX(vs_state
), /* always required, enabled or not */
5447 &brw_binding_table_pointers
,
5448 &genX(blend_constant_color
),
5452 &genX(polygon_stipple
),
5453 &genX(polygon_stipple_offset
),
5455 &genX(line_stipple
),
5459 &genX(drawing_rect
),
5460 &brw_indices
, /* must come before brw_vertices */
5461 &genX(index_buffer
),
5464 &brw_constant_buffer
5467 static const struct brw_tracked_state
*render_atoms
[] =
5469 &genX(sf_clip_viewport
),
5471 /* Command packets: */
5476 &genX(blend_state
), /* must do before cc unit */
5477 &genX(color_calc_state
), /* must do before cc unit */
5478 &genX(depth_stencil_state
), /* must do before cc unit */
5480 &genX(vs_push_constants
), /* Before vs_state */
5481 &genX(gs_push_constants
), /* Before gs_state */
5482 &genX(wm_push_constants
), /* Before wm_state */
5484 /* Surface state setup. Must come before the VS/WM unit. The binding
5485 * table upload must be last.
5487 &brw_vs_pull_constants
,
5488 &brw_vs_ubo_surfaces
,
5489 &brw_gs_pull_constants
,
5490 &brw_gs_ubo_surfaces
,
5491 &brw_wm_pull_constants
,
5492 &brw_wm_ubo_surfaces
,
5493 &gen6_renderbuffer_surfaces
,
5494 &brw_renderbuffer_read_surfaces
,
5495 &brw_texture_surfaces
,
5497 &brw_vs_binding_table
,
5498 &gen6_gs_binding_table
,
5499 &brw_wm_binding_table
,
5504 &gen6_sampler_state
,
5505 &genX(multisample_state
),
5513 &genX(scissor_state
),
5515 &gen6_binding_table_pointers
,
5519 &genX(polygon_stipple
),
5520 &genX(polygon_stipple_offset
),
5522 &genX(line_stipple
),
5524 &genX(drawing_rect
),
5526 &brw_indices
, /* must come before brw_vertices */
5527 &genX(index_buffer
),
5531 static const struct brw_tracked_state
*render_atoms
[] =
5533 /* Command packets: */
5536 &genX(sf_clip_viewport
),
5539 &gen7_push_constant_space
,
5541 &genX(blend_state
), /* must do before cc unit */
5542 &genX(color_calc_state
), /* must do before cc unit */
5543 &genX(depth_stencil_state
), /* must do before cc unit */
5545 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5546 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5547 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5548 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5549 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5551 &genX(vs_push_constants
), /* Before vs_state */
5552 &genX(tcs_push_constants
),
5553 &genX(tes_push_constants
),
5554 &genX(gs_push_constants
), /* Before gs_state */
5555 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5557 /* Surface state setup. Must come before the VS/WM unit. The binding
5558 * table upload must be last.
5560 &brw_vs_pull_constants
,
5561 &brw_vs_ubo_surfaces
,
5562 &brw_tcs_pull_constants
,
5563 &brw_tcs_ubo_surfaces
,
5564 &brw_tes_pull_constants
,
5565 &brw_tes_ubo_surfaces
,
5566 &brw_gs_pull_constants
,
5567 &brw_gs_ubo_surfaces
,
5568 &brw_wm_pull_constants
,
5569 &brw_wm_ubo_surfaces
,
5570 &gen6_renderbuffer_surfaces
,
5571 &brw_renderbuffer_read_surfaces
,
5572 &brw_texture_surfaces
,
5574 &genX(push_constant_packets
),
5576 &brw_vs_binding_table
,
5577 &brw_tcs_binding_table
,
5578 &brw_tes_binding_table
,
5579 &brw_gs_binding_table
,
5580 &brw_wm_binding_table
,
5584 &genX(tcs_samplers
),
5585 &genX(tes_samplers
),
5587 &genX(multisample_state
),
5601 &genX(scissor_state
),
5605 &genX(polygon_stipple
),
5606 &genX(polygon_stipple_offset
),
5608 &genX(line_stipple
),
5610 &genX(drawing_rect
),
5612 &brw_indices
, /* must come before brw_vertices */
5613 &genX(index_buffer
),
5621 static const struct brw_tracked_state
*render_atoms
[] =
5624 &genX(sf_clip_viewport
),
5627 &gen7_push_constant_space
,
5630 &genX(color_calc_state
),
5632 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
5633 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
5634 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
5635 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
5636 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
5638 &genX(vs_push_constants
), /* Before vs_state */
5639 &genX(tcs_push_constants
),
5640 &genX(tes_push_constants
),
5641 &genX(gs_push_constants
), /* Before gs_state */
5642 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
5644 /* Surface state setup. Must come before the VS/WM unit. The binding
5645 * table upload must be last.
5647 &brw_vs_pull_constants
,
5648 &brw_vs_ubo_surfaces
,
5649 &brw_tcs_pull_constants
,
5650 &brw_tcs_ubo_surfaces
,
5651 &brw_tes_pull_constants
,
5652 &brw_tes_ubo_surfaces
,
5653 &brw_gs_pull_constants
,
5654 &brw_gs_ubo_surfaces
,
5655 &brw_wm_pull_constants
,
5656 &brw_wm_ubo_surfaces
,
5657 &gen6_renderbuffer_surfaces
,
5658 &brw_renderbuffer_read_surfaces
,
5659 &brw_texture_surfaces
,
5661 &genX(push_constant_packets
),
5663 &brw_vs_binding_table
,
5664 &brw_tcs_binding_table
,
5665 &brw_tes_binding_table
,
5666 &brw_gs_binding_table
,
5667 &brw_wm_binding_table
,
5671 &genX(tcs_samplers
),
5672 &genX(tes_samplers
),
5674 &genX(multisample_state
),
5683 &genX(raster_state
),
5689 &genX(depth_stencil_state
),
5692 &genX(scissor_state
),
5696 &genX(polygon_stipple
),
5697 &genX(polygon_stipple_offset
),
5699 &genX(line_stipple
),
5701 &genX(drawing_rect
),
5706 &genX(index_buffer
),
5714 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
5715 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
5716 render_atoms
, ARRAY_SIZE(render_atoms
));
5719 static const struct brw_tracked_state
*compute_atoms
[] =
5722 &brw_cs_image_surfaces
,
5723 &genX(cs_push_constants
),
5724 &genX(cs_pull_constants
),
5725 &brw_cs_ubo_surfaces
,
5726 &brw_cs_texture_surfaces
,
5727 &brw_cs_work_groups_surface
,
5732 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
5733 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
5734 compute_atoms
, ARRAY_SIZE(compute_atoms
));
5736 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);