2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/state.h"
36 #include "brw_context.h"
38 #include "brw_defines.h"
41 #include "brw_multisample_state.h"
42 #include "brw_state.h"
46 #include "intel_batchbuffer.h"
47 #include "intel_buffer_objects.h"
48 #include "intel_fbo.h"
50 #include "main/enums.h"
51 #include "main/fbobject.h"
52 #include "main/framebuffer.h"
53 #include "main/glformats.h"
54 #include "main/shaderapi.h"
55 #include "main/stencil.h"
56 #include "main/transformfeedback.h"
57 #include "main/varray.h"
58 #include "main/viewport.h"
61 emit_dwords(struct brw_context
*brw
, unsigned n
)
63 intel_batchbuffer_begin(brw
, n
, RENDER_RING
);
64 uint32_t *map
= brw
->batch
.map_next
;
65 brw
->batch
.map_next
+= n
;
66 intel_batchbuffer_advance(brw
);
72 uint32_t read_domains
;
73 uint32_t write_domain
;
78 emit_reloc(struct brw_context
*brw
,
79 void *location
, struct brw_address address
, uint32_t delta
)
81 uint32_t offset
= (char *) location
- (char *) brw
->batch
.map
;
83 return brw_emit_reloc(&brw
->batch
, offset
, address
.bo
,
84 address
.offset
+ delta
,
86 address
.write_domain
);
89 #define __gen_address_type struct brw_address
90 #define __gen_user_data struct brw_context
93 __gen_combine_address(struct brw_context
*brw
, void *location
,
94 struct brw_address address
, uint32_t delta
)
96 if (address
.bo
== NULL
) {
97 return address
.offset
+ delta
;
99 return emit_reloc(brw
, location
, address
, delta
);
103 static inline struct brw_address
104 render_bo(struct brw_bo
*bo
, uint32_t offset
)
106 return (struct brw_address
) {
109 .read_domains
= I915_GEM_DOMAIN_RENDER
,
110 .write_domain
= I915_GEM_DOMAIN_RENDER
,
114 static inline struct brw_address
115 render_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
117 return (struct brw_address
) {
120 .read_domains
= I915_GEM_DOMAIN_RENDER
,
125 static inline struct brw_address
126 instruction_bo(struct brw_bo
*bo
, uint32_t offset
)
128 return (struct brw_address
) {
131 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
132 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
136 static inline struct brw_address
137 instruction_ro_bo(struct brw_bo
*bo
, uint32_t offset
)
139 return (struct brw_address
) {
142 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
147 static inline struct brw_address
148 vertex_bo(struct brw_bo
*bo
, uint32_t offset
)
150 return (struct brw_address
) {
153 .read_domains
= I915_GEM_DOMAIN_VERTEX
,
159 static inline struct brw_address
160 KSP(struct brw_context
*brw
, uint32_t offset
)
162 return instruction_bo(brw
->cache
.bo
, offset
);
165 static inline struct brw_address
166 KSP_ro(struct brw_context
*brw
, uint32_t offset
)
168 return instruction_ro_bo(brw
->cache
.bo
, offset
);
171 static inline uint32_t
172 KSP(struct brw_context
*brw
, uint32_t offset
)
181 #include "genxml/genX_pack.h"
183 #define _brw_cmd_length(cmd) cmd ## _length
184 #define _brw_cmd_length_bias(cmd) cmd ## _length_bias
185 #define _brw_cmd_header(cmd) cmd ## _header
186 #define _brw_cmd_pack(cmd) cmd ## _pack
188 #define brw_batch_emit(brw, cmd, name) \
189 for (struct cmd name = { _brw_cmd_header(cmd) }, \
190 *_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
191 __builtin_expect(_dst != NULL, 1); \
192 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
195 #define brw_batch_emitn(brw, cmd, n, ...) ({ \
196 uint32_t *_dw = emit_dwords(brw, n); \
197 struct cmd template = { \
198 _brw_cmd_header(cmd), \
199 .DWordLength = n - _brw_cmd_length_bias(cmd), \
202 _brw_cmd_pack(cmd)(brw, _dw, &template); \
203 _dw + 1; /* Array starts at dw[1] */ \
206 #define brw_state_emit(brw, cmd, align, offset, name) \
207 for (struct cmd name = { 0, }, \
208 *_dst = brw_state_batch(brw, _brw_cmd_length(cmd) * 4, \
210 __builtin_expect(_dst != NULL, 1); \
211 _brw_cmd_pack(cmd)(brw, (void *)_dst, &name), \
215 * Polygon stipple packet
218 genX(upload_polygon_stipple
)(struct brw_context
*brw
)
220 struct gl_context
*ctx
= &brw
->ctx
;
223 if (!ctx
->Polygon
.StippleFlag
)
226 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
227 /* Polygon stipple is provided in OpenGL order, i.e. bottom
228 * row first. If we're rendering to a window (i.e. the
229 * default frame buffer object, 0), then we need to invert
230 * it to match our pixel layout. But if we're rendering
231 * to a FBO (i.e. any named frame buffer object), we *don't*
232 * need to invert - we already match the layout.
234 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
235 for (unsigned i
= 0; i
< 32; i
++)
236 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
238 for (unsigned i
= 0; i
< 32; i
++)
239 poly
.PatternRow
[i
] = ctx
->PolygonStipple
[i
];
244 static const struct brw_tracked_state
genX(polygon_stipple
) = {
246 .mesa
= _NEW_POLYGON
|
248 .brw
= BRW_NEW_CONTEXT
,
250 .emit
= genX(upload_polygon_stipple
),
254 * Polygon stipple offset packet
257 genX(upload_polygon_stipple_offset
)(struct brw_context
*brw
)
259 struct gl_context
*ctx
= &brw
->ctx
;
262 if (!ctx
->Polygon
.StippleFlag
)
265 brw_batch_emit(brw
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), poly
) {
268 * If we're drawing to a system window we have to invert the Y axis
269 * in order to match the OpenGL pixel coordinate system, and our
270 * offset must be matched to the window position. If we're drawing
271 * to a user-created FBO then our native pixel coordinate system
272 * works just fine, and there's no window system to worry about.
274 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
275 poly
.PolygonStippleYOffset
=
276 (32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31;
281 static const struct brw_tracked_state
genX(polygon_stipple_offset
) = {
283 .mesa
= _NEW_BUFFERS
|
285 .brw
= BRW_NEW_CONTEXT
,
287 .emit
= genX(upload_polygon_stipple_offset
),
291 * Line stipple packet
294 genX(upload_line_stipple
)(struct brw_context
*brw
)
296 struct gl_context
*ctx
= &brw
->ctx
;
298 if (!ctx
->Line
.StippleFlag
)
301 brw_batch_emit(brw
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
302 line
.LineStipplePattern
= ctx
->Line
.StipplePattern
;
304 line
.LineStippleInverseRepeatCount
= 1.0f
/ ctx
->Line
.StippleFactor
;
305 line
.LineStippleRepeatCount
= ctx
->Line
.StippleFactor
;
309 static const struct brw_tracked_state
genX(line_stipple
) = {
312 .brw
= BRW_NEW_CONTEXT
,
314 .emit
= genX(upload_line_stipple
),
317 /* Constant single cliprect for framebuffer object or DRI2 drawing */
319 genX(upload_drawing_rect
)(struct brw_context
*brw
)
321 struct gl_context
*ctx
= &brw
->ctx
;
322 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
323 const unsigned int fb_width
= _mesa_geometric_width(fb
);
324 const unsigned int fb_height
= _mesa_geometric_height(fb
);
326 brw_batch_emit(brw
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
327 rect
.ClippedDrawingRectangleXMax
= fb_width
- 1;
328 rect
.ClippedDrawingRectangleYMax
= fb_height
- 1;
332 static const struct brw_tracked_state
genX(drawing_rect
) = {
334 .mesa
= _NEW_BUFFERS
,
335 .brw
= BRW_NEW_BLORP
|
338 .emit
= genX(upload_drawing_rect
),
342 genX(emit_vertex_buffer_state
)(struct brw_context
*brw
,
346 unsigned start_offset
,
351 struct GENX(VERTEX_BUFFER_STATE
) buf_state
= {
352 .VertexBufferIndex
= buffer_nr
,
353 .BufferPitch
= stride
,
354 .BufferStartingAddress
= vertex_bo(bo
, start_offset
),
356 .BufferSize
= end_offset
- start_offset
,
360 .AddressModifyEnable
= true,
364 .BufferAccessType
= step_rate
? INSTANCEDATA
: VERTEXDATA
,
365 .InstanceDataStepRate
= step_rate
,
367 .EndAddress
= vertex_bo(bo
, end_offset
- 1),
372 .VertexBufferMOCS
= CNL_MOCS_WB
,
374 .VertexBufferMOCS
= SKL_MOCS_WB
,
376 .VertexBufferMOCS
= BDW_MOCS_WB
,
378 .VertexBufferMOCS
= GEN7_MOCS_L3
,
382 GENX(VERTEX_BUFFER_STATE_pack
)(brw
, dw
, &buf_state
);
383 return dw
+ GENX(VERTEX_BUFFER_STATE_length
);
387 is_passthru_format(uint32_t format
)
390 case ISL_FORMAT_R64_PASSTHRU
:
391 case ISL_FORMAT_R64G64_PASSTHRU
:
392 case ISL_FORMAT_R64G64B64_PASSTHRU
:
393 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
401 uploads_needed(uint32_t format
)
403 if (!is_passthru_format(format
))
407 case ISL_FORMAT_R64_PASSTHRU
:
408 case ISL_FORMAT_R64G64_PASSTHRU
:
410 case ISL_FORMAT_R64G64B64_PASSTHRU
:
411 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
414 unreachable("not reached");
419 * Returns the format that we are finally going to use when upload a vertex
420 * element. It will only change if we are using *64*PASSTHRU formats, as for
421 * gen < 8 they need to be splitted on two *32*FLOAT formats.
423 * @upload points in which upload we are. Valid values are [0,1]
426 downsize_format_if_needed(uint32_t format
,
429 assert(upload
== 0 || upload
== 1);
431 if (!is_passthru_format(format
))
435 case ISL_FORMAT_R64_PASSTHRU
:
436 return ISL_FORMAT_R32G32_FLOAT
;
437 case ISL_FORMAT_R64G64_PASSTHRU
:
438 return ISL_FORMAT_R32G32B32A32_FLOAT
;
439 case ISL_FORMAT_R64G64B64_PASSTHRU
:
440 return !upload
? ISL_FORMAT_R32G32B32A32_FLOAT
441 : ISL_FORMAT_R32G32_FLOAT
;
442 case ISL_FORMAT_R64G64B64A64_PASSTHRU
:
443 return ISL_FORMAT_R32G32B32A32_FLOAT
;
445 unreachable("not reached");
450 * Returns the number of componentes associated with a format that is used on
451 * a 64 to 32 format split. See downsize_format()
454 upload_format_size(uint32_t upload_format
)
456 switch (upload_format
) {
457 case ISL_FORMAT_R32G32_FLOAT
:
459 case ISL_FORMAT_R32G32B32A32_FLOAT
:
462 unreachable("not reached");
467 genX(emit_vertices
)(struct brw_context
*brw
)
471 brw_prepare_vertices(brw
);
472 brw_prepare_shader_draw_parameters(brw
);
475 brw_emit_query_begin(brw
);
478 const struct brw_vs_prog_data
*vs_prog_data
=
479 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
482 struct gl_context
*ctx
= &brw
->ctx
;
483 const bool uses_edge_flag
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
484 ctx
->Polygon
.BackMode
!= GL_FILL
);
486 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
487 unsigned vue
= brw
->vb
.nr_enabled
;
489 /* The element for the edge flags must always be last, so we have to
490 * insert the SGVS before it in that case.
492 if (uses_edge_flag
) {
498 "Trying to insert VID/IID past 33rd vertex element, "
499 "need to reorder the vertex attrbutes.");
501 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
) {
502 if (vs_prog_data
->uses_vertexid
) {
503 vfs
.VertexIDEnable
= true;
504 vfs
.VertexIDComponentNumber
= 2;
505 vfs
.VertexIDElementOffset
= vue
;
508 if (vs_prog_data
->uses_instanceid
) {
509 vfs
.InstanceIDEnable
= true;
510 vfs
.InstanceIDComponentNumber
= 3;
511 vfs
.InstanceIDElementOffset
= vue
;
515 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
516 vfi
.InstancingEnable
= true;
517 vfi
.VertexElementIndex
= vue
;
520 brw_batch_emit(brw
, GENX(3DSTATE_VF_SGVS
), vfs
);
523 /* Normally we don't need an element for the SGVS attribute because the
524 * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
525 * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
526 * we're using draw parameters then we need an element for the those
527 * values. Additionally if there is an edge flag element then the SGVS
528 * can't be inserted past that so we need a dummy element to ensure that
529 * the edge flag is the last one.
531 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
532 vs_prog_data
->uses_baseinstance
||
533 ((vs_prog_data
->uses_instanceid
||
534 vs_prog_data
->uses_vertexid
)
537 const bool needs_sgvs_element
= (vs_prog_data
->uses_basevertex
||
538 vs_prog_data
->uses_baseinstance
||
539 vs_prog_data
->uses_instanceid
||
540 vs_prog_data
->uses_vertexid
);
542 unsigned nr_elements
=
543 brw
->vb
.nr_enabled
+ needs_sgvs_element
+ vs_prog_data
->uses_drawid
;
546 /* If any of the formats of vb.enabled needs more that one upload, we need
547 * to add it to nr_elements
549 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
550 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
551 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
553 if (uploads_needed(format
) > 1)
558 /* If the VS doesn't read any inputs (calculating vertex position from
559 * a state variable for some reason, for example), emit a single pad
560 * VERTEX_ELEMENT struct and bail.
562 * The stale VB state stays in place, but they don't do anything unless
563 * a VE loads from them.
565 if (nr_elements
== 0) {
566 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
567 1 + GENX(VERTEX_ELEMENT_STATE_length
));
568 struct GENX(VERTEX_ELEMENT_STATE
) elem
= {
570 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
571 .Component0Control
= VFCOMP_STORE_0
,
572 .Component1Control
= VFCOMP_STORE_0
,
573 .Component2Control
= VFCOMP_STORE_0
,
574 .Component3Control
= VFCOMP_STORE_1_FP
,
576 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem
);
580 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
581 const bool uses_draw_params
=
582 vs_prog_data
->uses_basevertex
||
583 vs_prog_data
->uses_baseinstance
;
584 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
585 uses_draw_params
+ vs_prog_data
->uses_drawid
;
588 assert(nr_buffers
<= (GEN_GEN
>= 6 ? 33 : 17));
590 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_BUFFERS
),
591 1 + GENX(VERTEX_BUFFER_STATE_length
) * nr_buffers
);
593 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
594 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
595 /* Prior to Haswell and Bay Trail we have to use 4-component formats
596 * to fake 3-component ones. In particular, we do this for
597 * half-float and 8 and 16-bit integer formats. This means that the
598 * vertex element may poke over the end of the buffer by 2 bytes.
600 const unsigned padding
=
601 (GEN_GEN
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
602 const unsigned end
= buffer
->offset
+ buffer
->size
+ padding
;
603 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, i
, buffer
->bo
,
610 if (uses_draw_params
) {
611 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
,
612 brw
->draw
.draw_params_bo
,
613 brw
->draw
.draw_params_offset
,
614 brw
->draw
.draw_params_bo
->size
,
619 if (vs_prog_data
->uses_drawid
) {
620 dw
= genX(emit_vertex_buffer_state
)(brw
, dw
, brw
->vb
.nr_buffers
+ 1,
621 brw
->draw
.draw_id_bo
,
622 brw
->draw
.draw_id_offset
,
623 brw
->draw
.draw_id_bo
->size
,
629 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
630 * presumably for VertexID/InstanceID.
633 assert(nr_elements
<= 34);
634 const struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
636 assert(nr_elements
<= 18);
639 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_VERTEX_ELEMENTS
),
640 1 + GENX(VERTEX_ELEMENT_STATE_length
) * nr_elements
);
642 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
643 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
644 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
645 uint32_t comp0
= VFCOMP_STORE_SRC
;
646 uint32_t comp1
= VFCOMP_STORE_SRC
;
647 uint32_t comp2
= VFCOMP_STORE_SRC
;
648 uint32_t comp3
= VFCOMP_STORE_SRC
;
649 const unsigned num_uploads
= GEN_GEN
< 8 ? uploads_needed(format
) : 1;
652 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
653 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
654 * element which has edge flag enabled."
656 assert(!(is_passthru_format(format
) && uses_edge_flag
));
659 /* The gen4 driver expects edgeflag to come in as a float, and passes
660 * that float on to the tests in the clipper. Mesa's current vertex
661 * attribute value for EdgeFlag is stored as a float, which works out.
662 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
663 * integer ubyte. Just rewrite that to convert to a float.
665 * Gen6+ passes edgeflag as sideband along with the vertex, instead
666 * of in the VUE. We have to upload it sideband as the last vertex
667 * element according to the B-Spec.
670 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
671 gen6_edgeflag_input
= input
;
676 for (unsigned c
= 0; c
< num_uploads
; c
++) {
677 const uint32_t upload_format
= GEN_GEN
>= 8 ? format
:
678 downsize_format_if_needed(format
, c
);
679 /* If we need more that one upload, the offset stride would be 128
680 * bits (16 bytes), as for previous uploads we are using the full
682 const unsigned offset
= input
->offset
+ c
* 16;
684 const int size
= (GEN_GEN
< 8 && is_passthru_format(format
)) ?
685 upload_format_size(upload_format
) : input
->glarray
->Size
;
688 case 0: comp0
= VFCOMP_STORE_0
;
689 case 1: comp1
= VFCOMP_STORE_0
;
690 case 2: comp2
= VFCOMP_STORE_0
;
692 if (GEN_GEN
>= 8 && input
->glarray
->Doubles
) {
693 comp3
= VFCOMP_STORE_0
;
694 } else if (input
->glarray
->Integer
) {
695 comp3
= VFCOMP_STORE_1_INT
;
697 comp3
= VFCOMP_STORE_1_FP
;
704 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
706 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
707 * formats, 64-bit components are stored in the URB without any
708 * conversion. In this case, vertex elements must be written as 128
709 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
710 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
711 * component into the URB, Component 1 must be specified as
712 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
713 * order to output a 128-bit vertex element, or Components 1-3 must
714 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
715 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
716 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
719 if (input
->glarray
->Doubles
&& !input
->is_dual_slot
) {
720 /* Store vertex elements which correspond to double and dvec2 vertex
721 * shader inputs as 128-bit vertex elements, instead of 256-bits.
723 comp2
= VFCOMP_NOSTORE
;
724 comp3
= VFCOMP_NOSTORE
;
728 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
729 .VertexBufferIndex
= input
->buffer
,
731 .SourceElementFormat
= upload_format
,
732 .SourceElementOffset
= offset
,
733 .Component0Control
= comp0
,
734 .Component1Control
= comp1
,
735 .Component2Control
= comp2
,
736 .Component3Control
= comp3
,
738 .DestinationElementOffset
= i
* 4,
742 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
743 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
747 if (needs_sgvs_element
) {
748 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
750 .Component0Control
= VFCOMP_STORE_0
,
751 .Component1Control
= VFCOMP_STORE_0
,
752 .Component2Control
= VFCOMP_STORE_0
,
753 .Component3Control
= VFCOMP_STORE_0
,
755 .DestinationElementOffset
= i
* 4,
760 if (vs_prog_data
->uses_basevertex
||
761 vs_prog_data
->uses_baseinstance
) {
762 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
763 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
764 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
765 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
768 elem_state
.VertexBufferIndex
= brw
->vb
.nr_buffers
;
769 elem_state
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
770 if (vs_prog_data
->uses_basevertex
)
771 elem_state
.Component0Control
= VFCOMP_STORE_SRC
;
773 if (vs_prog_data
->uses_baseinstance
)
774 elem_state
.Component1Control
= VFCOMP_STORE_SRC
;
776 if (vs_prog_data
->uses_vertexid
)
777 elem_state
.Component2Control
= VFCOMP_STORE_VID
;
779 if (vs_prog_data
->uses_instanceid
)
780 elem_state
.Component3Control
= VFCOMP_STORE_IID
;
783 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
784 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
787 if (vs_prog_data
->uses_drawid
) {
788 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
790 .VertexBufferIndex
= brw
->vb
.nr_buffers
+ 1,
791 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
792 .Component0Control
= VFCOMP_STORE_SRC
,
793 .Component1Control
= VFCOMP_STORE_0
,
794 .Component2Control
= VFCOMP_STORE_0
,
795 .Component3Control
= VFCOMP_STORE_0
,
797 .DestinationElementOffset
= i
* 4,
801 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
802 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
806 if (gen6_edgeflag_input
) {
807 const uint32_t format
=
808 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
810 struct GENX(VERTEX_ELEMENT_STATE
) elem_state
= {
812 .VertexBufferIndex
= gen6_edgeflag_input
->buffer
,
813 .EdgeFlagEnable
= true,
814 .SourceElementFormat
= format
,
815 .SourceElementOffset
= gen6_edgeflag_input
->offset
,
816 .Component0Control
= VFCOMP_STORE_SRC
,
817 .Component1Control
= VFCOMP_STORE_0
,
818 .Component2Control
= VFCOMP_STORE_0
,
819 .Component3Control
= VFCOMP_STORE_0
,
822 GENX(VERTEX_ELEMENT_STATE_pack
)(brw
, dw
, &elem_state
);
823 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
828 for (unsigned i
= 0, j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
829 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
830 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
831 unsigned element_index
;
833 /* The edge flag element is reordered to be the last one in the code
834 * above so we need to compensate for that in the element indices used
837 if (input
== gen6_edgeflag_input
)
838 element_index
= nr_elements
- 1;
842 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
843 vfi
.VertexElementIndex
= element_index
;
844 vfi
.InstancingEnable
= buffer
->step_rate
!= 0;
845 vfi
.InstanceDataStepRate
= buffer
->step_rate
;
849 if (vs_prog_data
->uses_drawid
) {
850 const unsigned element
= brw
->vb
.nr_enabled
+ needs_sgvs_element
;
852 brw_batch_emit(brw
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
853 vfi
.VertexElementIndex
= element
;
859 static const struct brw_tracked_state
genX(vertices
) = {
861 .mesa
= _NEW_POLYGON
,
862 .brw
= BRW_NEW_BATCH
|
865 BRW_NEW_VS_PROG_DATA
,
867 .emit
= genX(emit_vertices
),
871 genX(emit_index_buffer
)(struct brw_context
*brw
)
873 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
875 if (index_buffer
== NULL
)
878 brw_batch_emit(brw
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
879 #if GEN_GEN < 8 && !GEN_IS_HASWELL
880 ib
.CutIndexEnable
= brw
->prim_restart
.enable_cut_index
;
882 ib
.IndexFormat
= brw_get_index_type(index_buffer
->index_size
);
883 ib
.BufferStartingAddress
= vertex_bo(brw
->ib
.bo
, 0);
885 ib
.IndexBufferMOCS
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
886 ib
.BufferSize
= brw
->ib
.size
;
888 ib
.BufferEndingAddress
= vertex_bo(brw
->ib
.bo
, brw
->ib
.size
- 1);
893 static const struct brw_tracked_state
genX(index_buffer
) = {
896 .brw
= BRW_NEW_BATCH
|
898 BRW_NEW_INDEX_BUFFER
,
900 .emit
= genX(emit_index_buffer
),
903 #if GEN_IS_HASWELL || GEN_GEN >= 8
905 genX(upload_cut_index
)(struct brw_context
*brw
)
907 const struct gl_context
*ctx
= &brw
->ctx
;
909 brw_batch_emit(brw
, GENX(3DSTATE_VF
), vf
) {
910 if (ctx
->Array
._PrimitiveRestart
&& brw
->ib
.ib
) {
911 vf
.IndexedDrawCutIndexEnable
= true;
912 vf
.CutIndex
= _mesa_primitive_restart_index(ctx
, brw
->ib
.index_size
);
917 const struct brw_tracked_state
genX(cut_index
) = {
919 .mesa
= _NEW_TRANSFORM
,
920 .brw
= BRW_NEW_INDEX_BUFFER
,
922 .emit
= genX(upload_cut_index
),
928 * Determine the appropriate attribute override value to store into the
929 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
930 * override value contains two pieces of information: the location of the
931 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
932 * flag indicating whether to "swizzle" the attribute based on the direction
933 * the triangle is facing.
935 * If an attribute is "swizzled", then the given VUE location is used for
936 * front-facing triangles, and the VUE location that immediately follows is
937 * used for back-facing triangles. We use this to implement the mapping from
938 * gl_FrontColor/gl_BackColor to gl_Color.
940 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
941 * being instructed to begin reading attribute data. It can be set to a
942 * nonzero value to prevent the SF unit from wasting time reading elements of
943 * the VUE that are not needed by the fragment shader. It is measured in
944 * 256-bit increments.
947 genX(get_attr_override
)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
,
948 const struct brw_vue_map
*vue_map
,
949 int urb_entry_read_offset
, int fs_attr
,
950 bool two_side_color
, uint32_t *max_source_attr
)
952 /* Find the VUE slot for this attribute. */
953 int slot
= vue_map
->varying_to_slot
[fs_attr
];
955 /* Viewport and Layer are stored in the VUE header. We need to override
956 * them to zero if earlier stages didn't write them, as GL requires that
957 * they read back as zero when not explicitly set.
959 if (fs_attr
== VARYING_SLOT_VIEWPORT
|| fs_attr
== VARYING_SLOT_LAYER
) {
960 attr
->ComponentOverrideX
= true;
961 attr
->ComponentOverrideW
= true;
962 attr
->ConstantSource
= CONST_0000
;
964 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
965 attr
->ComponentOverrideY
= true;
966 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
967 attr
->ComponentOverrideZ
= true;
972 /* If there was only a back color written but not front, use back
973 * as the color instead of undefined
975 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
976 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
977 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
978 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
981 /* This attribute does not exist in the VUE--that means that the vertex
982 * shader did not write to it. This means that either:
984 * (a) This attribute is a texture coordinate, and it is going to be
985 * replaced with point coordinates (as a consequence of a call to
986 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
987 * hardware will ignore whatever attribute override we supply.
989 * (b) This attribute is read by the fragment shader but not written by
990 * the vertex shader, so its value is undefined. Therefore the
991 * attribute override we supply doesn't matter.
993 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
994 * previous shader stage.
996 * Note that we don't have to worry about the cases where the attribute
997 * is gl_PointCoord or is undergoing point sprite coordinate
998 * replacement, because in those cases, this function isn't called.
1000 * In case (c), we need to program the attribute overrides so that the
1001 * primitive ID will be stored in this slot. In every other case, the
1002 * attribute override we supply doesn't matter. So just go ahead and
1003 * program primitive ID in every case.
1005 attr
->ComponentOverrideW
= true;
1006 attr
->ComponentOverrideX
= true;
1007 attr
->ComponentOverrideY
= true;
1008 attr
->ComponentOverrideZ
= true;
1009 attr
->ConstantSource
= PRIM_ID
;
1013 /* Compute the location of the attribute relative to urb_entry_read_offset.
1014 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1015 * it counts for two 128-bit VUE slots.
1017 int source_attr
= slot
- 2 * urb_entry_read_offset
;
1018 assert(source_attr
>= 0 && source_attr
< 32);
1020 /* If we are doing two-sided color, and the VUE slot following this one
1021 * represents a back-facing color, then we need to instruct the SF unit to
1022 * do back-facing swizzling.
1024 bool swizzling
= two_side_color
&&
1025 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1026 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1027 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1028 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
));
1030 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1031 if (*max_source_attr
< source_attr
+ swizzling
)
1032 *max_source_attr
= source_attr
+ swizzling
;
1034 attr
->SourceAttribute
= source_attr
;
1036 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1041 genX(calculate_attr_overrides
)(const struct brw_context
*brw
,
1042 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr_overrides
,
1043 uint32_t *point_sprite_enables
,
1044 uint32_t *urb_entry_read_length
,
1045 uint32_t *urb_entry_read_offset
)
1047 const struct gl_context
*ctx
= &brw
->ctx
;
1050 const struct gl_point_attrib
*point
= &ctx
->Point
;
1052 /* BRW_NEW_FS_PROG_DATA */
1053 const struct brw_wm_prog_data
*wm_prog_data
=
1054 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1055 uint32_t max_source_attr
= 0;
1057 *point_sprite_enables
= 0;
1059 /* BRW_NEW_FRAGMENT_PROGRAM
1061 * If the fragment shader reads VARYING_SLOT_LAYER, then we need to pass in
1062 * the full vertex header. Otherwise, we can program the SF to start
1063 * reading at an offset of 1 (2 varying slots) to skip unnecessary data:
1064 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1065 * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
1068 bool fs_needs_vue_header
= brw
->fragment_program
->info
.inputs_read
&
1069 (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1071 *urb_entry_read_offset
= fs_needs_vue_header
? 0 : 1;
1073 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1074 * description of dw10 Point Sprite Texture Coordinate Enable:
1076 * "This field must be programmed to zero when non-point primitives
1079 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1080 * must be programmed to zero when rendering non-point primitives, but
1081 * the IvyBridge PRM does, and if we don't, we get garbage.
1083 * This is not required on Haswell, as the hardware ignores this state
1084 * when drawing non-points -- although we do still need to be careful to
1085 * correctly set the attr overrides.
1088 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1090 bool drawing_points
= brw_is_drawing_points(brw
);
1092 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1093 int input_index
= wm_prog_data
->urb_setup
[attr
];
1095 if (input_index
< 0)
1099 bool point_sprite
= false;
1100 if (drawing_points
) {
1101 if (point
->PointSprite
&&
1102 (attr
>= VARYING_SLOT_TEX0
&& attr
<= VARYING_SLOT_TEX7
) &&
1103 (point
->CoordReplace
& (1u << (attr
- VARYING_SLOT_TEX0
)))) {
1104 point_sprite
= true;
1107 if (attr
== VARYING_SLOT_PNTC
)
1108 point_sprite
= true;
1111 *point_sprite_enables
|= (1 << input_index
);
1114 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1115 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attribute
= { 0 };
1117 if (!point_sprite
) {
1118 genX(get_attr_override
)(&attribute
,
1119 &brw
->vue_map_geom_out
,
1120 *urb_entry_read_offset
, attr
,
1121 _mesa_vertex_program_two_side_enabled(ctx
),
1125 /* The hardware can only do the overrides on 16 overrides at a
1126 * time, and the other up to 16 have to be lined up so that the
1127 * input index = the output index. We'll need to do some
1128 * tweaking to make sure that's the case.
1130 if (input_index
< 16)
1131 attr_overrides
[input_index
] = attribute
;
1133 assert(attribute
.SourceAttribute
== input_index
);
1136 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1137 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1139 * "This field should be set to the minimum length required to read the
1140 * maximum source attribute. The maximum source attribute is indicated
1141 * by the maximum value of the enabled Attribute # Source Attribute if
1142 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1143 * enable is not set.
1144 * read_length = ceiling((max_source_attr + 1) / 2)
1146 * [errata] Corruption/Hang possible if length programmed larger than
1149 * Similar text exists for Ivy Bridge.
1151 *urb_entry_read_length
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
1155 /* ---------------------------------------------------------------------- */
1159 genX(upload_depth_stencil_state
)(struct brw_context
*brw
)
1161 struct gl_context
*ctx
= &brw
->ctx
;
1164 struct intel_renderbuffer
*depth_irb
=
1165 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
1168 struct gl_depthbuffer_attrib
*depth
= &ctx
->Depth
;
1171 struct gl_stencil_attrib
*stencil
= &ctx
->Stencil
;
1172 const int b
= stencil
->_BackFace
;
1175 brw_batch_emit(brw
, GENX(3DSTATE_WM_DEPTH_STENCIL
), wmds
) {
1178 brw_state_emit(brw
, GENX(DEPTH_STENCIL_STATE
), 64, &ds_offset
, wmds
) {
1180 if (depth
->Test
&& depth_irb
) {
1181 wmds
.DepthTestEnable
= true;
1182 wmds
.DepthBufferWriteEnable
= brw_depth_writes_enabled(brw
);
1183 wmds
.DepthTestFunction
= intel_translate_compare_func(depth
->Func
);
1186 if (brw
->stencil_enabled
) {
1187 wmds
.StencilTestEnable
= true;
1188 wmds
.StencilWriteMask
= stencil
->WriteMask
[0] & 0xff;
1189 wmds
.StencilTestMask
= stencil
->ValueMask
[0] & 0xff;
1191 wmds
.StencilTestFunction
=
1192 intel_translate_compare_func(stencil
->Function
[0]);
1193 wmds
.StencilFailOp
=
1194 intel_translate_stencil_op(stencil
->FailFunc
[0]);
1195 wmds
.StencilPassDepthPassOp
=
1196 intel_translate_stencil_op(stencil
->ZPassFunc
[0]);
1197 wmds
.StencilPassDepthFailOp
=
1198 intel_translate_stencil_op(stencil
->ZFailFunc
[0]);
1200 wmds
.StencilBufferWriteEnable
= brw
->stencil_write_enabled
;
1202 if (brw
->stencil_two_sided
) {
1203 wmds
.DoubleSidedStencilEnable
= true;
1204 wmds
.BackfaceStencilWriteMask
= stencil
->WriteMask
[b
] & 0xff;
1205 wmds
.BackfaceStencilTestMask
= stencil
->ValueMask
[b
] & 0xff;
1207 wmds
.BackfaceStencilTestFunction
=
1208 intel_translate_compare_func(stencil
->Function
[b
]);
1209 wmds
.BackfaceStencilFailOp
=
1210 intel_translate_stencil_op(stencil
->FailFunc
[b
]);
1211 wmds
.BackfaceStencilPassDepthPassOp
=
1212 intel_translate_stencil_op(stencil
->ZPassFunc
[b
]);
1213 wmds
.BackfaceStencilPassDepthFailOp
=
1214 intel_translate_stencil_op(stencil
->ZFailFunc
[b
]);
1218 wmds
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
1219 wmds
.BackfaceStencilReferenceValue
= _mesa_get_stencil_ref(ctx
, b
);
1225 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1226 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1227 ptr
.DEPTH_STENCIL_STATEChange
= true;
1230 brw_batch_emit(brw
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), ptr
) {
1231 ptr
.PointertoDEPTH_STENCIL_STATE
= ds_offset
;
1236 static const struct brw_tracked_state
genX(depth_stencil_state
) = {
1238 .mesa
= _NEW_BUFFERS
|
1241 .brw
= BRW_NEW_BLORP
|
1242 (GEN_GEN
>= 8 ? BRW_NEW_CONTEXT
1244 BRW_NEW_STATE_BASE_ADDRESS
),
1246 .emit
= genX(upload_depth_stencil_state
),
1250 /* ---------------------------------------------------------------------- */
1254 genX(upload_clip_state
)(struct brw_context
*brw
)
1256 struct gl_context
*ctx
= &brw
->ctx
;
1259 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1261 /* BRW_NEW_FS_PROG_DATA */
1262 struct brw_wm_prog_data
*wm_prog_data
=
1263 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1265 brw_batch_emit(brw
, GENX(3DSTATE_CLIP
), clip
) {
1266 clip
.StatisticsEnable
= !brw
->meta_in_progress
;
1268 if (wm_prog_data
->barycentric_interp_modes
&
1269 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
1270 clip
.NonPerspectiveBarycentricEnable
= true;
1273 clip
.EarlyCullEnable
= true;
1277 clip
.FrontWinding
= brw
->polygon_front_bit
== _mesa_is_user_fbo(fb
);
1279 if (ctx
->Polygon
.CullFlag
) {
1280 switch (ctx
->Polygon
.CullFaceMode
) {
1282 clip
.CullMode
= CULLMODE_FRONT
;
1285 clip
.CullMode
= CULLMODE_BACK
;
1287 case GL_FRONT_AND_BACK
:
1288 clip
.CullMode
= CULLMODE_BOTH
;
1291 unreachable("Should not get here: invalid CullFlag");
1294 clip
.CullMode
= CULLMODE_NONE
;
1299 clip
.UserClipDistanceCullTestEnableBitmask
=
1300 brw_vue_prog_data(brw
->vs
.base
.prog_data
)->cull_distance_mask
;
1302 clip
.ViewportZClipTestEnable
= !ctx
->Transform
.DepthClamp
;
1306 if (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
) {
1307 clip
.TriangleStripListProvokingVertexSelect
= 0;
1308 clip
.TriangleFanProvokingVertexSelect
= 1;
1309 clip
.LineStripListProvokingVertexSelect
= 0;
1311 clip
.TriangleStripListProvokingVertexSelect
= 2;
1312 clip
.TriangleFanProvokingVertexSelect
= 2;
1313 clip
.LineStripListProvokingVertexSelect
= 1;
1316 /* _NEW_TRANSFORM */
1317 clip
.UserClipDistanceClipTestEnableBitmask
=
1318 ctx
->Transform
.ClipPlanesEnabled
;
1321 clip
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1324 if (ctx
->Transform
.ClipDepthMode
== GL_ZERO_TO_ONE
)
1325 clip
.APIMode
= APIMODE_D3D
;
1327 clip
.APIMode
= APIMODE_OGL
;
1329 clip
.GuardbandClipTestEnable
= true;
1331 /* BRW_NEW_VIEWPORT_COUNT */
1332 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1334 if (ctx
->RasterDiscard
) {
1335 clip
.ClipMode
= CLIPMODE_REJECT_ALL
;
1337 perf_debug("Rasterizer discard is currently implemented via the "
1338 "clipper; having the GS not write primitives would "
1339 "likely be faster.\n");
1342 clip
.ClipMode
= CLIPMODE_NORMAL
;
1345 clip
.ClipEnable
= true;
1348 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1350 if (!brw_is_drawing_points(brw
) && !brw_is_drawing_lines(brw
))
1351 clip
.ViewportXYClipTestEnable
= true;
1353 clip
.MinimumPointWidth
= 0.125;
1354 clip
.MaximumPointWidth
= 255.875;
1355 clip
.MaximumVPIndex
= viewport_count
- 1;
1356 if (_mesa_geometric_layers(fb
) == 0)
1357 clip
.ForceZeroRTAIndexEnable
= true;
1361 static const struct brw_tracked_state
genX(clip_state
) = {
1363 .mesa
= _NEW_BUFFERS
|
1367 .brw
= BRW_NEW_BLORP
|
1369 BRW_NEW_FS_PROG_DATA
|
1370 BRW_NEW_GS_PROG_DATA
|
1371 BRW_NEW_VS_PROG_DATA
|
1372 BRW_NEW_META_IN_PROGRESS
|
1374 BRW_NEW_RASTERIZER_DISCARD
|
1375 BRW_NEW_TES_PROG_DATA
|
1376 BRW_NEW_VIEWPORT_COUNT
,
1378 .emit
= genX(upload_clip_state
),
1382 /* ---------------------------------------------------------------------- */
1385 genX(upload_sf
)(struct brw_context
*brw
)
1387 struct gl_context
*ctx
= &brw
->ctx
;
1392 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1393 UNUSED
const bool multisampled_fbo
=
1394 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1398 const struct brw_sf_prog_data
*sf_prog_data
= brw
->sf
.prog_data
;
1400 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1402 brw_state_emit(brw
, GENX(SF_STATE
), 64, &brw
->sf
.state_offset
, sf
) {
1403 sf
.KernelStartPointer
= KSP_ro(brw
, brw
->sf
.prog_offset
);
1404 sf
.FloatingPointMode
= FLOATING_POINT_MODE_Alternate
;
1405 sf
.GRFRegisterCount
= DIV_ROUND_UP(sf_prog_data
->total_grf
, 16) - 1;
1406 sf
.DispatchGRFStartRegisterForURBData
= 3;
1407 sf
.VertexURBEntryReadOffset
= BRW_SF_URB_ENTRY_READ_OFFSET
;
1408 sf
.VertexURBEntryReadLength
= sf_prog_data
->urb_read_length
;
1409 sf
.NumberofURBEntries
= brw
->urb
.nr_sf_entries
;
1410 sf
.URBEntryAllocationSize
= brw
->urb
.sfsize
- 1;
1412 /* STATE_PREFETCH command description describes this state as being
1413 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1416 sf
.SetupViewportStateOffset
=
1417 instruction_ro_bo(brw
->batch
.bo
, brw
->sf
.vp_offset
);
1419 sf
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1421 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1422 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1424 sf
.MaximumNumberofThreads
=
1425 MIN2(GEN_GEN
== 5 ? 48 : 24, brw
->urb
.nr_sf_entries
) - 1;
1427 sf
.SpritePointEnable
= ctx
->Point
.PointSprite
;
1429 sf
.DestinationOriginHorizontalBias
= 0.5;
1430 sf
.DestinationOriginVerticalBias
= 0.5;
1432 brw_batch_emit(brw
, GENX(3DSTATE_SF
), sf
) {
1433 sf
.StatisticsEnable
= true;
1435 sf
.ViewportTransformEnable
= true;
1439 sf
.DepthBufferSurfaceFormat
= brw_depthbuffer_format(brw
);
1444 sf
.FrontWinding
= brw
->polygon_front_bit
== render_to_fbo
;
1446 sf
.GlobalDepthOffsetEnableSolid
= ctx
->Polygon
.OffsetFill
;
1447 sf
.GlobalDepthOffsetEnableWireframe
= ctx
->Polygon
.OffsetLine
;
1448 sf
.GlobalDepthOffsetEnablePoint
= ctx
->Polygon
.OffsetPoint
;
1450 switch (ctx
->Polygon
.FrontMode
) {
1452 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
1455 sf
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
1458 sf
.FrontFaceFillMode
= FILL_MODE_POINT
;
1461 unreachable("not reached");
1464 switch (ctx
->Polygon
.BackMode
) {
1466 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
1469 sf
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
1472 sf
.BackFaceFillMode
= FILL_MODE_POINT
;
1475 unreachable("not reached");
1478 if (multisampled_fbo
&& ctx
->Multisample
.Enabled
)
1479 sf
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1481 sf
.GlobalDepthOffsetConstant
= ctx
->Polygon
.OffsetUnits
* 2;
1482 sf
.GlobalDepthOffsetScale
= ctx
->Polygon
.OffsetFactor
;
1483 sf
.GlobalDepthOffsetClamp
= ctx
->Polygon
.OffsetClamp
;
1486 sf
.ScissorRectangleEnable
= true;
1488 if (ctx
->Polygon
.CullFlag
) {
1489 switch (ctx
->Polygon
.CullFaceMode
) {
1491 sf
.CullMode
= CULLMODE_FRONT
;
1494 sf
.CullMode
= CULLMODE_BACK
;
1496 case GL_FRONT_AND_BACK
:
1497 sf
.CullMode
= CULLMODE_BOTH
;
1500 unreachable("not reached");
1503 sf
.CullMode
= CULLMODE_NONE
;
1507 sf
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1514 if (brw
->is_cherryview
)
1515 sf
.CHVLineWidth
= brw_get_line_width(brw
);
1517 sf
.LineWidth
= brw_get_line_width(brw
);
1519 sf
.LineWidth
= brw_get_line_width(brw
);
1522 if (ctx
->Line
.SmoothFlag
) {
1523 sf
.LineEndCapAntialiasingRegionWidth
= _10pixels
;
1525 sf
.AntiAliasingEnable
= true;
1529 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1530 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1531 /* Clamp to the hardware limits */
1532 sf
.PointWidth
= CLAMP(point_size
, 0.125f
, 255.875f
);
1534 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1535 if (use_state_point_size(brw
))
1536 sf
.PointWidthSource
= State
;
1539 /* _NEW_POINT | _NEW_MULTISAMPLE */
1540 if ((ctx
->Point
.SmoothFlag
|| _mesa_is_multisample_enabled(ctx
)) &&
1541 !ctx
->Point
.PointSprite
)
1542 sf
.SmoothPointEnable
= true;
1545 #if GEN_IS_G4X || GEN_GEN >= 5
1546 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1550 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
1551 sf
.TriangleStripListProvokingVertexSelect
= 2;
1552 sf
.TriangleFanProvokingVertexSelect
= 2;
1553 sf
.LineStripListProvokingVertexSelect
= 1;
1555 sf
.TriangleFanProvokingVertexSelect
= 1;
1559 /* BRW_NEW_FS_PROG_DATA */
1560 const struct brw_wm_prog_data
*wm_prog_data
=
1561 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1563 sf
.AttributeSwizzleEnable
= true;
1564 sf
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1567 * Window coordinates in an FBO are inverted, which means point
1568 * sprite origin must be inverted, too.
1570 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
) {
1571 sf
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
1573 sf
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
1576 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1577 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1579 uint32_t urb_entry_read_length
;
1580 uint32_t urb_entry_read_offset
;
1581 uint32_t point_sprite_enables
;
1582 genX(calculate_attr_overrides
)(brw
, sf
.Attribute
, &point_sprite_enables
,
1583 &urb_entry_read_length
,
1584 &urb_entry_read_offset
);
1585 sf
.VertexURBEntryReadLength
= urb_entry_read_length
;
1586 sf
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
1587 sf
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
1588 sf
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1593 static const struct brw_tracked_state
genX(sf_state
) = {
1595 .mesa
= _NEW_LIGHT
|
1599 (GEN_GEN
>= 6 ? _NEW_MULTISAMPLE
: 0) |
1600 (GEN_GEN
<= 7 ? _NEW_BUFFERS
| _NEW_POLYGON
: 0),
1601 .brw
= BRW_NEW_BLORP
|
1602 BRW_NEW_VUE_MAP_GEOM_OUT
|
1603 (GEN_GEN
<= 5 ? BRW_NEW_BATCH
|
1604 BRW_NEW_PROGRAM_CACHE
|
1605 BRW_NEW_SF_PROG_DATA
|
1609 (GEN_GEN
>= 6 ? BRW_NEW_CONTEXT
: 0) |
1610 (GEN_GEN
>= 6 && GEN_GEN
<= 7 ?
1611 BRW_NEW_GS_PROG_DATA
|
1613 BRW_NEW_TES_PROG_DATA
1615 (GEN_GEN
== 6 ? BRW_NEW_FS_PROG_DATA
|
1616 BRW_NEW_FRAGMENT_PROGRAM
1619 .emit
= genX(upload_sf
),
1622 /* ---------------------------------------------------------------------- */
1626 genX(upload_wm
)(struct brw_context
*brw
)
1628 struct gl_context
*ctx
= &brw
->ctx
;
1630 /* BRW_NEW_FS_PROG_DATA */
1631 const struct brw_wm_prog_data
*wm_prog_data
=
1632 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1634 UNUSED
bool writes_depth
=
1635 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
1638 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
1639 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1641 /* We can't fold this into gen6_upload_wm_push_constants(), because
1642 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1643 * (3DSTATE_CONSTANT_PS [DevSNB]):
1645 * "[DevSNB]: This packet must be followed by WM_STATE."
1647 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_PS
), wmcp
) {
1648 if (wm_prog_data
->base
.nr_params
!= 0) {
1649 wmcp
.Buffer0Valid
= true;
1650 /* Pointer to the WM constant buffer. Covered by the set of
1651 * state flags from gen6_upload_wm_push_constants.
1653 wmcp
.PointertoPSConstantBuffer0
= stage_state
->push_const_offset
;
1654 wmcp
.PSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1659 brw_batch_emit(brw
, GENX(3DSTATE_WM
), wm
) {
1660 wm
.StatisticsEnable
= true;
1661 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1662 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1665 if (wm_prog_data
->base
.use_alt_mode
)
1666 wm
.FloatingPointMode
= Alternate
;
1668 wm
.SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4);
1669 wm
.BindingTableEntryCount
= wm_prog_data
->base
.binding_table
.size_bytes
/ 4;
1670 wm
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1671 wm
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1672 wm
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1673 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1674 wm_prog_data
->base
.dispatch_grf_start_reg
;
1675 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1676 wm_prog_data
->dispatch_grf_start_reg_2
;
1677 wm
.KernelStartPointer0
= stage_state
->prog_offset
;
1678 wm
.KernelStartPointer2
= stage_state
->prog_offset
+
1679 wm_prog_data
->prog_offset_2
;
1680 wm
.DualSourceBlendEnable
=
1681 wm_prog_data
->dual_src_blend
&& (ctx
->Color
.BlendEnabled
& 1) &&
1682 ctx
->Color
.Blend
[0]._UsesDualSrc
;
1683 wm
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1684 wm
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1686 /* From the SNB PRM, volume 2 part 1, page 281:
1687 * "If the PS kernel does not need the Position XY Offsets
1688 * to compute a Position XY value, then this field should be
1689 * programmed to POSOFFSET_NONE."
1691 * "SW Recommendation: If the PS kernel needs the Position Offsets
1692 * to compute a Position XY value, this field should match Position
1693 * ZW Interpolation Mode to ensure a consistent position.xyzw
1695 * We only require XY sample offsets. So, this recommendation doesn't
1696 * look useful at the moment. We might need this in future.
1698 if (wm_prog_data
->uses_pos_offset
)
1699 wm
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
1701 wm
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
1703 if (wm_prog_data
->base
.total_scratch
) {
1704 wm
.ScratchSpaceBasePointer
=
1705 render_bo(stage_state
->scratch_bo
,
1706 ffs(stage_state
->per_thread_scratch
) - 11);
1709 wm
.PixelShaderComputedDepth
= writes_depth
;
1712 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1715 wm
.LineStippleEnable
= ctx
->Line
.StippleFlag
;
1718 wm
.PolygonStippleEnable
= ctx
->Polygon
.StippleFlag
;
1719 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
1723 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
1725 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1726 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1727 if (wm_prog_data
->uses_kill
||
1728 _mesa_is_alpha_test_enabled(ctx
) ||
1729 _mesa_is_alpha_to_coverage_enabled(ctx
) ||
1730 wm_prog_data
->uses_omask
) {
1731 wm
.PixelShaderKillsPixel
= true;
1734 /* _NEW_BUFFERS | _NEW_COLOR */
1735 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
1736 wm_prog_data
->has_side_effects
|| wm
.PixelShaderKillsPixel
) {
1737 wm
.ThreadDispatchEnable
= true;
1739 if (multisampled_fbo
) {
1740 /* _NEW_MULTISAMPLE */
1741 if (ctx
->Multisample
.Enabled
)
1742 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1744 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1746 if (wm_prog_data
->persample_dispatch
)
1747 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1749 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1751 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1752 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1756 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1757 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1760 /* The "UAV access enable" bits are unnecessary on HSW because they only
1761 * seem to have an effect on the HW-assisted coherency mechanism which we
1762 * don't need, and the rasterization-related UAV_ONLY flag and the
1763 * DISPATCH_ENABLE bit can be set independently from it.
1764 * C.f. gen8_upload_ps_extra().
1766 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
1770 if (!(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
1771 wm_prog_data
->has_side_effects
)
1777 /* BRW_NEW_FS_PROG_DATA */
1778 if (wm_prog_data
->early_fragment_tests
)
1779 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1780 else if (wm_prog_data
->has_side_effects
)
1781 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1786 static const struct brw_tracked_state
genX(wm_state
) = {
1790 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
1794 (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
1795 .brw
= BRW_NEW_BLORP
|
1796 BRW_NEW_FS_PROG_DATA
|
1797 (GEN_GEN
< 7 ? BRW_NEW_BATCH
: BRW_NEW_CONTEXT
),
1799 .emit
= genX(upload_wm
),
1803 /* ---------------------------------------------------------------------- */
1805 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1806 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
1807 pkt.SamplerCount = \
1808 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1809 pkt.BindingTableEntryCount = \
1810 stage_prog_data->binding_table.size_bytes / 4; \
1811 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
1813 if (stage_prog_data->total_scratch) { \
1814 pkt.ScratchSpaceBasePointer = \
1815 render_bo(stage_state->scratch_bo, 0); \
1816 pkt.PerThreadScratchSpace = \
1817 ffs(stage_state->per_thread_scratch) - 11; \
1820 pkt.DispatchGRFStartRegisterForURBData = \
1821 stage_prog_data->dispatch_grf_start_reg; \
1822 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1823 pkt.prefix##URBEntryReadOffset = 0; \
1825 pkt.StatisticsEnable = true; \
1829 genX(upload_vs_state
)(struct brw_context
*brw
)
1831 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
1832 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1833 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
1835 /* BRW_NEW_VS_PROG_DATA */
1836 const struct brw_vue_prog_data
*vue_prog_data
=
1837 brw_vue_prog_data(brw
->vs
.base
.prog_data
);
1838 const struct brw_stage_prog_data
*stage_prog_data
= &vue_prog_data
->base
;
1840 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
||
1841 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
);
1844 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1845 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1847 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
1848 * command that causes the VS Function Enable to toggle. Pipeline
1849 * flush can be executed by sending a PIPE_CONTROL command with CS
1850 * stall bit set and a post sync operation.
1852 * We've already done such a flush at the start of state upload, so we
1853 * don't need to do another one here.
1855 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), cvs
) {
1856 if (stage_state
->push_const_size
!= 0) {
1857 cvs
.Buffer0Valid
= true;
1858 cvs
.PointertoVSConstantBuffer0
= stage_state
->push_const_offset
;
1859 cvs
.VSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
1864 if (GEN_GEN
== 7 && devinfo
->is_ivybridge
)
1865 gen7_emit_vs_workaround_flush(brw
);
1868 brw_batch_emit(brw
, GENX(3DSTATE_VS
), vs
) {
1870 ctx
->NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
1871 brw_state_emit(brw
, GENX(VS_STATE
), 32, &stage_state
->state_offset
, vs
) {
1873 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1875 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1878 vs
.GRFRegisterCount
= DIV_ROUND_UP(vue_prog_data
->total_grf
, 16) - 1;
1879 vs
.ConstantURBEntryReadLength
= stage_prog_data
->curb_read_length
;
1880 vs
.ConstantURBEntryReadOffset
= brw
->curbe
.vs_start
* 2;
1882 vs
.NumberofURBEntries
= brw
->urb
.nr_vs_entries
>> (GEN_GEN
== 5 ? 2 : 0);
1883 vs
.URBEntryAllocationSize
= brw
->urb
.vsize
- 1;
1885 vs
.MaximumNumberofThreads
=
1886 CLAMP(brw
->urb
.nr_vs_entries
/ 2, 1, devinfo
->max_vs_threads
) - 1;
1888 vs
.StatisticsEnable
= false;
1889 vs
.SamplerStatePointer
=
1890 instruction_ro_bo(brw
->batch
.bo
, stage_state
->sampler_offset
);
1894 /* Force single program flow on Ironlake. We cannot reliably get
1895 * all applications working without it. See:
1896 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
1898 * The most notable and reliably failing application is the Humus
1901 vs
.SingleProgramFlow
= true;
1902 vs
.SamplerCount
= 0; /* hardware requirement */
1906 vs
.SIMD8DispatchEnable
=
1907 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
;
1909 vs
.UserClipDistanceCullTestEnableBitmask
=
1910 vue_prog_data
->cull_distance_mask
;
1915 /* Based on my reading of the simulator, the VS constants don't get
1916 * pulled into the VS FF unit until an appropriate pipeline flush
1917 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
1918 * references to them into a little FIFO. The flushes are common,
1919 * but don't reliably happen between this and a 3DPRIMITIVE, causing
1920 * the primitive to use the wrong constants. Then the FIFO
1921 * containing the constant setup gets added to again on the next
1922 * constants change, and eventually when a flush does happen the
1923 * unit is overwhelmed by constant changes and dies.
1925 * To avoid this, send a PIPE_CONTROL down the line that will
1926 * update the unit immediately loading the constants. The flush
1927 * type bits here were those set by the STATE_BASE_ADDRESS whose
1928 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
1929 * bug reports that led to this workaround, and may be more than
1930 * what is strictly required to avoid the issue.
1932 brw_emit_pipe_control_flush(brw
,
1933 PIPE_CONTROL_DEPTH_STALL
|
1934 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1935 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
1939 static const struct brw_tracked_state
genX(vs_state
) = {
1941 .mesa
= (GEN_GEN
== 6 ? (_NEW_PROGRAM_CONSTANTS
| _NEW_TRANSFORM
) : 0),
1942 .brw
= BRW_NEW_BATCH
|
1945 BRW_NEW_VS_PROG_DATA
|
1946 (GEN_GEN
== 6 ? BRW_NEW_VERTEX_PROGRAM
: 0) |
1947 (GEN_GEN
<= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
1948 BRW_NEW_PROGRAM_CACHE
|
1949 BRW_NEW_SAMPLER_STATE_TABLE
|
1953 .emit
= genX(upload_vs_state
),
1956 /* ---------------------------------------------------------------------- */
1959 genX(upload_cc_viewport
)(struct brw_context
*brw
)
1961 struct gl_context
*ctx
= &brw
->ctx
;
1963 /* BRW_NEW_VIEWPORT_COUNT */
1964 const unsigned viewport_count
= brw
->clip
.viewport_count
;
1966 struct GENX(CC_VIEWPORT
) ccv
;
1967 uint32_t cc_vp_offset
;
1969 brw_state_batch(brw
, 4 * GENX(CC_VIEWPORT_length
) * viewport_count
,
1972 for (unsigned i
= 0; i
< viewport_count
; i
++) {
1973 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
1974 const struct gl_viewport_attrib
*vp
= &ctx
->ViewportArray
[i
];
1975 if (ctx
->Transform
.DepthClamp
) {
1976 ccv
.MinimumDepth
= MIN2(vp
->Near
, vp
->Far
);
1977 ccv
.MaximumDepth
= MAX2(vp
->Near
, vp
->Far
);
1979 ccv
.MinimumDepth
= 0.0;
1980 ccv
.MaximumDepth
= 1.0;
1982 GENX(CC_VIEWPORT_pack
)(NULL
, cc_map
, &ccv
);
1983 cc_map
+= GENX(CC_VIEWPORT_length
);
1987 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1988 ptr
.CCViewportPointer
= cc_vp_offset
;
1991 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
1992 vp
.CCViewportStateChange
= 1;
1993 vp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1996 brw
->cc
.vp_offset
= cc_vp_offset
;
1997 ctx
->NewDriverState
|= BRW_NEW_CC_VP
;
2001 const struct brw_tracked_state
genX(cc_vp
) = {
2003 .mesa
= _NEW_TRANSFORM
|
2005 .brw
= BRW_NEW_BATCH
|
2007 BRW_NEW_VIEWPORT_COUNT
,
2009 .emit
= genX(upload_cc_viewport
)
2012 /* ---------------------------------------------------------------------- */
2015 set_scissor_bits(const struct gl_context
*ctx
, int i
,
2016 bool render_to_fbo
, unsigned fb_width
, unsigned fb_height
,
2017 struct GENX(SCISSOR_RECT
) *sc
)
2021 bbox
[0] = MAX2(ctx
->ViewportArray
[i
].X
, 0);
2022 bbox
[1] = MIN2(bbox
[0] + ctx
->ViewportArray
[i
].Width
, fb_width
);
2023 bbox
[2] = MAX2(ctx
->ViewportArray
[i
].Y
, 0);
2024 bbox
[3] = MIN2(bbox
[2] + ctx
->ViewportArray
[i
].Height
, fb_height
);
2025 _mesa_intersect_scissor_bounding_box(ctx
, i
, bbox
);
2027 if (bbox
[0] == bbox
[1] || bbox
[2] == bbox
[3]) {
2028 /* If the scissor was out of bounds and got clamped to 0 width/height
2029 * at the bounds, the subtraction of 1 from maximums could produce a
2030 * negative number and thus not clip anything. Instead, just provide
2031 * a min > max scissor inside the bounds, which produces the expected
2034 sc
->ScissorRectangleXMin
= 1;
2035 sc
->ScissorRectangleXMax
= 0;
2036 sc
->ScissorRectangleYMin
= 1;
2037 sc
->ScissorRectangleYMax
= 0;
2038 } else if (render_to_fbo
) {
2039 /* texmemory: Y=0=bottom */
2040 sc
->ScissorRectangleXMin
= bbox
[0];
2041 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2042 sc
->ScissorRectangleYMin
= bbox
[2];
2043 sc
->ScissorRectangleYMax
= bbox
[3] - 1;
2045 /* memory: Y=0=top */
2046 sc
->ScissorRectangleXMin
= bbox
[0];
2047 sc
->ScissorRectangleXMax
= bbox
[1] - 1;
2048 sc
->ScissorRectangleYMin
= fb_height
- bbox
[3];
2049 sc
->ScissorRectangleYMax
= fb_height
- bbox
[2] - 1;
2055 genX(upload_scissor_state
)(struct brw_context
*brw
)
2057 struct gl_context
*ctx
= &brw
->ctx
;
2058 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2059 struct GENX(SCISSOR_RECT
) scissor
;
2060 uint32_t scissor_state_offset
;
2061 const unsigned int fb_width
= _mesa_geometric_width(ctx
->DrawBuffer
);
2062 const unsigned int fb_height
= _mesa_geometric_height(ctx
->DrawBuffer
);
2063 uint32_t *scissor_map
;
2065 /* BRW_NEW_VIEWPORT_COUNT */
2066 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2068 scissor_map
= brw_state_batch(
2069 brw
, GENX(SCISSOR_RECT_length
) * sizeof(uint32_t) * viewport_count
,
2070 32, &scissor_state_offset
);
2072 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2074 /* The scissor only needs to handle the intersection of drawable and
2075 * scissor rect. Clipping to the boundaries of static shared buffers
2076 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2078 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2079 * inclusive but max is exclusive.
2081 for (unsigned i
= 0; i
< viewport_count
; i
++) {
2082 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
, &scissor
);
2083 GENX(SCISSOR_RECT_pack
)(
2084 NULL
, scissor_map
+ i
* GENX(SCISSOR_RECT_length
), &scissor
);
2087 brw_batch_emit(brw
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2088 ptr
.ScissorRectPointer
= scissor_state_offset
;
2092 static const struct brw_tracked_state
genX(scissor_state
) = {
2094 .mesa
= _NEW_BUFFERS
|
2097 .brw
= BRW_NEW_BATCH
|
2099 BRW_NEW_VIEWPORT_COUNT
,
2101 .emit
= genX(upload_scissor_state
),
2105 /* ---------------------------------------------------------------------- */
2108 brw_calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2109 float m00
, float m11
, float m30
, float m31
,
2110 float *xmin
, float *xmax
,
2111 float *ymin
, float *ymax
)
2113 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2114 * Strips and Fans documentation:
2116 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2117 * fixed-point "guardband" range supported by the rasterization hardware"
2121 * "In almost all circumstances, if an object’s vertices are actually
2122 * modified by this clamping (i.e., had X or Y coordinates outside of
2123 * the guardband extent the rendered object will not match the intended
2124 * result. Therefore software should take steps to ensure that this does
2125 * not happen - e.g., by clipping objects such that they do not exceed
2126 * these limits after the Drawing Rectangle is applied."
2128 * I believe the fundamental restriction is that the rasterizer (in
2129 * the SF/WM stages) have a limit on the number of pixels that can be
2130 * rasterized. We need to ensure any coordinates beyond the rasterizer
2131 * limit are handled by the clipper. So effectively that limit becomes
2132 * the clipper's guardband size.
2134 * It goes on to say:
2136 * "In addition, in order to be correctly rendered, objects must have a
2137 * screenspace bounding box not exceeding 8K in the X or Y direction.
2138 * This additional restriction must also be comprehended by software,
2139 * i.e., enforced by use of clipping."
2141 * This makes no sense. Gen7+ hardware supports 16K render targets,
2142 * and you definitely need to be able to draw polygons that fill the
2143 * surface. Our assumption is that the rasterizer was limited to 8K
2144 * on Sandybridge, which only supports 8K surfaces, and it was actually
2145 * increased to 16K on Ivybridge and later.
2147 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2149 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2151 if (m00
!= 0 && m11
!= 0) {
2152 /* First, we compute the screen-space render area */
2153 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2154 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2155 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2156 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2158 /* We want the guardband to be centered on that */
2159 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2160 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2161 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2162 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2164 /* Now we need it in native device coordinates */
2165 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2166 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2167 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2168 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2170 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2171 * flipped upside-down. X should be fine though.
2173 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2174 *xmin
= ndc_gb_xmin
;
2175 *xmax
= ndc_gb_xmax
;
2176 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2177 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2179 /* The viewport scales to 0, so nothing will be rendered. */
2188 genX(upload_sf_clip_viewport
)(struct brw_context
*brw
)
2190 struct gl_context
*ctx
= &brw
->ctx
;
2191 float y_scale
, y_bias
;
2193 /* BRW_NEW_VIEWPORT_COUNT */
2194 const unsigned viewport_count
= brw
->clip
.viewport_count
;
2197 const bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2198 const uint32_t fb_width
= (float)_mesa_geometric_width(ctx
->DrawBuffer
);
2199 const uint32_t fb_height
= (float)_mesa_geometric_height(ctx
->DrawBuffer
);
2203 struct GENX(SF_CLIP_VIEWPORT
) sfv
;
2204 uint32_t sf_clip_vp_offset
;
2205 uint32_t *sf_clip_map
=
2206 brw_state_batch(brw
, GENX(SF_CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2207 64, &sf_clip_vp_offset
);
2209 struct GENX(SF_VIEWPORT
) sfv
;
2210 struct GENX(CLIP_VIEWPORT
) clv
;
2211 uint32_t sf_vp_offset
, clip_vp_offset
;
2213 brw_state_batch(brw
, GENX(SF_VIEWPORT_length
) * 4 * viewport_count
,
2215 uint32_t *clip_map
=
2216 brw_state_batch(brw
, GENX(CLIP_VIEWPORT_length
) * 4 * viewport_count
,
2217 32, &clip_vp_offset
);
2221 if (render_to_fbo
) {
2226 y_bias
= (float)fb_height
;
2229 for (unsigned i
= 0; i
< brw
->clip
.viewport_count
; i
++) {
2230 /* _NEW_VIEWPORT: Guardband Clipping */
2231 float scale
[3], translate
[3], gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
2232 _mesa_get_viewport_xform(ctx
, i
, scale
, translate
);
2234 sfv
.ViewportMatrixElementm00
= scale
[0];
2235 sfv
.ViewportMatrixElementm11
= scale
[1] * y_scale
,
2236 sfv
.ViewportMatrixElementm22
= scale
[2],
2237 sfv
.ViewportMatrixElementm30
= translate
[0],
2238 sfv
.ViewportMatrixElementm31
= translate
[1] * y_scale
+ y_bias
,
2239 sfv
.ViewportMatrixElementm32
= translate
[2],
2240 brw_calculate_guardband_size(fb_width
, fb_height
,
2241 sfv
.ViewportMatrixElementm00
,
2242 sfv
.ViewportMatrixElementm11
,
2243 sfv
.ViewportMatrixElementm30
,
2244 sfv
.ViewportMatrixElementm31
,
2245 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
2248 clv
.XMinClipGuardband
= gb_xmin
;
2249 clv
.XMaxClipGuardband
= gb_xmax
;
2250 clv
.YMinClipGuardband
= gb_ymin
;
2251 clv
.YMaxClipGuardband
= gb_ymax
;
2254 set_scissor_bits(ctx
, i
, render_to_fbo
, fb_width
, fb_height
,
2255 &sfv
.ScissorRectangle
);
2257 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2258 * The hardware will take the intersection of the drawing rectangle,
2259 * scissor rectangle, and the viewport extents. We don't need to be
2260 * smart, and can therefore just program the viewport extents.
2262 const float viewport_Xmax
=
2263 ctx
->ViewportArray
[i
].X
+ ctx
->ViewportArray
[i
].Width
;
2264 const float viewport_Ymax
=
2265 ctx
->ViewportArray
[i
].Y
+ ctx
->ViewportArray
[i
].Height
;
2267 if (render_to_fbo
) {
2268 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2269 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2270 sfv
.YMinViewPort
= ctx
->ViewportArray
[i
].Y
;
2271 sfv
.YMaxViewPort
= viewport_Ymax
- 1;
2273 sfv
.XMinViewPort
= ctx
->ViewportArray
[i
].X
;
2274 sfv
.XMaxViewPort
= viewport_Xmax
- 1;
2275 sfv
.YMinViewPort
= fb_height
- viewport_Ymax
;
2276 sfv
.YMaxViewPort
= fb_height
- ctx
->ViewportArray
[i
].Y
- 1;
2281 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_map
, &sfv
);
2282 sf_clip_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2284 GENX(SF_VIEWPORT_pack
)(NULL
, sf_map
, &sfv
);
2285 GENX(CLIP_VIEWPORT_pack
)(NULL
, clip_map
, &clv
);
2286 sf_map
+= GENX(SF_VIEWPORT_length
);
2287 clip_map
+= GENX(CLIP_VIEWPORT_length
);
2292 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2293 ptr
.SFClipViewportPointer
= sf_clip_vp_offset
;
2296 brw_batch_emit(brw
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vp
) {
2297 vp
.SFViewportStateChange
= 1;
2298 vp
.CLIPViewportStateChange
= 1;
2299 vp
.PointertoCLIP_VIEWPORT
= clip_vp_offset
;
2300 vp
.PointertoSF_VIEWPORT
= sf_vp_offset
;
2303 brw
->sf
.vp_offset
= sf_vp_offset
;
2304 brw
->clip
.vp_offset
= clip_vp_offset
;
2305 brw
->ctx
.NewDriverState
|= BRW_NEW_SF_VP
| BRW_NEW_CLIP_VP
;
2309 static const struct brw_tracked_state
genX(sf_clip_viewport
) = {
2311 .mesa
= _NEW_BUFFERS
|
2313 (GEN_GEN
<= 5 ? _NEW_SCISSOR
: 0),
2314 .brw
= BRW_NEW_BATCH
|
2316 BRW_NEW_VIEWPORT_COUNT
,
2318 .emit
= genX(upload_sf_clip_viewport
),
2321 /* ---------------------------------------------------------------------- */
2325 genX(upload_gs_state
)(struct brw_context
*brw
)
2327 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2328 const struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2329 /* BRW_NEW_GEOMETRY_PROGRAM */
2330 bool active
= brw
->geometry_program
;
2332 /* BRW_NEW_GS_PROG_DATA */
2333 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
2334 const struct brw_vue_prog_data
*vue_prog_data
=
2335 brw_vue_prog_data(stage_prog_data
);
2337 const struct brw_gs_prog_data
*gs_prog_data
=
2338 brw_gs_prog_data(stage_prog_data
);
2342 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_GS
), cgs
) {
2343 if (active
&& stage_state
->push_const_size
!= 0) {
2344 cgs
.Buffer0Valid
= true;
2345 cgs
.PointertoGSConstantBuffer0
= stage_state
->push_const_offset
;
2346 cgs
.GSConstantBuffer0ReadLength
= stage_state
->push_const_size
- 1;
2351 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2353 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2354 * Geometry > Geometry Shader > State:
2356 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2357 * whole fixed function pipeline when the GS enable changes value in
2360 * The hardware architects have clarified that in this context "flush the
2361 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2364 if (brw
->gt
== 2 && brw
->gs
.enabled
!= active
)
2365 gen7_emit_cs_stall_flush(brw
);
2369 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2370 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2373 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2374 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2375 gs
.ControlDataHeaderSize
=
2376 gs_prog_data
->control_data_header_size_hwords
;
2378 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2379 gs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
2381 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2383 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2386 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2387 * Ivy Bridge and Haswell.
2389 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2390 * strip to be delivered to the geometry shader in an order that does
2391 * not strictly follow the OpenGL spec, but preserves triangle
2392 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2393 * the geometry shader sees triangles:
2395 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2397 * (Clearing the bit is even worse, because it fails to preserve
2400 * Triangle strips with adjacency always ordered in a way that preserves
2401 * triangle orientation but does not strictly follow the OpenGL spec,
2402 * regardless of the setting of this bit.
2404 * On Haswell, both triangle strips and triangle strips with adjacency
2405 * are always ordered in a way that preserves triangle orientation.
2406 * Setting this bit causes the ordering to strictly follow the OpenGL
2409 * So in either case we want to set the bit. Unfortunately on Ivy
2410 * Bridge this will get the order close to correct but not perfect.
2412 gs
.ReorderMode
= TRAILING
;
2413 gs
.MaximumNumberofThreads
=
2414 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2415 : (devinfo
->max_gs_threads
- 1);
2418 gs
.SOStatisticsEnable
= true;
2419 gs
.RenderingEnabled
= 1;
2420 if (brw
->geometry_program
->info
.has_transform_feedback_varyings
)
2421 gs
.SVBIPayloadEnable
= true;
2423 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2424 * was previously done for gen6.
2426 * TODO: test with both disabled to see if the HW is behaving
2427 * as expected, like in gen7.
2429 gs
.SingleProgramFlow
= true;
2430 gs
.VectorMaskEnable
= true;
2434 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2436 if (gs_prog_data
->static_vertex_count
!= -1) {
2437 gs
.StaticOutput
= true;
2438 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2440 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2442 gs
.UserClipDistanceCullTestEnableBitmask
=
2443 vue_prog_data
->cull_distance_mask
;
2445 const int urb_entry_write_offset
= 1;
2446 const uint32_t urb_entry_output_length
=
2447 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2448 urb_entry_write_offset
;
2450 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2451 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2455 } else if (brw
->ff_gs
.prog_active
) {
2456 /* In gen6, transform feedback for the VS stage is done with an ad-hoc GS
2457 * program. This function provides the needed 3DSTATE_GS for this.
2459 upload_gs_state_for_tf(brw
);
2462 brw_batch_emit(brw
, GENX(3DSTATE_GS
), gs
) {
2463 gs
.StatisticsEnable
= true;
2465 gs
.RenderingEnabled
= true;
2469 gs
.DispatchGRFStartRegisterForURBData
= 1;
2471 gs
.IncludeVertexHandles
= true;
2477 brw
->gs
.enabled
= active
;
2481 static const struct brw_tracked_state
genX(gs_state
) = {
2483 .mesa
= (GEN_GEN
< 7 ? _NEW_PROGRAM_CONSTANTS
: 0),
2484 .brw
= BRW_NEW_BATCH
|
2487 BRW_NEW_GEOMETRY_PROGRAM
|
2488 BRW_NEW_GS_PROG_DATA
|
2489 (GEN_GEN
< 7 ? BRW_NEW_FF_GS_PROG_DATA
: 0),
2491 .emit
= genX(upload_gs_state
),
2495 /* ---------------------------------------------------------------------- */
2497 UNUSED
static GLenum
2498 fix_dual_blend_alpha_to_one(GLenum function
)
2504 case GL_ONE_MINUS_SRC1_ALPHA
:
2511 #define blend_factor(x) brw_translate_blend_factor(x)
2512 #define blend_eqn(x) brw_translate_blend_equation(x)
2516 genX(upload_blend_state
)(struct brw_context
*brw
)
2518 struct gl_context
*ctx
= &brw
->ctx
;
2521 /* We need at least one BLEND_STATE written, because we might do
2522 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2523 * for computed depth or alpha test), which will do an FB write
2524 * with render target 0, which will reference BLEND_STATE[0] for
2525 * alpha test enable.
2527 int nr_draw_buffers
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
2528 if (nr_draw_buffers
== 0 && ctx
->Color
.AlphaEnabled
)
2529 nr_draw_buffers
= 1;
2531 size
= GENX(BLEND_STATE_ENTRY_length
) * 4 * nr_draw_buffers
;
2533 size
+= GENX(BLEND_STATE_length
) * 4;
2536 uint32_t *blend_map
;
2537 blend_map
= brw_state_batch(brw
, size
, 64, &brw
->cc
.blend_state_offset
);
2540 struct GENX(BLEND_STATE
) blend
= { 0 };
2543 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2544 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2547 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2548 * "If drawbuffer zero is not NONE and the buffer it references has an
2549 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2550 * operations are skipped."
2552 if (!(ctx
->DrawBuffer
->_IntegerBuffers
& 0x1)) {
2553 /* _NEW_MULTISAMPLE */
2554 if (_mesa_is_multisample_enabled(ctx
)) {
2555 if (ctx
->Multisample
.SampleAlphaToCoverage
) {
2556 blend
.AlphaToCoverageEnable
= true;
2557 blend
.AlphaToCoverageDitherEnable
= GEN_GEN
>= 7;
2559 if (ctx
->Multisample
.SampleAlphaToOne
)
2560 blend
.AlphaToOneEnable
= true;
2564 if (ctx
->Color
.AlphaEnabled
) {
2565 blend
.AlphaTestEnable
= true;
2566 blend
.AlphaTestFunction
=
2567 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
2570 if (ctx
->Color
.DitherFlag
) {
2571 blend
.ColorDitherEnable
= true;
2576 for (int i
= 0; i
< nr_draw_buffers
; i
++) {
2577 struct GENX(BLEND_STATE_ENTRY
) entry
= { 0 };
2583 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
2585 /* Used for implementing the following bit of GL_EXT_texture_integer:
2586 * "Per-fragment operations that require floating-point color
2587 * components, including multisample alpha operations, alpha test,
2588 * blending, and dithering, have no effect when the corresponding
2589 * colors are written to an integer color buffer."
2591 bool integer
= ctx
->DrawBuffer
->_IntegerBuffers
& (0x1 << i
);
2594 if (ctx
->Color
.ColorLogicOpEnabled
) {
2595 GLenum rb_type
= rb
? _mesa_get_format_datatype(rb
->Format
)
2596 : GL_UNSIGNED_NORMALIZED
;
2597 WARN_ONCE(ctx
->Color
.LogicOp
!= GL_COPY
&&
2598 rb_type
!= GL_UNSIGNED_NORMALIZED
&&
2599 rb_type
!= GL_FLOAT
, "Ignoring %s logic op on %s "
2601 _mesa_enum_to_string(ctx
->Color
.LogicOp
),
2602 _mesa_enum_to_string(rb_type
));
2603 if (GEN_GEN
>= 8 || rb_type
== GL_UNSIGNED_NORMALIZED
) {
2604 entry
.LogicOpEnable
= true;
2605 entry
.LogicOpFunction
=
2606 intel_translate_logic_op(ctx
->Color
.LogicOp
);
2608 } else if (ctx
->Color
.BlendEnabled
& (1 << i
) && !integer
&&
2609 !ctx
->Color
._AdvancedBlendMode
) {
2610 GLenum eqRGB
= ctx
->Color
.Blend
[i
].EquationRGB
;
2611 GLenum eqA
= ctx
->Color
.Blend
[i
].EquationA
;
2612 GLenum srcRGB
= ctx
->Color
.Blend
[i
].SrcRGB
;
2613 GLenum dstRGB
= ctx
->Color
.Blend
[i
].DstRGB
;
2614 GLenum srcA
= ctx
->Color
.Blend
[i
].SrcA
;
2615 GLenum dstA
= ctx
->Color
.Blend
[i
].DstA
;
2617 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
2618 srcRGB
= dstRGB
= GL_ONE
;
2620 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
2621 srcA
= dstA
= GL_ONE
;
2623 /* Due to hardware limitations, the destination may have information
2624 * in an alpha channel even when the format specifies no alpha
2625 * channel. In order to avoid getting any incorrect blending due to
2626 * that alpha channel, coerce the blend factors to values that will
2627 * not read the alpha channel, but will instead use the correct
2628 * implicit value for alpha.
2630 if (rb
&& !_mesa_base_format_has_channel(rb
->_BaseFormat
,
2631 GL_TEXTURE_ALPHA_TYPE
)) {
2632 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
2633 srcA
= brw_fix_xRGB_alpha(srcA
);
2634 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
2635 dstA
= brw_fix_xRGB_alpha(dstA
);
2638 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2639 * "If Dual Source Blending is enabled, this bit must be disabled."
2641 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2642 * and leave it enabled anyway.
2644 if (ctx
->Color
.Blend
[i
]._UsesDualSrc
&& blend
.AlphaToOneEnable
) {
2645 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
2646 srcA
= fix_dual_blend_alpha_to_one(srcA
);
2647 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
2648 dstA
= fix_dual_blend_alpha_to_one(dstA
);
2651 entry
.ColorBufferBlendEnable
= true;
2652 entry
.DestinationBlendFactor
= blend_factor(dstRGB
);
2653 entry
.SourceBlendFactor
= blend_factor(srcRGB
);
2654 entry
.DestinationAlphaBlendFactor
= blend_factor(dstA
);
2655 entry
.SourceAlphaBlendFactor
= blend_factor(srcA
);
2656 entry
.ColorBlendFunction
= blend_eqn(eqRGB
);
2657 entry
.AlphaBlendFunction
= blend_eqn(eqA
);
2659 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
2660 blend
.IndependentAlphaBlendEnable
= true;
2663 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
2664 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
2666 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
2667 * clamping in the fragment shader. For its clamping of
2668 * blending, the spec says:
2670 * "RESOLVED: For fixed-point color buffers, the inputs and
2671 * the result of the blending equation are clamped. For
2672 * floating-point color buffers, no clamping occurs."
2674 * So, generally, we want clamping to the render target's range.
2675 * And, good news, the hardware tables for both pre- and
2676 * post-blend color clamping are either ignored, or any are
2677 * allowed, or clamping is required but RT range clamping is a
2680 entry
.PreBlendColorClampEnable
= true;
2681 entry
.PostBlendColorClampEnable
= true;
2682 entry
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
2684 entry
.WriteDisableRed
= !ctx
->Color
.ColorMask
[i
][0];
2685 entry
.WriteDisableGreen
= !ctx
->Color
.ColorMask
[i
][1];
2686 entry
.WriteDisableBlue
= !ctx
->Color
.ColorMask
[i
][2];
2687 entry
.WriteDisableAlpha
= !ctx
->Color
.ColorMask
[i
][3];
2690 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[1 + i
* 2], &entry
);
2692 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, &blend_map
[i
* 2], &entry
);
2698 GENX(BLEND_STATE_pack
)(NULL
, blend_map
, &blend
);
2702 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2703 ptr
.PointertoBLEND_STATE
= brw
->cc
.blend_state_offset
;
2704 ptr
.BLEND_STATEChange
= true;
2707 brw_batch_emit(brw
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2708 ptr
.BlendStatePointer
= brw
->cc
.blend_state_offset
;
2710 ptr
.BlendStatePointerValid
= true;
2716 static const struct brw_tracked_state
genX(blend_state
) = {
2718 .mesa
= _NEW_BUFFERS
|
2721 .brw
= BRW_NEW_BATCH
|
2723 BRW_NEW_STATE_BASE_ADDRESS
,
2725 .emit
= genX(upload_blend_state
),
2729 /* ---------------------------------------------------------------------- */
2732 UNUSED
static const uint32_t push_constant_opcodes
[] = {
2733 [MESA_SHADER_VERTEX
] = 21,
2734 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2735 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2736 [MESA_SHADER_GEOMETRY
] = 22,
2737 [MESA_SHADER_FRAGMENT
] = 23,
2738 [MESA_SHADER_COMPUTE
] = 0,
2742 upload_constant_state(struct brw_context
*brw
,
2743 struct brw_stage_state
*stage_state
,
2744 bool active
, uint32_t stage
)
2746 UNUSED
uint32_t mocs
= GEN_GEN
< 8 ? GEN7_MOCS_L3
: 0;
2747 active
= active
&& stage_state
->push_const_size
!= 0;
2749 brw_batch_emit(brw
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2750 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2752 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2753 pkt
.ConstantBody
.ReadLength
[2] = stage_state
->push_const_size
;
2754 pkt
.ConstantBody
.Buffer
[2] =
2755 render_ro_bo(brw
->curbe
.curbe_bo
, stage_state
->push_const_offset
);
2757 pkt
.ConstantBody
.ReadLength
[0] = stage_state
->push_const_size
;
2758 pkt
.ConstantBody
.Buffer
[0].offset
=
2759 stage_state
->push_const_offset
| mocs
;
2764 brw
->ctx
.NewDriverState
|= GEN_GEN
>= 9 ? BRW_NEW_SURFACES
: 0;
2770 genX(upload_vs_push_constants
)(struct brw_context
*brw
)
2772 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
2774 /* _BRW_NEW_VERTEX_PROGRAM */
2775 const struct brw_program
*vp
= brw_program_const(brw
->vertex_program
);
2776 /* BRW_NEW_VS_PROG_DATA */
2777 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
2779 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_VERTEX
);
2780 gen6_upload_push_constants(brw
, &vp
->program
, prog_data
, stage_state
);
2783 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !brw
->is_baytrail
)
2784 gen7_emit_vs_workaround_flush(brw
);
2786 upload_constant_state(brw
, stage_state
, true /* active */,
2787 MESA_SHADER_VERTEX
);
2791 static const struct brw_tracked_state
genX(vs_push_constants
) = {
2793 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2795 .brw
= BRW_NEW_BATCH
|
2797 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
2798 BRW_NEW_VERTEX_PROGRAM
|
2799 BRW_NEW_VS_PROG_DATA
,
2801 .emit
= genX(upload_vs_push_constants
),
2805 genX(upload_gs_push_constants
)(struct brw_context
*brw
)
2807 struct brw_stage_state
*stage_state
= &brw
->gs
.base
;
2809 /* BRW_NEW_GEOMETRY_PROGRAM */
2810 const struct brw_program
*gp
= brw_program_const(brw
->geometry_program
);
2813 /* BRW_NEW_GS_PROG_DATA */
2814 struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
2816 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_GEOMETRY
);
2817 gen6_upload_push_constants(brw
, &gp
->program
, prog_data
, stage_state
);
2821 upload_constant_state(brw
, stage_state
, gp
, MESA_SHADER_GEOMETRY
);
2825 static const struct brw_tracked_state
genX(gs_push_constants
) = {
2827 .mesa
= _NEW_PROGRAM_CONSTANTS
|
2829 .brw
= BRW_NEW_BATCH
|
2831 BRW_NEW_GEOMETRY_PROGRAM
|
2832 BRW_NEW_GS_PROG_DATA
|
2833 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2835 .emit
= genX(upload_gs_push_constants
),
2839 genX(upload_wm_push_constants
)(struct brw_context
*brw
)
2841 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
2842 /* BRW_NEW_FRAGMENT_PROGRAM */
2843 const struct brw_program
*fp
= brw_program_const(brw
->fragment_program
);
2844 /* BRW_NEW_FS_PROG_DATA */
2845 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
2847 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
2849 gen6_upload_push_constants(brw
, &fp
->program
, prog_data
, stage_state
);
2852 upload_constant_state(brw
, stage_state
, true, MESA_SHADER_FRAGMENT
);
2856 static const struct brw_tracked_state
genX(wm_push_constants
) = {
2858 .mesa
= _NEW_PROGRAM_CONSTANTS
,
2859 .brw
= BRW_NEW_BATCH
|
2861 BRW_NEW_FRAGMENT_PROGRAM
|
2862 BRW_NEW_FS_PROG_DATA
|
2863 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
2865 .emit
= genX(upload_wm_push_constants
),
2869 /* ---------------------------------------------------------------------- */
2873 genX(determine_sample_mask
)(struct brw_context
*brw
)
2875 struct gl_context
*ctx
= &brw
->ctx
;
2876 float coverage
= 1.0f
;
2877 float coverage_invert
= false;
2878 unsigned sample_mask
= ~0u;
2880 /* BRW_NEW_NUM_SAMPLES */
2881 unsigned num_samples
= brw
->num_samples
;
2883 if (_mesa_is_multisample_enabled(ctx
)) {
2884 if (ctx
->Multisample
.SampleCoverage
) {
2885 coverage
= ctx
->Multisample
.SampleCoverageValue
;
2886 coverage_invert
= ctx
->Multisample
.SampleCoverageInvert
;
2888 if (ctx
->Multisample
.SampleMask
) {
2889 sample_mask
= ctx
->Multisample
.SampleMaskValue
;
2893 if (num_samples
> 1) {
2894 int coverage_int
= (int) (num_samples
* coverage
+ 0.5f
);
2895 uint32_t coverage_bits
= (1 << coverage_int
) - 1;
2896 if (coverage_invert
)
2897 coverage_bits
^= (1 << num_samples
) - 1;
2898 return coverage_bits
& sample_mask
;
2905 genX(emit_3dstate_multisample2
)(struct brw_context
*brw
,
2906 unsigned num_samples
)
2908 assert(brw
->num_samples
<= 16);
2910 unsigned log2_samples
= ffs(MAX2(num_samples
, 1)) - 1;
2912 brw_batch_emit(brw
, GENX(3DSTATE_MULTISAMPLE
), multi
) {
2913 multi
.PixelLocation
= CENTER
;
2914 multi
.NumberofMultisamples
= log2_samples
;
2916 GEN_SAMPLE_POS_4X(multi
.Sample
);
2918 switch (num_samples
) {
2920 GEN_SAMPLE_POS_1X(multi
.Sample
);
2923 GEN_SAMPLE_POS_2X(multi
.Sample
);
2926 GEN_SAMPLE_POS_4X(multi
.Sample
);
2929 GEN_SAMPLE_POS_8X(multi
.Sample
);
2939 genX(upload_multisample_state
)(struct brw_context
*brw
)
2941 genX(emit_3dstate_multisample2
)(brw
, brw
->num_samples
);
2943 brw_batch_emit(brw
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
2944 sm
.SampleMask
= genX(determine_sample_mask
)(brw
);
2948 static const struct brw_tracked_state
genX(multisample_state
) = {
2950 .mesa
= _NEW_MULTISAMPLE
,
2951 .brw
= BRW_NEW_BLORP
|
2953 BRW_NEW_NUM_SAMPLES
,
2955 .emit
= genX(upload_multisample_state
)
2959 /* ---------------------------------------------------------------------- */
2963 genX(upload_color_calc_state
)(struct brw_context
*brw
)
2965 struct gl_context
*ctx
= &brw
->ctx
;
2967 brw_state_emit(brw
, GENX(COLOR_CALC_STATE
), 64, &brw
->cc
.state_offset
, cc
) {
2969 cc
.AlphaTestFormat
= ALPHATEST_UNORM8
;
2970 UNCLAMPED_FLOAT_TO_UBYTE(cc
.AlphaReferenceValueAsUNORM8
,
2971 ctx
->Color
.AlphaRef
);
2975 cc
.StencilReferenceValue
= _mesa_get_stencil_ref(ctx
, 0);
2976 cc
.BackfaceStencilReferenceValue
=
2977 _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
2981 cc
.BlendConstantColorRed
= ctx
->Color
.BlendColorUnclamped
[0];
2982 cc
.BlendConstantColorGreen
= ctx
->Color
.BlendColorUnclamped
[1];
2983 cc
.BlendConstantColorBlue
= ctx
->Color
.BlendColorUnclamped
[2];
2984 cc
.BlendConstantColorAlpha
= ctx
->Color
.BlendColorUnclamped
[3];
2987 brw_batch_emit(brw
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2988 ptr
.ColorCalcStatePointer
= brw
->cc
.state_offset
;
2990 ptr
.ColorCalcStatePointerValid
= true;
2995 static const struct brw_tracked_state
genX(color_calc_state
) = {
2997 .mesa
= _NEW_COLOR
|
2999 .brw
= BRW_NEW_BATCH
|
3002 BRW_NEW_STATE_BASE_ADDRESS
,
3004 .emit
= genX(upload_color_calc_state
),
3009 /* ---------------------------------------------------------------------- */
3013 genX(upload_sbe
)(struct brw_context
*brw
)
3015 struct gl_context
*ctx
= &brw
->ctx
;
3016 /* BRW_NEW_FS_PROG_DATA */
3017 const struct brw_wm_prog_data
*wm_prog_data
=
3018 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3020 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = { { 0 } };
3022 #define attr_overrides sbe.Attribute
3024 uint32_t urb_entry_read_length
;
3025 uint32_t urb_entry_read_offset
;
3026 uint32_t point_sprite_enables
;
3028 brw_batch_emit(brw
, GENX(3DSTATE_SBE
), sbe
) {
3029 sbe
.AttributeSwizzleEnable
= true;
3030 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3033 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3037 * Window coordinates in an FBO are inverted, which means point
3038 * sprite origin must be inverted.
3040 if ((ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
) != render_to_fbo
)
3041 sbe
.PointSpriteTextureCoordinateOrigin
= LOWERLEFT
;
3043 sbe
.PointSpriteTextureCoordinateOrigin
= UPPERLEFT
;
3045 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3046 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3047 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3048 * BRW_NEW_VUE_MAP_GEOM_OUT
3050 genX(calculate_attr_overrides
)(brw
,
3052 &point_sprite_enables
,
3053 &urb_entry_read_length
,
3054 &urb_entry_read_offset
);
3056 /* Typically, the URB entry read length and offset should be programmed
3057 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3058 * stage which produces geometry. However, we don't know the proper
3059 * value until we call calculate_attr_overrides().
3061 * To fit with our existing code, we override the inherited values and
3062 * specify it here directly, as we did on previous generations.
3064 sbe
.VertexURBEntryReadLength
= urb_entry_read_length
;
3065 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
3066 sbe
.PointSpriteTextureCoordinateEnable
= point_sprite_enables
;
3067 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3070 sbe
.ForceVertexURBEntryReadLength
= true;
3071 sbe
.ForceVertexURBEntryReadOffset
= true;
3075 /* prepare the active component dwords */
3076 int input_index
= 0;
3077 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
3078 if (!(brw
->fragment_program
->info
.inputs_read
&
3079 BITFIELD64_BIT(attr
))) {
3083 assert(input_index
< 32);
3085 sbe
.AttributeActiveComponentFormat
[input_index
] = ACTIVE_COMPONENT_XYZW
;
3092 brw_batch_emit(brw
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3093 for (int i
= 0; i
< 16; i
++)
3094 sbes
.Attribute
[i
] = attr_overrides
[i
];
3098 #undef attr_overrides
3101 static const struct brw_tracked_state
genX(sbe_state
) = {
3103 .mesa
= _NEW_BUFFERS
|
3108 .brw
= BRW_NEW_BLORP
|
3110 BRW_NEW_FRAGMENT_PROGRAM
|
3111 BRW_NEW_FS_PROG_DATA
|
3112 BRW_NEW_GS_PROG_DATA
|
3113 BRW_NEW_TES_PROG_DATA
|
3114 BRW_NEW_VUE_MAP_GEOM_OUT
|
3115 (GEN_GEN
== 7 ? BRW_NEW_PRIMITIVE
3118 .emit
= genX(upload_sbe
),
3122 /* ---------------------------------------------------------------------- */
3126 * Outputs the 3DSTATE_SO_DECL_LIST command.
3128 * The data output is a series of 64-bit entries containing a SO_DECL per
3129 * stream. We only have one stream of rendering coming out of the GS unit, so
3130 * we only emit stream 0 (low 16 bits) SO_DECLs.
3133 genX(upload_3dstate_so_decl_list
)(struct brw_context
*brw
,
3134 const struct brw_vue_map
*vue_map
)
3136 struct gl_context
*ctx
= &brw
->ctx
;
3137 /* BRW_NEW_TRANSFORM_FEEDBACK */
3138 struct gl_transform_feedback_object
*xfb_obj
=
3139 ctx
->TransformFeedback
.CurrentObject
;
3140 const struct gl_transform_feedback_info
*linked_xfb_info
=
3141 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3142 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3143 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3144 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3145 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3147 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3149 memset(so_decl
, 0, sizeof(so_decl
));
3151 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3152 * command feels strange -- each dword pair contains a SO_DECL per stream.
3154 for (unsigned i
= 0; i
< linked_xfb_info
->NumOutputs
; i
++) {
3155 const struct gl_transform_feedback_output
*output
=
3156 &linked_xfb_info
->Outputs
[i
];
3157 const int buffer
= output
->OutputBuffer
;
3158 const int varying
= output
->OutputRegister
;
3159 const unsigned stream_id
= output
->StreamId
;
3160 assert(stream_id
< MAX_VERTEX_STREAMS
);
3162 buffer_mask
[stream_id
] |= 1 << buffer
;
3164 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3166 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3167 * array. Instead, it simply increments DstOffset for the following
3168 * input by the number of components that should be skipped.
3170 * Our hardware is unusual in that it requires us to program SO_DECLs
3171 * for fake "hole" components, rather than simply taking the offset
3172 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3173 * program as many size = 4 holes as we can, then a final hole to
3174 * accommodate the final 1, 2, or 3 remaining.
3176 int skip_components
= output
->DstOffset
- next_offset
[buffer
];
3178 while (skip_components
> 0) {
3179 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3181 .OutputBufferSlot
= output
->OutputBuffer
,
3182 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3184 skip_components
-= 4;
3187 next_offset
[buffer
] = output
->DstOffset
+ output
->NumComponents
;
3189 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3190 .OutputBufferSlot
= output
->OutputBuffer
,
3191 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3193 ((1 << output
->NumComponents
) - 1) << output
->ComponentOffset
,
3196 if (decls
[stream_id
] > max_decls
)
3197 max_decls
= decls
[stream_id
];
3201 dw
= brw_batch_emitn(brw
, GENX(3DSTATE_SO_DECL_LIST
), 3 + 2 * max_decls
,
3202 .StreamtoBufferSelects0
= buffer_mask
[0],
3203 .StreamtoBufferSelects1
= buffer_mask
[1],
3204 .StreamtoBufferSelects2
= buffer_mask
[2],
3205 .StreamtoBufferSelects3
= buffer_mask
[3],
3206 .NumEntries0
= decls
[0],
3207 .NumEntries1
= decls
[1],
3208 .NumEntries2
= decls
[2],
3209 .NumEntries3
= decls
[3]);
3211 for (int i
= 0; i
< max_decls
; i
++) {
3212 GENX(SO_DECL_ENTRY_pack
)(
3213 brw
, dw
+ 2 + i
* 2,
3214 &(struct GENX(SO_DECL_ENTRY
)) {
3215 .Stream0Decl
= so_decl
[0][i
],
3216 .Stream1Decl
= so_decl
[1][i
],
3217 .Stream2Decl
= so_decl
[2][i
],
3218 .Stream3Decl
= so_decl
[3][i
],
3224 genX(upload_3dstate_so_buffers
)(struct brw_context
*brw
)
3226 struct gl_context
*ctx
= &brw
->ctx
;
3227 /* BRW_NEW_TRANSFORM_FEEDBACK */
3228 struct gl_transform_feedback_object
*xfb_obj
=
3229 ctx
->TransformFeedback
.CurrentObject
;
3231 const struct gl_transform_feedback_info
*linked_xfb_info
=
3232 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3234 struct brw_transform_feedback_object
*brw_obj
=
3235 (struct brw_transform_feedback_object
*) xfb_obj
;
3236 uint32_t mocs_wb
= GEN_GEN
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
3239 /* Set up the up to 4 output buffers. These are the ranges defined in the
3240 * gl_transform_feedback_object.
3242 for (int i
= 0; i
< 4; i
++) {
3243 struct intel_buffer_object
*bufferobj
=
3244 intel_buffer_object(xfb_obj
->Buffers
[i
]);
3247 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3248 sob
.SOBufferIndex
= i
;
3253 uint32_t start
= xfb_obj
->Offset
[i
];
3254 assert(start
% 4 == 0);
3255 uint32_t end
= ALIGN(start
+ xfb_obj
->Size
[i
], 4);
3257 intel_bufferobj_buffer(brw
, bufferobj
, start
, end
- start
);
3258 assert(end
<= bo
->size
);
3260 brw_batch_emit(brw
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3261 sob
.SOBufferIndex
= i
;
3263 sob
.SurfaceBaseAddress
= render_bo(bo
, start
);
3265 sob
.SurfacePitch
= linked_xfb_info
->Buffers
[i
].Stride
* 4;
3266 sob
.SurfaceEndAddress
= render_bo(bo
, end
);
3268 sob
.SOBufferEnable
= true;
3269 sob
.StreamOffsetWriteEnable
= true;
3270 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3271 sob
.SOBufferMOCS
= mocs_wb
;
3273 sob
.SurfaceSize
= MAX2(xfb_obj
->Size
[i
] / 4, 1) - 1;
3274 sob
.StreamOutputBufferOffsetAddress
=
3275 instruction_bo(brw_obj
->offset_bo
, i
* sizeof(uint32_t));
3277 if (brw_obj
->zero_offsets
) {
3278 /* Zero out the offset and write that to offset_bo */
3279 sob
.StreamOffset
= 0;
3281 /* Use offset_bo as the "Stream Offset." */
3282 sob
.StreamOffset
= 0xFFFFFFFF;
3289 brw_obj
->zero_offsets
= false;
3294 query_active(struct gl_query_object
*q
)
3296 return q
&& q
->Active
;
3300 genX(upload_3dstate_streamout
)(struct brw_context
*brw
, bool active
,
3301 const struct brw_vue_map
*vue_map
)
3303 struct gl_context
*ctx
= &brw
->ctx
;
3304 /* BRW_NEW_TRANSFORM_FEEDBACK */
3305 struct gl_transform_feedback_object
*xfb_obj
=
3306 ctx
->TransformFeedback
.CurrentObject
;
3308 brw_batch_emit(brw
, GENX(3DSTATE_STREAMOUT
), sos
) {
3310 int urb_entry_read_offset
= 0;
3311 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3312 urb_entry_read_offset
;
3314 sos
.SOFunctionEnable
= true;
3315 sos
.SOStatisticsEnable
= true;
3317 /* BRW_NEW_RASTERIZER_DISCARD */
3318 if (ctx
->RasterDiscard
) {
3319 if (!query_active(ctx
->Query
.PrimitivesGenerated
[0])) {
3320 sos
.RenderingDisable
= true;
3322 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3323 "query active relies on the clipper.");
3328 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
)
3329 sos
.ReorderMode
= TRAILING
;
3332 sos
.SOBufferEnable0
= xfb_obj
->Buffers
[0] != NULL
;
3333 sos
.SOBufferEnable1
= xfb_obj
->Buffers
[1] != NULL
;
3334 sos
.SOBufferEnable2
= xfb_obj
->Buffers
[2] != NULL
;
3335 sos
.SOBufferEnable3
= xfb_obj
->Buffers
[3] != NULL
;
3337 const struct gl_transform_feedback_info
*linked_xfb_info
=
3338 xfb_obj
->program
->sh
.LinkedTransformFeedback
;
3339 /* Set buffer pitches; 0 means unbound. */
3340 if (xfb_obj
->Buffers
[0])
3341 sos
.Buffer0SurfacePitch
= linked_xfb_info
->Buffers
[0].Stride
* 4;
3342 if (xfb_obj
->Buffers
[1])
3343 sos
.Buffer1SurfacePitch
= linked_xfb_info
->Buffers
[1].Stride
* 4;
3344 if (xfb_obj
->Buffers
[2])
3345 sos
.Buffer2SurfacePitch
= linked_xfb_info
->Buffers
[2].Stride
* 4;
3346 if (xfb_obj
->Buffers
[3])
3347 sos
.Buffer3SurfacePitch
= linked_xfb_info
->Buffers
[3].Stride
* 4;
3350 /* We always read the whole vertex. This could be reduced at some
3351 * point by reading less and offsetting the register index in the
3354 sos
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3355 sos
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3356 sos
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3357 sos
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3358 sos
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3359 sos
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3360 sos
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3361 sos
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3367 genX(upload_sol
)(struct brw_context
*brw
)
3369 struct gl_context
*ctx
= &brw
->ctx
;
3370 /* BRW_NEW_TRANSFORM_FEEDBACK */
3371 bool active
= _mesa_is_xfb_active_and_unpaused(ctx
);
3374 genX(upload_3dstate_so_buffers
)(brw
);
3376 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3377 genX(upload_3dstate_so_decl_list
)(brw
, &brw
->vue_map_geom_out
);
3380 /* Finally, set up the SOL stage. This command must always follow updates to
3381 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3382 * MMIO register updates (current performed by the kernel at each batch
3385 genX(upload_3dstate_streamout
)(brw
, active
, &brw
->vue_map_geom_out
);
3388 static const struct brw_tracked_state
genX(sol_state
) = {
3391 .brw
= BRW_NEW_BATCH
|
3393 BRW_NEW_RASTERIZER_DISCARD
|
3394 BRW_NEW_VUE_MAP_GEOM_OUT
|
3395 BRW_NEW_TRANSFORM_FEEDBACK
,
3397 .emit
= genX(upload_sol
),
3401 /* ---------------------------------------------------------------------- */
3405 genX(upload_ps
)(struct brw_context
*brw
)
3407 UNUSED
const struct gl_context
*ctx
= &brw
->ctx
;
3408 UNUSED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3410 /* BRW_NEW_FS_PROG_DATA */
3411 const struct brw_wm_prog_data
*prog_data
=
3412 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3413 const struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
3418 brw_batch_emit(brw
, GENX(3DSTATE_PS
), ps
) {
3419 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3420 * incorrect for subspans where some of the pixels are unlit. We believe
3421 * the bit just didn't take effect in previous generations.
3423 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
3426 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
3428 /* BRW_NEW_FS_PROG_DATA */
3429 ps
.BindingTableEntryCount
= prog_data
->base
.binding_table
.size_bytes
/ 4;
3431 if (prog_data
->base
.use_alt_mode
)
3432 ps
.FloatingPointMode
= Alternate
;
3434 /* Haswell requires the sample mask to be set in this packet as well as
3435 * in 3DSTATE_SAMPLE_MASK; the values should match.
3438 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3440 ps
.SampleMask
= genX(determine_sample_mask(brw
));
3443 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
3444 * it implicitly scales for different GT levels (which have some # of
3447 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
3450 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
3452 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
3454 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
3457 if (prog_data
->base
.nr_params
> 0)
3458 ps
.PushConstantEnable
= true;
3461 /* From the IVB PRM, volume 2 part 1, page 287:
3462 * "This bit is inserted in the PS payload header and made available to
3463 * the DataPort (either via the message header or via header bypass) to
3464 * indicate that oMask data (one or two phases) is included in Render
3465 * Target Write messages. If present, the oMask data is used to mask off
3468 ps
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
3470 /* The hardware wedges if you have this bit set but don't turn on any
3471 * dual source blend factors.
3473 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3475 ps
.DualSourceBlendEnable
= prog_data
->dual_src_blend
&&
3476 (ctx
->Color
.BlendEnabled
& 1) &&
3477 ctx
->Color
.Blend
[0]._UsesDualSrc
;
3479 /* BRW_NEW_FS_PROG_DATA */
3480 ps
.AttributeEnable
= (prog_data
->num_varying_inputs
!= 0);
3483 /* From the documentation for this packet:
3484 * "If the PS kernel does not need the Position XY Offsets to
3485 * compute a Position Value, then this field should be programmed
3486 * to POSOFFSET_NONE."
3488 * "SW Recommendation: If the PS kernel needs the Position Offsets
3489 * to compute a Position XY value, this field should match Position
3490 * ZW Interpolation Mode to ensure a consistent position.xyzw
3493 * We only require XY sample offsets. So, this recommendation doesn't
3494 * look useful at the moment. We might need this in future.
3496 if (prog_data
->uses_pos_offset
)
3497 ps
.PositionXYOffsetSelect
= POSOFFSET_SAMPLE
;
3499 ps
.PositionXYOffsetSelect
= POSOFFSET_NONE
;
3501 ps
.RenderTargetFastClearEnable
= brw
->wm
.fast_clear_op
;
3502 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
3503 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
3504 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3505 prog_data
->base
.dispatch_grf_start_reg
;
3506 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3507 prog_data
->dispatch_grf_start_reg_2
;
3509 ps
.KernelStartPointer0
= stage_state
->prog_offset
;
3510 ps
.KernelStartPointer2
= stage_state
->prog_offset
+
3511 prog_data
->prog_offset_2
;
3513 if (prog_data
->base
.total_scratch
) {
3514 ps
.ScratchSpaceBasePointer
=
3515 render_bo(stage_state
->scratch_bo
,
3516 ffs(stage_state
->per_thread_scratch
) - 11);
3521 static const struct brw_tracked_state
genX(ps_state
) = {
3523 .mesa
= _NEW_MULTISAMPLE
|
3524 (GEN_GEN
< 8 ? _NEW_BUFFERS
|
3527 .brw
= BRW_NEW_BATCH
|
3529 BRW_NEW_FS_PROG_DATA
,
3531 .emit
= genX(upload_ps
),
3535 /* ---------------------------------------------------------------------- */
3539 genX(upload_hs_state
)(struct brw_context
*brw
)
3541 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3542 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3543 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3544 const struct brw_vue_prog_data
*vue_prog_data
=
3545 brw_vue_prog_data(stage_prog_data
);
3547 /* BRW_NEW_TES_PROG_DATA */
3548 struct brw_tcs_prog_data
*tcs_prog_data
=
3549 brw_tcs_prog_data(stage_prog_data
);
3551 if (!tcs_prog_data
) {
3552 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
);
3554 brw_batch_emit(brw
, GENX(3DSTATE_HS
), hs
) {
3555 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
3557 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3558 hs
.IncludeVertexHandles
= true;
3560 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3565 static const struct brw_tracked_state
genX(hs_state
) = {
3568 .brw
= BRW_NEW_BATCH
|
3570 BRW_NEW_TCS_PROG_DATA
|
3571 BRW_NEW_TESS_PROGRAMS
,
3573 .emit
= genX(upload_hs_state
),
3577 genX(upload_ds_state
)(struct brw_context
*brw
)
3579 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3580 const struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3581 struct brw_stage_prog_data
*stage_prog_data
= stage_state
->prog_data
;
3583 /* BRW_NEW_TES_PROG_DATA */
3584 const struct brw_tes_prog_data
*tes_prog_data
=
3585 brw_tes_prog_data(stage_prog_data
);
3586 const struct brw_vue_prog_data
*vue_prog_data
=
3587 brw_vue_prog_data(stage_prog_data
);
3589 if (!tes_prog_data
) {
3590 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
);
3592 brw_batch_emit(brw
, GENX(3DSTATE_DS
), ds
) {
3593 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
3595 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3596 ds
.ComputeWCoordinateEnable
=
3597 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3600 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_SIMD8
)
3601 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3602 ds
.UserClipDistanceCullTestEnableBitmask
=
3603 vue_prog_data
->cull_distance_mask
;
3609 static const struct brw_tracked_state
genX(ds_state
) = {
3612 .brw
= BRW_NEW_BATCH
|
3614 BRW_NEW_TESS_PROGRAMS
|
3615 BRW_NEW_TES_PROG_DATA
,
3617 .emit
= genX(upload_ds_state
),
3620 /* ---------------------------------------------------------------------- */
3623 upload_te_state(struct brw_context
*brw
)
3625 /* BRW_NEW_TESS_PROGRAMS */
3626 bool active
= brw
->tess_eval_program
;
3628 /* BRW_NEW_TES_PROG_DATA */
3629 const struct brw_tes_prog_data
*tes_prog_data
=
3630 brw_tes_prog_data(brw
->tes
.base
.prog_data
);
3633 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
) {
3634 te
.Partitioning
= tes_prog_data
->partitioning
;
3635 te
.OutputTopology
= tes_prog_data
->output_topology
;
3636 te
.TEDomain
= tes_prog_data
->domain
;
3638 te
.MaximumTessellationFactorOdd
= 63.0;
3639 te
.MaximumTessellationFactorNotOdd
= 64.0;
3642 brw_batch_emit(brw
, GENX(3DSTATE_TE
), te
);
3646 static const struct brw_tracked_state
genX(te_state
) = {
3649 .brw
= BRW_NEW_BLORP
|
3651 BRW_NEW_TES_PROG_DATA
|
3652 BRW_NEW_TESS_PROGRAMS
,
3654 .emit
= upload_te_state
,
3657 /* ---------------------------------------------------------------------- */
3660 genX(upload_tes_push_constants
)(struct brw_context
*brw
)
3662 struct brw_stage_state
*stage_state
= &brw
->tes
.base
;
3663 /* BRW_NEW_TESS_PROGRAMS */
3664 const struct brw_program
*tep
= brw_program_const(brw
->tess_eval_program
);
3667 /* BRW_NEW_TES_PROG_DATA */
3668 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
3669 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_EVAL
);
3670 gen6_upload_push_constants(brw
, &tep
->program
, prog_data
, stage_state
);
3673 upload_constant_state(brw
, stage_state
, tep
, MESA_SHADER_TESS_EVAL
);
3676 static const struct brw_tracked_state
genX(tes_push_constants
) = {
3678 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3679 .brw
= BRW_NEW_BATCH
|
3681 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3682 BRW_NEW_TESS_PROGRAMS
|
3683 BRW_NEW_TES_PROG_DATA
,
3685 .emit
= genX(upload_tes_push_constants
),
3689 genX(upload_tcs_push_constants
)(struct brw_context
*brw
)
3691 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
3692 /* BRW_NEW_TESS_PROGRAMS */
3693 const struct brw_program
*tcp
= brw_program_const(brw
->tess_ctrl_program
);
3694 bool active
= brw
->tess_eval_program
;
3697 /* BRW_NEW_TCS_PROG_DATA */
3698 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
3700 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_TESS_CTRL
);
3701 gen6_upload_push_constants(brw
, &tcp
->program
, prog_data
, stage_state
);
3704 upload_constant_state(brw
, stage_state
, active
, MESA_SHADER_TESS_CTRL
);
3707 static const struct brw_tracked_state
genX(tcs_push_constants
) = {
3709 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3710 .brw
= BRW_NEW_BATCH
|
3712 BRW_NEW_DEFAULT_TESS_LEVELS
|
3713 BRW_NEW_PUSH_CONSTANT_ALLOCATION
|
3714 BRW_NEW_TESS_PROGRAMS
|
3715 BRW_NEW_TCS_PROG_DATA
,
3717 .emit
= genX(upload_tcs_push_constants
),
3722 /* ---------------------------------------------------------------------- */
3726 genX(upload_cs_state
)(struct brw_context
*brw
)
3728 if (!brw
->cs
.base
.prog_data
)
3732 uint32_t *desc
= (uint32_t*) brw_state_batch(
3733 brw
, GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t), 64,
3736 struct brw_stage_state
*stage_state
= &brw
->cs
.base
;
3737 struct brw_stage_prog_data
*prog_data
= stage_state
->prog_data
;
3738 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3739 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3741 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
3742 brw_emit_buffer_surface_state(
3743 brw
, &stage_state
->surf_offset
[
3744 prog_data
->binding_table
.shader_time_start
],
3745 brw
->shader_time
.bo
, 0, ISL_FORMAT_RAW
,
3746 brw
->shader_time
.bo
->size
, 1, true);
3749 uint32_t *bind
= brw_state_batch(brw
, prog_data
->binding_table
.size_bytes
,
3750 32, &stage_state
->bind_bo_offset
);
3752 brw_batch_emit(brw
, GENX(MEDIA_VFE_STATE
), vfe
) {
3753 if (prog_data
->total_scratch
) {
3757 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
3758 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
3760 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 11;
3761 } else if (GEN_IS_HASWELL
) {
3762 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
3763 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
3765 bo_offset
= ffs(stage_state
->per_thread_scratch
) - 12;
3767 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
3768 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
3770 bo_offset
= stage_state
->per_thread_scratch
/ 1024 - 1;
3772 vfe
.ScratchSpaceBasePointer
=
3773 render_bo(stage_state
->scratch_bo
, bo_offset
);
3776 const uint32_t subslices
= MAX2(brw
->screen
->subslice_total
, 1);
3777 vfe
.MaximumNumberofThreads
= devinfo
->max_cs_threads
* subslices
- 1;
3778 vfe
.NumberofURBEntries
= GEN_GEN
>= 8 ? 2 : 0;
3779 vfe
.ResetGatewayTimer
=
3780 Resettingrelativetimerandlatchingtheglobaltimestamp
;
3782 vfe
.BypassGatewayControl
= BypassingOpenGatewayCloseGatewayprotocol
;
3788 /* We are uploading duplicated copies of push constant uniforms for each
3789 * thread. Although the local id data needs to vary per thread, it won't
3790 * change for other uniform data. Unfortunately this duplication is
3791 * required for gen7. As of Haswell, this duplication can be avoided,
3792 * but this older mechanism with duplicated data continues to work.
3794 * FINISHME: As of Haswell, we could make use of the
3795 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
3796 * field to only store one copy of uniform data.
3798 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
3799 * which is described in the GPGPU_WALKER command and in the Broadwell
3800 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
3801 * Operations => GPGPU Mode => Indirect Payload Storage.
3803 * Note: The constant data is built in brw_upload_cs_push_constants
3806 vfe
.URBEntryAllocationSize
= GEN_GEN
>= 8 ? 2 : 0;
3808 const uint32_t vfe_curbe_allocation
=
3809 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
3810 cs_prog_data
->push
.cross_thread
.regs
, 2);
3811 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
3814 if (cs_prog_data
->push
.total
.size
> 0) {
3815 brw_batch_emit(brw
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3816 curbe
.CURBETotalDataLength
=
3817 ALIGN(cs_prog_data
->push
.total
.size
, 64);
3818 curbe
.CURBEDataStartAddress
= stage_state
->push_const_offset
;
3822 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
3823 memcpy(bind
, stage_state
->surf_offset
,
3824 prog_data
->binding_table
.size_bytes
);
3825 const struct GENX(INTERFACE_DESCRIPTOR_DATA
) idd
= {
3826 .KernelStartPointer
= brw
->cs
.base
.prog_offset
,
3827 .SamplerStatePointer
= stage_state
->sampler_offset
,
3828 .SamplerCount
= DIV_ROUND_UP(stage_state
->sampler_count
, 4) >> 2,
3829 .BindingTablePointer
= stage_state
->bind_bo_offset
,
3830 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
3831 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
3832 .SharedLocalMemorySize
= encode_slm_size(devinfo
->gen
,
3833 prog_data
->total_shared
),
3834 .BarrierEnable
= cs_prog_data
->uses_barrier
,
3835 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3836 .CrossThreadConstantDataReadLength
=
3837 cs_prog_data
->push
.cross_thread
.regs
,
3841 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(brw
, desc
, &idd
);
3843 brw_batch_emit(brw
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
3844 load
.InterfaceDescriptorTotalLength
=
3845 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3846 load
.InterfaceDescriptorDataStartAddress
= offset
;
3850 static const struct brw_tracked_state
genX(cs_state
) = {
3852 .mesa
= _NEW_PROGRAM_CONSTANTS
,
3853 .brw
= BRW_NEW_BATCH
|
3855 BRW_NEW_CS_PROG_DATA
|
3856 BRW_NEW_SAMPLER_STATE_TABLE
|
3859 .emit
= genX(upload_cs_state
)
3864 /* ---------------------------------------------------------------------- */
3868 genX(upload_raster
)(struct brw_context
*brw
)
3870 struct gl_context
*ctx
= &brw
->ctx
;
3873 bool render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3876 struct gl_polygon_attrib
*polygon
= &ctx
->Polygon
;
3879 struct gl_point_attrib
*point
= &ctx
->Point
;
3881 brw_batch_emit(brw
, GENX(3DSTATE_RASTER
), raster
) {
3882 if (brw
->polygon_front_bit
== render_to_fbo
)
3883 raster
.FrontWinding
= CounterClockwise
;
3885 if (polygon
->CullFlag
) {
3886 switch (polygon
->CullFaceMode
) {
3888 raster
.CullMode
= CULLMODE_FRONT
;
3891 raster
.CullMode
= CULLMODE_BACK
;
3893 case GL_FRONT_AND_BACK
:
3894 raster
.CullMode
= CULLMODE_BOTH
;
3897 unreachable("not reached");
3900 raster
.CullMode
= CULLMODE_NONE
;
3903 point
->SmoothFlag
= raster
.SmoothPointEnable
;
3905 raster
.DXMultisampleRasterizationEnable
=
3906 _mesa_is_multisample_enabled(ctx
);
3908 raster
.GlobalDepthOffsetEnableSolid
= polygon
->OffsetFill
;
3909 raster
.GlobalDepthOffsetEnableWireframe
= polygon
->OffsetLine
;
3910 raster
.GlobalDepthOffsetEnablePoint
= polygon
->OffsetPoint
;
3912 switch (polygon
->FrontMode
) {
3914 raster
.FrontFaceFillMode
= FILL_MODE_SOLID
;
3917 raster
.FrontFaceFillMode
= FILL_MODE_WIREFRAME
;
3920 raster
.FrontFaceFillMode
= FILL_MODE_POINT
;
3923 unreachable("not reached");
3926 switch (polygon
->BackMode
) {
3928 raster
.BackFaceFillMode
= FILL_MODE_SOLID
;
3931 raster
.BackFaceFillMode
= FILL_MODE_WIREFRAME
;
3934 raster
.BackFaceFillMode
= FILL_MODE_POINT
;
3937 unreachable("not reached");
3941 raster
.AntialiasingEnable
= ctx
->Line
.SmoothFlag
;
3944 raster
.ScissorRectangleEnable
= ctx
->Scissor
.EnableFlags
;
3946 /* _NEW_TRANSFORM */
3947 if (!ctx
->Transform
.DepthClamp
) {
3949 raster
.ViewportZFarClipTestEnable
= true;
3950 raster
.ViewportZNearClipTestEnable
= true;
3952 raster
.ViewportZClipTestEnable
= true;
3956 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
3958 raster
.ConservativeRasterizationEnable
=
3959 ctx
->IntelConservativeRasterization
;
3962 raster
.GlobalDepthOffsetClamp
= polygon
->OffsetClamp
;
3963 raster
.GlobalDepthOffsetScale
= polygon
->OffsetFactor
;
3965 raster
.GlobalDepthOffsetConstant
= polygon
->OffsetUnits
* 2;
3969 static const struct brw_tracked_state
genX(raster_state
) = {
3971 .mesa
= _NEW_BUFFERS
|
3978 .brw
= BRW_NEW_BLORP
|
3980 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
3982 .emit
= genX(upload_raster
),
3986 /* ---------------------------------------------------------------------- */
3990 genX(upload_ps_extra
)(struct brw_context
*brw
)
3992 UNUSED
struct gl_context
*ctx
= &brw
->ctx
;
3994 const struct brw_wm_prog_data
*prog_data
=
3995 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
3997 brw_batch_emit(brw
, GENX(3DSTATE_PS_EXTRA
), psx
) {
3998 psx
.PixelShaderValid
= true;
3999 psx
.PixelShaderComputedDepthMode
= prog_data
->computed_depth_mode
;
4000 psx
.PixelShaderKillsPixel
= prog_data
->uses_kill
;
4001 psx
.AttributeEnable
= prog_data
->num_varying_inputs
!= 0;
4002 psx
.PixelShaderUsesSourceDepth
= prog_data
->uses_src_depth
;
4003 psx
.PixelShaderUsesSourceW
= prog_data
->uses_src_w
;
4004 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
4006 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4007 if (prog_data
->uses_sample_mask
) {
4009 if (prog_data
->post_depth_coverage
)
4010 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4011 else if (prog_data
->inner_coverage
&& ctx
->IntelConservativeRasterization
)
4012 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4014 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4016 psx
.PixelShaderUsesInputCoverageMask
= true;
4020 psx
.oMaskPresenttoRenderTarget
= prog_data
->uses_omask
;
4022 psx
.PixelShaderPullsBary
= prog_data
->pulls_bary
;
4023 psx
.PixelShaderComputesStencil
= prog_data
->computed_stencil
;
4026 /* The stricter cross-primitive coherency guarantees that the hardware
4027 * gives us with the "Accesses UAV" bit set for at least one shader stage
4028 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4029 * are redundant within the current image, atomic counter and SSBO GL
4030 * APIs, which all have very loose ordering and coherency requirements
4031 * and generally rely on the application to insert explicit barriers when
4032 * a shader invocation is expected to see the memory writes performed by
4033 * the invocations of some previous primitive. Regardless of the value
4034 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4035 * cause an in most cases useless DC flush when the lowermost stage with
4036 * the bit set finishes execution.
4038 * It would be nice to disable it, but in some cases we can't because on
4039 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4040 * signal (which could be set independently from the coherency mechanism
4041 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4042 * determine whether the hardware skips execution of the fragment shader
4043 * or not via the ThreadDispatchEnable signal. However if we know that
4044 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4045 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4046 * difference so we may just disable it here.
4048 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4049 * take into account KillPixels when no depth or stencil writes are
4050 * enabled. In order for occlusion queries to work correctly with no
4051 * attachments, we need to force-enable here.
4053 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4056 if ((prog_data
->has_side_effects
|| prog_data
->uses_kill
) &&
4057 !brw_color_buffer_write_enabled(brw
))
4058 psx
.PixelShaderHasUAV
= true;
4062 const struct brw_tracked_state
genX(ps_extra
) = {
4064 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
4065 .brw
= BRW_NEW_BLORP
|
4067 BRW_NEW_FRAGMENT_PROGRAM
|
4068 BRW_NEW_FS_PROG_DATA
|
4069 BRW_NEW_CONSERVATIVE_RASTERIZATION
,
4071 .emit
= genX(upload_ps_extra
),
4075 /* ---------------------------------------------------------------------- */
4079 genX(upload_ps_blend
)(struct brw_context
*brw
)
4081 struct gl_context
*ctx
= &brw
->ctx
;
4084 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
4085 const bool buffer0_is_integer
= ctx
->DrawBuffer
->_IntegerBuffers
& 0x1;
4088 struct gl_colorbuffer_attrib
*color
= &ctx
->Color
;
4090 brw_batch_emit(brw
, GENX(3DSTATE_PS_BLEND
), pb
) {
4091 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4092 pb
.HasWriteableRT
= brw_color_buffer_write_enabled(brw
);
4094 bool alpha_to_one
= false;
4096 if (!buffer0_is_integer
) {
4097 /* _NEW_MULTISAMPLE */
4099 if (_mesa_is_multisample_enabled(ctx
)) {
4100 pb
.AlphaToCoverageEnable
= ctx
->Multisample
.SampleAlphaToCoverage
;
4101 alpha_to_one
= ctx
->Multisample
.SampleAlphaToOne
;
4104 pb
.AlphaTestEnable
= color
->AlphaEnabled
;
4107 /* Used for implementing the following bit of GL_EXT_texture_integer:
4108 * "Per-fragment operations that require floating-point color
4109 * components, including multisample alpha operations, alpha test,
4110 * blending, and dithering, have no effect when the corresponding
4111 * colors are written to an integer color buffer."
4113 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4114 * "If drawbuffer zero is not NONE and the buffer it references has an
4115 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4116 * operations are skipped."
4118 if (rb
&& !buffer0_is_integer
&& (color
->BlendEnabled
& 1)) {
4119 GLenum eqRGB
= color
->Blend
[0].EquationRGB
;
4120 GLenum eqA
= color
->Blend
[0].EquationA
;
4121 GLenum srcRGB
= color
->Blend
[0].SrcRGB
;
4122 GLenum dstRGB
= color
->Blend
[0].DstRGB
;
4123 GLenum srcA
= color
->Blend
[0].SrcA
;
4124 GLenum dstA
= color
->Blend
[0].DstA
;
4126 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
)
4127 srcRGB
= dstRGB
= GL_ONE
;
4129 if (eqA
== GL_MIN
|| eqA
== GL_MAX
)
4130 srcA
= dstA
= GL_ONE
;
4132 /* Due to hardware limitations, the destination may have information
4133 * in an alpha channel even when the format specifies no alpha
4134 * channel. In order to avoid getting any incorrect blending due to
4135 * that alpha channel, coerce the blend factors to values that will
4136 * not read the alpha channel, but will instead use the correct
4137 * implicit value for alpha.
4139 if (!_mesa_base_format_has_channel(rb
->_BaseFormat
,
4140 GL_TEXTURE_ALPHA_TYPE
)) {
4141 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
4142 srcA
= brw_fix_xRGB_alpha(srcA
);
4143 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
4144 dstA
= brw_fix_xRGB_alpha(dstA
);
4147 /* Alpha to One doesn't work with Dual Color Blending. Override
4148 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4150 if (alpha_to_one
&& color
->Blend
[0]._UsesDualSrc
) {
4151 srcRGB
= fix_dual_blend_alpha_to_one(srcRGB
);
4152 srcA
= fix_dual_blend_alpha_to_one(srcA
);
4153 dstRGB
= fix_dual_blend_alpha_to_one(dstRGB
);
4154 dstA
= fix_dual_blend_alpha_to_one(dstA
);
4157 pb
.ColorBufferBlendEnable
= true;
4158 pb
.SourceAlphaBlendFactor
= brw_translate_blend_factor(srcA
);
4159 pb
.DestinationAlphaBlendFactor
= brw_translate_blend_factor(dstA
);
4160 pb
.SourceBlendFactor
= brw_translate_blend_factor(srcRGB
);
4161 pb
.DestinationBlendFactor
= brw_translate_blend_factor(dstRGB
);
4163 pb
.IndependentAlphaBlendEnable
=
4164 srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
;
4169 static const struct brw_tracked_state
genX(ps_blend
) = {
4171 .mesa
= _NEW_BUFFERS
|
4174 .brw
= BRW_NEW_BLORP
|
4176 BRW_NEW_FRAGMENT_PROGRAM
,
4178 .emit
= genX(upload_ps_blend
)
4182 /* ---------------------------------------------------------------------- */
4186 genX(emit_vf_topology
)(struct brw_context
*brw
)
4188 brw_batch_emit(brw
, GENX(3DSTATE_VF_TOPOLOGY
), vftopo
) {
4189 vftopo
.PrimitiveTopologyType
= brw
->primitive
;
4193 static const struct brw_tracked_state
genX(vf_topology
) = {
4196 .brw
= BRW_NEW_BLORP
|
4199 .emit
= genX(emit_vf_topology
),
4203 /* ---------------------------------------------------------------------- */
4207 genX(emit_mi_report_perf_count
)(struct brw_context
*brw
,
4209 uint32_t offset_in_bytes
,
4212 brw_batch_emit(brw
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
4213 mi_rpc
.MemoryAddress
= instruction_bo(bo
, offset_in_bytes
);
4214 mi_rpc
.ReportID
= report_id
;
4219 /* ---------------------------------------------------------------------- */
4222 genX(init_atoms
)(struct brw_context
*brw
)
4225 static const struct brw_tracked_state
*render_atoms
[] =
4227 /* Once all the programs are done, we know how large urb entry
4228 * sizes need to be and can decide if we need to change the urb
4232 &brw_recalculate_urb_fence
,
4237 /* Surface state setup. Must come before the VS/WM unit. The binding
4238 * table upload must be last.
4240 &brw_vs_pull_constants
,
4241 &brw_wm_pull_constants
,
4242 &brw_renderbuffer_surfaces
,
4243 &brw_renderbuffer_read_surfaces
,
4244 &brw_texture_surfaces
,
4245 &brw_vs_binding_table
,
4246 &brw_wm_binding_table
,
4251 /* These set up state for brw_psp_urb_cbs */
4253 &genX(sf_clip_viewport
),
4255 &genX(vs_state
), /* always required, enabled or not */
4261 &brw_invariant_state
,
4263 &brw_binding_table_pointers
,
4264 &brw_blend_constant_color
,
4268 &genX(polygon_stipple
),
4269 &genX(polygon_stipple_offset
),
4271 &genX(line_stipple
),
4275 &genX(drawing_rect
),
4276 &brw_indices
, /* must come before brw_vertices */
4277 &genX(index_buffer
),
4280 &brw_constant_buffer
4283 static const struct brw_tracked_state
*render_atoms
[] =
4285 &genX(sf_clip_viewport
),
4287 /* Command packets: */
4292 &genX(blend_state
), /* must do before cc unit */
4293 &genX(color_calc_state
), /* must do before cc unit */
4294 &genX(depth_stencil_state
), /* must do before cc unit */
4296 &genX(vs_push_constants
), /* Before vs_state */
4297 &genX(gs_push_constants
), /* Before gs_state */
4298 &genX(wm_push_constants
), /* Before wm_state */
4300 /* Surface state setup. Must come before the VS/WM unit. The binding
4301 * table upload must be last.
4303 &brw_vs_pull_constants
,
4304 &brw_vs_ubo_surfaces
,
4305 &brw_gs_pull_constants
,
4306 &brw_gs_ubo_surfaces
,
4307 &brw_wm_pull_constants
,
4308 &brw_wm_ubo_surfaces
,
4309 &gen6_renderbuffer_surfaces
,
4310 &brw_renderbuffer_read_surfaces
,
4311 &brw_texture_surfaces
,
4313 &brw_vs_binding_table
,
4314 &gen6_gs_binding_table
,
4315 &brw_wm_binding_table
,
4320 &gen6_sampler_state
,
4321 &genX(multisample_state
),
4329 &genX(scissor_state
),
4331 &gen6_binding_table_pointers
,
4335 &genX(polygon_stipple
),
4336 &genX(polygon_stipple_offset
),
4338 &genX(line_stipple
),
4340 &genX(drawing_rect
),
4342 &brw_indices
, /* must come before brw_vertices */
4343 &genX(index_buffer
),
4347 static const struct brw_tracked_state
*render_atoms
[] =
4349 /* Command packets: */
4352 &genX(sf_clip_viewport
),
4355 &gen7_push_constant_space
,
4357 &genX(blend_state
), /* must do before cc unit */
4358 &genX(color_calc_state
), /* must do before cc unit */
4359 &genX(depth_stencil_state
), /* must do before cc unit */
4361 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4362 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4363 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4364 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4365 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4367 &genX(vs_push_constants
), /* Before vs_state */
4368 &genX(tcs_push_constants
),
4369 &genX(tes_push_constants
),
4370 &genX(gs_push_constants
), /* Before gs_state */
4371 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4373 /* Surface state setup. Must come before the VS/WM unit. The binding
4374 * table upload must be last.
4376 &brw_vs_pull_constants
,
4377 &brw_vs_ubo_surfaces
,
4378 &brw_vs_abo_surfaces
,
4379 &brw_tcs_pull_constants
,
4380 &brw_tcs_ubo_surfaces
,
4381 &brw_tcs_abo_surfaces
,
4382 &brw_tes_pull_constants
,
4383 &brw_tes_ubo_surfaces
,
4384 &brw_tes_abo_surfaces
,
4385 &brw_gs_pull_constants
,
4386 &brw_gs_ubo_surfaces
,
4387 &brw_gs_abo_surfaces
,
4388 &brw_wm_pull_constants
,
4389 &brw_wm_ubo_surfaces
,
4390 &brw_wm_abo_surfaces
,
4391 &gen6_renderbuffer_surfaces
,
4392 &brw_renderbuffer_read_surfaces
,
4393 &brw_texture_surfaces
,
4394 &brw_vs_binding_table
,
4395 &brw_tcs_binding_table
,
4396 &brw_tes_binding_table
,
4397 &brw_gs_binding_table
,
4398 &brw_wm_binding_table
,
4405 &genX(multisample_state
),
4419 &genX(scissor_state
),
4423 &genX(polygon_stipple
),
4424 &genX(polygon_stipple_offset
),
4426 &genX(line_stipple
),
4428 &genX(drawing_rect
),
4430 &brw_indices
, /* must come before brw_vertices */
4431 &genX(index_buffer
),
4439 static const struct brw_tracked_state
*render_atoms
[] =
4442 &genX(sf_clip_viewport
),
4445 &gen7_push_constant_space
,
4448 &genX(color_calc_state
),
4450 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
4451 &brw_tcs_image_surfaces
, /* Before tcs push/pull constants and binding table */
4452 &brw_tes_image_surfaces
, /* Before tes push/pull constants and binding table */
4453 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
4454 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
4456 &genX(vs_push_constants
), /* Before vs_state */
4457 &genX(tcs_push_constants
),
4458 &genX(tes_push_constants
),
4459 &genX(gs_push_constants
), /* Before gs_state */
4460 &genX(wm_push_constants
), /* Before wm_surfaces and constant_buffer */
4462 /* Surface state setup. Must come before the VS/WM unit. The binding
4463 * table upload must be last.
4465 &brw_vs_pull_constants
,
4466 &brw_vs_ubo_surfaces
,
4467 &brw_vs_abo_surfaces
,
4468 &brw_tcs_pull_constants
,
4469 &brw_tcs_ubo_surfaces
,
4470 &brw_tcs_abo_surfaces
,
4471 &brw_tes_pull_constants
,
4472 &brw_tes_ubo_surfaces
,
4473 &brw_tes_abo_surfaces
,
4474 &brw_gs_pull_constants
,
4475 &brw_gs_ubo_surfaces
,
4476 &brw_gs_abo_surfaces
,
4477 &brw_wm_pull_constants
,
4478 &brw_wm_ubo_surfaces
,
4479 &brw_wm_abo_surfaces
,
4480 &gen6_renderbuffer_surfaces
,
4481 &brw_renderbuffer_read_surfaces
,
4482 &brw_texture_surfaces
,
4483 &brw_vs_binding_table
,
4484 &brw_tcs_binding_table
,
4485 &brw_tes_binding_table
,
4486 &brw_gs_binding_table
,
4487 &brw_wm_binding_table
,
4494 &genX(multisample_state
),
4503 &genX(raster_state
),
4509 &genX(depth_stencil_state
),
4512 &genX(scissor_state
),
4516 &genX(polygon_stipple
),
4517 &genX(polygon_stipple_offset
),
4519 &genX(line_stipple
),
4521 &genX(drawing_rect
),
4526 &genX(index_buffer
),
4534 STATIC_ASSERT(ARRAY_SIZE(render_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
4535 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
4536 render_atoms
, ARRAY_SIZE(render_atoms
));
4539 static const struct brw_tracked_state
*compute_atoms
[] =
4542 &brw_cs_image_surfaces
,
4543 &gen7_cs_push_constants
,
4544 &brw_cs_pull_constants
,
4545 &brw_cs_ubo_surfaces
,
4546 &brw_cs_abo_surfaces
,
4547 &brw_cs_texture_surfaces
,
4548 &brw_cs_work_groups_surface
,
4553 STATIC_ASSERT(ARRAY_SIZE(compute_atoms
) <= ARRAY_SIZE(brw
->compute_atoms
));
4554 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
4555 compute_atoms
, ARRAY_SIZE(compute_atoms
));
4557 brw
->vtbl
.emit_mi_report_perf_count
= genX(emit_mi_report_perf_count
);