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25 /** @file hsw_queryobj.c
27 * Support for query buffer objects (GL_ARB_query_buffer_object) on Haswell+.
29 #include "main/imports.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "intel_batchbuffer.h"
34 #include "intel_buffer_objects.h"
40 mult_gpr0_by_80(struct brw_context
*brw
)
42 static const uint32_t maths
[] = {
43 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
44 MI_MATH_ALU2(LOAD
, SRCB
, R0
),
46 MI_MATH_ALU2(STORE
, R1
, ACCU
),
47 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
48 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
50 MI_MATH_ALU2(STORE
, R1
, ACCU
),
51 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
52 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
54 MI_MATH_ALU2(STORE
, R1
, ACCU
),
55 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
56 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
58 /* GPR1 = 16 * GPR0 */
59 MI_MATH_ALU2(STORE
, R1
, ACCU
),
60 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
61 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
63 MI_MATH_ALU2(STORE
, R2
, ACCU
),
64 MI_MATH_ALU2(LOAD
, SRCA
, R2
),
65 MI_MATH_ALU2(LOAD
, SRCB
, R2
),
67 /* GPR2 = 64 * GPR0 */
68 MI_MATH_ALU2(STORE
, R2
, ACCU
),
69 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
70 MI_MATH_ALU2(LOAD
, SRCB
, R2
),
72 /* GPR0 = 80 * GPR0 */
73 MI_MATH_ALU2(STORE
, R0
, ACCU
),
76 BEGIN_BATCH(1 + ARRAY_SIZE(maths
));
77 OUT_BATCH(HSW_MI_MATH
| (1 + ARRAY_SIZE(maths
) - 2));
79 for (int m
= 0; m
< ARRAY_SIZE(maths
); m
++)
86 * GPR0 = GPR0 & ((1ull << n) - 1);
89 keep_gpr0_lower_n_bits(struct brw_context
*brw
, uint32_t n
)
91 static const uint32_t maths
[] = {
92 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
93 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
95 MI_MATH_ALU2(STORE
, R0
, ACCU
),
99 brw_load_register_imm64(brw
, HSW_CS_GPR(1), (1ull << n
) - 1);
101 BEGIN_BATCH(1 + ARRAY_SIZE(maths
));
102 OUT_BATCH(HSW_MI_MATH
| (1 + ARRAY_SIZE(maths
) - 2));
104 for (int m
= 0; m
< ARRAY_SIZE(maths
); m
++)
114 shl_gpr0_by_30_bits(struct brw_context
*brw
)
116 /* First we mask 34 bits of GPR0 to prevent overflow */
117 keep_gpr0_lower_n_bits(brw
, 34);
119 static const uint32_t shl_maths
[] = {
120 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
121 MI_MATH_ALU2(LOAD
, SRCB
, R0
),
123 MI_MATH_ALU2(STORE
, R0
, ACCU
),
126 const uint32_t outer_count
= 5;
127 const uint32_t inner_count
= 6;
128 STATIC_ASSERT(outer_count
* inner_count
== 30);
129 const uint32_t cmd_len
= 1 + inner_count
* ARRAY_SIZE(shl_maths
);
130 const uint32_t batch_len
= cmd_len
* outer_count
;
132 BEGIN_BATCH(batch_len
);
134 /* We'll emit 5 commands, each shifting GPR0 left by 6 bits, for a total of
137 for (int o
= 0; o
< outer_count
; o
++) {
138 /* Submit one MI_MATH to shift left by 6 bits */
139 OUT_BATCH(HSW_MI_MATH
| (cmd_len
- 2));
140 for (int i
= 0; i
< inner_count
; i
++)
141 for (int m
= 0; m
< ARRAY_SIZE(shl_maths
); m
++)
142 OUT_BATCH(shl_maths
[m
]);
151 * Note that the upper 30 bits of GPR0 are lost!
154 shr_gpr0_by_2_bits(struct brw_context
*brw
)
156 shl_gpr0_by_30_bits(brw
);
157 brw_load_register_reg(brw
, HSW_CS_GPR(0) + 4, HSW_CS_GPR(0));
158 brw_load_register_imm32(brw
, HSW_CS_GPR(0) + 4, 0);
162 * GPR0 = (GPR0 == 0) ? 0 : 1;
165 gpr0_to_bool(struct brw_context
*brw
)
167 static const uint32_t maths
[] = {
168 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
169 MI_MATH_ALU1(LOAD0
, SRCB
),
171 MI_MATH_ALU2(STOREINV
, R0
, ZF
),
172 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
173 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
175 MI_MATH_ALU2(STORE
, R0
, ACCU
),
178 brw_load_register_imm64(brw
, HSW_CS_GPR(1), 1ull);
180 BEGIN_BATCH(1 + ARRAY_SIZE(maths
));
181 OUT_BATCH(HSW_MI_MATH
| (1 + ARRAY_SIZE(maths
) - 2));
183 for (int m
= 0; m
< ARRAY_SIZE(maths
); m
++)
190 load_overflow_data_to_cs_gprs(struct brw_context
*brw
,
191 struct brw_query_object
*query
,
194 int offset
= idx
* sizeof(uint64_t) * 4;
196 brw_load_register_mem64(brw
, HSW_CS_GPR(1), query
->bo
, offset
);
198 offset
+= sizeof(uint64_t);
199 brw_load_register_mem64(brw
, HSW_CS_GPR(2), query
->bo
, offset
);
201 offset
+= sizeof(uint64_t);
202 brw_load_register_mem64(brw
, HSW_CS_GPR(3), query
->bo
, offset
);
204 offset
+= sizeof(uint64_t);
205 brw_load_register_mem64(brw
, HSW_CS_GPR(4), query
->bo
, offset
);
215 calc_overflow_for_stream(struct brw_context
*brw
)
217 static const uint32_t maths
[] = {
218 MI_MATH_ALU2(LOAD
, SRCA
, R4
),
219 MI_MATH_ALU2(LOAD
, SRCB
, R3
),
221 MI_MATH_ALU2(STORE
, R3
, ACCU
),
222 MI_MATH_ALU2(LOAD
, SRCA
, R2
),
223 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
225 MI_MATH_ALU2(STORE
, R1
, ACCU
),
226 MI_MATH_ALU2(LOAD
, SRCA
, R3
),
227 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
229 MI_MATH_ALU2(STORE
, R1
, ACCU
),
230 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
231 MI_MATH_ALU2(LOAD
, SRCB
, R0
),
233 MI_MATH_ALU2(STORE
, R0
, ACCU
),
236 BEGIN_BATCH(1 + ARRAY_SIZE(maths
));
237 OUT_BATCH(HSW_MI_MATH
| (1 + ARRAY_SIZE(maths
) - 2));
239 for (int m
= 0; m
< ARRAY_SIZE(maths
); m
++)
246 calc_overflow_to_gpr0(struct brw_context
*brw
, struct brw_query_object
*query
,
249 brw_load_register_imm64(brw
, HSW_CS_GPR(0), 0ull);
251 for (int i
= 0; i
< count
; i
++) {
252 load_overflow_data_to_cs_gprs(brw
, query
, i
);
253 calc_overflow_for_stream(brw
);
258 * Take a query and calculate whether there was overflow during transform
259 * feedback. Store the result in the gpr0 register.
262 hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
263 struct brw_query_object
*query
,
266 calc_overflow_to_gpr0(brw
, query
, count
);
271 hsw_result_to_gpr0(struct gl_context
*ctx
, struct brw_query_object
*query
,
272 struct gl_buffer_object
*buf
, intptr_t offset
,
273 GLenum pname
, GLenum ptype
)
275 struct brw_context
*brw
= brw_context(ctx
);
276 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
279 assert(pname
!= GL_QUERY_TARGET
);
281 if (pname
== GL_QUERY_RESULT_AVAILABLE
) {
282 /* The query result availability is stored at offset 0 of the buffer. */
283 brw_load_register_mem64(brw
,
286 2 * sizeof(uint64_t));
290 if (pname
== GL_QUERY_RESULT
) {
291 /* Since GL_QUERY_RESULT_NO_WAIT wasn't used, they want us to stall to
292 * make sure the query is available.
294 brw_emit_pipe_control_flush(brw
,
295 PIPE_CONTROL_CS_STALL
|
296 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
299 if (query
->Base
.Target
== GL_TIMESTAMP
) {
300 brw_load_register_mem64(brw
,
303 0 * sizeof(uint64_t));
304 } else if (query
->Base
.Target
== GL_TRANSFORM_FEEDBACK_STREAM_OVERFLOW_ARB
305 || query
->Base
.Target
== GL_TRANSFORM_FEEDBACK_OVERFLOW_ARB
) {
306 /* Don't do anything in advance here, since the math for this is a little
310 brw_load_register_mem64(brw
,
313 0 * sizeof(uint64_t));
314 brw_load_register_mem64(brw
,
317 1 * sizeof(uint64_t));
320 OUT_BATCH(HSW_MI_MATH
| (5 - 2));
322 OUT_BATCH(MI_MATH_ALU2(LOAD
, SRCA
, R2
));
323 OUT_BATCH(MI_MATH_ALU2(LOAD
, SRCB
, R1
));
324 OUT_BATCH(MI_MATH_ALU0(SUB
));
325 OUT_BATCH(MI_MATH_ALU2(STORE
, R0
, ACCU
));
330 switch (query
->Base
.Target
) {
331 case GL_FRAGMENT_SHADER_INVOCATIONS_ARB
:
332 /* Implement the "WaDividePSInvocationCountBy4:HSW,BDW" workaround:
333 * "Invocation counter is 4 times actual. WA: SW to divide HW reported
334 * PS Invocations value by 4."
336 * Prior to Haswell, invocation count was counted by the WM, and it
337 * buggily counted invocations in units of subspans (2x2 unit). To get the
338 * correct value, the CS multiplied this by 4. With HSW the logic moved,
339 * and correctly emitted the number of pixel shader invocations, but,
340 * whomever forgot to undo the multiply by 4.
342 if (devinfo
->gen
== 8 || devinfo
->is_haswell
)
343 shr_gpr0_by_2_bits(brw
);
345 case GL_TIME_ELAPSED
:
347 mult_gpr0_by_80(brw
);
348 if (query
->Base
.Target
== GL_TIMESTAMP
) {
349 keep_gpr0_lower_n_bits(brw
, 36);
352 case GL_ANY_SAMPLES_PASSED
:
353 case GL_ANY_SAMPLES_PASSED_CONSERVATIVE
:
356 case GL_TRANSFORM_FEEDBACK_STREAM_OVERFLOW_ARB
:
357 hsw_overflow_result_to_gpr0(brw
, query
, 1);
359 case GL_TRANSFORM_FEEDBACK_OVERFLOW_ARB
:
360 hsw_overflow_result_to_gpr0(brw
, query
, MAX_VERTEX_STREAMS
);
366 * Store immediate data into the user buffer using the requested size.
369 store_query_result_imm(struct brw_context
*brw
, struct brw_bo
*bo
,
370 uint32_t offset
, GLenum ptype
, uint64_t imm
)
374 case GL_UNSIGNED_INT
:
375 brw_store_data_imm32(brw
, bo
, offset
, imm
);
378 case GL_UNSIGNED_INT64_ARB
:
379 brw_store_data_imm64(brw
, bo
, offset
, imm
);
382 unreachable("Unexpected result type");
387 set_predicate(struct brw_context
*brw
, struct brw_bo
*query_bo
)
389 brw_load_register_imm64(brw
, MI_PREDICATE_SRC1
, 0ull);
391 /* Load query availability into SRC0 */
392 brw_load_register_mem64(brw
, MI_PREDICATE_SRC0
, query_bo
,
393 2 * sizeof(uint64_t));
395 /* predicate = !(query_availability == 0); */
397 OUT_BATCH(GEN7_MI_PREDICATE
|
398 MI_PREDICATE_LOADOP_LOADINV
|
399 MI_PREDICATE_COMBINEOP_SET
|
400 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
405 * Store data from the register into the user buffer using the requested size.
406 * The write also enables the predication to prevent writing the result if the
407 * query has not finished yet.
410 store_query_result_reg(struct brw_context
*brw
, struct brw_bo
*bo
,
411 uint32_t offset
, GLenum ptype
, uint32_t reg
,
412 const bool pipelined
)
414 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
415 uint32_t cmd_size
= devinfo
->gen
>= 8 ? 4 : 3;
416 uint32_t dwords
= (ptype
== GL_INT
|| ptype
== GL_UNSIGNED_INT
) ? 1 : 2;
417 assert(devinfo
->gen
>= 6);
419 BEGIN_BATCH(dwords
* cmd_size
);
420 for (int i
= 0; i
< dwords
; i
++) {
421 OUT_BATCH(MI_STORE_REGISTER_MEM
|
422 (pipelined
? MI_STORE_REGISTER_MEM_PREDICATE
: 0) |
424 OUT_BATCH(reg
+ 4 * i
);
425 if (devinfo
->gen
>= 8) {
426 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ 4 * i
);
428 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ 4 * i
);
435 hsw_store_query_result(struct gl_context
*ctx
, struct gl_query_object
*q
,
436 struct gl_buffer_object
*buf
, intptr_t offset
,
437 GLenum pname
, GLenum ptype
)
439 struct brw_context
*brw
= brw_context(ctx
);
440 struct brw_query_object
*query
= (struct brw_query_object
*)q
;
441 struct intel_buffer_object
*bo
= intel_buffer_object(buf
);
442 const bool pipelined
= brw_is_query_pipelined(query
);
444 if (pname
== GL_QUERY_TARGET
) {
445 store_query_result_imm(brw
, bo
->buffer
, offset
, ptype
,
448 } else if (pname
== GL_QUERY_RESULT_AVAILABLE
&& !pipelined
) {
449 store_query_result_imm(brw
, bo
->buffer
, offset
, ptype
, 1ull);
450 } else if (query
->bo
) {
451 /* The query bo still around. Therefore, we:
453 * 1. Compute the current result in GPR0
454 * 2. Set the command streamer predicate based on query availability
455 * 3. (With predication) Write GPR0 to the requested buffer
457 hsw_result_to_gpr0(ctx
, query
, buf
, offset
, pname
, ptype
);
459 set_predicate(brw
, query
->bo
);
460 store_query_result_reg(brw
, bo
->buffer
, offset
, ptype
, HSW_CS_GPR(0),
463 /* The query bo is gone, so the query must have been processed into
464 * client memory. In this case we can fill the buffer location with the
465 * requested data using MI_STORE_DATA_IMM.
468 case GL_QUERY_RESULT_AVAILABLE
:
469 store_query_result_imm(brw
, bo
->buffer
, offset
, ptype
, 1ull);
471 case GL_QUERY_RESULT_NO_WAIT
:
472 case GL_QUERY_RESULT
:
473 store_query_result_imm(brw
, bo
->buffer
, offset
, ptype
,
477 unreachable("Unexpected result type");
483 /* Initialize hsw+-specific query object functions. */
484 void hsw_init_queryobj_functions(struct dd_function_table
*functions
)
486 gen6_init_queryobj_functions(functions
);
487 functions
->StoreQueryResult
= hsw_store_query_result
;