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25 /** @file hsw_queryobj.c
27 * Support for query buffer objects (GL_ARB_query_buffer_object) on Haswell+.
29 #include "main/imports.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "intel_batchbuffer.h"
34 #include "intel_buffer_objects.h"
35 #include "intel_reg.h"
41 mult_gpr0_by_80(struct brw_context
*brw
)
43 static const uint32_t maths
[] = {
44 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
45 MI_MATH_ALU2(LOAD
, SRCB
, R0
),
47 MI_MATH_ALU2(STORE
, R1
, ACCU
),
48 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
49 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
51 MI_MATH_ALU2(STORE
, R1
, ACCU
),
52 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
53 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
55 MI_MATH_ALU2(STORE
, R1
, ACCU
),
56 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
57 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
59 /* GPR1 = 16 * GPR0 */
60 MI_MATH_ALU2(STORE
, R1
, ACCU
),
61 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
62 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
64 MI_MATH_ALU2(STORE
, R2
, ACCU
),
65 MI_MATH_ALU2(LOAD
, SRCA
, R2
),
66 MI_MATH_ALU2(LOAD
, SRCB
, R2
),
68 /* GPR2 = 64 * GPR0 */
69 MI_MATH_ALU2(STORE
, R2
, ACCU
),
70 MI_MATH_ALU2(LOAD
, SRCA
, R1
),
71 MI_MATH_ALU2(LOAD
, SRCB
, R2
),
73 /* GPR0 = 80 * GPR0 */
74 MI_MATH_ALU2(STORE
, R0
, ACCU
),
77 BEGIN_BATCH(1 + ARRAY_SIZE(maths
));
78 OUT_BATCH(HSW_MI_MATH
| (1 + ARRAY_SIZE(maths
) - 2));
80 for (int m
= 0; m
< ARRAY_SIZE(maths
); m
++)
87 * GPR0 = GPR0 & ((1ull << n) - 1);
90 keep_gpr0_lower_n_bits(struct brw_context
*brw
, uint32_t n
)
92 static const uint32_t maths
[] = {
93 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
94 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
96 MI_MATH_ALU2(STORE
, R0
, ACCU
),
100 brw_load_register_imm64(brw
, HSW_CS_GPR(1), (1ull << n
) - 1);
102 BEGIN_BATCH(1 + ARRAY_SIZE(maths
));
103 OUT_BATCH(HSW_MI_MATH
| (1 + ARRAY_SIZE(maths
) - 2));
105 for (int m
= 0; m
< ARRAY_SIZE(maths
); m
++)
115 shl_gpr0_by_30_bits(struct brw_context
*brw
)
117 /* First we mask 34 bits of GPR0 to prevent overflow */
118 keep_gpr0_lower_n_bits(brw
, 34);
120 static const uint32_t shl_maths
[] = {
121 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
122 MI_MATH_ALU2(LOAD
, SRCB
, R0
),
124 MI_MATH_ALU2(STORE
, R0
, ACCU
),
127 const uint32_t outer_count
= 5;
128 const uint32_t inner_count
= 6;
129 STATIC_ASSERT(outer_count
* inner_count
== 30);
130 const uint32_t cmd_len
= 1 + inner_count
* ARRAY_SIZE(shl_maths
);
131 const uint32_t batch_len
= cmd_len
* outer_count
;
133 BEGIN_BATCH(batch_len
);
135 /* We'll emit 5 commands, each shifting GPR0 left by 6 bits, for a total of
138 for (int o
= 0; o
< outer_count
; o
++) {
139 /* Submit one MI_MATH to shift left by 6 bits */
140 OUT_BATCH(HSW_MI_MATH
| (cmd_len
- 2));
141 for (int i
= 0; i
< inner_count
; i
++)
142 for (int m
= 0; m
< ARRAY_SIZE(shl_maths
); m
++)
143 OUT_BATCH(shl_maths
[m
]);
152 * Note that the upper 30 bits of GPR0 are lost!
155 shr_gpr0_by_2_bits(struct brw_context
*brw
)
157 shl_gpr0_by_30_bits(brw
);
158 brw_load_register_reg(brw
, HSW_CS_GPR(0) + 4, HSW_CS_GPR(0));
159 brw_load_register_imm32(brw
, HSW_CS_GPR(0) + 4, 0);
163 * GPR0 = (GPR0 == 0) ? 0 : 1;
166 gpr0_to_bool(struct brw_context
*brw
)
168 static const uint32_t maths
[] = {
169 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
170 MI_MATH_ALU1(LOAD0
, SRCB
),
172 MI_MATH_ALU2(STOREINV
, R0
, ZF
),
173 MI_MATH_ALU2(LOAD
, SRCA
, R0
),
174 MI_MATH_ALU2(LOAD
, SRCB
, R1
),
176 MI_MATH_ALU2(STORE
, R0
, ACCU
),
179 brw_load_register_imm64(brw
, HSW_CS_GPR(1), 1ull);
181 BEGIN_BATCH(1 + ARRAY_SIZE(maths
));
182 OUT_BATCH(HSW_MI_MATH
| (1 + ARRAY_SIZE(maths
) - 2));
184 for (int m
= 0; m
< ARRAY_SIZE(maths
); m
++)
191 hsw_result_to_gpr0(struct gl_context
*ctx
, struct brw_query_object
*query
,
192 struct gl_buffer_object
*buf
, intptr_t offset
,
193 GLenum pname
, GLenum ptype
)
195 struct brw_context
*brw
= brw_context(ctx
);
198 assert(pname
!= GL_QUERY_TARGET
);
200 if (pname
== GL_QUERY_RESULT_AVAILABLE
) {
201 /* The query result availability is stored at offset 0 of the buffer. */
202 brw_load_register_mem64(brw
,
205 I915_GEM_DOMAIN_INSTRUCTION
,
206 I915_GEM_DOMAIN_INSTRUCTION
,
207 2 * sizeof(uint64_t));
211 if (pname
== GL_QUERY_RESULT
) {
212 /* Since GL_QUERY_RESULT_NO_WAIT wasn't used, they want us to stall to
213 * make sure the query is available.
215 brw_emit_pipe_control_flush(brw
,
216 PIPE_CONTROL_CS_STALL
|
217 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
220 if (query
->Base
.Target
== GL_TIMESTAMP
) {
221 brw_load_register_mem64(brw
,
224 I915_GEM_DOMAIN_INSTRUCTION
,
225 I915_GEM_DOMAIN_INSTRUCTION
,
226 0 * sizeof(uint64_t));
228 brw_load_register_mem64(brw
,
231 I915_GEM_DOMAIN_INSTRUCTION
,
232 I915_GEM_DOMAIN_INSTRUCTION
,
233 0 * sizeof(uint64_t));
234 brw_load_register_mem64(brw
,
237 I915_GEM_DOMAIN_INSTRUCTION
,
238 I915_GEM_DOMAIN_INSTRUCTION
,
239 1 * sizeof(uint64_t));
242 OUT_BATCH(HSW_MI_MATH
| (5 - 2));
244 OUT_BATCH(MI_MATH_ALU2(LOAD
, SRCA
, R2
));
245 OUT_BATCH(MI_MATH_ALU2(LOAD
, SRCB
, R1
));
246 OUT_BATCH(MI_MATH_ALU0(SUB
));
247 OUT_BATCH(MI_MATH_ALU2(STORE
, R0
, ACCU
));
252 switch (query
->Base
.Target
) {
253 case GL_FRAGMENT_SHADER_INVOCATIONS_ARB
:
254 /* Implement the "WaDividePSInvocationCountBy4:HSW,BDW" workaround:
255 * "Invocation counter is 4 times actual. WA: SW to divide HW reported
256 * PS Invocations value by 4."
258 * Prior to Haswell, invocation count was counted by the WM, and it
259 * buggily counted invocations in units of subspans (2x2 unit). To get the
260 * correct value, the CS multiplied this by 4. With HSW the logic moved,
261 * and correctly emitted the number of pixel shader invocations, but,
262 * whomever forgot to undo the multiply by 4.
264 if (brw
->gen
== 8 || brw
->is_haswell
)
265 shr_gpr0_by_2_bits(brw
);
267 case GL_TIME_ELAPSED
:
269 mult_gpr0_by_80(brw
);
270 if (query
->Base
.Target
== GL_TIMESTAMP
) {
271 keep_gpr0_lower_n_bits(brw
, 36);
274 case GL_ANY_SAMPLES_PASSED
:
275 case GL_ANY_SAMPLES_PASSED_CONSERVATIVE
:
282 * Store immediate data into the user buffer using the requested size.
285 store_query_result_imm(struct brw_context
*brw
, drm_intel_bo
*bo
,
286 uint32_t offset
, GLenum ptype
, uint64_t imm
)
290 case GL_UNSIGNED_INT
:
291 brw_store_data_imm32(brw
, bo
, offset
, imm
);
294 case GL_UNSIGNED_INT64_ARB
:
295 brw_store_data_imm64(brw
, bo
, offset
, imm
);
298 unreachable("Unexpected result type");
303 set_predicate(struct brw_context
*brw
, drm_intel_bo
*query_bo
)
305 brw_load_register_imm64(brw
, MI_PREDICATE_SRC1
, 0ull);
307 /* Load query availability into SRC0 */
308 brw_load_register_mem64(brw
, MI_PREDICATE_SRC0
, query_bo
,
309 I915_GEM_DOMAIN_INSTRUCTION
, 0,
310 2 * sizeof(uint64_t));
312 /* predicate = !(query_availability == 0); */
314 OUT_BATCH(GEN7_MI_PREDICATE
|
315 MI_PREDICATE_LOADOP_LOADINV
|
316 MI_PREDICATE_COMBINEOP_SET
|
317 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
322 * Store data from the register into the user buffer using the requested size.
323 * The write also enables the predication to prevent writing the result if the
324 * query has not finished yet.
327 store_query_result_reg(struct brw_context
*brw
, drm_intel_bo
*bo
,
328 uint32_t offset
, GLenum ptype
, uint32_t reg
,
329 const bool pipelined
)
331 uint32_t cmd_size
= brw
->gen
>= 8 ? 4 : 3;
332 uint32_t dwords
= (ptype
== GL_INT
|| ptype
== GL_UNSIGNED_INT
) ? 1 : 2;
333 assert(brw
->gen
>= 6);
335 BEGIN_BATCH(dwords
* cmd_size
);
336 for (int i
= 0; i
< dwords
; i
++) {
337 OUT_BATCH(MI_STORE_REGISTER_MEM
|
338 (pipelined
? MI_STORE_REGISTER_MEM_PREDICATE
: 0) |
340 OUT_BATCH(reg
+ 4 * i
);
342 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
,
343 I915_GEM_DOMAIN_INSTRUCTION
, offset
+ 4 * i
);
345 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
,
346 I915_GEM_DOMAIN_INSTRUCTION
, offset
+ 4 * i
);
353 hsw_store_query_result(struct gl_context
*ctx
, struct gl_query_object
*q
,
354 struct gl_buffer_object
*buf
, intptr_t offset
,
355 GLenum pname
, GLenum ptype
)
357 struct brw_context
*brw
= brw_context(ctx
);
358 struct brw_query_object
*query
= (struct brw_query_object
*)q
;
359 struct intel_buffer_object
*bo
= intel_buffer_object(buf
);
360 const bool pipelined
= brw_is_query_pipelined(query
);
362 if (pname
== GL_QUERY_TARGET
) {
363 store_query_result_imm(brw
, bo
->buffer
, offset
, ptype
,
366 } else if (pname
== GL_QUERY_RESULT_AVAILABLE
&& !pipelined
) {
367 store_query_result_imm(brw
, bo
->buffer
, offset
, ptype
, 1ull);
368 } else if (query
->bo
) {
369 /* The query bo still around. Therefore, we:
371 * 1. Compute the current result in GPR0
372 * 2. Set the command streamer predicate based on query availability
373 * 3. (With predication) Write GPR0 to the requested buffer
375 hsw_result_to_gpr0(ctx
, query
, buf
, offset
, pname
, ptype
);
377 set_predicate(brw
, query
->bo
);
378 store_query_result_reg(brw
, bo
->buffer
, offset
, ptype
, HSW_CS_GPR(0),
381 /* The query bo is gone, so the query must have been processed into
382 * client memory. In this case we can fill the buffer location with the
383 * requested data using MI_STORE_DATA_IMM.
386 case GL_QUERY_RESULT_AVAILABLE
:
387 store_query_result_imm(brw
, bo
->buffer
, offset
, ptype
, 1ull);
389 case GL_QUERY_RESULT_NO_WAIT
:
390 case GL_QUERY_RESULT
:
391 store_query_result_imm(brw
, bo
->buffer
, offset
, ptype
,
395 unreachable("Unexpected result type");
401 /* Initialize hsw+-specific query object functions. */
402 void hsw_init_queryobj_functions(struct dd_function_table
*functions
)
404 gen6_init_queryobj_functions(functions
);
405 functions
->StoreQueryResult
= hsw_store_query_result
;