2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
36 #include "util/hash_table.h"
41 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
44 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
45 struct brw_bufmgr
*bufmgr
,
49 uint_key_compare(const void *a
, const void *b
)
55 uint_key_hash(const void *key
)
57 return (uintptr_t) key
;
61 intel_batchbuffer_init(struct intel_batchbuffer
*batch
,
62 struct brw_bufmgr
*bufmgr
,
65 intel_batchbuffer_reset(batch
, bufmgr
, has_llc
);
68 batch
->cpu_map
= malloc(BATCH_SZ
);
69 batch
->map
= batch
->cpu_map
;
70 batch
->map_next
= batch
->cpu_map
;
73 batch
->reloc_count
= 0;
74 batch
->reloc_array_size
= 250;
75 batch
->relocs
= malloc(batch
->reloc_array_size
*
76 sizeof(struct drm_i915_gem_relocation_entry
));
77 batch
->exec_count
= 0;
78 batch
->exec_array_size
= 100;
80 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
82 malloc(batch
->exec_array_size
* sizeof(batch
->exec_objects
[0]));
84 if (INTEL_DEBUG
& DEBUG_BATCH
) {
85 batch
->state_batch_sizes
=
86 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
91 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
92 struct brw_bufmgr
*bufmgr
,
95 if (batch
->last_bo
!= NULL
) {
96 brw_bo_unreference(batch
->last_bo
);
97 batch
->last_bo
= NULL
;
99 batch
->last_bo
= batch
->bo
;
101 batch
->bo
= brw_bo_alloc(bufmgr
, "batchbuffer", BATCH_SZ
, 4096);
103 brw_bo_map(NULL
, batch
->bo
, true);
104 batch
->map
= batch
->bo
->virtual;
106 batch
->map_next
= batch
->map
;
108 batch
->reserved_space
= BATCH_RESERVED
;
109 batch
->state_batch_offset
= batch
->bo
->size
;
110 batch
->needs_sol_reset
= false;
111 batch
->state_base_address_emitted
= false;
113 /* We don't know what ring the new batch will be sent to until we see the
114 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
116 batch
->ring
= UNKNOWN_RING
;
118 if (batch
->state_batch_sizes
)
119 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
123 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
125 intel_batchbuffer_reset(&brw
->batch
, brw
->bufmgr
, brw
->has_llc
);
126 brw_render_cache_set_clear(brw
);
130 intel_batchbuffer_save_state(struct brw_context
*brw
)
132 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
133 brw
->batch
.saved
.reloc_count
= brw
->batch
.reloc_count
;
134 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
138 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
140 for (int i
= brw
->batch
.saved
.exec_count
;
141 i
< brw
->batch
.exec_count
; i
++) {
142 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
143 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
146 brw
->batch
.reloc_count
= brw
->batch
.saved
.reloc_count
;
147 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
149 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
150 if (USED_BATCH(brw
->batch
) == 0)
151 brw
->batch
.ring
= UNKNOWN_RING
;
155 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
157 free(batch
->cpu_map
);
159 for (int i
= 0; i
< batch
->exec_count
; i
++) {
160 if (batch
->exec_bos
[i
] != batch
->bo
) {
161 brw_bo_unreference(batch
->exec_bos
[i
]);
165 free(batch
->exec_bos
);
166 free(batch
->exec_objects
);
168 brw_bo_unreference(batch
->last_bo
);
169 brw_bo_unreference(batch
->bo
);
170 if (batch
->state_batch_sizes
)
171 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
175 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
176 enum brw_gpu_ring ring
)
178 /* If we're switching rings, implicitly flush the batch. */
179 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
181 intel_batchbuffer_flush(brw
);
185 assert(sz
< BATCH_SZ
- BATCH_RESERVED
);
187 if (intel_batchbuffer_space(&brw
->batch
) < sz
)
188 intel_batchbuffer_flush(brw
);
190 /* The intel_batchbuffer_flush() calls above might have changed
191 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
193 brw
->batch
.ring
= ring
;
198 #define BLUE_HEADER CSI "0;44m"
199 #define NORMAL CSI "0m"
203 decode_struct(struct brw_context
*brw
, struct gen_spec
*spec
,
204 const char *struct_name
, uint32_t *data
,
205 uint32_t gtt_offset
, uint32_t offset
, bool color
)
207 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
211 fprintf(stderr
, "%s\n", struct_name
);
212 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
213 &data
[offset
/ 4], color
);
217 decode_structs(struct brw_context
*brw
, struct gen_spec
*spec
,
218 const char *struct_name
,
219 uint32_t *data
, uint32_t gtt_offset
, uint32_t offset
,
220 int struct_size
, bool color
)
222 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
226 int entries
= brw_state_batch_size(brw
, offset
) / struct_size
;
227 for (int i
= 0; i
< entries
; i
++) {
228 fprintf(stderr
, "%s %d\n", struct_name
, i
);
229 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
230 &data
[(offset
+ i
* struct_size
) / 4], color
);
235 do_batch_dump(struct brw_context
*brw
)
237 struct intel_batchbuffer
*batch
= &brw
->batch
;
238 struct gen_spec
*spec
= gen_spec_load(&brw
->screen
->devinfo
);
240 if (batch
->ring
!= RENDER_RING
)
243 int ret
= brw_bo_map(brw
, batch
->bo
, false);
246 "WARNING: failed to map batchbuffer (%s), "
247 "dumping uploaded data instead.\n", strerror(ret
));
250 uint32_t *data
= batch
->bo
->virtual ? batch
->bo
->virtual : batch
->map
;
251 uint32_t *end
= data
+ USED_BATCH(*batch
);
252 uint32_t gtt_offset
= batch
->bo
->virtual ? batch
->bo
->offset64
: 0;
255 bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
256 const char *header_color
= color
? BLUE_HEADER
: "";
257 const char *reset_color
= color
? NORMAL
: "";
259 for (uint32_t *p
= data
; p
< end
; p
+= length
) {
260 struct gen_group
*inst
= gen_spec_find_instruction(spec
, p
);
261 length
= gen_group_get_length(inst
, p
);
262 assert(inst
== NULL
|| length
> 0);
263 length
= MAX2(1, length
);
265 fprintf(stderr
, "unknown instruction %08x\n", p
[0]);
269 uint64_t offset
= gtt_offset
+ 4 * (p
- data
);
271 fprintf(stderr
, "%s0x%08"PRIx64
": 0x%08x: %-80s%s\n", header_color
,
272 offset
, p
[0], gen_group_get_name(inst
), reset_color
);
274 gen_print_group(stderr
, inst
, offset
, p
, color
);
276 switch (gen_group_get_opcode(inst
) >> 16) {
277 case _3DSTATE_PIPELINED_POINTERS
:
278 /* Note: these Gen4-5 pointers are full relocations rather than
279 * offsets from the start of the batch. So we need to subtract
280 * gtt_offset (the start of the batch) to obtain an offset we
281 * can add to the map and get at the data.
283 decode_struct(brw
, spec
, "VS_STATE", data
, gtt_offset
,
284 (p
[1] & ~0x1fu
) - gtt_offset
, color
);
286 decode_struct(brw
, spec
, "GS_STATE", data
, gtt_offset
,
287 (p
[2] & ~0x1fu
) - gtt_offset
, color
);
290 decode_struct(brw
, spec
, "CLIP_STATE", data
, gtt_offset
,
291 (p
[3] & ~0x1fu
) - gtt_offset
, color
);
293 decode_struct(brw
, spec
, "SF_STATE", data
, gtt_offset
,
294 (p
[4] & ~0x1fu
) - gtt_offset
, color
);
295 decode_struct(brw
, spec
, "WM_STATE", data
, gtt_offset
,
296 (p
[5] & ~0x1fu
) - gtt_offset
, color
);
297 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
, gtt_offset
,
298 (p
[6] & ~0x3fu
) - gtt_offset
, color
);
300 case _3DSTATE_BINDING_TABLE_POINTERS_VS
:
301 case _3DSTATE_BINDING_TABLE_POINTERS_HS
:
302 case _3DSTATE_BINDING_TABLE_POINTERS_DS
:
303 case _3DSTATE_BINDING_TABLE_POINTERS_GS
:
304 case _3DSTATE_BINDING_TABLE_POINTERS_PS
: {
305 struct gen_group
*group
=
306 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
310 uint32_t bt_offset
= p
[1] & ~0x1fu
;
311 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
312 uint32_t *bt_pointers
= &data
[bt_offset
/ 4];
313 for (int i
= 0; i
< bt_entries
; i
++) {
314 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
315 gen_print_group(stderr
, group
, gtt_offset
+ bt_pointers
[i
],
316 &data
[bt_pointers
[i
] / 4], color
);
320 case _3DSTATE_SAMPLER_STATE_POINTERS_VS
:
321 case _3DSTATE_SAMPLER_STATE_POINTERS_HS
:
322 case _3DSTATE_SAMPLER_STATE_POINTERS_DS
:
323 case _3DSTATE_SAMPLER_STATE_POINTERS_GS
:
324 case _3DSTATE_SAMPLER_STATE_POINTERS_PS
:
325 decode_structs(brw
, spec
, "SAMPLER_STATE", data
,
326 gtt_offset
, p
[1] & ~0x1fu
, 4 * 4, color
);
328 case _3DSTATE_VIEWPORT_STATE_POINTERS
:
329 decode_structs(brw
, spec
, "CLIP_VIEWPORT", data
,
330 gtt_offset
, p
[1] & ~0x3fu
, 4 * 4, color
);
331 decode_structs(brw
, spec
, "SF_VIEWPORT", data
,
332 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
333 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
334 gtt_offset
, p
[3] & ~0x3fu
, 2 * 4, color
);
336 case _3DSTATE_VIEWPORT_STATE_POINTERS_CC
:
337 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
338 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
340 case _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
:
341 decode_structs(brw
, spec
, "SF_CLIP_VIEWPORT", data
,
342 gtt_offset
, p
[1] & ~0x3fu
, 16 * 4, color
);
344 case _3DSTATE_SCISSOR_STATE_POINTERS
:
345 decode_structs(brw
, spec
, "SCISSOR_RECT", data
,
346 gtt_offset
, p
[1] & ~0x1fu
, 2 * 4, color
);
348 case _3DSTATE_BLEND_STATE_POINTERS
:
349 /* TODO: handle Gen8+ extra dword at the beginning */
350 decode_structs(brw
, spec
, "BLEND_STATE", data
,
351 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
353 case _3DSTATE_CC_STATE_POINTERS
:
355 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
356 gtt_offset
, p
[1] & ~0x3fu
, color
);
357 } else if (brw
->gen
== 6) {
358 decode_structs(brw
, spec
, "BLEND_STATE", data
,
359 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
360 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
361 gtt_offset
, p
[2] & ~0x3fu
, color
);
362 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
363 gtt_offset
, p
[3] & ~0x3fu
, color
);
366 case _3DSTATE_DEPTH_STENCIL_STATE_POINTERS
:
367 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
368 gtt_offset
, p
[1] & ~0x3fu
, color
);
374 brw_bo_unmap(batch
->bo
);
378 static void do_batch_dump(struct brw_context
*brw
) { }
382 * Called when starting a new batch buffer.
385 brw_new_batch(struct brw_context
*brw
)
387 /* Unreference any BOs held by the previous batch, and reset counts. */
388 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
389 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
390 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
392 brw
->batch
.exec_bos
[i
] = NULL
;
394 brw
->batch
.reloc_count
= 0;
395 brw
->batch
.exec_count
= 0;
396 brw
->batch
.aperture_space
= BATCH_SZ
;
398 /* Create a new batchbuffer and reset the associated state: */
399 intel_batchbuffer_reset_and_clear_render_cache(brw
);
401 /* If the kernel supports hardware contexts, then most hardware state is
402 * preserved between batches; we only need to re-emit state that is required
403 * to be in every batch. Otherwise we need to re-emit all the state that
404 * would otherwise be stored in the context (which for all intents and
405 * purposes means everything).
407 if (brw
->hw_ctx
== 0)
408 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
410 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
412 brw
->ib
.index_size
= -1;
414 /* We need to periodically reap the shader time results, because rollover
415 * happens every few seconds. We also want to see results every once in a
416 * while, because many programs won't cleanly destroy our context, so the
417 * end-of-run printout may not happen.
419 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
420 brw_collect_and_report_shader_time(brw
);
424 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
427 * This function can emit state (say, to preserve registers that aren't saved
428 * between batches). All of this state MUST fit in the reserved space at the
429 * end of the batchbuffer. If you add more GPU state, increase the reserved
430 * space by updating the BATCH_RESERVED macro.
433 brw_finish_batch(struct brw_context
*brw
)
435 /* Capture the closing pipeline statistics register values necessary to
436 * support query objects (in the non-hardware context world).
438 brw_emit_query_end(brw
);
440 if (brw
->batch
.ring
== RENDER_RING
) {
441 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
442 * assume that the L3 cache is configured according to the hardware
446 gen7_restore_default_l3_config(brw
);
448 if (brw
->is_haswell
) {
449 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
450 * 3DSTATE_CC_STATE_POINTERS > "Note":
452 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
453 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
455 * From the example in the docs, it seems to expect a regular pipe control
456 * flush here as well. We may have done it already, but meh.
458 * See also WaAvoidRCZCounterRollover.
460 brw_emit_mi_flush(brw
);
462 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
463 OUT_BATCH(brw
->cc
.state_offset
| 1);
465 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
466 PIPE_CONTROL_CS_STALL
);
470 /* Mark that the current program cache BO has been used by the GPU.
471 * It will be reallocated if we need to put new programs in for the
474 brw
->cache
.bo_used_by_gpu
= true;
478 throttle(struct brw_context
*brw
)
480 /* Wait for the swapbuffers before the one we just emitted, so we
481 * don't get too many swaps outstanding for apps that are GPU-heavy
484 * We're using intelDRI2Flush (called from the loader before
485 * swapbuffer) and glFlush (for front buffer rendering) as the
486 * indicator that a frame is done and then throttle when we get
487 * here as we prepare to render the next frame. At this point for
488 * round trips for swap/copy and getting new buffers are done and
489 * we'll spend less time waiting on the GPU.
491 * Unfortunately, we don't have a handle to the batch containing
492 * the swap, and getting our hands on that doesn't seem worth it,
493 * so we just use the first batch we emitted after the last swap.
495 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
496 if (brw
->throttle_batch
[1]) {
497 if (!brw
->disable_throttling
) {
498 /* Pass NULL rather than brw so we avoid perf_debug warnings;
499 * stalling is common and expected here...
501 brw_bo_wait_rendering(NULL
, brw
->throttle_batch
[1]);
503 brw_bo_unreference(brw
->throttle_batch
[1]);
505 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
506 brw
->throttle_batch
[0] = NULL
;
507 brw
->need_swap_throttle
= false;
508 /* Throttling here is more precise than the throttle ioctl, so skip it */
509 brw
->need_flush_throttle
= false;
512 if (brw
->need_flush_throttle
) {
513 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
514 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
515 brw
->need_flush_throttle
= false;
520 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
522 if (bo
!= batch
->bo
) {
523 for (int i
= 0; i
< batch
->exec_count
; i
++) {
524 if (batch
->exec_bos
[i
] == bo
)
528 brw_bo_reference(bo
);
531 if (batch
->exec_count
== batch
->exec_array_size
) {
532 batch
->exec_array_size
*= 2;
534 realloc(batch
->exec_bos
,
535 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
536 batch
->exec_objects
=
537 realloc(batch
->exec_objects
,
538 batch
->exec_array_size
* sizeof(batch
->exec_objects
[0]));
541 struct drm_i915_gem_exec_object2
*validation_entry
=
542 &batch
->exec_objects
[batch
->exec_count
];
543 validation_entry
->handle
= bo
->gem_handle
;
544 if (bo
== batch
->bo
) {
545 validation_entry
->relocation_count
= batch
->reloc_count
;
546 validation_entry
->relocs_ptr
= (uintptr_t) batch
->relocs
;
548 validation_entry
->relocation_count
= 0;
549 validation_entry
->relocs_ptr
= 0;
551 validation_entry
->alignment
= bo
->align
;
552 validation_entry
->offset
= bo
->offset64
;
553 validation_entry
->flags
= 0;
554 validation_entry
->rsvd1
= 0;
555 validation_entry
->rsvd2
= 0;
557 batch
->exec_bos
[batch
->exec_count
] = bo
;
559 batch
->aperture_space
+= bo
->size
;
564 struct intel_batchbuffer
*batch
,
571 struct drm_i915_gem_execbuffer2 execbuf
= {
572 .buffers_ptr
= (uintptr_t) batch
->exec_objects
,
573 .buffer_count
= batch
->exec_count
,
574 .batch_start_offset
= 0,
577 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
580 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
582 if (in_fence
!= -1) {
583 execbuf
.rsvd2
= in_fence
;
584 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
587 if (out_fence
!= NULL
) {
588 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
590 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
593 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
597 for (int i
= 0; i
< batch
->exec_count
; i
++) {
598 struct brw_bo
*bo
= batch
->exec_bos
[i
];
602 /* Update brw_bo::offset64 */
603 if (batch
->exec_objects
[i
].offset
!= bo
->offset64
) {
604 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
605 bo
->gem_handle
, bo
->offset64
, batch
->exec_objects
[i
].offset
);
606 bo
->offset64
= batch
->exec_objects
[i
].offset
;
610 if (ret
== 0 && out_fence
!= NULL
)
611 *out_fence
= execbuf
.rsvd2
>> 32;
617 do_flush_locked(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
619 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
620 struct intel_batchbuffer
*batch
= &brw
->batch
;
624 brw_bo_unmap(batch
->bo
);
626 ret
= brw_bo_subdata(batch
->bo
, 0, 4 * USED_BATCH(*batch
), batch
->map
);
627 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
628 ret
= brw_bo_subdata(batch
->bo
,
629 batch
->state_batch_offset
,
630 batch
->bo
->size
- batch
->state_batch_offset
,
631 (char *)batch
->map
+ batch
->state_batch_offset
);
635 if (!brw
->screen
->no_hw
) {
638 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
639 flags
= I915_EXEC_BLT
;
641 flags
= I915_EXEC_RENDER
;
643 if (batch
->needs_sol_reset
)
644 flags
|= I915_EXEC_GEN7_SOL_RESET
;
647 uint32_t hw_ctx
= batch
->ring
== RENDER_RING
? brw
->hw_ctx
: 0;
649 /* Add the batch itself to the end of the validation list */
650 add_exec_bo(batch
, batch
->bo
);
652 ret
= execbuffer(dri_screen
->fd
, batch
, hw_ctx
,
653 4 * USED_BATCH(*batch
),
654 in_fence_fd
, out_fence_fd
, flags
);
660 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
663 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
664 brw_check_for_reset(brw
);
667 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
675 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
678 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
679 * of the returned fd.
682 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
683 int in_fence_fd
, int *out_fence_fd
,
684 const char *file
, int line
)
688 if (USED_BATCH(brw
->batch
) == 0)
691 if (brw
->throttle_batch
[0] == NULL
) {
692 brw
->throttle_batch
[0] = brw
->batch
.bo
;
693 brw_bo_reference(brw
->throttle_batch
[0]);
696 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
697 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
698 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
699 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
700 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
701 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
702 bytes_for_commands
, bytes_for_state
,
704 100.0f
* total_bytes
/ BATCH_SZ
);
707 brw
->batch
.reserved_space
= 0;
709 brw_finish_batch(brw
);
711 /* Mark the end of the buffer. */
712 intel_batchbuffer_emit_dword(&brw
->batch
, MI_BATCH_BUFFER_END
);
713 if (USED_BATCH(brw
->batch
) & 1) {
714 /* Round batchbuffer usage to 2 DWORDs. */
715 intel_batchbuffer_emit_dword(&brw
->batch
, MI_NOOP
);
718 intel_upload_finish(brw
);
720 /* Check that we didn't just wrap our batchbuffer at a bad time. */
721 assert(!brw
->no_batch_wrap
);
723 ret
= do_flush_locked(brw
, in_fence_fd
, out_fence_fd
);
725 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
726 fprintf(stderr
, "waiting for idle\n");
727 brw_bo_wait_rendering(brw
, brw
->batch
.bo
);
730 /* Start a new batch buffer. */
737 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
739 return brw
->batch
.aperture_space
+ extra_space
<=
740 brw
->screen
->aperture_threshold
;
744 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
746 for (int i
= 0; i
< batch
->exec_count
; i
++) {
747 if (batch
->exec_bos
[i
] == bo
)
753 /* This is the only way buffers get added to the validate list.
756 brw_emit_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
757 struct brw_bo
*target
, uint32_t target_offset
,
758 uint32_t read_domains
, uint32_t write_domain
)
762 if (batch
->reloc_count
== batch
->reloc_array_size
) {
763 batch
->reloc_array_size
*= 2;
764 batch
->relocs
= realloc(batch
->relocs
,
765 batch
->reloc_array_size
*
766 sizeof(struct drm_i915_gem_relocation_entry
));
770 assert(batch_offset
<= BATCH_SZ
- sizeof(uint32_t));
771 assert(_mesa_bitcount(write_domain
) <= 1);
773 if (target
!= batch
->bo
)
774 add_exec_bo(batch
, target
);
776 struct drm_i915_gem_relocation_entry
*reloc
=
777 &batch
->relocs
[batch
->reloc_count
];
779 batch
->reloc_count
++;
781 /* ensure gcc doesn't reload */
782 offset64
= *((volatile uint64_t *)&target
->offset64
);
783 reloc
->offset
= batch_offset
;
784 reloc
->delta
= target_offset
;
785 reloc
->target_handle
= target
->gem_handle
;
786 reloc
->read_domains
= read_domains
;
787 reloc
->write_domain
= write_domain
;
788 reloc
->presumed_offset
= offset64
;
790 /* Using the old buffer offset, write in what the right data would be, in
791 * case the buffer doesn't move and we can short-circuit the relocation
792 * processing in the kernel
794 return offset64
+ target_offset
;
798 intel_batchbuffer_data(struct brw_context
*brw
,
799 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
801 assert((bytes
& 3) == 0);
802 intel_batchbuffer_require_space(brw
, bytes
, ring
);
803 memcpy(brw
->batch
.map_next
, data
, bytes
);
804 brw
->batch
.map_next
+= bytes
>> 2;
808 load_sized_register_mem(struct brw_context
*brw
,
811 uint32_t read_domains
, uint32_t write_domain
,
817 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
818 assert(brw
->gen
>= 7);
821 BEGIN_BATCH(4 * size
);
822 for (i
= 0; i
< size
; i
++) {
823 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
824 OUT_BATCH(reg
+ i
* 4);
825 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
+ i
* 4);
829 BEGIN_BATCH(3 * size
);
830 for (i
= 0; i
< size
; i
++) {
831 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
832 OUT_BATCH(reg
+ i
* 4);
833 OUT_RELOC(bo
, read_domains
, write_domain
, offset
+ i
* 4);
840 brw_load_register_mem(struct brw_context
*brw
,
843 uint32_t read_domains
, uint32_t write_domain
,
846 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 1);
850 brw_load_register_mem64(struct brw_context
*brw
,
853 uint32_t read_domains
, uint32_t write_domain
,
856 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 2);
860 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
863 brw_store_register_mem32(struct brw_context
*brw
,
864 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
866 assert(brw
->gen
>= 6);
870 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
872 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
877 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
879 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
886 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
889 brw_store_register_mem64(struct brw_context
*brw
,
890 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
892 assert(brw
->gen
>= 6);
894 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
895 * read a full 64-bit register, we need to do two of them.
899 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
901 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
903 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
904 OUT_BATCH(reg
+ sizeof(uint32_t));
905 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
906 offset
+ sizeof(uint32_t));
910 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
912 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
914 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
915 OUT_BATCH(reg
+ sizeof(uint32_t));
916 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
917 offset
+ sizeof(uint32_t));
923 * Write a 32-bit register using immediate data.
926 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
928 assert(brw
->gen
>= 6);
931 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
938 * Write a 64-bit register using immediate data.
941 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
943 assert(brw
->gen
>= 6);
946 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
948 OUT_BATCH(imm
& 0xffffffff);
950 OUT_BATCH(imm
>> 32);
955 * Copies a 32-bit register.
958 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
960 assert(brw
->gen
>= 8 || brw
->is_haswell
);
963 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
970 * Copies a 64-bit register.
973 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
975 assert(brw
->gen
>= 8 || brw
->is_haswell
);
978 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
981 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
982 OUT_BATCH(src
+ sizeof(uint32_t));
983 OUT_BATCH(dest
+ sizeof(uint32_t));
988 * Write 32-bits of immediate data to a GPU memory buffer.
991 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
992 uint32_t offset
, uint32_t imm
)
994 assert(brw
->gen
>= 6);
997 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
999 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1002 OUT_BATCH(0); /* MBZ */
1003 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1011 * Write 64-bits of immediate data to a GPU memory buffer.
1014 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1015 uint32_t offset
, uint64_t imm
)
1017 assert(brw
->gen
>= 6);
1020 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1022 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1025 OUT_BATCH(0); /* MBZ */
1026 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1029 OUT_BATCH(imm
& 0xffffffffu
);
1030 OUT_BATCH(imm
>> 32);