1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "brw_context.h"
36 intel_batchbuffer_reset(struct intel_context
*intel
);
38 struct cached_batch_item
{
39 struct cached_batch_item
*next
;
44 static void clear_cache( struct intel_context
*intel
)
46 struct cached_batch_item
*item
= intel
->batch
.cached_items
;
49 struct cached_batch_item
*next
= item
->next
;
54 intel
->batch
.cached_items
= NULL
;
58 intel_batchbuffer_init(struct intel_context
*intel
)
60 intel_batchbuffer_reset(intel
);
62 if (intel
->gen
>= 6) {
63 /* We can't just use brw_state_batch to get a chunk of space for
64 * the gen6 workaround because it involves actually writing to
65 * the buffer, and the kernel doesn't let us write to the batch.
67 intel
->batch
.workaround_bo
= drm_intel_bo_alloc(intel
->bufmgr
,
68 "pipe_control workaround",
72 if (!intel
->has_llc
) {
73 intel
->batch
.cpu_map
= malloc(BATCH_SZ
);
74 intel
->batch
.map
= intel
->batch
.cpu_map
;
79 intel_batchbuffer_reset(struct intel_context
*intel
)
81 if (intel
->batch
.last_bo
!= NULL
) {
82 drm_intel_bo_unreference(intel
->batch
.last_bo
);
83 intel
->batch
.last_bo
= NULL
;
85 intel
->batch
.last_bo
= intel
->batch
.bo
;
89 intel
->batch
.bo
= drm_intel_bo_alloc(intel
->bufmgr
, "batchbuffer",
92 drm_intel_bo_map(intel
->batch
.bo
, true);
93 intel
->batch
.map
= intel
->batch
.bo
->virtual;
96 intel
->batch
.reserved_space
= BATCH_RESERVED
;
97 intel
->batch
.state_batch_offset
= intel
->batch
.bo
->size
;
98 intel
->batch
.used
= 0;
99 intel
->batch
.needs_sol_reset
= false;
103 intel_batchbuffer_save_state(struct intel_context
*intel
)
105 intel
->batch
.saved
.used
= intel
->batch
.used
;
106 intel
->batch
.saved
.reloc_count
=
107 drm_intel_gem_bo_get_reloc_count(intel
->batch
.bo
);
111 intel_batchbuffer_reset_to_saved(struct intel_context
*intel
)
113 drm_intel_gem_bo_clear_relocs(intel
->batch
.bo
, intel
->batch
.saved
.reloc_count
);
115 intel
->batch
.used
= intel
->batch
.saved
.used
;
117 /* Cached batch state is dead, since we just cleared some unknown part of the
118 * batchbuffer. Assume that the caller resets any other state necessary.
124 intel_batchbuffer_free(struct intel_context
*intel
)
126 free(intel
->batch
.cpu_map
);
127 drm_intel_bo_unreference(intel
->batch
.last_bo
);
128 drm_intel_bo_unreference(intel
->batch
.bo
);
129 drm_intel_bo_unreference(intel
->batch
.workaround_bo
);
134 do_batch_dump(struct intel_context
*intel
)
136 struct drm_intel_decode
*decode
;
137 struct intel_batchbuffer
*batch
= &intel
->batch
;
140 decode
= drm_intel_decode_context_alloc(intel
->intelScreen
->deviceID
);
144 ret
= drm_intel_bo_map(batch
->bo
, false);
146 drm_intel_decode_set_batch_pointer(decode
,
152 "WARNING: failed to map batchbuffer (%s), "
153 "dumping uploaded data instead.\n", strerror(ret
));
155 drm_intel_decode_set_batch_pointer(decode
,
161 drm_intel_decode(decode
);
163 drm_intel_decode_context_free(decode
);
166 drm_intel_bo_unmap(batch
->bo
);
168 brw_debug_batch(intel
);
172 /* TODO: Push this whole function into bufmgr.
175 do_flush_locked(struct intel_context
*intel
)
177 struct intel_batchbuffer
*batch
= &intel
->batch
;
180 if (intel
->has_llc
) {
181 drm_intel_bo_unmap(batch
->bo
);
183 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
184 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
185 ret
= drm_intel_bo_subdata(batch
->bo
,
186 batch
->state_batch_offset
,
187 batch
->bo
->size
- batch
->state_batch_offset
,
188 (char *)batch
->map
+ batch
->state_batch_offset
);
192 if (!intel
->intelScreen
->no_hw
) {
195 if (intel
->gen
< 6 || !batch
->is_blit
) {
196 flags
= I915_EXEC_RENDER
;
198 flags
= I915_EXEC_BLT
;
201 if (batch
->needs_sol_reset
)
202 flags
|= I915_EXEC_GEN7_SOL_RESET
;
205 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
206 brw_annotate_aub(intel
);
207 if (intel
->hw_ctx
== NULL
|| batch
->is_blit
) {
208 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
211 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, intel
->hw_ctx
,
212 4 * batch
->used
, flags
);
217 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
218 do_batch_dump(intel
);
221 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
224 intel
->vtbl
.new_batch(intel
);
230 _intel_batchbuffer_flush(struct intel_context
*intel
,
231 const char *file
, int line
)
235 if (intel
->batch
.used
== 0)
238 if (intel
->first_post_swapbuffers_batch
== NULL
) {
239 intel
->first_post_swapbuffers_batch
= intel
->batch
.bo
;
240 drm_intel_bo_reference(intel
->first_post_swapbuffers_batch
);
243 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
244 fprintf(stderr
, "%s:%d: Batchbuffer flush with %db used\n", file
, line
,
245 4*intel
->batch
.used
);
247 intel
->batch
.reserved_space
= 0;
249 if (intel
->vtbl
.finish_batch
)
250 intel
->vtbl
.finish_batch(intel
);
252 /* Mark the end of the buffer. */
253 intel_batchbuffer_emit_dword(intel
, MI_BATCH_BUFFER_END
);
254 if (intel
->batch
.used
& 1) {
255 /* Round batchbuffer usage to 2 DWORDs. */
256 intel_batchbuffer_emit_dword(intel
, MI_NOOP
);
259 intel_upload_finish(intel
);
261 /* Check that we didn't just wrap our batchbuffer at a bad time. */
262 assert(!intel
->no_batch_wrap
);
264 ret
= do_flush_locked(intel
);
266 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
267 fprintf(stderr
, "waiting for idle\n");
268 drm_intel_bo_wait_rendering(intel
->batch
.bo
);
273 intel_batchbuffer_reset(intel
);
279 /* This is the only way buffers get added to the validate list.
282 intel_batchbuffer_emit_reloc(struct intel_context
*intel
,
283 drm_intel_bo
*buffer
,
284 uint32_t read_domains
, uint32_t write_domain
,
289 ret
= drm_intel_bo_emit_reloc(intel
->batch
.bo
, 4*intel
->batch
.used
,
291 read_domains
, write_domain
);
296 * Using the old buffer offset, write in what the right data would be, in case
297 * the buffer doesn't move and we can short-circuit the relocation processing
300 intel_batchbuffer_emit_dword(intel
, buffer
->offset
+ delta
);
306 intel_batchbuffer_emit_reloc_fenced(struct intel_context
*intel
,
307 drm_intel_bo
*buffer
,
308 uint32_t read_domains
,
309 uint32_t write_domain
,
314 ret
= drm_intel_bo_emit_reloc_fence(intel
->batch
.bo
, 4*intel
->batch
.used
,
316 read_domains
, write_domain
);
321 * Using the old buffer offset, write in what the right data would
322 * be, in case the buffer doesn't move and we can short-circuit the
323 * relocation processing in the kernel
325 intel_batchbuffer_emit_dword(intel
, buffer
->offset
+ delta
);
331 intel_batchbuffer_data(struct intel_context
*intel
,
332 const void *data
, GLuint bytes
, bool is_blit
)
334 assert((bytes
& 3) == 0);
335 intel_batchbuffer_require_space(intel
, bytes
, is_blit
);
336 __memcpy(intel
->batch
.map
+ intel
->batch
.used
, data
, bytes
);
337 intel
->batch
.used
+= bytes
>> 2;
341 intel_batchbuffer_cached_advance(struct intel_context
*intel
)
343 struct cached_batch_item
**prev
= &intel
->batch
.cached_items
, *item
;
344 uint32_t sz
= (intel
->batch
.used
- intel
->batch
.emit
) * sizeof(uint32_t);
345 uint32_t *start
= intel
->batch
.map
+ intel
->batch
.emit
;
346 uint16_t op
= *start
>> 16;
352 old
= intel
->batch
.map
+ item
->header
;
353 if (op
== *old
>> 16) {
354 if (item
->size
== sz
&& memcmp(old
, start
, sz
) == 0) {
355 if (prev
!= &intel
->batch
.cached_items
) {
357 item
->next
= intel
->batch
.cached_items
;
358 intel
->batch
.cached_items
= item
;
360 intel
->batch
.used
= intel
->batch
.emit
;
369 item
= malloc(sizeof(struct cached_batch_item
));
373 item
->next
= intel
->batch
.cached_items
;
374 intel
->batch
.cached_items
= item
;
378 item
->header
= intel
->batch
.emit
;
382 * Restriction [DevSNB, DevIVB]:
384 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
385 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
386 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
387 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
388 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
389 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
390 * unless SW can otherwise guarantee that the pipeline from WM onwards is
391 * already flushed (e.g., via a preceding MI_FLUSH).
394 intel_emit_depth_stall_flushes(struct intel_context
*intel
)
396 assert(intel
->gen
>= 6 && intel
->gen
<= 7);
399 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
400 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
401 OUT_BATCH(0); /* address */
402 OUT_BATCH(0); /* write data */
406 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
407 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
408 OUT_BATCH(0); /* address */
409 OUT_BATCH(0); /* write data */
413 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
414 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
415 OUT_BATCH(0); /* address */
416 OUT_BATCH(0); /* write data */
421 * From the BSpec, volume 2a.03: VS Stage Input / State:
422 * "[DevIVB] A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
423 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
424 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
425 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
426 * to be sent before any combination of VS associated 3DSTATE."
429 gen7_emit_vs_workaround_flush(struct intel_context
*intel
)
431 assert(intel
->gen
== 7);
434 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
435 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE
);
436 OUT_RELOC(intel
->batch
.workaround_bo
,
437 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
438 OUT_BATCH(0); /* write data */
443 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
444 * implementing two workarounds on gen6. From section 1.4.7.1
445 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
447 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
448 * produced by non-pipelined state commands), software needs to first
449 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
452 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
453 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
455 * And the workaround for these two requires this workaround first:
457 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
458 * BEFORE the pipe-control with a post-sync op and no write-cache
461 * And this last workaround is tricky because of the requirements on
462 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
465 * "1 of the following must also be set:
466 * - Render Target Cache Flush Enable ([12] of DW1)
467 * - Depth Cache Flush Enable ([0] of DW1)
468 * - Stall at Pixel Scoreboard ([1] of DW1)
469 * - Depth Stall ([13] of DW1)
470 * - Post-Sync Operation ([13] of DW1)
471 * - Notify Enable ([8] of DW1)"
473 * The cache flushes require the workaround flush that triggered this
474 * one, so we can't use it. Depth stall would trigger the same.
475 * Post-sync nonzero is what triggered this second workaround, so we
476 * can't use that one either. Notify enable is IRQs, which aren't
477 * really our business. That leaves only stall at scoreboard.
480 intel_emit_post_sync_nonzero_flush(struct intel_context
*intel
)
482 if (!intel
->batch
.need_workaround_flush
)
486 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
487 OUT_BATCH(PIPE_CONTROL_CS_STALL
|
488 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
489 OUT_BATCH(0); /* address */
490 OUT_BATCH(0); /* write data */
494 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
495 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE
);
496 OUT_RELOC(intel
->batch
.workaround_bo
,
497 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
498 OUT_BATCH(0); /* write data */
501 intel
->batch
.need_workaround_flush
= false;
504 /* Emit a pipelined flush to either flush render and texture cache for
505 * reading from a FBO-drawn texture, or flush so that frontbuffer
506 * render appears on the screen in DRI1.
508 * This is also used for the always_flush_cache driconf debug option.
511 intel_batchbuffer_emit_mi_flush(struct intel_context
*intel
)
513 if (intel
->gen
>= 6) {
514 if (intel
->batch
.is_blit
) {
516 OUT_BATCH(MI_FLUSH_DW
);
522 if (intel
->gen
== 6) {
523 /* Hardware workaround: SNB B-Spec says:
525 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
526 * Flush Enable =1, a PIPE_CONTROL with any non-zero
527 * post-sync-op is required.
529 intel_emit_post_sync_nonzero_flush(intel
);
533 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
534 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH
|
535 PIPE_CONTROL_WRITE_FLUSH
|
536 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
537 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
538 PIPE_CONTROL_TC_FLUSH
|
539 PIPE_CONTROL_NO_WRITE
|
540 PIPE_CONTROL_CS_STALL
);
541 OUT_BATCH(0); /* write address */
542 OUT_BATCH(0); /* write data */
547 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2) |
548 PIPE_CONTROL_WRITE_FLUSH
|
549 PIPE_CONTROL_NO_WRITE
);
550 OUT_BATCH(0); /* write address */
551 OUT_BATCH(0); /* write data */
552 OUT_BATCH(0); /* write data */