1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "brw_context.h"
36 intel_batchbuffer_reset(struct brw_context
*brw
);
38 struct cached_batch_item
{
39 struct cached_batch_item
*next
;
45 clear_cache(struct brw_context
*brw
)
47 struct cached_batch_item
*item
= brw
->batch
.cached_items
;
50 struct cached_batch_item
*next
= item
->next
;
55 brw
->batch
.cached_items
= NULL
;
59 intel_batchbuffer_init(struct brw_context
*brw
)
61 intel_batchbuffer_reset(brw
);
64 /* We can't just use brw_state_batch to get a chunk of space for
65 * the gen6 workaround because it involves actually writing to
66 * the buffer, and the kernel doesn't let us write to the batch.
68 brw
->batch
.workaround_bo
= drm_intel_bo_alloc(brw
->bufmgr
,
69 "pipe_control workaround",
74 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
75 brw
->batch
.map
= brw
->batch
.cpu_map
;
80 intel_batchbuffer_reset(struct brw_context
*brw
)
82 if (brw
->batch
.last_bo
!= NULL
) {
83 drm_intel_bo_unreference(brw
->batch
.last_bo
);
84 brw
->batch
.last_bo
= NULL
;
86 brw
->batch
.last_bo
= brw
->batch
.bo
;
90 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
93 drm_intel_bo_map(brw
->batch
.bo
, true);
94 brw
->batch
.map
= brw
->batch
.bo
->virtual;
97 brw
->batch
.reserved_space
= BATCH_RESERVED
;
98 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
100 brw
->batch
.needs_sol_reset
= false;
104 intel_batchbuffer_save_state(struct brw_context
*brw
)
106 brw
->batch
.saved
.used
= brw
->batch
.used
;
107 brw
->batch
.saved
.reloc_count
=
108 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
112 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
114 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
116 brw
->batch
.used
= brw
->batch
.saved
.used
;
118 /* Cached batch state is dead, since we just cleared some unknown part of the
119 * batchbuffer. Assume that the caller resets any other state necessary.
125 intel_batchbuffer_free(struct brw_context
*brw
)
127 free(brw
->batch
.cpu_map
);
128 drm_intel_bo_unreference(brw
->batch
.last_bo
);
129 drm_intel_bo_unreference(brw
->batch
.bo
);
130 drm_intel_bo_unreference(brw
->batch
.workaround_bo
);
135 do_batch_dump(struct brw_context
*brw
)
137 struct drm_intel_decode
*decode
;
138 struct intel_batchbuffer
*batch
= &brw
->batch
;
141 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
145 ret
= drm_intel_bo_map(batch
->bo
, false);
147 drm_intel_decode_set_batch_pointer(decode
,
153 "WARNING: failed to map batchbuffer (%s), "
154 "dumping uploaded data instead.\n", strerror(ret
));
156 drm_intel_decode_set_batch_pointer(decode
,
162 drm_intel_decode(decode
);
164 drm_intel_decode_context_free(decode
);
167 drm_intel_bo_unmap(batch
->bo
);
169 brw_debug_batch(brw
);
173 /* TODO: Push this whole function into bufmgr.
176 do_flush_locked(struct brw_context
*brw
)
178 struct intel_batchbuffer
*batch
= &brw
->batch
;
182 drm_intel_bo_unmap(batch
->bo
);
184 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
185 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
186 ret
= drm_intel_bo_subdata(batch
->bo
,
187 batch
->state_batch_offset
,
188 batch
->bo
->size
- batch
->state_batch_offset
,
189 (char *)batch
->map
+ batch
->state_batch_offset
);
193 if (!brw
->intelScreen
->no_hw
) {
196 if (brw
->gen
< 6 || !batch
->is_blit
) {
197 flags
= I915_EXEC_RENDER
;
199 flags
= I915_EXEC_BLT
;
202 if (batch
->needs_sol_reset
)
203 flags
|= I915_EXEC_GEN7_SOL_RESET
;
206 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
207 brw_annotate_aub(brw
);
208 if (brw
->hw_ctx
== NULL
|| batch
->is_blit
) {
209 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
212 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
213 4 * batch
->used
, flags
);
218 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
222 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
225 brw
->vtbl
.new_batch(brw
);
231 _intel_batchbuffer_flush(struct brw_context
*brw
,
232 const char *file
, int line
)
236 if (brw
->batch
.used
== 0)
239 if (brw
->first_post_swapbuffers_batch
== NULL
) {
240 brw
->first_post_swapbuffers_batch
= brw
->batch
.bo
;
241 drm_intel_bo_reference(brw
->first_post_swapbuffers_batch
);
244 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
245 int bytes_for_commands
= 4 * brw
->batch
.used
;
246 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
247 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
248 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
249 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
250 bytes_for_commands
, bytes_for_state
,
252 100.0f
* total_bytes
/ BATCH_SZ
);
255 brw
->batch
.reserved_space
= 0;
257 if (brw
->vtbl
.finish_batch
)
258 brw
->vtbl
.finish_batch(brw
);
260 /* Mark the end of the buffer. */
261 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
262 if (brw
->batch
.used
& 1) {
263 /* Round batchbuffer usage to 2 DWORDs. */
264 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
267 intel_upload_finish(brw
);
269 /* Check that we didn't just wrap our batchbuffer at a bad time. */
270 assert(!brw
->no_batch_wrap
);
272 ret
= do_flush_locked(brw
);
274 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
275 fprintf(stderr
, "waiting for idle\n");
276 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
281 intel_batchbuffer_reset(brw
);
287 /* This is the only way buffers get added to the validate list.
290 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
291 drm_intel_bo
*buffer
,
292 uint32_t read_domains
, uint32_t write_domain
,
297 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
299 read_domains
, write_domain
);
304 * Using the old buffer offset, write in what the right data would be, in case
305 * the buffer doesn't move and we can short-circuit the relocation processing
308 intel_batchbuffer_emit_dword(brw
, buffer
->offset
+ delta
);
314 intel_batchbuffer_emit_reloc_fenced(struct brw_context
*brw
,
315 drm_intel_bo
*buffer
,
316 uint32_t read_domains
,
317 uint32_t write_domain
,
322 ret
= drm_intel_bo_emit_reloc_fence(brw
->batch
.bo
, 4*brw
->batch
.used
,
324 read_domains
, write_domain
);
329 * Using the old buffer offset, write in what the right data would
330 * be, in case the buffer doesn't move and we can short-circuit the
331 * relocation processing in the kernel
333 intel_batchbuffer_emit_dword(brw
, buffer
->offset
+ delta
);
339 intel_batchbuffer_data(struct brw_context
*brw
,
340 const void *data
, GLuint bytes
, bool is_blit
)
342 assert((bytes
& 3) == 0);
343 intel_batchbuffer_require_space(brw
, bytes
, is_blit
);
344 __memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
345 brw
->batch
.used
+= bytes
>> 2;
349 intel_batchbuffer_cached_advance(struct brw_context
*brw
)
351 struct cached_batch_item
**prev
= &brw
->batch
.cached_items
, *item
;
352 uint32_t sz
= (brw
->batch
.used
- brw
->batch
.emit
) * sizeof(uint32_t);
353 uint32_t *start
= brw
->batch
.map
+ brw
->batch
.emit
;
354 uint16_t op
= *start
>> 16;
360 old
= brw
->batch
.map
+ item
->header
;
361 if (op
== *old
>> 16) {
362 if (item
->size
== sz
&& memcmp(old
, start
, sz
) == 0) {
363 if (prev
!= &brw
->batch
.cached_items
) {
365 item
->next
= brw
->batch
.cached_items
;
366 brw
->batch
.cached_items
= item
;
368 brw
->batch
.used
= brw
->batch
.emit
;
377 item
= malloc(sizeof(struct cached_batch_item
));
381 item
->next
= brw
->batch
.cached_items
;
382 brw
->batch
.cached_items
= item
;
386 item
->header
= brw
->batch
.emit
;
390 * Restriction [DevSNB, DevIVB]:
392 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
393 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
394 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
395 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
396 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
397 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
398 * unless SW can otherwise guarantee that the pipeline from WM onwards is
399 * already flushed (e.g., via a preceding MI_FLUSH).
402 intel_emit_depth_stall_flushes(struct brw_context
*brw
)
404 assert(brw
->gen
>= 6 && brw
->gen
<= 7);
407 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
408 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
409 OUT_BATCH(0); /* address */
410 OUT_BATCH(0); /* write data */
414 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
415 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
416 OUT_BATCH(0); /* address */
417 OUT_BATCH(0); /* write data */
421 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
422 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
423 OUT_BATCH(0); /* address */
424 OUT_BATCH(0); /* write data */
429 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
430 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
431 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
432 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
433 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
434 * to be sent before any combination of VS associated 3DSTATE."
437 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
439 assert(brw
->gen
== 7);
442 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
443 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE
);
444 OUT_RELOC(brw
->batch
.workaround_bo
,
445 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
446 OUT_BATCH(0); /* write data */
451 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
452 * implementing two workarounds on gen6. From section 1.4.7.1
453 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
455 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
456 * produced by non-pipelined state commands), software needs to first
457 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
460 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
461 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
463 * And the workaround for these two requires this workaround first:
465 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
466 * BEFORE the pipe-control with a post-sync op and no write-cache
469 * And this last workaround is tricky because of the requirements on
470 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
473 * "1 of the following must also be set:
474 * - Render Target Cache Flush Enable ([12] of DW1)
475 * - Depth Cache Flush Enable ([0] of DW1)
476 * - Stall at Pixel Scoreboard ([1] of DW1)
477 * - Depth Stall ([13] of DW1)
478 * - Post-Sync Operation ([13] of DW1)
479 * - Notify Enable ([8] of DW1)"
481 * The cache flushes require the workaround flush that triggered this
482 * one, so we can't use it. Depth stall would trigger the same.
483 * Post-sync nonzero is what triggered this second workaround, so we
484 * can't use that one either. Notify enable is IRQs, which aren't
485 * really our business. That leaves only stall at scoreboard.
488 intel_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
490 if (!brw
->batch
.need_workaround_flush
)
494 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
495 OUT_BATCH(PIPE_CONTROL_CS_STALL
|
496 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
497 OUT_BATCH(0); /* address */
498 OUT_BATCH(0); /* write data */
502 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
503 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE
);
504 OUT_RELOC(brw
->batch
.workaround_bo
,
505 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
506 OUT_BATCH(0); /* write data */
509 brw
->batch
.need_workaround_flush
= false;
512 /* Emit a pipelined flush to either flush render and texture cache for
513 * reading from a FBO-drawn texture, or flush so that frontbuffer
514 * render appears on the screen in DRI1.
516 * This is also used for the always_flush_cache driconf debug option.
519 intel_batchbuffer_emit_mi_flush(struct brw_context
*brw
)
522 if (brw
->batch
.is_blit
) {
524 OUT_BATCH(MI_FLUSH_DW
);
531 /* Hardware workaround: SNB B-Spec says:
533 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
534 * Flush Enable =1, a PIPE_CONTROL with any non-zero
535 * post-sync-op is required.
537 intel_emit_post_sync_nonzero_flush(brw
);
541 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
542 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH
|
543 PIPE_CONTROL_WRITE_FLUSH
|
544 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
545 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
546 PIPE_CONTROL_TC_FLUSH
|
547 PIPE_CONTROL_NO_WRITE
|
548 PIPE_CONTROL_CS_STALL
);
549 OUT_BATCH(0); /* write address */
550 OUT_BATCH(0); /* write data */
555 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2) |
556 PIPE_CONTROL_WRITE_FLUSH
|
557 PIPE_CONTROL_NO_WRITE
);
558 OUT_BATCH(0); /* write address */
559 OUT_BATCH(0); /* write data */
560 OUT_BATCH(0); /* write data */