2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
35 #include "common/gen_gem.h"
37 #include "util/hash_table.h"
42 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
45 * Target sizes of the batch and state buffers. We create the initial
46 * buffers at these sizes, and flush when they're nearly full. If we
47 * underestimate how close we are to the end, and suddenly need more space
48 * in the middle of a draw, we can grow the buffers, and finish the draw.
49 * At that point, we'll be over our target size, so the next operation
50 * should flush. Each time we flush the batch, we recreate both buffers
51 * at the original target size, so it doesn't grow without bound.
53 #define BATCH_SZ (20 * 1024)
54 #define STATE_SZ (16 * 1024)
57 intel_batchbuffer_reset(struct brw_context
*brw
);
59 brw_new_batch(struct brw_context
*brw
);
62 dump_validation_list(struct intel_batchbuffer
*batch
)
64 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
66 for (int i
= 0; i
< batch
->exec_count
; i
++) {
67 uint64_t flags
= batch
->validation_list
[i
].flags
;
68 assert(batch
->validation_list
[i
].handle
==
69 batch
->exec_bos
[i
]->gem_handle
);
70 fprintf(stderr
, "[%2d]: %2d %-14s %p %s%-7s @ 0x%016llx%s (%"PRIu64
"B)\n",
72 batch
->validation_list
[i
].handle
,
73 batch
->exec_bos
[i
]->name
,
75 (flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) ? "(48b" : "(32b",
76 (flags
& EXEC_OBJECT_WRITE
) ? " write)" : ")",
77 batch
->validation_list
[i
].offset
,
78 (flags
& EXEC_OBJECT_PINNED
) ? " (pinned)" : "",
79 batch
->exec_bos
[i
]->size
);
83 static struct gen_batch_decode_bo
84 decode_get_bo(void *v_brw
, uint64_t address
)
86 struct brw_context
*brw
= v_brw
;
87 struct intel_batchbuffer
*batch
= &brw
->batch
;
89 for (int i
= 0; i
< batch
->exec_count
; i
++) {
90 struct brw_bo
*bo
= batch
->exec_bos
[i
];
91 /* The decoder zeroes out the top 16 bits, so we need to as well */
92 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
94 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
95 return (struct gen_batch_decode_bo
) {
98 .map
= brw_bo_map(brw
, bo
, MAP_READ
) + (address
- bo_address
),
103 return (struct gen_batch_decode_bo
) { };
107 decode_get_state_size(void *v_brw
, uint32_t offset_from_dsba
)
109 struct brw_context
*brw
= v_brw
;
110 struct intel_batchbuffer
*batch
= &brw
->batch
;
111 struct hash_entry
*entry
=
112 _mesa_hash_table_search(batch
->state_batch_sizes
,
113 (void *) (uintptr_t) offset_from_dsba
);
114 return entry
? (uintptr_t) entry
->data
: 0;
118 uint_key_compare(const void *a
, const void *b
)
124 uint_key_hash(const void *key
)
126 return (uintptr_t) key
;
130 init_reloc_list(struct brw_reloc_list
*rlist
, int count
)
132 rlist
->reloc_count
= 0;
133 rlist
->reloc_array_size
= count
;
134 rlist
->relocs
= malloc(rlist
->reloc_array_size
*
135 sizeof(struct drm_i915_gem_relocation_entry
));
139 intel_batchbuffer_init(struct brw_context
*brw
)
141 struct intel_screen
*screen
= brw
->screen
;
142 struct intel_batchbuffer
*batch
= &brw
->batch
;
143 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
145 batch
->use_shadow_copy
= !devinfo
->has_llc
;
147 init_reloc_list(&batch
->batch_relocs
, 250);
148 init_reloc_list(&batch
->state_relocs
, 250);
150 batch
->batch
.map
= NULL
;
151 batch
->state
.map
= NULL
;
152 batch
->exec_count
= 0;
153 batch
->exec_array_size
= 100;
155 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
156 batch
->validation_list
=
157 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
159 if (INTEL_DEBUG
& DEBUG_BATCH
) {
160 batch
->state_batch_sizes
=
161 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
163 const unsigned decode_flags
=
164 GEN_BATCH_DECODE_FULL
|
165 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
166 GEN_BATCH_DECODE_OFFSETS
|
167 GEN_BATCH_DECODE_FLOATS
;
169 gen_batch_decode_ctx_init(&batch
->decoder
, devinfo
, stderr
,
170 decode_flags
, NULL
, decode_get_bo
,
171 decode_get_state_size
, brw
);
172 batch
->decoder
.max_vbo_decoded_lines
= 100;
175 batch
->use_batch_first
=
176 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
178 /* PIPE_CONTROL needs a w/a but only on gen6 */
179 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
180 if (devinfo
->gen
== 6)
181 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
183 intel_batchbuffer_reset(brw
);
186 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
189 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
191 unsigned index
= READ_ONCE(bo
->index
);
193 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
196 /* May have been shared between multiple active batches */
197 for (index
= 0; index
< batch
->exec_count
; index
++) {
198 if (batch
->exec_bos
[index
] == bo
)
202 brw_bo_reference(bo
);
204 if (batch
->exec_count
== batch
->exec_array_size
) {
205 batch
->exec_array_size
*= 2;
207 realloc(batch
->exec_bos
,
208 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
209 batch
->validation_list
=
210 realloc(batch
->validation_list
,
211 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
214 batch
->validation_list
[batch
->exec_count
] =
215 (struct drm_i915_gem_exec_object2
) {
216 .handle
= bo
->gem_handle
,
217 .offset
= bo
->gtt_offset
,
221 bo
->index
= batch
->exec_count
;
222 batch
->exec_bos
[batch
->exec_count
] = bo
;
223 batch
->aperture_space
+= bo
->size
;
225 return batch
->exec_count
++;
229 recreate_growing_buffer(struct brw_context
*brw
,
230 struct brw_growing_bo
*grow
,
231 const char *name
, unsigned size
,
232 enum brw_memory_zone memzone
)
234 struct intel_screen
*screen
= brw
->screen
;
235 struct intel_batchbuffer
*batch
= &brw
->batch
;
236 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
238 /* We can't grow buffers when using softpin, so just overallocate them. */
239 if (brw_using_softpin(bufmgr
))
242 grow
->bo
= brw_bo_alloc(bufmgr
, name
, size
, memzone
);
243 grow
->bo
->kflags
|= can_do_exec_capture(screen
) ? EXEC_OBJECT_CAPTURE
: 0;
244 grow
->partial_bo
= NULL
;
245 grow
->partial_bo_map
= NULL
;
246 grow
->partial_bytes
= 0;
247 grow
->memzone
= memzone
;
249 if (batch
->use_shadow_copy
)
250 grow
->map
= realloc(grow
->map
, grow
->bo
->size
);
252 grow
->map
= brw_bo_map(brw
, grow
->bo
, MAP_READ
| MAP_WRITE
);
256 intel_batchbuffer_reset(struct brw_context
*brw
)
258 struct intel_batchbuffer
*batch
= &brw
->batch
;
260 if (batch
->last_bo
!= NULL
) {
261 brw_bo_unreference(batch
->last_bo
);
262 batch
->last_bo
= NULL
;
264 batch
->last_bo
= batch
->batch
.bo
;
266 recreate_growing_buffer(brw
, &batch
->batch
, "batchbuffer", BATCH_SZ
,
268 batch
->map_next
= batch
->batch
.map
;
270 recreate_growing_buffer(brw
, &batch
->state
, "statebuffer", STATE_SZ
,
271 BRW_MEMZONE_DYNAMIC
);
273 /* Avoid making 0 a valid state offset - otherwise the decoder will try
274 * and decode data when we use offset 0 as a null pointer.
276 batch
->state_used
= 1;
278 add_exec_bo(batch
, batch
->batch
.bo
);
279 assert(batch
->batch
.bo
->index
== 0);
281 batch
->needs_sol_reset
= false;
282 batch
->state_base_address_emitted
= false;
284 if (batch
->state_batch_sizes
)
285 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
289 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
291 intel_batchbuffer_reset(brw
);
292 brw_cache_sets_clear(brw
);
296 intel_batchbuffer_save_state(struct brw_context
*brw
)
298 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
299 brw
->batch
.saved
.batch_reloc_count
= brw
->batch
.batch_relocs
.reloc_count
;
300 brw
->batch
.saved
.state_reloc_count
= brw
->batch
.state_relocs
.reloc_count
;
301 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
305 intel_batchbuffer_saved_state_is_empty(struct brw_context
*brw
)
307 struct intel_batchbuffer
*batch
= &brw
->batch
;
308 return (batch
->saved
.map_next
== batch
->batch
.map
);
312 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
314 for (int i
= brw
->batch
.saved
.exec_count
;
315 i
< brw
->batch
.exec_count
; i
++) {
316 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
318 brw
->batch
.batch_relocs
.reloc_count
= brw
->batch
.saved
.batch_reloc_count
;
319 brw
->batch
.state_relocs
.reloc_count
= brw
->batch
.saved
.state_reloc_count
;
320 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
322 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
323 if (USED_BATCH(brw
->batch
) == 0)
328 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
330 if (batch
->use_shadow_copy
) {
331 free(batch
->batch
.map
);
332 free(batch
->state
.map
);
335 for (int i
= 0; i
< batch
->exec_count
; i
++) {
336 brw_bo_unreference(batch
->exec_bos
[i
]);
338 free(batch
->batch_relocs
.relocs
);
339 free(batch
->state_relocs
.relocs
);
340 free(batch
->exec_bos
);
341 free(batch
->validation_list
);
343 brw_bo_unreference(batch
->last_bo
);
344 brw_bo_unreference(batch
->batch
.bo
);
345 brw_bo_unreference(batch
->state
.bo
);
346 if (batch
->state_batch_sizes
) {
347 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
348 gen_batch_decode_ctx_finish(&batch
->decoder
);
353 * Finish copying the old batch/state buffer's contents to the new one
354 * after we tried to "grow" the buffer in an earlier operation.
357 finish_growing_bos(struct brw_growing_bo
*grow
)
359 struct brw_bo
*old_bo
= grow
->partial_bo
;
363 memcpy(grow
->map
, grow
->partial_bo_map
, grow
->partial_bytes
);
365 grow
->partial_bo
= NULL
;
366 grow
->partial_bo_map
= NULL
;
367 grow
->partial_bytes
= 0;
369 brw_bo_unreference(old_bo
);
373 replace_bo_in_reloc_list(struct brw_reloc_list
*rlist
,
374 uint32_t old_handle
, uint32_t new_handle
)
376 for (int i
= 0; i
< rlist
->reloc_count
; i
++) {
377 if (rlist
->relocs
[i
].target_handle
== old_handle
)
378 rlist
->relocs
[i
].target_handle
= new_handle
;
383 * Grow either the batch or state buffer to a new larger size.
385 * We can't actually grow buffers, so we allocate a new one, copy over
386 * the existing contents, and update our lists to refer to the new one.
388 * Note that this is only temporary - each new batch recreates the buffers
389 * at their original target size (BATCH_SZ or STATE_SZ).
392 grow_buffer(struct brw_context
*brw
,
393 struct brw_growing_bo
*grow
,
394 unsigned existing_bytes
,
397 struct intel_batchbuffer
*batch
= &brw
->batch
;
398 struct brw_bufmgr
*bufmgr
= brw
->bufmgr
;
399 struct brw_bo
*bo
= grow
->bo
;
401 /* We can't grow buffers that are softpinned, as the growing mechanism
402 * involves putting a larger buffer at the same gtt_offset...and we've
403 * only allocated the smaller amount of VMA. Without relocations, this
404 * simply won't work. This should never happen, however.
406 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
408 perf_debug("Growing %s - ran out of space\n", bo
->name
);
410 if (grow
->partial_bo
) {
411 /* We've already grown once, and now we need to do it again.
412 * Finish our last grow operation so we can start a new one.
413 * This should basically never happen.
415 perf_debug("Had to grow multiple times");
416 finish_growing_bos(grow
);
419 struct brw_bo
*new_bo
=
420 brw_bo_alloc(bufmgr
, bo
->name
, new_size
, grow
->memzone
);
422 /* Copy existing data to the new larger buffer */
423 grow
->partial_bo_map
= grow
->map
;
425 if (batch
->use_shadow_copy
) {
426 /* We can't safely use realloc, as it may move the existing buffer,
427 * breaking existing pointers the caller may still be using. Just
428 * malloc a new copy and memcpy it like the normal BO path.
430 * Use bo->size rather than new_size because the bufmgr may have
431 * rounded up the size, and we want the shadow size to match.
433 grow
->map
= malloc(new_bo
->size
);
435 grow
->map
= brw_bo_map(brw
, new_bo
, MAP_READ
| MAP_WRITE
);
438 /* Try to put the new BO at the same GTT offset as the old BO (which
439 * we're throwing away, so it doesn't need to be there).
441 * This guarantees that our relocations continue to work: values we've
442 * already written into the buffer, values we're going to write into the
443 * buffer, and the validation/relocation lists all will match.
445 * Also preserve kflags for EXEC_OBJECT_CAPTURE.
447 new_bo
->gtt_offset
= bo
->gtt_offset
;
448 new_bo
->index
= bo
->index
;
449 new_bo
->kflags
= bo
->kflags
;
451 /* Batch/state buffers are per-context, and if we've run out of space,
452 * we must have actually used them before, so...they will be in the list.
454 assert(bo
->index
< batch
->exec_count
);
455 assert(batch
->exec_bos
[bo
->index
] == bo
);
457 /* Update the validation list to use the new BO. */
458 batch
->validation_list
[bo
->index
].handle
= new_bo
->gem_handle
;
460 if (!batch
->use_batch_first
) {
461 /* We're not using I915_EXEC_HANDLE_LUT, which means we need to go
462 * update the relocation list entries to point at the new BO as well.
463 * (With newer kernels, the "handle" is an offset into the validation
464 * list, which remains unchanged, so we can skip this.)
466 replace_bo_in_reloc_list(&batch
->batch_relocs
,
467 bo
->gem_handle
, new_bo
->gem_handle
);
468 replace_bo_in_reloc_list(&batch
->state_relocs
,
469 bo
->gem_handle
, new_bo
->gem_handle
);
472 /* Exchange the two BOs...without breaking pointers to the old BO.
474 * Consider this scenario:
476 * 1. Somebody calls brw_state_batch() to get a region of memory, and
477 * and then creates a brw_address pointing to brw->batch.state.bo.
478 * 2. They then call brw_state_batch() a second time, which happens to
479 * grow and replace the state buffer. They then try to emit a
480 * relocation to their first section of memory.
482 * If we replace the brw->batch.state.bo pointer at step 2, we would
483 * break the address created in step 1. They'd have a pointer to the
484 * old destroyed BO. Emitting a relocation would add this dead BO to
485 * the validation list...causing /both/ statebuffers to be in the list,
486 * and all kinds of disasters.
488 * This is not a contrived case - BLORP vertex data upload hits this.
490 * There are worse scenarios too. Fences for GL sync objects reference
491 * brw->batch.batch.bo. If we replaced the batch pointer when growing,
492 * we'd need to chase down every fence and update it to point to the
493 * new BO. Otherwise, it would refer to a "batch" that never actually
494 * gets submitted, and would fail to trigger.
496 * To work around both of these issues, we transmutate the buffers in
497 * place, making the existing struct brw_bo represent the new buffer,
498 * and "new_bo" represent the old BO. This is highly unusual, but it
499 * seems like a necessary evil.
501 * We also defer the memcpy of the existing batch's contents. Callers
502 * may make multiple brw_state_batch calls, and retain pointers to the
503 * old BO's map. We'll perform the memcpy in finish_growing_bo() when
504 * we finally submit the batch, at which point we've finished uploading
505 * state, and nobody should have any old references anymore.
507 * To do that, we keep a reference to the old BO in grow->partial_bo,
508 * and store the number of bytes to copy in grow->partial_bytes. We
509 * can monkey with the refcounts directly without atomics because these
510 * are per-context BOs and they can only be touched by this thread.
512 assert(new_bo
->refcount
== 1);
513 new_bo
->refcount
= bo
->refcount
;
517 memcpy(&tmp
, bo
, sizeof(struct brw_bo
));
518 memcpy(bo
, new_bo
, sizeof(struct brw_bo
));
519 memcpy(new_bo
, &tmp
, sizeof(struct brw_bo
));
521 grow
->partial_bo
= new_bo
; /* the one reference of the OLD bo */
522 grow
->partial_bytes
= existing_bytes
;
526 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
)
528 struct intel_batchbuffer
*batch
= &brw
->batch
;
530 const unsigned batch_used
= USED_BATCH(*batch
) * 4;
531 if (batch_used
+ sz
>= BATCH_SZ
&& !batch
->no_wrap
) {
532 intel_batchbuffer_flush(brw
);
533 } else if (batch_used
+ sz
>= batch
->batch
.bo
->size
) {
534 const unsigned new_size
=
535 MIN2(batch
->batch
.bo
->size
+ batch
->batch
.bo
->size
/ 2,
537 grow_buffer(brw
, &batch
->batch
, batch_used
, new_size
);
538 batch
->map_next
= (void *) batch
->batch
.map
+ batch_used
;
539 assert(batch_used
+ sz
< batch
->batch
.bo
->size
);
544 * Called when starting a new batch buffer.
547 brw_new_batch(struct brw_context
*brw
)
549 /* Unreference any BOs held by the previous batch, and reset counts. */
550 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
551 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
552 brw
->batch
.exec_bos
[i
] = NULL
;
554 brw
->batch
.batch_relocs
.reloc_count
= 0;
555 brw
->batch
.state_relocs
.reloc_count
= 0;
556 brw
->batch
.exec_count
= 0;
557 brw
->batch
.aperture_space
= 0;
559 brw_bo_unreference(brw
->batch
.state
.bo
);
561 /* Create a new batchbuffer and reset the associated state: */
562 intel_batchbuffer_reset_and_clear_render_cache(brw
);
564 /* If the kernel supports hardware contexts, then most hardware state is
565 * preserved between batches; we only need to re-emit state that is required
566 * to be in every batch. Otherwise we need to re-emit all the state that
567 * would otherwise be stored in the context (which for all intents and
568 * purposes means everything).
570 if (brw
->hw_ctx
== 0) {
571 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
572 brw_upload_invariant_state(brw
);
575 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
577 brw
->ib
.index_size
= -1;
579 /* We need to periodically reap the shader time results, because rollover
580 * happens every few seconds. We also want to see results every once in a
581 * while, because many programs won't cleanly destroy our context, so the
582 * end-of-run printout may not happen.
584 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
585 brw_collect_and_report_shader_time(brw
);
589 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
592 * This function can emit state (say, to preserve registers that aren't saved
596 brw_finish_batch(struct brw_context
*brw
)
598 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
600 brw
->batch
.no_wrap
= true;
602 /* Capture the closing pipeline statistics register values necessary to
603 * support query objects (in the non-hardware context world).
605 brw_emit_query_end(brw
);
607 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
608 * assume that the L3 cache is configured according to the hardware
609 * defaults. On Kernel 4.16+, we no longer need to do this.
611 if (devinfo
->gen
>= 7 &&
612 !(brw
->screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
))
613 gen7_restore_default_l3_config(brw
);
615 if (devinfo
->is_haswell
) {
616 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
617 * 3DSTATE_CC_STATE_POINTERS > "Note":
619 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
620 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
622 * From the example in the docs, it seems to expect a regular pipe control
623 * flush here as well. We may have done it already, but meh.
625 * See also WaAvoidRCZCounterRollover.
627 brw_emit_mi_flush(brw
);
629 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
630 OUT_BATCH(brw
->cc
.state_offset
| 1);
632 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
633 PIPE_CONTROL_CS_STALL
);
636 /* Do not restore push constant packets during context restore. */
637 if (devinfo
->gen
>= 7)
638 gen10_emit_isp_disable(brw
);
640 /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
641 * requires our batch size to be QWord aligned, so we pad it out if
642 * necessary by emitting an extra MI_NOOP after the end.
644 intel_batchbuffer_require_space(brw
, 8);
645 *brw
->batch
.map_next
++ = MI_BATCH_BUFFER_END
;
646 if (USED_BATCH(brw
->batch
) & 1) {
647 *brw
->batch
.map_next
++ = MI_NOOP
;
650 brw
->batch
.no_wrap
= false;
654 throttle(struct brw_context
*brw
)
656 /* Wait for the swapbuffers before the one we just emitted, so we
657 * don't get too many swaps outstanding for apps that are GPU-heavy
660 * We're using intelDRI2Flush (called from the loader before
661 * swapbuffer) and glFlush (for front buffer rendering) as the
662 * indicator that a frame is done and then throttle when we get
663 * here as we prepare to render the next frame. At this point for
664 * round trips for swap/copy and getting new buffers are done and
665 * we'll spend less time waiting on the GPU.
667 * Unfortunately, we don't have a handle to the batch containing
668 * the swap, and getting our hands on that doesn't seem worth it,
669 * so we just use the first batch we emitted after the last swap.
671 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
672 if (brw
->throttle_batch
[1]) {
673 if (!brw
->disable_throttling
) {
674 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
676 brw_bo_unreference(brw
->throttle_batch
[1]);
678 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
679 brw
->throttle_batch
[0] = NULL
;
680 brw
->need_swap_throttle
= false;
681 /* Throttling here is more precise than the throttle ioctl, so skip it */
682 brw
->need_flush_throttle
= false;
685 if (brw
->need_flush_throttle
) {
686 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
687 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
688 brw
->need_flush_throttle
= false;
694 struct intel_batchbuffer
*batch
,
701 struct drm_i915_gem_execbuffer2 execbuf
= {
702 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
703 .buffer_count
= batch
->exec_count
,
704 .batch_start_offset
= 0,
707 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
710 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
712 if (in_fence
!= -1) {
713 execbuf
.rsvd2
= in_fence
;
714 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
717 if (out_fence
!= NULL
) {
718 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
720 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
723 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
727 for (int i
= 0; i
< batch
->exec_count
; i
++) {
728 struct brw_bo
*bo
= batch
->exec_bos
[i
];
733 /* Update brw_bo::gtt_offset */
734 if (batch
->validation_list
[i
].offset
!= bo
->gtt_offset
) {
735 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
736 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
737 bo
->gem_handle
, bo
->gtt_offset
,
738 batch
->validation_list
[i
].offset
);
739 bo
->gtt_offset
= batch
->validation_list
[i
].offset
;
743 if (ret
== 0 && out_fence
!= NULL
)
744 *out_fence
= execbuf
.rsvd2
>> 32;
750 submit_batch(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
752 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
753 struct intel_batchbuffer
*batch
= &brw
->batch
;
756 if (batch
->use_shadow_copy
) {
757 void *bo_map
= brw_bo_map(brw
, batch
->batch
.bo
, MAP_WRITE
);
758 memcpy(bo_map
, batch
->batch
.map
, 4 * USED_BATCH(*batch
));
760 bo_map
= brw_bo_map(brw
, batch
->state
.bo
, MAP_WRITE
);
761 memcpy(bo_map
, batch
->state
.map
, batch
->state_used
);
764 brw_bo_unmap(batch
->batch
.bo
);
765 brw_bo_unmap(batch
->state
.bo
);
767 if (!brw
->screen
->no_hw
) {
768 /* The requirement for using I915_EXEC_NO_RELOC are:
770 * The addresses written in the objects must match the corresponding
771 * reloc.gtt_offset which in turn must match the corresponding
774 * Any render targets written to in the batch must be flagged with
777 * To avoid stalling, execobject.offset should match the current
778 * address of that object within the active context.
780 int flags
= I915_EXEC_NO_RELOC
| I915_EXEC_RENDER
;
782 if (batch
->needs_sol_reset
)
783 flags
|= I915_EXEC_GEN7_SOL_RESET
;
785 /* Set statebuffer relocations */
786 const unsigned state_index
= batch
->state
.bo
->index
;
787 if (state_index
< batch
->exec_count
&&
788 batch
->exec_bos
[state_index
] == batch
->state
.bo
) {
789 struct drm_i915_gem_exec_object2
*entry
=
790 &batch
->validation_list
[state_index
];
791 assert(entry
->handle
== batch
->state
.bo
->gem_handle
);
792 entry
->relocation_count
= batch
->state_relocs
.reloc_count
;
793 entry
->relocs_ptr
= (uintptr_t) batch
->state_relocs
.relocs
;
796 /* Set batchbuffer relocations */
797 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
798 assert(entry
->handle
== batch
->batch
.bo
->gem_handle
);
799 entry
->relocation_count
= batch
->batch_relocs
.reloc_count
;
800 entry
->relocs_ptr
= (uintptr_t) batch
->batch_relocs
.relocs
;
802 if (batch
->use_batch_first
) {
803 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
805 /* Move the batch to the end of the validation list */
806 struct drm_i915_gem_exec_object2 tmp
;
807 struct brw_bo
*tmp_bo
;
808 const unsigned index
= batch
->exec_count
- 1;
811 *entry
= batch
->validation_list
[index
];
812 batch
->validation_list
[index
] = tmp
;
814 tmp_bo
= batch
->exec_bos
[0];
815 batch
->exec_bos
[0] = batch
->exec_bos
[index
];
816 batch
->exec_bos
[index
] = tmp_bo
;
819 ret
= execbuffer(dri_screen
->fd
, batch
, brw
->hw_ctx
,
820 4 * USED_BATCH(*batch
),
821 in_fence_fd
, out_fence_fd
, flags
);
826 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
827 gen_print_batch(&batch
->decoder
, batch
->batch
.map
,
828 4 * USED_BATCH(*batch
),
829 batch
->batch
.bo
->gtt_offset
);
832 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
833 brw_check_for_reset(brw
);
836 fprintf(stderr
, "i965: Failed to submit batchbuffer: %s\n",
845 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
848 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
849 * of the returned fd.
852 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
853 int in_fence_fd
, int *out_fence_fd
,
854 const char *file
, int line
)
858 if (USED_BATCH(brw
->batch
) == 0)
861 /* Check that we didn't just wrap our batchbuffer at a bad time. */
862 assert(!brw
->batch
.no_wrap
);
864 brw_finish_batch(brw
);
865 brw_upload_finish(&brw
->upload
);
867 finish_growing_bos(&brw
->batch
.batch
);
868 finish_growing_bos(&brw
->batch
.state
);
870 if (brw
->throttle_batch
[0] == NULL
) {
871 brw
->throttle_batch
[0] = brw
->batch
.batch
.bo
;
872 brw_bo_reference(brw
->throttle_batch
[0]);
875 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
876 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
877 int bytes_for_state
= brw
->batch
.state_used
;
878 fprintf(stderr
, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
879 " %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
880 " %4d batch relocs, %4d state relocs\n", file
, line
,
881 bytes_for_commands
, 100.0f
* bytes_for_commands
/ BATCH_SZ
,
882 bytes_for_state
, 100.0f
* bytes_for_state
/ STATE_SZ
,
883 brw
->batch
.exec_count
,
884 (float) (brw
->batch
.aperture_space
/ (1024 * 1024)),
885 brw
->batch
.batch_relocs
.reloc_count
,
886 brw
->batch
.state_relocs
.reloc_count
);
888 dump_validation_list(&brw
->batch
);
891 ret
= submit_batch(brw
, in_fence_fd
, out_fence_fd
);
893 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
894 fprintf(stderr
, "waiting for idle\n");
895 brw_bo_wait_rendering(brw
->batch
.batch
.bo
);
898 /* Start a new batch buffer. */
905 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
907 unsigned index
= READ_ONCE(bo
->index
);
908 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
911 for (int i
= 0; i
< batch
->exec_count
; i
++) {
912 if (batch
->exec_bos
[i
] == bo
)
918 /* This is the only way buffers get added to the validate list.
921 emit_reloc(struct intel_batchbuffer
*batch
,
922 struct brw_reloc_list
*rlist
, uint32_t offset
,
923 struct brw_bo
*target
, int32_t target_offset
,
924 unsigned int reloc_flags
)
926 assert(target
!= NULL
);
928 if (target
->kflags
& EXEC_OBJECT_PINNED
) {
929 brw_use_pinned_bo(batch
, target
, reloc_flags
& RELOC_WRITE
);
930 return gen_canonical_address(target
->gtt_offset
+ target_offset
);
933 unsigned int index
= add_exec_bo(batch
, target
);
934 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
936 if (rlist
->reloc_count
== rlist
->reloc_array_size
) {
937 rlist
->reloc_array_size
*= 2;
938 rlist
->relocs
= realloc(rlist
->relocs
,
939 rlist
->reloc_array_size
*
940 sizeof(struct drm_i915_gem_relocation_entry
));
943 if (reloc_flags
& RELOC_32BIT
) {
944 /* Restrict this buffer to the low 32 bits of the address space.
946 * Altering the validation list flags restricts it for this batch,
947 * but we also alter the BO's kflags to restrict it permanently
948 * (until the BO is destroyed and put back in the cache). Buffers
949 * may stay bound across batches, and we want keep it constrained.
951 target
->kflags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
952 entry
->flags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
954 /* RELOC_32BIT is not an EXEC_OBJECT_* flag, so get rid of it. */
955 reloc_flags
&= ~RELOC_32BIT
;
959 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
961 rlist
->relocs
[rlist
->reloc_count
++] =
962 (struct drm_i915_gem_relocation_entry
) {
964 .delta
= target_offset
,
965 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
966 .presumed_offset
= entry
->offset
,
969 /* Using the old buffer offset, write in what the right data would be, in
970 * case the buffer doesn't move and we can short-circuit the relocation
971 * processing in the kernel
973 return entry
->offset
+ target_offset
;
977 brw_use_pinned_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
,
978 unsigned writable_flag
)
980 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
981 assert((writable_flag
& ~EXEC_OBJECT_WRITE
) == 0);
983 unsigned int index
= add_exec_bo(batch
, bo
);
984 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
985 assert(entry
->offset
== bo
->gtt_offset
);
988 entry
->flags
|= EXEC_OBJECT_WRITE
;
992 brw_batch_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
993 struct brw_bo
*target
, uint32_t target_offset
,
994 unsigned int reloc_flags
)
996 assert(batch_offset
<= batch
->batch
.bo
->size
- sizeof(uint32_t));
998 return emit_reloc(batch
, &batch
->batch_relocs
, batch_offset
,
999 target
, target_offset
, reloc_flags
);
1003 brw_state_reloc(struct intel_batchbuffer
*batch
, uint32_t state_offset
,
1004 struct brw_bo
*target
, uint32_t target_offset
,
1005 unsigned int reloc_flags
)
1007 assert(state_offset
<= batch
->state
.bo
->size
- sizeof(uint32_t));
1009 return emit_reloc(batch
, &batch
->state_relocs
, state_offset
,
1010 target
, target_offset
, reloc_flags
);
1014 * Reserve some space in the statebuffer, or flush.
1016 * This is used to estimate when we're near the end of the batch,
1017 * so we can flush early.
1020 brw_require_statebuffer_space(struct brw_context
*brw
, int size
)
1022 if (brw
->batch
.state_used
+ size
>= STATE_SZ
)
1023 intel_batchbuffer_flush(brw
);
1027 * Allocates a block of space in the batchbuffer for indirect state.
1030 brw_state_batch(struct brw_context
*brw
,
1033 uint32_t *out_offset
)
1035 struct intel_batchbuffer
*batch
= &brw
->batch
;
1037 assert(size
< batch
->state
.bo
->size
);
1039 uint32_t offset
= ALIGN(batch
->state_used
, alignment
);
1041 if (offset
+ size
>= STATE_SZ
&& !batch
->no_wrap
) {
1042 intel_batchbuffer_flush(brw
);
1043 offset
= ALIGN(batch
->state_used
, alignment
);
1044 } else if (offset
+ size
>= batch
->state
.bo
->size
) {
1045 const unsigned new_size
=
1046 MIN2(batch
->state
.bo
->size
+ batch
->state
.bo
->size
/ 2,
1048 grow_buffer(brw
, &batch
->state
, batch
->state_used
, new_size
);
1049 assert(offset
+ size
< batch
->state
.bo
->size
);
1052 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
1053 _mesa_hash_table_insert(batch
->state_batch_sizes
,
1054 (void *) (uintptr_t) offset
,
1055 (void *) (uintptr_t) size
);
1058 batch
->state_used
= offset
+ size
;
1060 *out_offset
= offset
;
1061 return batch
->state
.map
+ (offset
>> 2);
1065 intel_batchbuffer_data(struct brw_context
*brw
,
1066 const void *data
, GLuint bytes
)
1068 assert((bytes
& 3) == 0);
1069 intel_batchbuffer_require_space(brw
, bytes
);
1070 memcpy(brw
->batch
.map_next
, data
, bytes
);
1071 brw
->batch
.map_next
+= bytes
>> 2;
1075 load_sized_register_mem(struct brw_context
*brw
,
1081 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1084 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
1085 assert(devinfo
->gen
>= 7);
1087 if (devinfo
->gen
>= 8) {
1088 BEGIN_BATCH(4 * size
);
1089 for (i
= 0; i
< size
; i
++) {
1090 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
1091 OUT_BATCH(reg
+ i
* 4);
1092 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
1096 BEGIN_BATCH(3 * size
);
1097 for (i
= 0; i
< size
; i
++) {
1098 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
1099 OUT_BATCH(reg
+ i
* 4);
1100 OUT_RELOC(bo
, 0, offset
+ i
* 4);
1107 brw_load_register_mem(struct brw_context
*brw
,
1112 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
1116 brw_load_register_mem64(struct brw_context
*brw
,
1121 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
1125 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
1128 brw_store_register_mem32(struct brw_context
*brw
,
1129 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1131 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1133 assert(devinfo
->gen
>= 6);
1135 if (devinfo
->gen
>= 8) {
1137 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1139 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1143 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1145 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1151 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
1154 brw_store_register_mem64(struct brw_context
*brw
,
1155 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1157 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1159 assert(devinfo
->gen
>= 6);
1161 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
1162 * read a full 64-bit register, we need to do two of them.
1164 if (devinfo
->gen
>= 8) {
1166 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1168 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1169 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1170 OUT_BATCH(reg
+ sizeof(uint32_t));
1171 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
1175 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1177 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1178 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1179 OUT_BATCH(reg
+ sizeof(uint32_t));
1180 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
1186 * Write a 32-bit register using immediate data.
1189 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
1191 assert(brw
->screen
->devinfo
.gen
>= 6);
1194 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
1201 * Write a 64-bit register using immediate data.
1204 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
1206 assert(brw
->screen
->devinfo
.gen
>= 6);
1209 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
1211 OUT_BATCH(imm
& 0xffffffff);
1213 OUT_BATCH(imm
>> 32);
1218 * Copies a 32-bit register.
1221 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1223 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1226 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1233 * Copies a 64-bit register.
1236 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1238 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1241 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1244 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1245 OUT_BATCH(src
+ sizeof(uint32_t));
1246 OUT_BATCH(dest
+ sizeof(uint32_t));
1251 * Write 32-bits of immediate data to a GPU memory buffer.
1254 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1255 uint32_t offset
, uint32_t imm
)
1257 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1259 assert(devinfo
->gen
>= 6);
1262 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1263 if (devinfo
->gen
>= 8)
1264 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1266 OUT_BATCH(0); /* MBZ */
1267 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1274 * Write 64-bits of immediate data to a GPU memory buffer.
1277 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1278 uint32_t offset
, uint64_t imm
)
1280 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1282 assert(devinfo
->gen
>= 6);
1285 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1286 if (devinfo
->gen
>= 8)
1287 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1289 OUT_BATCH(0); /* MBZ */
1290 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1292 OUT_BATCH(imm
& 0xffffffffu
);
1293 OUT_BATCH(imm
>> 32);