2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
36 #include "util/hash_table.h"
41 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
44 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
45 struct brw_bufmgr
*bufmgr
,
49 uint_key_compare(const void *a
, const void *b
)
55 uint_key_hash(const void *key
)
57 return (uintptr_t) key
;
61 intel_batchbuffer_init(struct intel_batchbuffer
*batch
,
62 struct brw_bufmgr
*bufmgr
,
65 struct brw_context
*brw
= container_of(batch
, brw
, batch
);
68 batch
->cpu_map
= malloc(BATCH_SZ
);
69 batch
->map
= batch
->cpu_map
;
70 batch
->map_next
= batch
->cpu_map
;
73 batch
->reloc_count
= 0;
74 batch
->reloc_array_size
= 250;
75 batch
->relocs
= malloc(batch
->reloc_array_size
*
76 sizeof(struct drm_i915_gem_relocation_entry
));
77 batch
->exec_count
= 0;
78 batch
->exec_array_size
= 100;
80 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
81 batch
->validation_list
=
82 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
84 if (INTEL_DEBUG
& DEBUG_BATCH
) {
85 batch
->state_batch_sizes
=
86 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
89 batch
->use_batch_first
=
90 brw
->screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
92 intel_batchbuffer_reset(batch
, bufmgr
, has_llc
);
95 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
98 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
100 unsigned index
= READ_ONCE(bo
->index
);
102 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
105 /* May have been shared between multiple active batches */
106 for (index
= 0; index
< batch
->exec_count
; index
++) {
107 if (batch
->exec_bos
[index
] == bo
)
112 brw_bo_reference(bo
);
114 if (batch
->exec_count
== batch
->exec_array_size
) {
115 batch
->exec_array_size
*= 2;
117 realloc(batch
->exec_bos
,
118 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
119 batch
->validation_list
=
120 realloc(batch
->validation_list
,
121 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
124 struct drm_i915_gem_exec_object2
*validation_entry
=
125 &batch
->validation_list
[batch
->exec_count
];
126 validation_entry
->handle
= bo
->gem_handle
;
127 validation_entry
->relocation_count
= 0;
128 validation_entry
->relocs_ptr
= 0;
129 validation_entry
->alignment
= bo
->align
;
130 validation_entry
->offset
= bo
->offset64
;
131 validation_entry
->flags
= bo
->kflags
;
132 validation_entry
->rsvd1
= 0;
133 validation_entry
->rsvd2
= 0;
135 bo
->index
= batch
->exec_count
;
136 batch
->exec_bos
[batch
->exec_count
] = bo
;
137 batch
->aperture_space
+= bo
->size
;
139 return batch
->exec_count
++;
143 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
144 struct brw_bufmgr
*bufmgr
,
147 if (batch
->last_bo
!= NULL
) {
148 brw_bo_unreference(batch
->last_bo
);
149 batch
->last_bo
= NULL
;
151 batch
->last_bo
= batch
->bo
;
153 batch
->bo
= brw_bo_alloc(bufmgr
, "batchbuffer", BATCH_SZ
, 4096);
155 batch
->map
= brw_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
157 batch
->map_next
= batch
->map
;
159 add_exec_bo(batch
, batch
->bo
);
160 assert(batch
->bo
->index
== 0);
162 batch
->reserved_space
= BATCH_RESERVED
;
163 batch
->state_batch_offset
= batch
->bo
->size
;
164 batch
->needs_sol_reset
= false;
165 batch
->state_base_address_emitted
= false;
167 /* We don't know what ring the new batch will be sent to until we see the
168 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
170 batch
->ring
= UNKNOWN_RING
;
172 if (batch
->state_batch_sizes
)
173 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
177 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
179 intel_batchbuffer_reset(&brw
->batch
, brw
->bufmgr
, brw
->has_llc
);
180 brw_render_cache_set_clear(brw
);
184 intel_batchbuffer_save_state(struct brw_context
*brw
)
186 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
187 brw
->batch
.saved
.reloc_count
= brw
->batch
.reloc_count
;
188 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
192 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
194 for (int i
= brw
->batch
.saved
.exec_count
;
195 i
< brw
->batch
.exec_count
; i
++) {
196 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
197 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
200 brw
->batch
.reloc_count
= brw
->batch
.saved
.reloc_count
;
201 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
203 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
204 if (USED_BATCH(brw
->batch
) == 0)
205 brw
->batch
.ring
= UNKNOWN_RING
;
209 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
211 free(batch
->cpu_map
);
213 for (int i
= 0; i
< batch
->exec_count
; i
++) {
214 if (batch
->exec_bos
[i
] != batch
->bo
) {
215 brw_bo_unreference(batch
->exec_bos
[i
]);
219 free(batch
->exec_bos
);
220 free(batch
->validation_list
);
222 brw_bo_unreference(batch
->last_bo
);
223 brw_bo_unreference(batch
->bo
);
224 if (batch
->state_batch_sizes
)
225 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
229 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
230 enum brw_gpu_ring ring
)
232 /* If we're switching rings, implicitly flush the batch. */
233 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
235 intel_batchbuffer_flush(brw
);
239 assert(sz
< BATCH_SZ
- BATCH_RESERVED
);
241 if (intel_batchbuffer_space(&brw
->batch
) < sz
)
242 intel_batchbuffer_flush(brw
);
244 /* The intel_batchbuffer_flush() calls above might have changed
245 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
247 brw
->batch
.ring
= ring
;
252 #define BLUE_HEADER CSI "0;44m"
253 #define NORMAL CSI "0m"
257 decode_struct(struct brw_context
*brw
, struct gen_spec
*spec
,
258 const char *struct_name
, uint32_t *data
,
259 uint32_t gtt_offset
, uint32_t offset
, bool color
)
261 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
265 fprintf(stderr
, "%s\n", struct_name
);
266 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
267 &data
[offset
/ 4], color
);
271 decode_structs(struct brw_context
*brw
, struct gen_spec
*spec
,
272 const char *struct_name
,
273 uint32_t *data
, uint32_t gtt_offset
, uint32_t offset
,
274 int struct_size
, bool color
)
276 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
280 int entries
= brw_state_batch_size(brw
, offset
) / struct_size
;
281 for (int i
= 0; i
< entries
; i
++) {
282 fprintf(stderr
, "%s %d\n", struct_name
, i
);
283 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
284 &data
[(offset
+ i
* struct_size
) / 4], color
);
289 do_batch_dump(struct brw_context
*brw
)
291 struct intel_batchbuffer
*batch
= &brw
->batch
;
292 struct gen_spec
*spec
= gen_spec_load(&brw
->screen
->devinfo
);
294 if (batch
->ring
!= RENDER_RING
)
297 void *map
= brw_bo_map(brw
, batch
->bo
, MAP_READ
);
300 "WARNING: failed to map batchbuffer, "
301 "dumping uploaded data instead.\n");
304 uint32_t *data
= map
? map
: batch
->map
;
305 uint32_t *end
= data
+ USED_BATCH(*batch
);
306 uint32_t gtt_offset
= map
? batch
->bo
->offset64
: 0;
309 bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
310 const char *header_color
= color
? BLUE_HEADER
: "";
311 const char *reset_color
= color
? NORMAL
: "";
313 for (uint32_t *p
= data
; p
< end
; p
+= length
) {
314 struct gen_group
*inst
= gen_spec_find_instruction(spec
, p
);
315 length
= gen_group_get_length(inst
, p
);
316 assert(inst
== NULL
|| length
> 0);
317 length
= MAX2(1, length
);
319 fprintf(stderr
, "unknown instruction %08x\n", p
[0]);
323 uint64_t offset
= gtt_offset
+ 4 * (p
- data
);
325 fprintf(stderr
, "%s0x%08"PRIx64
": 0x%08x: %-80s%s\n", header_color
,
326 offset
, p
[0], gen_group_get_name(inst
), reset_color
);
328 gen_print_group(stderr
, inst
, offset
, p
, color
);
330 switch (gen_group_get_opcode(inst
) >> 16) {
331 case _3DSTATE_PIPELINED_POINTERS
:
332 /* Note: these Gen4-5 pointers are full relocations rather than
333 * offsets from the start of the batch. So we need to subtract
334 * gtt_offset (the start of the batch) to obtain an offset we
335 * can add to the map and get at the data.
337 decode_struct(brw
, spec
, "VS_STATE", data
, gtt_offset
,
338 (p
[1] & ~0x1fu
) - gtt_offset
, color
);
340 decode_struct(brw
, spec
, "GS_STATE", data
, gtt_offset
,
341 (p
[2] & ~0x1fu
) - gtt_offset
, color
);
344 decode_struct(brw
, spec
, "CLIP_STATE", data
, gtt_offset
,
345 (p
[3] & ~0x1fu
) - gtt_offset
, color
);
347 decode_struct(brw
, spec
, "SF_STATE", data
, gtt_offset
,
348 (p
[4] & ~0x1fu
) - gtt_offset
, color
);
349 decode_struct(brw
, spec
, "WM_STATE", data
, gtt_offset
,
350 (p
[5] & ~0x1fu
) - gtt_offset
, color
);
351 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
, gtt_offset
,
352 (p
[6] & ~0x3fu
) - gtt_offset
, color
);
354 case _3DSTATE_BINDING_TABLE_POINTERS_VS
:
355 case _3DSTATE_BINDING_TABLE_POINTERS_HS
:
356 case _3DSTATE_BINDING_TABLE_POINTERS_DS
:
357 case _3DSTATE_BINDING_TABLE_POINTERS_GS
:
358 case _3DSTATE_BINDING_TABLE_POINTERS_PS
: {
359 struct gen_group
*group
=
360 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
364 uint32_t bt_offset
= p
[1] & ~0x1fu
;
365 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
366 uint32_t *bt_pointers
= &data
[bt_offset
/ 4];
367 for (int i
= 0; i
< bt_entries
; i
++) {
368 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
369 gen_print_group(stderr
, group
, gtt_offset
+ bt_pointers
[i
],
370 &data
[bt_pointers
[i
] / 4], color
);
374 case _3DSTATE_SAMPLER_STATE_POINTERS_VS
:
375 case _3DSTATE_SAMPLER_STATE_POINTERS_HS
:
376 case _3DSTATE_SAMPLER_STATE_POINTERS_DS
:
377 case _3DSTATE_SAMPLER_STATE_POINTERS_GS
:
378 case _3DSTATE_SAMPLER_STATE_POINTERS_PS
:
379 decode_structs(brw
, spec
, "SAMPLER_STATE", data
,
380 gtt_offset
, p
[1] & ~0x1fu
, 4 * 4, color
);
382 case _3DSTATE_VIEWPORT_STATE_POINTERS
:
383 decode_structs(brw
, spec
, "CLIP_VIEWPORT", data
,
384 gtt_offset
, p
[1] & ~0x3fu
, 4 * 4, color
);
385 decode_structs(brw
, spec
, "SF_VIEWPORT", data
,
386 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
387 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
388 gtt_offset
, p
[3] & ~0x3fu
, 2 * 4, color
);
390 case _3DSTATE_VIEWPORT_STATE_POINTERS_CC
:
391 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
392 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
394 case _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
:
395 decode_structs(brw
, spec
, "SF_CLIP_VIEWPORT", data
,
396 gtt_offset
, p
[1] & ~0x3fu
, 16 * 4, color
);
398 case _3DSTATE_SCISSOR_STATE_POINTERS
:
399 decode_structs(brw
, spec
, "SCISSOR_RECT", data
,
400 gtt_offset
, p
[1] & ~0x1fu
, 2 * 4, color
);
402 case _3DSTATE_BLEND_STATE_POINTERS
:
403 /* TODO: handle Gen8+ extra dword at the beginning */
404 decode_structs(brw
, spec
, "BLEND_STATE", data
,
405 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
407 case _3DSTATE_CC_STATE_POINTERS
:
409 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
410 gtt_offset
, p
[1] & ~0x3fu
, color
);
411 } else if (brw
->gen
== 6) {
412 decode_structs(brw
, spec
, "BLEND_STATE", data
,
413 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
414 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
415 gtt_offset
, p
[2] & ~0x3fu
, color
);
416 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
417 gtt_offset
, p
[3] & ~0x3fu
, color
);
420 case _3DSTATE_DEPTH_STENCIL_STATE_POINTERS
:
421 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
422 gtt_offset
, p
[1] & ~0x3fu
, color
);
428 brw_bo_unmap(batch
->bo
);
432 static void do_batch_dump(struct brw_context
*brw
) { }
436 * Called when starting a new batch buffer.
439 brw_new_batch(struct brw_context
*brw
)
441 /* Unreference any BOs held by the previous batch, and reset counts. */
442 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
443 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
444 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
446 brw
->batch
.exec_bos
[i
] = NULL
;
448 brw
->batch
.reloc_count
= 0;
449 brw
->batch
.exec_count
= 0;
450 brw
->batch
.aperture_space
= BATCH_SZ
;
452 /* Create a new batchbuffer and reset the associated state: */
453 intel_batchbuffer_reset_and_clear_render_cache(brw
);
455 /* If the kernel supports hardware contexts, then most hardware state is
456 * preserved between batches; we only need to re-emit state that is required
457 * to be in every batch. Otherwise we need to re-emit all the state that
458 * would otherwise be stored in the context (which for all intents and
459 * purposes means everything).
461 if (brw
->hw_ctx
== 0)
462 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
464 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
466 brw
->ib
.index_size
= -1;
468 /* We need to periodically reap the shader time results, because rollover
469 * happens every few seconds. We also want to see results every once in a
470 * while, because many programs won't cleanly destroy our context, so the
471 * end-of-run printout may not happen.
473 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
474 brw_collect_and_report_shader_time(brw
);
478 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
481 * This function can emit state (say, to preserve registers that aren't saved
482 * between batches). All of this state MUST fit in the reserved space at the
483 * end of the batchbuffer. If you add more GPU state, increase the reserved
484 * space by updating the BATCH_RESERVED macro.
487 brw_finish_batch(struct brw_context
*brw
)
489 /* Capture the closing pipeline statistics register values necessary to
490 * support query objects (in the non-hardware context world).
492 brw_emit_query_end(brw
);
494 if (brw
->batch
.ring
== RENDER_RING
) {
495 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
496 * assume that the L3 cache is configured according to the hardware
500 gen7_restore_default_l3_config(brw
);
502 if (brw
->is_haswell
) {
503 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
504 * 3DSTATE_CC_STATE_POINTERS > "Note":
506 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
507 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
509 * From the example in the docs, it seems to expect a regular pipe control
510 * flush here as well. We may have done it already, but meh.
512 * See also WaAvoidRCZCounterRollover.
514 brw_emit_mi_flush(brw
);
516 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
517 OUT_BATCH(brw
->cc
.state_offset
| 1);
519 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
520 PIPE_CONTROL_CS_STALL
);
526 throttle(struct brw_context
*brw
)
528 /* Wait for the swapbuffers before the one we just emitted, so we
529 * don't get too many swaps outstanding for apps that are GPU-heavy
532 * We're using intelDRI2Flush (called from the loader before
533 * swapbuffer) and glFlush (for front buffer rendering) as the
534 * indicator that a frame is done and then throttle when we get
535 * here as we prepare to render the next frame. At this point for
536 * round trips for swap/copy and getting new buffers are done and
537 * we'll spend less time waiting on the GPU.
539 * Unfortunately, we don't have a handle to the batch containing
540 * the swap, and getting our hands on that doesn't seem worth it,
541 * so we just use the first batch we emitted after the last swap.
543 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
544 if (brw
->throttle_batch
[1]) {
545 if (!brw
->disable_throttling
) {
546 /* Pass NULL rather than brw so we avoid perf_debug warnings;
547 * stalling is common and expected here...
549 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
551 brw_bo_unreference(brw
->throttle_batch
[1]);
553 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
554 brw
->throttle_batch
[0] = NULL
;
555 brw
->need_swap_throttle
= false;
556 /* Throttling here is more precise than the throttle ioctl, so skip it */
557 brw
->need_flush_throttle
= false;
560 if (brw
->need_flush_throttle
) {
561 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
562 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
563 brw
->need_flush_throttle
= false;
569 struct intel_batchbuffer
*batch
,
576 struct drm_i915_gem_execbuffer2 execbuf
= {
577 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
578 .buffer_count
= batch
->exec_count
,
579 .batch_start_offset
= 0,
582 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
585 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
587 if (in_fence
!= -1) {
588 execbuf
.rsvd2
= in_fence
;
589 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
592 if (out_fence
!= NULL
) {
593 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
595 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
598 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
602 for (int i
= 0; i
< batch
->exec_count
; i
++) {
603 struct brw_bo
*bo
= batch
->exec_bos
[i
];
608 /* Update brw_bo::offset64 */
609 if (batch
->validation_list
[i
].offset
!= bo
->offset64
) {
610 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
611 bo
->gem_handle
, bo
->offset64
, batch
->validation_list
[i
].offset
);
612 bo
->offset64
= batch
->validation_list
[i
].offset
;
616 if (ret
== 0 && out_fence
!= NULL
)
617 *out_fence
= execbuf
.rsvd2
>> 32;
623 do_flush_locked(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
625 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
626 struct intel_batchbuffer
*batch
= &brw
->batch
;
630 brw_bo_unmap(batch
->bo
);
632 ret
= brw_bo_subdata(batch
->bo
, 0, 4 * USED_BATCH(*batch
), batch
->map
);
633 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
634 ret
= brw_bo_subdata(batch
->bo
,
635 batch
->state_batch_offset
,
636 batch
->bo
->size
- batch
->state_batch_offset
,
637 (char *)batch
->map
+ batch
->state_batch_offset
);
641 if (!brw
->screen
->no_hw
) {
642 /* The requirement for using I915_EXEC_NO_RELOC are:
644 * The addresses written in the objects must match the corresponding
645 * reloc.presumed_offset which in turn must match the corresponding
648 * Any render targets written to in the batch must be flagged with
651 * To avoid stalling, execobject.offset should match the current
652 * address of that object within the active context.
654 int flags
= I915_EXEC_NO_RELOC
;
656 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
657 flags
|= I915_EXEC_BLT
;
659 flags
|= I915_EXEC_RENDER
;
661 if (batch
->needs_sol_reset
)
662 flags
|= I915_EXEC_GEN7_SOL_RESET
;
665 uint32_t hw_ctx
= batch
->ring
== RENDER_RING
? brw
->hw_ctx
: 0;
667 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
668 assert(entry
->handle
== batch
->bo
->gem_handle
);
669 entry
->relocation_count
= batch
->reloc_count
;
670 entry
->relocs_ptr
= (uintptr_t) batch
->relocs
;
672 if (batch
->use_batch_first
) {
673 flags
|= I915_EXEC_BATCH_FIRST
;
675 /* Move the batch to the end of the validation list */
676 struct drm_i915_gem_exec_object2 tmp
;
677 const unsigned index
= batch
->exec_count
- 1;
680 *entry
= batch
->validation_list
[index
];
681 batch
->validation_list
[index
] = tmp
;
684 ret
= execbuffer(dri_screen
->fd
, batch
, hw_ctx
,
685 4 * USED_BATCH(*batch
),
686 in_fence_fd
, out_fence_fd
, flags
);
692 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
695 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
696 brw_check_for_reset(brw
);
699 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
707 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
710 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
711 * of the returned fd.
714 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
715 int in_fence_fd
, int *out_fence_fd
,
716 const char *file
, int line
)
720 if (USED_BATCH(brw
->batch
) == 0)
723 if (brw
->throttle_batch
[0] == NULL
) {
724 brw
->throttle_batch
[0] = brw
->batch
.bo
;
725 brw_bo_reference(brw
->throttle_batch
[0]);
728 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
729 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
730 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
731 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
732 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
733 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
734 bytes_for_commands
, bytes_for_state
,
736 100.0f
* total_bytes
/ BATCH_SZ
);
739 brw
->batch
.reserved_space
= 0;
741 brw_finish_batch(brw
);
743 /* Mark the end of the buffer. */
744 intel_batchbuffer_emit_dword(&brw
->batch
, MI_BATCH_BUFFER_END
);
745 if (USED_BATCH(brw
->batch
) & 1) {
746 /* Round batchbuffer usage to 2 DWORDs. */
747 intel_batchbuffer_emit_dword(&brw
->batch
, MI_NOOP
);
750 intel_upload_finish(brw
);
752 /* Check that we didn't just wrap our batchbuffer at a bad time. */
753 assert(!brw
->no_batch_wrap
);
755 ret
= do_flush_locked(brw
, in_fence_fd
, out_fence_fd
);
757 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
758 fprintf(stderr
, "waiting for idle\n");
759 brw_bo_wait_rendering(brw
->batch
.bo
);
762 /* Start a new batch buffer. */
769 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
771 return brw
->batch
.aperture_space
+ extra_space
<=
772 brw
->screen
->aperture_threshold
;
776 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
778 unsigned index
= READ_ONCE(bo
->index
);
779 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
782 for (int i
= 0; i
< batch
->exec_count
; i
++) {
783 if (batch
->exec_bos
[i
] == bo
)
789 /* This is the only way buffers get added to the validate list.
792 brw_emit_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
793 struct brw_bo
*target
, uint32_t target_offset
,
794 uint32_t read_domains
, uint32_t write_domain
)
796 assert(target
!= NULL
);
798 if (batch
->reloc_count
== batch
->reloc_array_size
) {
799 batch
->reloc_array_size
*= 2;
800 batch
->relocs
= realloc(batch
->relocs
,
801 batch
->reloc_array_size
*
802 sizeof(struct drm_i915_gem_relocation_entry
));
806 assert(batch_offset
<= BATCH_SZ
- sizeof(uint32_t));
807 assert(_mesa_bitcount(write_domain
) <= 1);
809 unsigned int index
= add_exec_bo(batch
, target
);
810 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
813 entry
->flags
|= EXEC_OBJECT_WRITE
;
815 /* PIPECONTROL needs a w/a on gen6 */
816 if (write_domain
== I915_GEM_DOMAIN_INSTRUCTION
) {
817 struct brw_context
*brw
= container_of(batch
, brw
, batch
);
819 entry
->flags
|= EXEC_OBJECT_NEEDS_GTT
;
823 batch
->relocs
[batch
->reloc_count
++] =
824 (struct drm_i915_gem_relocation_entry
) {
825 .offset
= batch_offset
,
826 .delta
= target_offset
,
827 .target_handle
= target
->gem_handle
,
828 .presumed_offset
= entry
->offset
,
831 /* Using the old buffer offset, write in what the right data would be, in
832 * case the buffer doesn't move and we can short-circuit the relocation
833 * processing in the kernel
835 return entry
->offset
+ target_offset
;
839 intel_batchbuffer_data(struct brw_context
*brw
,
840 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
842 assert((bytes
& 3) == 0);
843 intel_batchbuffer_require_space(brw
, bytes
, ring
);
844 memcpy(brw
->batch
.map_next
, data
, bytes
);
845 brw
->batch
.map_next
+= bytes
>> 2;
849 load_sized_register_mem(struct brw_context
*brw
,
852 uint32_t read_domains
, uint32_t write_domain
,
858 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
859 assert(brw
->gen
>= 7);
862 BEGIN_BATCH(4 * size
);
863 for (i
= 0; i
< size
; i
++) {
864 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
865 OUT_BATCH(reg
+ i
* 4);
866 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
+ i
* 4);
870 BEGIN_BATCH(3 * size
);
871 for (i
= 0; i
< size
; i
++) {
872 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
873 OUT_BATCH(reg
+ i
* 4);
874 OUT_RELOC(bo
, read_domains
, write_domain
, offset
+ i
* 4);
881 brw_load_register_mem(struct brw_context
*brw
,
884 uint32_t read_domains
, uint32_t write_domain
,
887 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 1);
891 brw_load_register_mem64(struct brw_context
*brw
,
894 uint32_t read_domains
, uint32_t write_domain
,
897 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 2);
901 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
904 brw_store_register_mem32(struct brw_context
*brw
,
905 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
907 assert(brw
->gen
>= 6);
911 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
913 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
918 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
920 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
927 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
930 brw_store_register_mem64(struct brw_context
*brw
,
931 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
933 assert(brw
->gen
>= 6);
935 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
936 * read a full 64-bit register, we need to do two of them.
940 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
942 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
944 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
945 OUT_BATCH(reg
+ sizeof(uint32_t));
946 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
947 offset
+ sizeof(uint32_t));
951 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
953 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
955 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
956 OUT_BATCH(reg
+ sizeof(uint32_t));
957 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
958 offset
+ sizeof(uint32_t));
964 * Write a 32-bit register using immediate data.
967 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
969 assert(brw
->gen
>= 6);
972 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
979 * Write a 64-bit register using immediate data.
982 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
984 assert(brw
->gen
>= 6);
987 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
989 OUT_BATCH(imm
& 0xffffffff);
991 OUT_BATCH(imm
>> 32);
996 * Copies a 32-bit register.
999 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1001 assert(brw
->gen
>= 8 || brw
->is_haswell
);
1004 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1011 * Copies a 64-bit register.
1014 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1016 assert(brw
->gen
>= 8 || brw
->is_haswell
);
1019 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1022 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1023 OUT_BATCH(src
+ sizeof(uint32_t));
1024 OUT_BATCH(dest
+ sizeof(uint32_t));
1029 * Write 32-bits of immediate data to a GPU memory buffer.
1032 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1033 uint32_t offset
, uint32_t imm
)
1035 assert(brw
->gen
>= 6);
1038 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1040 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1043 OUT_BATCH(0); /* MBZ */
1044 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1052 * Write 64-bits of immediate data to a GPU memory buffer.
1055 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1056 uint32_t offset
, uint64_t imm
)
1058 assert(brw
->gen
>= 6);
1061 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1063 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1066 OUT_BATCH(0); /* MBZ */
1067 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1070 OUT_BATCH(imm
& 0xffffffffu
);
1071 OUT_BATCH(imm
>> 32);