1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "intel_fbo.h"
34 #include "brw_context.h"
37 intel_batchbuffer_reset(struct brw_context
*brw
);
40 intel_batchbuffer_init(struct brw_context
*brw
)
42 intel_batchbuffer_reset(brw
);
45 /* We can't just use brw_state_batch to get a chunk of space for
46 * the gen6 workaround because it involves actually writing to
47 * the buffer, and the kernel doesn't let us write to the batch.
49 brw
->batch
.workaround_bo
= drm_intel_bo_alloc(brw
->bufmgr
,
50 "pipe_control workaround",
55 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
56 brw
->batch
.map
= brw
->batch
.cpu_map
;
61 intel_batchbuffer_reset(struct brw_context
*brw
)
63 if (brw
->batch
.last_bo
!= NULL
) {
64 drm_intel_bo_unreference(brw
->batch
.last_bo
);
65 brw
->batch
.last_bo
= NULL
;
67 brw
->batch
.last_bo
= brw
->batch
.bo
;
69 brw_render_cache_set_clear(brw
);
71 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
74 drm_intel_bo_map(brw
->batch
.bo
, true);
75 brw
->batch
.map
= brw
->batch
.bo
->virtual;
78 brw
->batch
.reserved_space
= BATCH_RESERVED
;
79 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
81 brw
->batch
.needs_sol_reset
= false;
82 brw
->batch
.pipe_controls_since_last_cs_stall
= 0;
84 /* We don't know what ring the new batch will be sent to until we see the
85 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
87 brw
->batch
.ring
= UNKNOWN_RING
;
91 intel_batchbuffer_save_state(struct brw_context
*brw
)
93 brw
->batch
.saved
.used
= brw
->batch
.used
;
94 brw
->batch
.saved
.reloc_count
=
95 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
99 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
101 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
103 brw
->batch
.used
= brw
->batch
.saved
.used
;
104 if (brw
->batch
.used
== 0)
105 brw
->batch
.ring
= UNKNOWN_RING
;
109 intel_batchbuffer_free(struct brw_context
*brw
)
111 free(brw
->batch
.cpu_map
);
112 drm_intel_bo_unreference(brw
->batch
.last_bo
);
113 drm_intel_bo_unreference(brw
->batch
.bo
);
114 drm_intel_bo_unreference(brw
->batch
.workaround_bo
);
118 do_batch_dump(struct brw_context
*brw
)
120 struct drm_intel_decode
*decode
;
121 struct intel_batchbuffer
*batch
= &brw
->batch
;
124 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
128 ret
= drm_intel_bo_map(batch
->bo
, false);
130 drm_intel_decode_set_batch_pointer(decode
,
136 "WARNING: failed to map batchbuffer (%s), "
137 "dumping uploaded data instead.\n", strerror(ret
));
139 drm_intel_decode_set_batch_pointer(decode
,
145 drm_intel_decode_set_output_file(decode
, stderr
);
146 drm_intel_decode(decode
);
148 drm_intel_decode_context_free(decode
);
151 drm_intel_bo_unmap(batch
->bo
);
153 brw_debug_batch(brw
);
158 intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
)
160 /* We may need to enable and snapshot OA counters. */
161 brw_perf_monitor_new_batch(brw
);
165 * Called when starting a new batch buffer.
168 brw_new_batch(struct brw_context
*brw
)
170 /* Create a new batchbuffer and reset the associated state: */
171 intel_batchbuffer_reset(brw
);
173 /* If the kernel supports hardware contexts, then most hardware state is
174 * preserved between batches; we only need to re-emit state that is required
175 * to be in every batch. Otherwise we need to re-emit all the state that
176 * would otherwise be stored in the context (which for all intents and
177 * purposes means everything).
179 if (brw
->hw_ctx
== NULL
)
180 brw
->state
.dirty
.brw
|= BRW_NEW_CONTEXT
;
182 brw
->state
.dirty
.brw
|= BRW_NEW_BATCH
;
184 brw
->state_batch_count
= 0;
188 /* We need to periodically reap the shader time results, because rollover
189 * happens every few seconds. We also want to see results every once in a
190 * while, because many programs won't cleanly destroy our context, so the
191 * end-of-run printout may not happen.
193 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
194 brw_collect_and_report_shader_time(brw
);
196 if (INTEL_DEBUG
& DEBUG_PERFMON
)
197 brw_dump_perf_monitors(brw
);
201 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
204 * This function can emit state (say, to preserve registers that aren't saved
205 * between batches). All of this state MUST fit in the reserved space at the
206 * end of the batchbuffer. If you add more GPU state, increase the reserved
207 * space by updating the BATCH_RESERVED macro.
210 brw_finish_batch(struct brw_context
*brw
)
212 /* Capture the closing pipeline statistics register values necessary to
213 * support query objects (in the non-hardware context world).
215 brw_emit_query_end(brw
);
217 /* We may also need to snapshot and disable OA counters. */
218 if (brw
->batch
.ring
== RENDER_RING
)
219 brw_perf_monitor_finish_batch(brw
);
221 /* Mark that the current program cache BO has been used by the GPU.
222 * It will be reallocated if we need to put new programs in for the
225 brw
->cache
.bo_used_by_gpu
= true;
228 /* TODO: Push this whole function into bufmgr.
231 do_flush_locked(struct brw_context
*brw
)
233 struct intel_batchbuffer
*batch
= &brw
->batch
;
237 drm_intel_bo_unmap(batch
->bo
);
239 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
240 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
241 ret
= drm_intel_bo_subdata(batch
->bo
,
242 batch
->state_batch_offset
,
243 batch
->bo
->size
- batch
->state_batch_offset
,
244 (char *)batch
->map
+ batch
->state_batch_offset
);
248 if (!brw
->intelScreen
->no_hw
) {
251 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
252 flags
= I915_EXEC_BLT
;
254 flags
= I915_EXEC_RENDER
;
256 if (batch
->needs_sol_reset
)
257 flags
|= I915_EXEC_GEN7_SOL_RESET
;
260 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
261 brw_annotate_aub(brw
);
262 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
263 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
266 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
267 4 * batch
->used
, flags
);
272 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
276 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
284 _intel_batchbuffer_flush(struct brw_context
*brw
,
285 const char *file
, int line
)
289 if (brw
->batch
.used
== 0)
292 if (brw
->first_post_swapbuffers_batch
== NULL
) {
293 brw
->first_post_swapbuffers_batch
= brw
->batch
.bo
;
294 drm_intel_bo_reference(brw
->first_post_swapbuffers_batch
);
297 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
298 int bytes_for_commands
= 4 * brw
->batch
.used
;
299 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
300 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
301 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
302 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
303 bytes_for_commands
, bytes_for_state
,
305 100.0f
* total_bytes
/ BATCH_SZ
);
308 brw
->batch
.reserved_space
= 0;
310 brw_finish_batch(brw
);
312 /* Mark the end of the buffer. */
313 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
314 if (brw
->batch
.used
& 1) {
315 /* Round batchbuffer usage to 2 DWORDs. */
316 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
319 intel_upload_finish(brw
);
321 /* Check that we didn't just wrap our batchbuffer at a bad time. */
322 assert(!brw
->no_batch_wrap
);
324 ret
= do_flush_locked(brw
);
326 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
327 fprintf(stderr
, "waiting for idle\n");
328 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
331 /* Start a new batch buffer. */
338 /* This is the only way buffers get added to the validate list.
341 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
342 drm_intel_bo
*buffer
,
343 uint32_t read_domains
, uint32_t write_domain
,
348 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
350 read_domains
, write_domain
);
354 /* Using the old buffer offset, write in what the right data would be, in
355 * case the buffer doesn't move and we can short-circuit the relocation
356 * processing in the kernel
358 intel_batchbuffer_emit_dword(brw
, buffer
->offset64
+ delta
);
364 intel_batchbuffer_emit_reloc64(struct brw_context
*brw
,
365 drm_intel_bo
*buffer
,
366 uint32_t read_domains
, uint32_t write_domain
,
369 int ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
371 read_domains
, write_domain
);
375 /* Using the old buffer offset, write in what the right data would be, in
376 * case the buffer doesn't move and we can short-circuit the relocation
377 * processing in the kernel
379 uint64_t offset
= buffer
->offset64
+ delta
;
380 intel_batchbuffer_emit_dword(brw
, offset
);
381 intel_batchbuffer_emit_dword(brw
, offset
>> 32);
388 intel_batchbuffer_data(struct brw_context
*brw
,
389 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
391 assert((bytes
& 3) == 0);
392 intel_batchbuffer_require_space(brw
, bytes
, ring
);
393 __memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
394 brw
->batch
.used
+= bytes
>> 2;
398 * According to the latest documentation, any PIPE_CONTROL with the
399 * "Command Streamer Stall" bit set must also have another bit set,
400 * with five different options:
402 * - Render Target Cache Flush
403 * - Depth Cache Flush
404 * - Stall at Pixel Scoreboard
405 * - Post-Sync Operation
408 * I chose "Stall at Pixel Scoreboard" since we've used it effectively
409 * in the past, but the choice is fairly arbitrary.
412 gen8_add_cs_stall_workaround_bits(uint32_t *flags
)
414 uint32_t wa_bits
= PIPE_CONTROL_WRITE_FLUSH
|
415 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
416 PIPE_CONTROL_WRITE_IMMEDIATE
|
417 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
418 PIPE_CONTROL_WRITE_TIMESTAMP
|
419 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
420 PIPE_CONTROL_DEPTH_STALL
;
422 /* If we're doing a CS stall, and don't already have one of the
423 * workaround bits set, add "Stall at Pixel Scoreboard."
425 if ((*flags
& PIPE_CONTROL_CS_STALL
) != 0 && (*flags
& wa_bits
) == 0)
426 *flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
429 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
431 * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
432 * only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
434 * Note that the kernel does CS stalls between batches, so we only need
435 * to count them within a batch.
438 gen7_cs_stall_every_four_pipe_controls(struct brw_context
*brw
, uint32_t flags
)
440 if (brw
->gen
== 7 && !brw
->is_haswell
) {
441 if (flags
& PIPE_CONTROL_CS_STALL
) {
442 /* If we're doing a CS stall, reset the counter and carry on. */
443 brw
->batch
.pipe_controls_since_last_cs_stall
= 0;
447 /* If this is the fourth pipe control without a CS stall, do one now. */
448 if (++brw
->batch
.pipe_controls_since_last_cs_stall
== 4) {
449 brw
->batch
.pipe_controls_since_last_cs_stall
= 0;
450 return PIPE_CONTROL_CS_STALL
;
457 * Emit a PIPE_CONTROL with various flushing flags.
459 * The caller is responsible for deciding what flags are appropriate for the
463 brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
)
466 gen8_add_cs_stall_workaround_bits(&flags
);
469 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
476 } else if (brw
->gen
>= 6) {
477 flags
|= gen7_cs_stall_every_four_pipe_controls(brw
, flags
);
480 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
488 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
497 * Emit a PIPE_CONTROL that writes to a buffer object.
499 * \p flags should contain one of the following items:
500 * - PIPE_CONTROL_WRITE_IMMEDIATE
501 * - PIPE_CONTROL_WRITE_TIMESTAMP
502 * - PIPE_CONTROL_WRITE_DEPTH_COUNT
505 brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
506 drm_intel_bo
*bo
, uint32_t offset
,
507 uint32_t imm_lower
, uint32_t imm_upper
)
510 gen8_add_cs_stall_workaround_bits(&flags
);
513 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
515 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
517 OUT_BATCH(imm_lower
);
518 OUT_BATCH(imm_upper
);
520 } else if (brw
->gen
>= 6) {
521 flags
|= gen7_cs_stall_every_four_pipe_controls(brw
, flags
);
523 /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
524 * on later platforms. We always use PPGTT on Gen7+.
526 unsigned gen6_gtt
= brw
->gen
== 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE
: 0;
529 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
531 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
533 OUT_BATCH(imm_lower
);
534 OUT_BATCH(imm_upper
);
538 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
539 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
540 PIPE_CONTROL_GLOBAL_GTT_WRITE
| offset
);
541 OUT_BATCH(imm_lower
);
542 OUT_BATCH(imm_upper
);
548 * Restriction [DevSNB, DevIVB]:
550 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
551 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
552 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
553 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
554 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
555 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
556 * unless SW can otherwise guarantee that the pipeline from WM onwards is
557 * already flushed (e.g., via a preceding MI_FLUSH).
560 intel_emit_depth_stall_flushes(struct brw_context
*brw
)
562 assert(brw
->gen
>= 6 && brw
->gen
<= 9);
564 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
565 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
566 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
570 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
571 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
572 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
573 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
574 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
575 * to be sent before any combination of VS associated 3DSTATE."
578 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
580 assert(brw
->gen
== 7);
581 brw_emit_pipe_control_write(brw
,
582 PIPE_CONTROL_WRITE_IMMEDIATE
583 | PIPE_CONTROL_DEPTH_STALL
,
584 brw
->batch
.workaround_bo
, 0,
590 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
593 gen7_emit_cs_stall_flush(struct brw_context
*brw
)
595 brw_emit_pipe_control_write(brw
,
596 PIPE_CONTROL_CS_STALL
597 | PIPE_CONTROL_WRITE_IMMEDIATE
,
598 brw
->batch
.workaround_bo
, 0,
604 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
605 * implementing two workarounds on gen6. From section 1.4.7.1
606 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
608 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
609 * produced by non-pipelined state commands), software needs to first
610 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
613 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
614 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
616 * And the workaround for these two requires this workaround first:
618 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
619 * BEFORE the pipe-control with a post-sync op and no write-cache
622 * And this last workaround is tricky because of the requirements on
623 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
626 * "1 of the following must also be set:
627 * - Render Target Cache Flush Enable ([12] of DW1)
628 * - Depth Cache Flush Enable ([0] of DW1)
629 * - Stall at Pixel Scoreboard ([1] of DW1)
630 * - Depth Stall ([13] of DW1)
631 * - Post-Sync Operation ([13] of DW1)
632 * - Notify Enable ([8] of DW1)"
634 * The cache flushes require the workaround flush that triggered this
635 * one, so we can't use it. Depth stall would trigger the same.
636 * Post-sync nonzero is what triggered this second workaround, so we
637 * can't use that one either. Notify enable is IRQs, which aren't
638 * really our business. That leaves only stall at scoreboard.
641 intel_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
643 brw_emit_pipe_control_flush(brw
,
644 PIPE_CONTROL_CS_STALL
|
645 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
647 brw_emit_pipe_control_write(brw
, PIPE_CONTROL_WRITE_IMMEDIATE
,
648 brw
->batch
.workaround_bo
, 0, 0, 0);
651 /* Emit a pipelined flush to either flush render and texture cache for
652 * reading from a FBO-drawn texture, or flush so that frontbuffer
653 * render appears on the screen in DRI1.
655 * This is also used for the always_flush_cache driconf debug option.
658 intel_batchbuffer_emit_mi_flush(struct brw_context
*brw
)
660 if (brw
->batch
.ring
== BLT_RING
&& brw
->gen
>= 6) {
662 OUT_BATCH(MI_FLUSH_DW
);
668 int flags
= PIPE_CONTROL_NO_WRITE
| PIPE_CONTROL_WRITE_FLUSH
;
671 /* Hardware workaround: SKL
673 * Emit Pipe Control with all bits set to zero before emitting
674 * a Pipe Control with VF Cache Invalidate set.
676 brw_emit_pipe_control_flush(brw
, 0);
679 flags
|= PIPE_CONTROL_INSTRUCTION_FLUSH
|
680 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
681 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
682 PIPE_CONTROL_TC_FLUSH
|
683 PIPE_CONTROL_CS_STALL
;
686 /* Hardware workaround: SNB B-Spec says:
688 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
689 * Flush Enable =1, a PIPE_CONTROL with any non-zero
690 * post-sync-op is required.
692 intel_emit_post_sync_nonzero_flush(brw
);
695 brw_emit_pipe_control_flush(brw
, flags
);
698 brw_render_cache_set_clear(brw
);
702 brw_load_register_mem(struct brw_context
*brw
,
705 uint32_t read_domains
, uint32_t write_domain
,
708 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
709 assert(brw
->gen
>= 7);
713 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
715 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
);
719 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
721 OUT_RELOC(bo
, read_domains
, write_domain
, offset
);