2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "intel_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
39 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
, dri_bufmgr
*bufmgr
,
43 intel_batchbuffer_init(struct intel_batchbuffer
*batch
, dri_bufmgr
*bufmgr
,
46 intel_batchbuffer_reset(batch
, bufmgr
, has_llc
);
49 batch
->cpu_map
= malloc(BATCH_SZ
);
50 batch
->map
= batch
->cpu_map
;
51 batch
->map_next
= batch
->cpu_map
;
56 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
, dri_bufmgr
*bufmgr
,
59 if (batch
->last_bo
!= NULL
) {
60 drm_intel_bo_unreference(batch
->last_bo
);
61 batch
->last_bo
= NULL
;
63 batch
->last_bo
= batch
->bo
;
65 batch
->bo
= drm_intel_bo_alloc(bufmgr
, "batchbuffer", BATCH_SZ
, 4096);
67 drm_intel_bo_map(batch
->bo
, true);
68 batch
->map
= batch
->bo
->virtual;
70 batch
->map_next
= batch
->map
;
72 batch
->reserved_space
= BATCH_RESERVED
;
73 batch
->state_batch_offset
= batch
->bo
->size
;
74 batch
->needs_sol_reset
= false;
75 batch
->state_base_address_emitted
= false;
77 /* We don't know what ring the new batch will be sent to until we see the
78 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
80 batch
->ring
= UNKNOWN_RING
;
84 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
86 intel_batchbuffer_reset(&brw
->batch
, brw
->bufmgr
, brw
->has_llc
);
87 brw_render_cache_set_clear(brw
);
91 intel_batchbuffer_save_state(struct brw_context
*brw
)
93 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
94 brw
->batch
.saved
.reloc_count
=
95 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
99 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
101 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
103 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
104 if (USED_BATCH(brw
->batch
) == 0)
105 brw
->batch
.ring
= UNKNOWN_RING
;
109 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
111 free(batch
->cpu_map
);
112 drm_intel_bo_unreference(batch
->last_bo
);
113 drm_intel_bo_unreference(batch
->bo
);
117 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
118 enum brw_gpu_ring ring
)
120 /* If we're switching rings, implicitly flush the batch. */
121 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
123 intel_batchbuffer_flush(brw
);
127 assert(sz
< BATCH_SZ
- BATCH_RESERVED
);
129 if (intel_batchbuffer_space(&brw
->batch
) < sz
)
130 intel_batchbuffer_flush(brw
);
132 /* The intel_batchbuffer_flush() calls above might have changed
133 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
135 brw
->batch
.ring
= ring
;
139 do_batch_dump(struct brw_context
*brw
)
141 struct drm_intel_decode
*decode
;
142 struct intel_batchbuffer
*batch
= &brw
->batch
;
145 decode
= drm_intel_decode_context_alloc(brw
->screen
->deviceID
);
149 ret
= drm_intel_bo_map(batch
->bo
, false);
151 drm_intel_decode_set_batch_pointer(decode
,
157 "WARNING: failed to map batchbuffer (%s), "
158 "dumping uploaded data instead.\n", strerror(ret
));
160 drm_intel_decode_set_batch_pointer(decode
,
166 drm_intel_decode_set_output_file(decode
, stderr
);
167 drm_intel_decode(decode
);
169 drm_intel_decode_context_free(decode
);
172 drm_intel_bo_unmap(batch
->bo
);
174 brw_debug_batch(brw
);
179 * Called when starting a new batch buffer.
182 brw_new_batch(struct brw_context
*brw
)
184 /* Create a new batchbuffer and reset the associated state: */
185 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, 0);
186 intel_batchbuffer_reset_and_clear_render_cache(brw
);
188 /* If the kernel supports hardware contexts, then most hardware state is
189 * preserved between batches; we only need to re-emit state that is required
190 * to be in every batch. Otherwise we need to re-emit all the state that
191 * would otherwise be stored in the context (which for all intents and
192 * purposes means everything).
194 if (brw
->hw_ctx
== NULL
)
195 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
197 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
199 brw
->state_batch_count
= 0;
203 /* We need to periodically reap the shader time results, because rollover
204 * happens every few seconds. We also want to see results every once in a
205 * while, because many programs won't cleanly destroy our context, so the
206 * end-of-run printout may not happen.
208 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
209 brw_collect_and_report_shader_time(brw
);
213 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
216 * This function can emit state (say, to preserve registers that aren't saved
217 * between batches). All of this state MUST fit in the reserved space at the
218 * end of the batchbuffer. If you add more GPU state, increase the reserved
219 * space by updating the BATCH_RESERVED macro.
222 brw_finish_batch(struct brw_context
*brw
)
224 /* Capture the closing pipeline statistics register values necessary to
225 * support query objects (in the non-hardware context world).
227 brw_emit_query_end(brw
);
229 if (brw
->batch
.ring
== RENDER_RING
) {
230 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
231 * assume that the L3 cache is configured according to the hardware
235 gen7_restore_default_l3_config(brw
);
237 if (brw
->is_haswell
) {
238 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
239 * 3DSTATE_CC_STATE_POINTERS > "Note":
241 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
242 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
244 * From the example in the docs, it seems to expect a regular pipe control
245 * flush here as well. We may have done it already, but meh.
247 * See also WaAvoidRCZCounterRollover.
249 brw_emit_mi_flush(brw
);
251 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
252 OUT_BATCH(brw
->cc
.state_offset
| 1);
254 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
255 PIPE_CONTROL_CS_STALL
);
259 /* Mark that the current program cache BO has been used by the GPU.
260 * It will be reallocated if we need to put new programs in for the
263 brw
->cache
.bo_used_by_gpu
= true;
267 throttle(struct brw_context
*brw
)
269 /* Wait for the swapbuffers before the one we just emitted, so we
270 * don't get too many swaps outstanding for apps that are GPU-heavy
273 * We're using intelDRI2Flush (called from the loader before
274 * swapbuffer) and glFlush (for front buffer rendering) as the
275 * indicator that a frame is done and then throttle when we get
276 * here as we prepare to render the next frame. At this point for
277 * round trips for swap/copy and getting new buffers are done and
278 * we'll spend less time waiting on the GPU.
280 * Unfortunately, we don't have a handle to the batch containing
281 * the swap, and getting our hands on that doesn't seem worth it,
282 * so we just use the first batch we emitted after the last swap.
284 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
285 if (brw
->throttle_batch
[1]) {
286 if (!brw
->disable_throttling
)
287 drm_intel_bo_wait_rendering(brw
->throttle_batch
[1]);
288 drm_intel_bo_unreference(brw
->throttle_batch
[1]);
290 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
291 brw
->throttle_batch
[0] = NULL
;
292 brw
->need_swap_throttle
= false;
293 /* Throttling here is more precise than the throttle ioctl, so skip it */
294 brw
->need_flush_throttle
= false;
297 if (brw
->need_flush_throttle
) {
298 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
299 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
300 brw
->need_flush_throttle
= false;
304 /* TODO: Push this whole function into bufmgr.
307 do_flush_locked(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
309 struct intel_batchbuffer
*batch
= &brw
->batch
;
313 drm_intel_bo_unmap(batch
->bo
);
315 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4 * USED_BATCH(*batch
), batch
->map
);
316 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
317 ret
= drm_intel_bo_subdata(batch
->bo
,
318 batch
->state_batch_offset
,
319 batch
->bo
->size
- batch
->state_batch_offset
,
320 (char *)batch
->map
+ batch
->state_batch_offset
);
324 if (!brw
->screen
->no_hw
) {
327 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
328 flags
= I915_EXEC_BLT
;
330 flags
= I915_EXEC_RENDER
;
332 if (batch
->needs_sol_reset
)
333 flags
|= I915_EXEC_GEN7_SOL_RESET
;
336 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
337 assert(in_fence_fd
== -1);
338 assert(out_fence_fd
== NULL
);
339 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * USED_BATCH(*batch
),
342 ret
= drm_intel_gem_bo_fence_exec(batch
->bo
, brw
->hw_ctx
,
343 4 * USED_BATCH(*batch
),
344 in_fence_fd
, out_fence_fd
,
352 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
355 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
356 brw_check_for_reset(brw
);
359 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
367 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
370 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
371 * of the returned fd.
374 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
375 int in_fence_fd
, int *out_fence_fd
,
376 const char *file
, int line
)
380 if (USED_BATCH(brw
->batch
) == 0)
383 if (brw
->throttle_batch
[0] == NULL
) {
384 brw
->throttle_batch
[0] = brw
->batch
.bo
;
385 drm_intel_bo_reference(brw
->throttle_batch
[0]);
388 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
389 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
390 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
391 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
392 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
393 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
394 bytes_for_commands
, bytes_for_state
,
396 100.0f
* total_bytes
/ BATCH_SZ
);
399 brw
->batch
.reserved_space
= 0;
401 brw_finish_batch(brw
);
403 /* Mark the end of the buffer. */
404 intel_batchbuffer_emit_dword(&brw
->batch
, MI_BATCH_BUFFER_END
);
405 if (USED_BATCH(brw
->batch
) & 1) {
406 /* Round batchbuffer usage to 2 DWORDs. */
407 intel_batchbuffer_emit_dword(&brw
->batch
, MI_NOOP
);
410 intel_upload_finish(brw
);
412 /* Check that we didn't just wrap our batchbuffer at a bad time. */
413 assert(!brw
->no_batch_wrap
);
415 ret
= do_flush_locked(brw
, in_fence_fd
, out_fence_fd
);
417 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
418 fprintf(stderr
, "waiting for idle\n");
419 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
422 /* Start a new batch buffer. */
429 /* This is the only way buffers get added to the validate list.
432 intel_batchbuffer_reloc(struct intel_batchbuffer
*batch
,
433 drm_intel_bo
*buffer
, uint32_t offset
,
434 uint32_t read_domains
, uint32_t write_domain
,
439 ret
= drm_intel_bo_emit_reloc(batch
->bo
, offset
,
441 read_domains
, write_domain
);
445 /* Using the old buffer offset, write in what the right data would be, in
446 * case the buffer doesn't move and we can short-circuit the relocation
447 * processing in the kernel
449 return buffer
->offset64
+ delta
;
453 intel_batchbuffer_reloc64(struct intel_batchbuffer
*batch
,
454 drm_intel_bo
*buffer
, uint32_t offset
,
455 uint32_t read_domains
, uint32_t write_domain
,
458 int ret
= drm_intel_bo_emit_reloc(batch
->bo
, offset
,
460 read_domains
, write_domain
);
464 /* Using the old buffer offset, write in what the right data would be, in
465 * case the buffer doesn't move and we can short-circuit the relocation
466 * processing in the kernel
468 return buffer
->offset64
+ delta
;
473 intel_batchbuffer_data(struct brw_context
*brw
,
474 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
476 assert((bytes
& 3) == 0);
477 intel_batchbuffer_require_space(brw
, bytes
, ring
);
478 memcpy(brw
->batch
.map_next
, data
, bytes
);
479 brw
->batch
.map_next
+= bytes
>> 2;
483 load_sized_register_mem(struct brw_context
*brw
,
486 uint32_t read_domains
, uint32_t write_domain
,
492 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
493 assert(brw
->gen
>= 7);
496 BEGIN_BATCH(4 * size
);
497 for (i
= 0; i
< size
; i
++) {
498 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
499 OUT_BATCH(reg
+ i
* 4);
500 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
+ i
* 4);
504 BEGIN_BATCH(3 * size
);
505 for (i
= 0; i
< size
; i
++) {
506 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
507 OUT_BATCH(reg
+ i
* 4);
508 OUT_RELOC(bo
, read_domains
, write_domain
, offset
+ i
* 4);
515 brw_load_register_mem(struct brw_context
*brw
,
518 uint32_t read_domains
, uint32_t write_domain
,
521 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 1);
525 brw_load_register_mem64(struct brw_context
*brw
,
528 uint32_t read_domains
, uint32_t write_domain
,
531 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 2);
535 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
538 brw_store_register_mem32(struct brw_context
*brw
,
539 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
)
541 assert(brw
->gen
>= 6);
545 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
547 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
552 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
554 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
561 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
564 brw_store_register_mem64(struct brw_context
*brw
,
565 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
)
567 assert(brw
->gen
>= 6);
569 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
570 * read a full 64-bit register, we need to do two of them.
574 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
576 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
578 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
579 OUT_BATCH(reg
+ sizeof(uint32_t));
580 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
581 offset
+ sizeof(uint32_t));
585 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
587 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
589 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
590 OUT_BATCH(reg
+ sizeof(uint32_t));
591 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
592 offset
+ sizeof(uint32_t));
598 * Write a 32-bit register using immediate data.
601 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
603 assert(brw
->gen
>= 6);
606 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
613 * Write a 64-bit register using immediate data.
616 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
618 assert(brw
->gen
>= 6);
621 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
623 OUT_BATCH(imm
& 0xffffffff);
625 OUT_BATCH(imm
>> 32);
630 * Copies a 32-bit register.
633 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
635 assert(brw
->gen
>= 8 || brw
->is_haswell
);
638 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
645 * Copies a 64-bit register.
648 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
650 assert(brw
->gen
>= 8 || brw
->is_haswell
);
653 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
656 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
657 OUT_BATCH(src
+ sizeof(uint32_t));
658 OUT_BATCH(dest
+ sizeof(uint32_t));
663 * Write 32-bits of immediate data to a GPU memory buffer.
666 brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
667 uint32_t offset
, uint32_t imm
)
669 assert(brw
->gen
>= 6);
672 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
674 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
677 OUT_BATCH(0); /* MBZ */
678 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
686 * Write 64-bits of immediate data to a GPU memory buffer.
689 brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
690 uint32_t offset
, uint64_t imm
)
692 assert(brw
->gen
>= 6);
695 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
697 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
700 OUT_BATCH(0); /* MBZ */
701 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
704 OUT_BATCH(imm
& 0xffffffffu
);
705 OUT_BATCH(imm
>> 32);