2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
36 #include "util/hash_table.h"
41 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
44 * Target sizes of the batch and state buffers. We create the initial
45 * buffers at these sizes, and flush when they're nearly full. If we
46 * underestimate how close we are to the end, and suddenly need more space
47 * in the middle of a draw, we can grow the buffers, and finish the draw.
48 * At that point, we'll be over our target size, so the next operation
49 * should flush. Each time we flush the batch, we recreate both buffers
50 * at the original target size, so it doesn't grow without bound.
52 #define BATCH_SZ (20 * 1024)
53 #define STATE_SZ (16 * 1024)
56 intel_batchbuffer_reset(struct brw_context
*brw
);
59 uint_key_compare(const void *a
, const void *b
)
65 uint_key_hash(const void *key
)
67 return (uintptr_t) key
;
71 init_reloc_list(struct brw_reloc_list
*rlist
, int count
)
73 rlist
->reloc_count
= 0;
74 rlist
->reloc_array_size
= count
;
75 rlist
->relocs
= malloc(rlist
->reloc_array_size
*
76 sizeof(struct drm_i915_gem_relocation_entry
));
80 intel_batchbuffer_init(struct brw_context
*brw
)
82 struct intel_screen
*screen
= brw
->screen
;
83 struct intel_batchbuffer
*batch
= &brw
->batch
;
84 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
86 batch
->use_shadow_copy
= !devinfo
->has_llc
;
88 if (batch
->use_shadow_copy
) {
89 batch
->batch
.map
= malloc(BATCH_SZ
);
90 batch
->map_next
= batch
->batch
.map
;
91 batch
->state
.map
= malloc(STATE_SZ
);
94 init_reloc_list(&batch
->batch_relocs
, 250);
95 init_reloc_list(&batch
->state_relocs
, 250);
97 batch
->exec_count
= 0;
98 batch
->exec_array_size
= 100;
100 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
101 batch
->validation_list
=
102 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
104 if (INTEL_DEBUG
& DEBUG_BATCH
) {
105 batch
->state_batch_sizes
=
106 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
109 batch
->use_batch_first
=
110 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
112 /* PIPE_CONTROL needs a w/a but only on gen6 */
113 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
114 if (devinfo
->gen
== 6)
115 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
117 intel_batchbuffer_reset(brw
);
120 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
123 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
125 unsigned index
= READ_ONCE(bo
->index
);
127 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
130 /* May have been shared between multiple active batches */
131 for (index
= 0; index
< batch
->exec_count
; index
++) {
132 if (batch
->exec_bos
[index
] == bo
)
136 brw_bo_reference(bo
);
138 if (batch
->exec_count
== batch
->exec_array_size
) {
139 batch
->exec_array_size
*= 2;
141 realloc(batch
->exec_bos
,
142 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
143 batch
->validation_list
=
144 realloc(batch
->validation_list
,
145 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
148 batch
->validation_list
[batch
->exec_count
] =
149 (struct drm_i915_gem_exec_object2
) {
150 .handle
= bo
->gem_handle
,
151 .alignment
= bo
->align
,
152 .offset
= bo
->gtt_offset
,
156 bo
->index
= batch
->exec_count
;
157 batch
->exec_bos
[batch
->exec_count
] = bo
;
158 batch
->aperture_space
+= bo
->size
;
160 return batch
->exec_count
++;
164 recreate_growing_buffer(struct brw_context
*brw
,
165 struct brw_growing_bo
*grow
,
166 const char *name
, unsigned size
)
168 struct intel_screen
*screen
= brw
->screen
;
169 struct intel_batchbuffer
*batch
= &brw
->batch
;
170 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
172 grow
->bo
= brw_bo_alloc(bufmgr
, name
, size
, 4096);
173 grow
->bo
->kflags
= can_do_exec_capture(screen
) ? EXEC_OBJECT_CAPTURE
: 0;
174 grow
->partial_bo
= NULL
;
175 grow
->partial_bo_map
= NULL
;
176 grow
->partial_bytes
= 0;
178 if (!batch
->use_shadow_copy
)
179 grow
->map
= brw_bo_map(brw
, grow
->bo
, MAP_READ
| MAP_WRITE
);
183 intel_batchbuffer_reset(struct brw_context
*brw
)
185 struct intel_batchbuffer
*batch
= &brw
->batch
;
187 if (batch
->last_bo
!= NULL
) {
188 brw_bo_unreference(batch
->last_bo
);
189 batch
->last_bo
= NULL
;
191 batch
->last_bo
= batch
->batch
.bo
;
193 recreate_growing_buffer(brw
, &batch
->batch
, "batchbuffer", BATCH_SZ
);
194 batch
->map_next
= batch
->batch
.map
;
196 recreate_growing_buffer(brw
, &batch
->state
, "statebuffer", STATE_SZ
);
198 /* Avoid making 0 a valid state offset - otherwise the decoder will try
199 * and decode data when we use offset 0 as a null pointer.
201 batch
->state_used
= 1;
203 add_exec_bo(batch
, batch
->batch
.bo
);
204 assert(batch
->batch
.bo
->index
== 0);
206 batch
->needs_sol_reset
= false;
207 batch
->state_base_address_emitted
= false;
209 /* We don't know what ring the new batch will be sent to until we see the
210 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
212 batch
->ring
= UNKNOWN_RING
;
214 if (batch
->state_batch_sizes
)
215 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
219 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
221 intel_batchbuffer_reset(brw
);
222 brw_cache_sets_clear(brw
);
226 intel_batchbuffer_save_state(struct brw_context
*brw
)
228 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
229 brw
->batch
.saved
.batch_reloc_count
= brw
->batch
.batch_relocs
.reloc_count
;
230 brw
->batch
.saved
.state_reloc_count
= brw
->batch
.state_relocs
.reloc_count
;
231 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
235 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
237 for (int i
= brw
->batch
.saved
.exec_count
;
238 i
< brw
->batch
.exec_count
; i
++) {
239 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
241 brw
->batch
.batch_relocs
.reloc_count
= brw
->batch
.saved
.batch_reloc_count
;
242 brw
->batch
.state_relocs
.reloc_count
= brw
->batch
.saved
.state_reloc_count
;
243 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
245 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
246 if (USED_BATCH(brw
->batch
) == 0)
247 brw
->batch
.ring
= UNKNOWN_RING
;
251 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
253 if (batch
->use_shadow_copy
) {
254 free(batch
->batch
.map
);
255 free(batch
->state
.map
);
258 for (int i
= 0; i
< batch
->exec_count
; i
++) {
259 brw_bo_unreference(batch
->exec_bos
[i
]);
261 free(batch
->batch_relocs
.relocs
);
262 free(batch
->state_relocs
.relocs
);
263 free(batch
->exec_bos
);
264 free(batch
->validation_list
);
266 brw_bo_unreference(batch
->last_bo
);
267 brw_bo_unreference(batch
->batch
.bo
);
268 brw_bo_unreference(batch
->state
.bo
);
269 if (batch
->state_batch_sizes
)
270 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
274 * Finish copying the old batch/state buffer's contents to the new one
275 * after we tried to "grow" the buffer in an earlier operation.
278 finish_growing_bos(struct brw_growing_bo
*grow
)
280 struct brw_bo
*old_bo
= grow
->partial_bo
;
284 memcpy(grow
->map
, grow
->partial_bo_map
, grow
->partial_bytes
);
286 grow
->partial_bo
= NULL
;
287 grow
->partial_bo_map
= NULL
;
288 grow
->partial_bytes
= 0;
290 brw_bo_unreference(old_bo
);
294 replace_bo_in_reloc_list(struct brw_reloc_list
*rlist
,
295 uint32_t old_handle
, uint32_t new_handle
)
297 for (int i
= 0; i
< rlist
->reloc_count
; i
++) {
298 if (rlist
->relocs
[i
].target_handle
== old_handle
)
299 rlist
->relocs
[i
].target_handle
= new_handle
;
304 * Grow either the batch or state buffer to a new larger size.
306 * We can't actually grow buffers, so we allocate a new one, copy over
307 * the existing contents, and update our lists to refer to the new one.
309 * Note that this is only temporary - each new batch recreates the buffers
310 * at their original target size (BATCH_SZ or STATE_SZ).
313 grow_buffer(struct brw_context
*brw
,
314 struct brw_growing_bo
*grow
,
315 unsigned existing_bytes
,
318 struct intel_batchbuffer
*batch
= &brw
->batch
;
319 struct brw_bufmgr
*bufmgr
= brw
->bufmgr
;
320 struct brw_bo
*bo
= grow
->bo
;
322 perf_debug("Growing %s - ran out of space\n", bo
->name
);
324 if (grow
->partial_bo
) {
325 /* We've already grown once, and now we need to do it again.
326 * Finish our last grow operation so we can start a new one.
327 * This should basically never happen.
329 perf_debug("Had to grow multiple times");
330 finish_growing_bos(grow
);
333 struct brw_bo
*new_bo
= brw_bo_alloc(bufmgr
, bo
->name
, new_size
, bo
->align
);
335 /* Copy existing data to the new larger buffer */
336 grow
->partial_bo_map
= grow
->map
;
338 if (batch
->use_shadow_copy
) {
339 /* We can't safely use realloc, as it may move the existing buffer,
340 * breaking existing pointers the caller may still be using. Just
341 * malloc a new copy and memcpy it like the normal BO path.
343 grow
->map
= malloc(new_size
);
345 grow
->map
= brw_bo_map(brw
, new_bo
, MAP_READ
| MAP_WRITE
);
348 /* Try to put the new BO at the same GTT offset as the old BO (which
349 * we're throwing away, so it doesn't need to be there).
351 * This guarantees that our relocations continue to work: values we've
352 * already written into the buffer, values we're going to write into the
353 * buffer, and the validation/relocation lists all will match.
355 * Also preserve kflags for EXEC_OBJECT_CAPTURE.
357 new_bo
->gtt_offset
= bo
->gtt_offset
;
358 new_bo
->index
= bo
->index
;
359 new_bo
->kflags
= bo
->kflags
;
361 /* Batch/state buffers are per-context, and if we've run out of space,
362 * we must have actually used them before, so...they will be in the list.
364 assert(bo
->index
< batch
->exec_count
);
365 assert(batch
->exec_bos
[bo
->index
] == bo
);
367 /* Update the validation list to use the new BO. */
368 batch
->validation_list
[bo
->index
].handle
= new_bo
->gem_handle
;
370 if (!batch
->use_batch_first
) {
371 /* We're not using I915_EXEC_HANDLE_LUT, which means we need to go
372 * update the relocation list entries to point at the new BO as well.
373 * (With newer kernels, the "handle" is an offset into the validation
374 * list, which remains unchanged, so we can skip this.)
376 replace_bo_in_reloc_list(&batch
->batch_relocs
,
377 bo
->gem_handle
, new_bo
->gem_handle
);
378 replace_bo_in_reloc_list(&batch
->state_relocs
,
379 bo
->gem_handle
, new_bo
->gem_handle
);
382 /* Exchange the two BOs...without breaking pointers to the old BO.
384 * Consider this scenario:
386 * 1. Somebody calls brw_state_batch() to get a region of memory, and
387 * and then creates a brw_address pointing to brw->batch.state.bo.
388 * 2. They then call brw_state_batch() a second time, which happens to
389 * grow and replace the state buffer. They then try to emit a
390 * relocation to their first section of memory.
392 * If we replace the brw->batch.state.bo pointer at step 2, we would
393 * break the address created in step 1. They'd have a pointer to the
394 * old destroyed BO. Emitting a relocation would add this dead BO to
395 * the validation list...causing /both/ statebuffers to be in the list,
396 * and all kinds of disasters.
398 * This is not a contrived case - BLORP vertex data upload hits this.
400 * There are worse scenarios too. Fences for GL sync objects reference
401 * brw->batch.batch.bo. If we replaced the batch pointer when growing,
402 * we'd need to chase down every fence and update it to point to the
403 * new BO. Otherwise, it would refer to a "batch" that never actually
404 * gets submitted, and would fail to trigger.
406 * To work around both of these issues, we transmutate the buffers in
407 * place, making the existing struct brw_bo represent the new buffer,
408 * and "new_bo" represent the old BO. This is highly unusual, but it
409 * seems like a necessary evil.
411 * We also defer the memcpy of the existing batch's contents. Callers
412 * may make multiple brw_state_batch calls, and retain pointers to the
413 * old BO's map. We'll perform the memcpy in finish_growing_bo() when
414 * we finally submit the batch, at which point we've finished uploading
415 * state, and nobody should have any old references anymore.
417 * To do that, we keep a reference to the old BO in grow->partial_bo,
418 * and store the number of bytes to copy in grow->partial_bytes. We
419 * can monkey with the refcounts directly without atomics because these
420 * are per-context BOs and they can only be touched by this thread.
422 assert(new_bo
->refcount
== 1);
423 new_bo
->refcount
= bo
->refcount
;
427 memcpy(&tmp
, bo
, sizeof(struct brw_bo
));
428 memcpy(bo
, new_bo
, sizeof(struct brw_bo
));
429 memcpy(new_bo
, &tmp
, sizeof(struct brw_bo
));
431 grow
->partial_bo
= new_bo
; /* the one reference of the OLD bo */
432 grow
->partial_bytes
= existing_bytes
;
436 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
437 enum brw_gpu_ring ring
)
439 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
440 struct intel_batchbuffer
*batch
= &brw
->batch
;
442 /* If we're switching rings, implicitly flush the batch. */
443 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
445 intel_batchbuffer_flush(brw
);
448 const unsigned batch_used
= USED_BATCH(*batch
) * 4;
449 if (batch_used
+ sz
>= BATCH_SZ
&& !batch
->no_wrap
) {
450 intel_batchbuffer_flush(brw
);
451 } else if (batch_used
+ sz
>= batch
->batch
.bo
->size
) {
452 const unsigned new_size
=
453 MIN2(batch
->batch
.bo
->size
+ batch
->batch
.bo
->size
/ 2,
455 grow_buffer(brw
, &batch
->batch
, batch_used
, new_size
);
456 batch
->map_next
= (void *) batch
->batch
.map
+ batch_used
;
457 assert(batch_used
+ sz
< batch
->batch
.bo
->size
);
460 /* The intel_batchbuffer_flush() calls above might have changed
461 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
463 brw
->batch
.ring
= ring
;
468 #define BLUE_HEADER CSI "0;44m"
469 #define NORMAL CSI "0m"
473 decode_struct(struct brw_context
*brw
, struct gen_spec
*spec
,
474 const char *struct_name
, uint32_t *data
,
475 uint32_t gtt_offset
, uint32_t offset
, bool color
)
477 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
481 fprintf(stderr
, "%s\n", struct_name
);
482 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
483 &data
[offset
/ 4], 0, color
);
487 decode_structs(struct brw_context
*brw
, struct gen_spec
*spec
,
488 const char *struct_name
,
489 uint32_t *data
, uint32_t gtt_offset
, uint32_t offset
,
490 int struct_size
, bool color
)
492 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
496 int entries
= brw_state_batch_size(brw
, offset
) / struct_size
;
497 for (int i
= 0; i
< entries
; i
++) {
498 fprintf(stderr
, "%s %d\n", struct_name
, i
);
499 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
500 &data
[(offset
+ i
* struct_size
) / 4], 0, color
);
505 do_batch_dump(struct brw_context
*brw
)
507 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
508 struct intel_batchbuffer
*batch
= &brw
->batch
;
509 struct gen_spec
*spec
= gen_spec_load(&brw
->screen
->devinfo
);
511 if (batch
->ring
!= RENDER_RING
)
514 uint32_t *batch_data
= brw_bo_map(brw
, batch
->batch
.bo
, MAP_READ
);
515 uint32_t *state
= brw_bo_map(brw
, batch
->state
.bo
, MAP_READ
);
516 if (batch_data
== NULL
|| state
== NULL
) {
517 fprintf(stderr
, "WARNING: failed to map batchbuffer/statebuffer\n");
521 uint32_t *end
= batch_data
+ USED_BATCH(*batch
);
522 uint32_t batch_gtt_offset
= batch
->batch
.bo
->gtt_offset
;
523 uint32_t state_gtt_offset
= batch
->state
.bo
->gtt_offset
;
526 bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
527 const char *header_color
= color
? BLUE_HEADER
: "";
528 const char *reset_color
= color
? NORMAL
: "";
530 for (uint32_t *p
= batch_data
; p
< end
; p
+= length
) {
531 struct gen_group
*inst
= gen_spec_find_instruction(spec
, p
);
532 length
= gen_group_get_length(inst
, p
);
533 assert(inst
== NULL
|| length
> 0);
534 length
= MAX2(1, length
);
536 fprintf(stderr
, "unknown instruction %08x\n", p
[0]);
540 uint64_t offset
= batch_gtt_offset
+ 4 * (p
- batch_data
);
542 fprintf(stderr
, "%s0x%08"PRIx64
": 0x%08x: %-80s%s\n", header_color
,
543 offset
, p
[0], gen_group_get_name(inst
), reset_color
);
545 gen_print_group(stderr
, inst
, offset
, p
, 0, color
);
547 switch (gen_group_get_opcode(inst
) >> 16) {
548 case _3DSTATE_PIPELINED_POINTERS
:
549 /* Note: these Gen4-5 pointers are full relocations rather than
550 * offsets from the start of the statebuffer. So we need to subtract
551 * gtt_offset (the start of the statebuffer) to obtain an offset we
552 * can add to the map and get at the data.
554 decode_struct(brw
, spec
, "VS_STATE", state
, state_gtt_offset
,
555 (p
[1] & ~0x1fu
) - state_gtt_offset
, color
);
557 decode_struct(brw
, spec
, "GS_STATE", state
, state_gtt_offset
,
558 (p
[2] & ~0x1fu
) - state_gtt_offset
, color
);
561 decode_struct(brw
, spec
, "CLIP_STATE", state
, state_gtt_offset
,
562 (p
[3] & ~0x1fu
) - state_gtt_offset
, color
);
564 decode_struct(brw
, spec
, "SF_STATE", state
, state_gtt_offset
,
565 (p
[4] & ~0x1fu
) - state_gtt_offset
, color
);
566 decode_struct(brw
, spec
, "WM_STATE", state
, state_gtt_offset
,
567 (p
[5] & ~0x1fu
) - state_gtt_offset
, color
);
568 decode_struct(brw
, spec
, "COLOR_CALC_STATE", state
, state_gtt_offset
,
569 (p
[6] & ~0x3fu
) - state_gtt_offset
, color
);
571 case _3DSTATE_BINDING_TABLE_POINTERS_VS
:
572 case _3DSTATE_BINDING_TABLE_POINTERS_HS
:
573 case _3DSTATE_BINDING_TABLE_POINTERS_DS
:
574 case _3DSTATE_BINDING_TABLE_POINTERS_GS
:
575 case _3DSTATE_BINDING_TABLE_POINTERS_PS
: {
576 struct gen_group
*group
=
577 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
581 uint32_t bt_offset
= p
[1] & ~0x1fu
;
582 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
583 uint32_t *bt_pointers
= &state
[bt_offset
/ 4];
584 for (int i
= 0; i
< bt_entries
; i
++) {
585 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
586 gen_print_group(stderr
, group
, state_gtt_offset
+ bt_pointers
[i
],
587 &state
[bt_pointers
[i
] / 4], 0, color
);
591 case _3DSTATE_SAMPLER_STATE_POINTERS_VS
:
592 case _3DSTATE_SAMPLER_STATE_POINTERS_HS
:
593 case _3DSTATE_SAMPLER_STATE_POINTERS_DS
:
594 case _3DSTATE_SAMPLER_STATE_POINTERS_GS
:
595 case _3DSTATE_SAMPLER_STATE_POINTERS_PS
:
596 decode_structs(brw
, spec
, "SAMPLER_STATE", state
,
597 state_gtt_offset
, p
[1] & ~0x1fu
, 4 * 4, color
);
599 case _3DSTATE_VIEWPORT_STATE_POINTERS
:
600 decode_structs(brw
, spec
, "CLIP_VIEWPORT", state
,
601 state_gtt_offset
, p
[1] & ~0x3fu
, 4 * 4, color
);
602 decode_structs(brw
, spec
, "SF_VIEWPORT", state
,
603 state_gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
604 decode_structs(brw
, spec
, "CC_VIEWPORT", state
,
605 state_gtt_offset
, p
[3] & ~0x3fu
, 2 * 4, color
);
607 case _3DSTATE_VIEWPORT_STATE_POINTERS_CC
:
608 decode_structs(brw
, spec
, "CC_VIEWPORT", state
,
609 state_gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
611 case _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
:
612 decode_structs(brw
, spec
, "SF_CLIP_VIEWPORT", state
,
613 state_gtt_offset
, p
[1] & ~0x3fu
, 16 * 4, color
);
615 case _3DSTATE_SCISSOR_STATE_POINTERS
:
616 decode_structs(brw
, spec
, "SCISSOR_RECT", state
,
617 state_gtt_offset
, p
[1] & ~0x1fu
, 2 * 4, color
);
619 case _3DSTATE_BLEND_STATE_POINTERS
:
620 /* TODO: handle Gen8+ extra dword at the beginning */
621 decode_structs(brw
, spec
, "BLEND_STATE", state
,
622 state_gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
624 case _3DSTATE_CC_STATE_POINTERS
:
625 if (devinfo
->gen
>= 7) {
626 decode_struct(brw
, spec
, "COLOR_CALC_STATE", state
,
627 state_gtt_offset
, p
[1] & ~0x3fu
, color
);
628 } else if (devinfo
->gen
== 6) {
629 decode_structs(brw
, spec
, "BLEND_STATE", state
,
630 state_gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
631 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", state
,
632 state_gtt_offset
, p
[2] & ~0x3fu
, color
);
633 decode_struct(brw
, spec
, "COLOR_CALC_STATE", state
,
634 state_gtt_offset
, p
[3] & ~0x3fu
, color
);
637 case _3DSTATE_DEPTH_STENCIL_STATE_POINTERS
:
638 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", state
,
639 state_gtt_offset
, p
[1] & ~0x3fu
, color
);
641 case MEDIA_INTERFACE_DESCRIPTOR_LOAD
: {
642 struct gen_group
*group
=
643 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
647 uint32_t idd_offset
= p
[3] & ~0x1fu
;
648 decode_struct(brw
, spec
, "INTERFACE_DESCRIPTOR_DATA", state
,
649 state_gtt_offset
, idd_offset
, color
);
651 uint32_t ss_offset
= state
[idd_offset
/ 4 + 3] & ~0x1fu
;
652 decode_structs(brw
, spec
, "SAMPLER_STATE", state
,
653 state_gtt_offset
, ss_offset
, 4 * 4, color
);
655 uint32_t bt_offset
= state
[idd_offset
/ 4 + 4] & ~0x1fu
;
656 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
657 uint32_t *bt_pointers
= &state
[bt_offset
/ 4];
658 for (int i
= 0; i
< bt_entries
; i
++) {
659 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
660 gen_print_group(stderr
, group
, state_gtt_offset
+ bt_pointers
[i
],
661 &state
[bt_pointers
[i
] / 4], 0, color
);
668 brw_bo_unmap(batch
->batch
.bo
);
669 brw_bo_unmap(batch
->state
.bo
);
672 static void do_batch_dump(struct brw_context
*brw
) { }
676 * Called when starting a new batch buffer.
679 brw_new_batch(struct brw_context
*brw
)
681 /* Unreference any BOs held by the previous batch, and reset counts. */
682 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
683 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
684 brw
->batch
.exec_bos
[i
] = NULL
;
686 brw
->batch
.batch_relocs
.reloc_count
= 0;
687 brw
->batch
.state_relocs
.reloc_count
= 0;
688 brw
->batch
.exec_count
= 0;
689 brw
->batch
.aperture_space
= 0;
691 brw_bo_unreference(brw
->batch
.state
.bo
);
693 /* Create a new batchbuffer and reset the associated state: */
694 intel_batchbuffer_reset_and_clear_render_cache(brw
);
696 /* If the kernel supports hardware contexts, then most hardware state is
697 * preserved between batches; we only need to re-emit state that is required
698 * to be in every batch. Otherwise we need to re-emit all the state that
699 * would otherwise be stored in the context (which for all intents and
700 * purposes means everything).
702 if (brw
->hw_ctx
== 0) {
703 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
704 brw_upload_invariant_state(brw
);
707 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
709 brw
->ib
.index_size
= -1;
711 /* We need to periodically reap the shader time results, because rollover
712 * happens every few seconds. We also want to see results every once in a
713 * while, because many programs won't cleanly destroy our context, so the
714 * end-of-run printout may not happen.
716 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
717 brw_collect_and_report_shader_time(brw
);
721 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
724 * This function can emit state (say, to preserve registers that aren't saved
728 brw_finish_batch(struct brw_context
*brw
)
730 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
732 brw
->batch
.no_wrap
= true;
734 /* Capture the closing pipeline statistics register values necessary to
735 * support query objects (in the non-hardware context world).
737 brw_emit_query_end(brw
);
739 if (brw
->batch
.ring
== RENDER_RING
) {
740 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
741 * assume that the L3 cache is configured according to the hardware
744 if (devinfo
->gen
>= 7)
745 gen7_restore_default_l3_config(brw
);
747 if (devinfo
->is_haswell
) {
748 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
749 * 3DSTATE_CC_STATE_POINTERS > "Note":
751 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
752 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
754 * From the example in the docs, it seems to expect a regular pipe control
755 * flush here as well. We may have done it already, but meh.
757 * See also WaAvoidRCZCounterRollover.
759 brw_emit_mi_flush(brw
);
761 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
762 OUT_BATCH(brw
->cc
.state_offset
| 1);
764 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
765 PIPE_CONTROL_CS_STALL
);
768 /* Do not restore push constant packets during context restore. */
769 if (devinfo
->gen
>= 7)
770 gen10_emit_isp_disable(brw
);
773 /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
774 * requires our batch size to be QWord aligned, so we pad it out if
775 * necessary by emitting an extra MI_NOOP after the end.
777 intel_batchbuffer_require_space(brw
, 8, brw
->batch
.ring
);
778 *brw
->batch
.map_next
++ = MI_BATCH_BUFFER_END
;
779 if (USED_BATCH(brw
->batch
) & 1) {
780 *brw
->batch
.map_next
++ = MI_NOOP
;
783 brw
->batch
.no_wrap
= false;
787 throttle(struct brw_context
*brw
)
789 /* Wait for the swapbuffers before the one we just emitted, so we
790 * don't get too many swaps outstanding for apps that are GPU-heavy
793 * We're using intelDRI2Flush (called from the loader before
794 * swapbuffer) and glFlush (for front buffer rendering) as the
795 * indicator that a frame is done and then throttle when we get
796 * here as we prepare to render the next frame. At this point for
797 * round trips for swap/copy and getting new buffers are done and
798 * we'll spend less time waiting on the GPU.
800 * Unfortunately, we don't have a handle to the batch containing
801 * the swap, and getting our hands on that doesn't seem worth it,
802 * so we just use the first batch we emitted after the last swap.
804 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
805 if (brw
->throttle_batch
[1]) {
806 if (!brw
->disable_throttling
) {
807 /* Pass NULL rather than brw so we avoid perf_debug warnings;
808 * stalling is common and expected here...
810 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
812 brw_bo_unreference(brw
->throttle_batch
[1]);
814 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
815 brw
->throttle_batch
[0] = NULL
;
816 brw
->need_swap_throttle
= false;
817 /* Throttling here is more precise than the throttle ioctl, so skip it */
818 brw
->need_flush_throttle
= false;
821 if (brw
->need_flush_throttle
) {
822 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
823 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
824 brw
->need_flush_throttle
= false;
830 struct intel_batchbuffer
*batch
,
837 struct drm_i915_gem_execbuffer2 execbuf
= {
838 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
839 .buffer_count
= batch
->exec_count
,
840 .batch_start_offset
= 0,
843 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
846 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
848 if (in_fence
!= -1) {
849 execbuf
.rsvd2
= in_fence
;
850 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
853 if (out_fence
!= NULL
) {
854 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
856 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
859 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
863 for (int i
= 0; i
< batch
->exec_count
; i
++) {
864 struct brw_bo
*bo
= batch
->exec_bos
[i
];
869 /* Update brw_bo::gtt_offset */
870 if (batch
->validation_list
[i
].offset
!= bo
->gtt_offset
) {
871 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
872 bo
->gem_handle
, bo
->gtt_offset
,
873 batch
->validation_list
[i
].offset
);
874 bo
->gtt_offset
= batch
->validation_list
[i
].offset
;
878 if (ret
== 0 && out_fence
!= NULL
)
879 *out_fence
= execbuf
.rsvd2
>> 32;
885 submit_batch(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
887 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
888 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
889 struct intel_batchbuffer
*batch
= &brw
->batch
;
892 if (batch
->use_shadow_copy
) {
893 void *bo_map
= brw_bo_map(brw
, batch
->batch
.bo
, MAP_WRITE
);
894 memcpy(bo_map
, batch
->batch
.map
, 4 * USED_BATCH(*batch
));
896 bo_map
= brw_bo_map(brw
, batch
->state
.bo
, MAP_WRITE
);
897 memcpy(bo_map
, batch
->state
.map
, batch
->state_used
);
900 brw_bo_unmap(batch
->batch
.bo
);
901 brw_bo_unmap(batch
->state
.bo
);
903 if (!brw
->screen
->no_hw
) {
904 /* The requirement for using I915_EXEC_NO_RELOC are:
906 * The addresses written in the objects must match the corresponding
907 * reloc.gtt_offset which in turn must match the corresponding
910 * Any render targets written to in the batch must be flagged with
913 * To avoid stalling, execobject.offset should match the current
914 * address of that object within the active context.
916 int flags
= I915_EXEC_NO_RELOC
;
918 if (devinfo
->gen
>= 6 && batch
->ring
== BLT_RING
) {
919 flags
|= I915_EXEC_BLT
;
921 flags
|= I915_EXEC_RENDER
;
923 if (batch
->needs_sol_reset
)
924 flags
|= I915_EXEC_GEN7_SOL_RESET
;
926 uint32_t hw_ctx
= batch
->ring
== RENDER_RING
? brw
->hw_ctx
: 0;
928 /* Set statebuffer relocations */
929 const unsigned state_index
= batch
->state
.bo
->index
;
930 if (state_index
< batch
->exec_count
&&
931 batch
->exec_bos
[state_index
] == batch
->state
.bo
) {
932 struct drm_i915_gem_exec_object2
*entry
=
933 &batch
->validation_list
[state_index
];
934 assert(entry
->handle
== batch
->state
.bo
->gem_handle
);
935 entry
->relocation_count
= batch
->state_relocs
.reloc_count
;
936 entry
->relocs_ptr
= (uintptr_t) batch
->state_relocs
.relocs
;
939 /* Set batchbuffer relocations */
940 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
941 assert(entry
->handle
== batch
->batch
.bo
->gem_handle
);
942 entry
->relocation_count
= batch
->batch_relocs
.reloc_count
;
943 entry
->relocs_ptr
= (uintptr_t) batch
->batch_relocs
.relocs
;
945 if (batch
->use_batch_first
) {
946 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
948 /* Move the batch to the end of the validation list */
949 struct drm_i915_gem_exec_object2 tmp
;
950 const unsigned index
= batch
->exec_count
- 1;
953 *entry
= batch
->validation_list
[index
];
954 batch
->validation_list
[index
] = tmp
;
957 ret
= execbuffer(dri_screen
->fd
, batch
, hw_ctx
,
958 4 * USED_BATCH(*batch
),
959 in_fence_fd
, out_fence_fd
, flags
);
964 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
967 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
968 brw_check_for_reset(brw
);
971 fprintf(stderr
, "i965: Failed to submit batchbuffer: %s\n",
980 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
983 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
984 * of the returned fd.
987 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
988 int in_fence_fd
, int *out_fence_fd
,
989 const char *file
, int line
)
993 if (USED_BATCH(brw
->batch
) == 0)
996 /* Check that we didn't just wrap our batchbuffer at a bad time. */
997 assert(!brw
->batch
.no_wrap
);
999 brw_finish_batch(brw
);
1000 intel_upload_finish(brw
);
1002 finish_growing_bos(&brw
->batch
.batch
);
1003 finish_growing_bos(&brw
->batch
.state
);
1005 if (brw
->throttle_batch
[0] == NULL
) {
1006 brw
->throttle_batch
[0] = brw
->batch
.batch
.bo
;
1007 brw_bo_reference(brw
->throttle_batch
[0]);
1010 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
1011 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
1012 int bytes_for_state
= brw
->batch
.state_used
;
1013 fprintf(stderr
, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
1014 " %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
1015 " %4d batch relocs, %4d state relocs\n", file
, line
,
1016 bytes_for_commands
, 100.0f
* bytes_for_commands
/ BATCH_SZ
,
1017 bytes_for_state
, 100.0f
* bytes_for_state
/ STATE_SZ
,
1018 brw
->batch
.exec_count
,
1019 (float) brw
->batch
.aperture_space
/ (1024 * 1024),
1020 brw
->batch
.batch_relocs
.reloc_count
,
1021 brw
->batch
.state_relocs
.reloc_count
);
1024 ret
= submit_batch(brw
, in_fence_fd
, out_fence_fd
);
1026 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
1027 fprintf(stderr
, "waiting for idle\n");
1028 brw_bo_wait_rendering(brw
->batch
.batch
.bo
);
1031 /* Start a new batch buffer. */
1038 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
1040 return brw
->batch
.aperture_space
+ extra_space
<=
1041 brw
->screen
->aperture_threshold
;
1045 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
1047 unsigned index
= READ_ONCE(bo
->index
);
1048 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
1051 for (int i
= 0; i
< batch
->exec_count
; i
++) {
1052 if (batch
->exec_bos
[i
] == bo
)
1058 /* This is the only way buffers get added to the validate list.
1061 emit_reloc(struct intel_batchbuffer
*batch
,
1062 struct brw_reloc_list
*rlist
, uint32_t offset
,
1063 struct brw_bo
*target
, uint32_t target_offset
,
1064 unsigned int reloc_flags
)
1066 assert(target
!= NULL
);
1068 if (rlist
->reloc_count
== rlist
->reloc_array_size
) {
1069 rlist
->reloc_array_size
*= 2;
1070 rlist
->relocs
= realloc(rlist
->relocs
,
1071 rlist
->reloc_array_size
*
1072 sizeof(struct drm_i915_gem_relocation_entry
));
1075 unsigned int index
= add_exec_bo(batch
, target
);
1076 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
1079 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
1081 rlist
->relocs
[rlist
->reloc_count
++] =
1082 (struct drm_i915_gem_relocation_entry
) {
1084 .delta
= target_offset
,
1085 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
1086 .presumed_offset
= entry
->offset
,
1089 /* Using the old buffer offset, write in what the right data would be, in
1090 * case the buffer doesn't move and we can short-circuit the relocation
1091 * processing in the kernel
1093 return entry
->offset
+ target_offset
;
1097 brw_batch_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
1098 struct brw_bo
*target
, uint32_t target_offset
,
1099 unsigned int reloc_flags
)
1101 assert(batch_offset
<= batch
->batch
.bo
->size
- sizeof(uint32_t));
1103 return emit_reloc(batch
, &batch
->batch_relocs
, batch_offset
,
1104 target
, target_offset
, reloc_flags
);
1108 brw_state_reloc(struct intel_batchbuffer
*batch
, uint32_t state_offset
,
1109 struct brw_bo
*target
, uint32_t target_offset
,
1110 unsigned int reloc_flags
)
1112 assert(state_offset
<= batch
->state
.bo
->size
- sizeof(uint32_t));
1114 return emit_reloc(batch
, &batch
->state_relocs
, state_offset
,
1115 target
, target_offset
, reloc_flags
);
1120 brw_state_batch_size(struct brw_context
*brw
, uint32_t offset
)
1122 struct hash_entry
*entry
=
1123 _mesa_hash_table_search(brw
->batch
.state_batch_sizes
,
1124 (void *) (uintptr_t) offset
);
1125 return entry
? (uintptr_t) entry
->data
: 0;
1129 * Reserve some space in the statebuffer, or flush.
1131 * This is used to estimate when we're near the end of the batch,
1132 * so we can flush early.
1135 brw_require_statebuffer_space(struct brw_context
*brw
, int size
)
1137 if (brw
->batch
.state_used
+ size
>= STATE_SZ
)
1138 intel_batchbuffer_flush(brw
);
1142 * Allocates a block of space in the batchbuffer for indirect state.
1145 brw_state_batch(struct brw_context
*brw
,
1148 uint32_t *out_offset
)
1150 struct intel_batchbuffer
*batch
= &brw
->batch
;
1152 assert(size
< batch
->state
.bo
->size
);
1154 uint32_t offset
= ALIGN(batch
->state_used
, alignment
);
1156 if (offset
+ size
>= STATE_SZ
&& !batch
->no_wrap
) {
1157 intel_batchbuffer_flush(brw
);
1158 offset
= ALIGN(batch
->state_used
, alignment
);
1159 } else if (offset
+ size
>= batch
->state
.bo
->size
) {
1160 const unsigned new_size
=
1161 MIN2(batch
->state
.bo
->size
+ batch
->state
.bo
->size
/ 2,
1163 grow_buffer(brw
, &batch
->state
, batch
->state_used
, new_size
);
1164 assert(offset
+ size
< batch
->state
.bo
->size
);
1167 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
1168 _mesa_hash_table_insert(batch
->state_batch_sizes
,
1169 (void *) (uintptr_t) offset
,
1170 (void *) (uintptr_t) size
);
1173 batch
->state_used
= offset
+ size
;
1175 *out_offset
= offset
;
1176 return batch
->state
.map
+ (offset
>> 2);
1180 intel_batchbuffer_data(struct brw_context
*brw
,
1181 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
1183 assert((bytes
& 3) == 0);
1184 intel_batchbuffer_require_space(brw
, bytes
, ring
);
1185 memcpy(brw
->batch
.map_next
, data
, bytes
);
1186 brw
->batch
.map_next
+= bytes
>> 2;
1190 load_sized_register_mem(struct brw_context
*brw
,
1196 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1199 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
1200 assert(devinfo
->gen
>= 7);
1202 if (devinfo
->gen
>= 8) {
1203 BEGIN_BATCH(4 * size
);
1204 for (i
= 0; i
< size
; i
++) {
1205 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
1206 OUT_BATCH(reg
+ i
* 4);
1207 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
1211 BEGIN_BATCH(3 * size
);
1212 for (i
= 0; i
< size
; i
++) {
1213 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
1214 OUT_BATCH(reg
+ i
* 4);
1215 OUT_RELOC(bo
, 0, offset
+ i
* 4);
1222 brw_load_register_mem(struct brw_context
*brw
,
1227 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
1231 brw_load_register_mem64(struct brw_context
*brw
,
1236 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
1240 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
1243 brw_store_register_mem32(struct brw_context
*brw
,
1244 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1246 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1248 assert(devinfo
->gen
>= 6);
1250 if (devinfo
->gen
>= 8) {
1252 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1254 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1258 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1260 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1266 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
1269 brw_store_register_mem64(struct brw_context
*brw
,
1270 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1272 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1274 assert(devinfo
->gen
>= 6);
1276 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
1277 * read a full 64-bit register, we need to do two of them.
1279 if (devinfo
->gen
>= 8) {
1281 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1283 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1284 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1285 OUT_BATCH(reg
+ sizeof(uint32_t));
1286 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
1290 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1292 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1293 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1294 OUT_BATCH(reg
+ sizeof(uint32_t));
1295 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
1301 * Write a 32-bit register using immediate data.
1304 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
1306 assert(brw
->screen
->devinfo
.gen
>= 6);
1309 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
1316 * Write a 64-bit register using immediate data.
1319 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
1321 assert(brw
->screen
->devinfo
.gen
>= 6);
1324 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
1326 OUT_BATCH(imm
& 0xffffffff);
1328 OUT_BATCH(imm
>> 32);
1333 * Copies a 32-bit register.
1336 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1338 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1341 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1348 * Copies a 64-bit register.
1351 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1353 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1356 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1359 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1360 OUT_BATCH(src
+ sizeof(uint32_t));
1361 OUT_BATCH(dest
+ sizeof(uint32_t));
1366 * Write 32-bits of immediate data to a GPU memory buffer.
1369 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1370 uint32_t offset
, uint32_t imm
)
1372 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1374 assert(devinfo
->gen
>= 6);
1377 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1378 if (devinfo
->gen
>= 8)
1379 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1381 OUT_BATCH(0); /* MBZ */
1382 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1389 * Write 64-bits of immediate data to a GPU memory buffer.
1392 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1393 uint32_t offset
, uint64_t imm
)
1395 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1397 assert(devinfo
->gen
>= 6);
1400 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1401 if (devinfo
->gen
>= 8)
1402 OUT_RELOC64(bo
, 0, offset
);
1404 OUT_BATCH(0); /* MBZ */
1405 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1407 OUT_BATCH(imm
& 0xffffffffu
);
1408 OUT_BATCH(imm
>> 32);