2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
35 #include "common/gen_gem.h"
37 #include "util/hash_table.h"
40 #include "drm-uapi/i915_drm.h"
42 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
45 * Target sizes of the batch and state buffers. We create the initial
46 * buffers at these sizes, and flush when they're nearly full. If we
47 * underestimate how close we are to the end, and suddenly need more space
48 * in the middle of a draw, we can grow the buffers, and finish the draw.
49 * At that point, we'll be over our target size, so the next operation
50 * should flush. Each time we flush the batch, we recreate both buffers
51 * at the original target size, so it doesn't grow without bound.
53 #define BATCH_SZ (20 * 1024)
54 #define STATE_SZ (16 * 1024)
57 intel_batchbuffer_reset(struct brw_context
*brw
);
59 brw_new_batch(struct brw_context
*brw
);
62 dump_validation_list(struct intel_batchbuffer
*batch
)
64 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
66 for (int i
= 0; i
< batch
->exec_count
; i
++) {
67 uint64_t flags
= batch
->validation_list
[i
].flags
;
68 assert(batch
->validation_list
[i
].handle
==
69 batch
->exec_bos
[i
]->gem_handle
);
70 fprintf(stderr
, "[%2d]: %2d %-14s %p %s%-7s @ 0x%016llx%s (%"PRIu64
"B)\n",
72 batch
->validation_list
[i
].handle
,
73 batch
->exec_bos
[i
]->name
,
75 (flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) ? "(48b" : "(32b",
76 (flags
& EXEC_OBJECT_WRITE
) ? " write)" : ")",
77 batch
->validation_list
[i
].offset
,
78 (flags
& EXEC_OBJECT_PINNED
) ? " (pinned)" : "",
79 batch
->exec_bos
[i
]->size
);
83 static struct gen_batch_decode_bo
84 decode_get_bo(void *v_brw
, bool ppgtt
, uint64_t address
)
86 struct brw_context
*brw
= v_brw
;
87 struct intel_batchbuffer
*batch
= &brw
->batch
;
89 for (int i
= 0; i
< batch
->exec_count
; i
++) {
90 struct brw_bo
*bo
= batch
->exec_bos
[i
];
91 /* The decoder zeroes out the top 16 bits, so we need to as well */
92 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
94 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
95 return (struct gen_batch_decode_bo
) {
98 .map
= brw_bo_map(brw
, bo
, MAP_READ
) + (address
- bo_address
),
103 return (struct gen_batch_decode_bo
) { };
107 decode_get_state_size(void *v_brw
, uint64_t address
, uint64_t base_address
)
109 struct brw_context
*brw
= v_brw
;
110 struct intel_batchbuffer
*batch
= &brw
->batch
;
111 unsigned size
= (uintptr_t)
112 _mesa_hash_table_u64_search(batch
->state_batch_sizes
,
113 address
- base_address
);
118 init_reloc_list(struct brw_reloc_list
*rlist
, int count
)
120 rlist
->reloc_count
= 0;
121 rlist
->reloc_array_size
= count
;
122 rlist
->relocs
= malloc(rlist
->reloc_array_size
*
123 sizeof(struct drm_i915_gem_relocation_entry
));
127 intel_batchbuffer_init(struct brw_context
*brw
)
129 struct intel_screen
*screen
= brw
->screen
;
130 struct intel_batchbuffer
*batch
= &brw
->batch
;
131 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
133 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
134 /* The shadow doesn't get relocs written so state decode fails. */
135 batch
->use_shadow_copy
= false;
137 batch
->use_shadow_copy
= !devinfo
->has_llc
;
139 init_reloc_list(&batch
->batch_relocs
, 250);
140 init_reloc_list(&batch
->state_relocs
, 250);
142 batch
->batch
.map
= NULL
;
143 batch
->state
.map
= NULL
;
144 batch
->exec_count
= 0;
145 batch
->exec_array_size
= 100;
147 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
148 batch
->validation_list
=
149 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
151 if (INTEL_DEBUG
& DEBUG_BATCH
) {
152 batch
->state_batch_sizes
=
153 _mesa_hash_table_u64_create(NULL
);
155 const unsigned decode_flags
=
156 GEN_BATCH_DECODE_FULL
|
157 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
158 GEN_BATCH_DECODE_OFFSETS
|
159 GEN_BATCH_DECODE_FLOATS
;
161 gen_batch_decode_ctx_init(&batch
->decoder
, devinfo
, stderr
,
162 decode_flags
, NULL
, decode_get_bo
,
163 decode_get_state_size
, brw
);
164 batch
->decoder
.max_vbo_decoded_lines
= 100;
167 batch
->use_batch_first
=
168 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
170 /* PIPE_CONTROL needs a w/a but only on gen6 */
171 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
172 if (devinfo
->gen
== 6)
173 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
175 intel_batchbuffer_reset(brw
);
178 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
181 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
183 assert(bo
->bufmgr
== batch
->batch
.bo
->bufmgr
);
185 unsigned index
= READ_ONCE(bo
->index
);
187 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
190 /* May have been shared between multiple active batches */
191 for (index
= 0; index
< batch
->exec_count
; index
++) {
192 if (batch
->exec_bos
[index
] == bo
)
196 brw_bo_reference(bo
);
198 if (batch
->exec_count
== batch
->exec_array_size
) {
199 batch
->exec_array_size
*= 2;
201 realloc(batch
->exec_bos
,
202 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
203 batch
->validation_list
=
204 realloc(batch
->validation_list
,
205 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
208 batch
->validation_list
[batch
->exec_count
] =
209 (struct drm_i915_gem_exec_object2
) {
210 .handle
= bo
->gem_handle
,
211 .offset
= bo
->gtt_offset
,
215 bo
->index
= batch
->exec_count
;
216 batch
->exec_bos
[batch
->exec_count
] = bo
;
217 batch
->aperture_space
+= bo
->size
;
219 return batch
->exec_count
++;
223 recreate_growing_buffer(struct brw_context
*brw
,
224 struct brw_growing_bo
*grow
,
225 const char *name
, unsigned size
,
226 enum brw_memory_zone memzone
)
228 struct intel_screen
*screen
= brw
->screen
;
229 struct intel_batchbuffer
*batch
= &brw
->batch
;
230 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
232 /* We can't grow buffers when using softpin, so just overallocate them. */
233 if (brw_using_softpin(bufmgr
))
236 grow
->bo
= brw_bo_alloc(bufmgr
, name
, size
, memzone
);
237 grow
->bo
->kflags
|= can_do_exec_capture(screen
) ? EXEC_OBJECT_CAPTURE
: 0;
238 grow
->partial_bo
= NULL
;
239 grow
->partial_bo_map
= NULL
;
240 grow
->partial_bytes
= 0;
241 grow
->memzone
= memzone
;
243 if (batch
->use_shadow_copy
)
244 grow
->map
= realloc(grow
->map
, grow
->bo
->size
);
246 grow
->map
= brw_bo_map(brw
, grow
->bo
, MAP_READ
| MAP_WRITE
);
250 intel_batchbuffer_reset(struct brw_context
*brw
)
252 struct intel_batchbuffer
*batch
= &brw
->batch
;
254 if (batch
->last_bo
!= NULL
) {
255 brw_bo_unreference(batch
->last_bo
);
256 batch
->last_bo
= NULL
;
258 batch
->last_bo
= batch
->batch
.bo
;
260 recreate_growing_buffer(brw
, &batch
->batch
, "batchbuffer", BATCH_SZ
,
262 batch
->map_next
= batch
->batch
.map
;
264 recreate_growing_buffer(brw
, &batch
->state
, "statebuffer", STATE_SZ
,
265 BRW_MEMZONE_DYNAMIC
);
267 /* Avoid making 0 a valid state offset - otherwise the decoder will try
268 * and decode data when we use offset 0 as a null pointer.
270 batch
->state_used
= 1;
272 add_exec_bo(batch
, batch
->batch
.bo
);
273 assert(batch
->batch
.bo
->index
== 0);
275 batch
->needs_sol_reset
= false;
276 batch
->state_base_address_emitted
= false;
278 if (batch
->state_batch_sizes
)
279 _mesa_hash_table_u64_clear(batch
->state_batch_sizes
, NULL
);
283 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
285 intel_batchbuffer_reset(brw
);
286 brw_cache_sets_clear(brw
);
290 intel_batchbuffer_save_state(struct brw_context
*brw
)
292 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
293 brw
->batch
.saved
.batch_reloc_count
= brw
->batch
.batch_relocs
.reloc_count
;
294 brw
->batch
.saved
.state_reloc_count
= brw
->batch
.state_relocs
.reloc_count
;
295 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
299 intel_batchbuffer_saved_state_is_empty(struct brw_context
*brw
)
301 struct intel_batchbuffer
*batch
= &brw
->batch
;
302 return (batch
->saved
.map_next
== batch
->batch
.map
);
306 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
308 for (int i
= brw
->batch
.saved
.exec_count
;
309 i
< brw
->batch
.exec_count
; i
++) {
310 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
312 brw
->batch
.batch_relocs
.reloc_count
= brw
->batch
.saved
.batch_reloc_count
;
313 brw
->batch
.state_relocs
.reloc_count
= brw
->batch
.saved
.state_reloc_count
;
314 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
316 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
317 if (USED_BATCH(brw
->batch
) == 0)
322 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
324 if (batch
->use_shadow_copy
) {
325 free(batch
->batch
.map
);
326 free(batch
->state
.map
);
329 for (int i
= 0; i
< batch
->exec_count
; i
++) {
330 brw_bo_unreference(batch
->exec_bos
[i
]);
332 free(batch
->batch_relocs
.relocs
);
333 free(batch
->state_relocs
.relocs
);
334 free(batch
->exec_bos
);
335 free(batch
->validation_list
);
337 brw_bo_unreference(batch
->last_bo
);
338 brw_bo_unreference(batch
->batch
.bo
);
339 brw_bo_unreference(batch
->state
.bo
);
340 if (batch
->state_batch_sizes
) {
341 _mesa_hash_table_u64_destroy(batch
->state_batch_sizes
, NULL
);
342 gen_batch_decode_ctx_finish(&batch
->decoder
);
347 * Finish copying the old batch/state buffer's contents to the new one
348 * after we tried to "grow" the buffer in an earlier operation.
351 finish_growing_bos(struct brw_growing_bo
*grow
)
353 struct brw_bo
*old_bo
= grow
->partial_bo
;
357 memcpy(grow
->map
, grow
->partial_bo_map
, grow
->partial_bytes
);
359 grow
->partial_bo
= NULL
;
360 grow
->partial_bo_map
= NULL
;
361 grow
->partial_bytes
= 0;
363 brw_bo_unreference(old_bo
);
367 replace_bo_in_reloc_list(struct brw_reloc_list
*rlist
,
368 uint32_t old_handle
, uint32_t new_handle
)
370 for (int i
= 0; i
< rlist
->reloc_count
; i
++) {
371 if (rlist
->relocs
[i
].target_handle
== old_handle
)
372 rlist
->relocs
[i
].target_handle
= new_handle
;
377 * Grow either the batch or state buffer to a new larger size.
379 * We can't actually grow buffers, so we allocate a new one, copy over
380 * the existing contents, and update our lists to refer to the new one.
382 * Note that this is only temporary - each new batch recreates the buffers
383 * at their original target size (BATCH_SZ or STATE_SZ).
386 grow_buffer(struct brw_context
*brw
,
387 struct brw_growing_bo
*grow
,
388 unsigned existing_bytes
,
391 struct intel_batchbuffer
*batch
= &brw
->batch
;
392 struct brw_bufmgr
*bufmgr
= brw
->bufmgr
;
393 struct brw_bo
*bo
= grow
->bo
;
395 /* We can't grow buffers that are softpinned, as the growing mechanism
396 * involves putting a larger buffer at the same gtt_offset...and we've
397 * only allocated the smaller amount of VMA. Without relocations, this
398 * simply won't work. This should never happen, however.
400 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
402 perf_debug("Growing %s - ran out of space\n", bo
->name
);
404 if (grow
->partial_bo
) {
405 /* We've already grown once, and now we need to do it again.
406 * Finish our last grow operation so we can start a new one.
407 * This should basically never happen.
409 perf_debug("Had to grow multiple times");
410 finish_growing_bos(grow
);
413 struct brw_bo
*new_bo
=
414 brw_bo_alloc(bufmgr
, bo
->name
, new_size
, grow
->memzone
);
416 /* Copy existing data to the new larger buffer */
417 grow
->partial_bo_map
= grow
->map
;
419 if (batch
->use_shadow_copy
) {
420 /* We can't safely use realloc, as it may move the existing buffer,
421 * breaking existing pointers the caller may still be using. Just
422 * malloc a new copy and memcpy it like the normal BO path.
424 * Use bo->size rather than new_size because the bufmgr may have
425 * rounded up the size, and we want the shadow size to match.
427 grow
->map
= malloc(new_bo
->size
);
429 grow
->map
= brw_bo_map(brw
, new_bo
, MAP_READ
| MAP_WRITE
);
432 /* Try to put the new BO at the same GTT offset as the old BO (which
433 * we're throwing away, so it doesn't need to be there).
435 * This guarantees that our relocations continue to work: values we've
436 * already written into the buffer, values we're going to write into the
437 * buffer, and the validation/relocation lists all will match.
439 * Also preserve kflags for EXEC_OBJECT_CAPTURE.
441 new_bo
->gtt_offset
= bo
->gtt_offset
;
442 new_bo
->index
= bo
->index
;
443 new_bo
->kflags
= bo
->kflags
;
445 /* Batch/state buffers are per-context, and if we've run out of space,
446 * we must have actually used them before, so...they will be in the list.
448 assert(bo
->index
< batch
->exec_count
);
449 assert(batch
->exec_bos
[bo
->index
] == bo
);
451 /* Update the validation list to use the new BO. */
452 batch
->validation_list
[bo
->index
].handle
= new_bo
->gem_handle
;
454 if (!batch
->use_batch_first
) {
455 /* We're not using I915_EXEC_HANDLE_LUT, which means we need to go
456 * update the relocation list entries to point at the new BO as well.
457 * (With newer kernels, the "handle" is an offset into the validation
458 * list, which remains unchanged, so we can skip this.)
460 replace_bo_in_reloc_list(&batch
->batch_relocs
,
461 bo
->gem_handle
, new_bo
->gem_handle
);
462 replace_bo_in_reloc_list(&batch
->state_relocs
,
463 bo
->gem_handle
, new_bo
->gem_handle
);
466 /* Exchange the two BOs...without breaking pointers to the old BO.
468 * Consider this scenario:
470 * 1. Somebody calls brw_state_batch() to get a region of memory, and
471 * and then creates a brw_address pointing to brw->batch.state.bo.
472 * 2. They then call brw_state_batch() a second time, which happens to
473 * grow and replace the state buffer. They then try to emit a
474 * relocation to their first section of memory.
476 * If we replace the brw->batch.state.bo pointer at step 2, we would
477 * break the address created in step 1. They'd have a pointer to the
478 * old destroyed BO. Emitting a relocation would add this dead BO to
479 * the validation list...causing /both/ statebuffers to be in the list,
480 * and all kinds of disasters.
482 * This is not a contrived case - BLORP vertex data upload hits this.
484 * There are worse scenarios too. Fences for GL sync objects reference
485 * brw->batch.batch.bo. If we replaced the batch pointer when growing,
486 * we'd need to chase down every fence and update it to point to the
487 * new BO. Otherwise, it would refer to a "batch" that never actually
488 * gets submitted, and would fail to trigger.
490 * To work around both of these issues, we transmutate the buffers in
491 * place, making the existing struct brw_bo represent the new buffer,
492 * and "new_bo" represent the old BO. This is highly unusual, but it
493 * seems like a necessary evil.
495 * We also defer the memcpy of the existing batch's contents. Callers
496 * may make multiple brw_state_batch calls, and retain pointers to the
497 * old BO's map. We'll perform the memcpy in finish_growing_bo() when
498 * we finally submit the batch, at which point we've finished uploading
499 * state, and nobody should have any old references anymore.
501 * To do that, we keep a reference to the old BO in grow->partial_bo,
502 * and store the number of bytes to copy in grow->partial_bytes. We
503 * can monkey with the refcounts directly without atomics because these
504 * are per-context BOs and they can only be touched by this thread.
506 assert(new_bo
->refcount
== 1);
507 new_bo
->refcount
= bo
->refcount
;
511 memcpy(&tmp
, bo
, sizeof(struct brw_bo
));
512 memcpy(bo
, new_bo
, sizeof(struct brw_bo
));
513 memcpy(new_bo
, &tmp
, sizeof(struct brw_bo
));
515 grow
->partial_bo
= new_bo
; /* the one reference of the OLD bo */
516 grow
->partial_bytes
= existing_bytes
;
520 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
)
522 struct intel_batchbuffer
*batch
= &brw
->batch
;
524 const unsigned batch_used
= USED_BATCH(*batch
) * 4;
525 if (batch_used
+ sz
>= BATCH_SZ
&& !batch
->no_wrap
) {
526 intel_batchbuffer_flush(brw
);
527 } else if (batch_used
+ sz
>= batch
->batch
.bo
->size
) {
528 const unsigned new_size
=
529 MIN2(batch
->batch
.bo
->size
+ batch
->batch
.bo
->size
/ 2,
531 grow_buffer(brw
, &batch
->batch
, batch_used
, new_size
);
532 batch
->map_next
= (void *) batch
->batch
.map
+ batch_used
;
533 assert(batch_used
+ sz
< batch
->batch
.bo
->size
);
538 * Called when starting a new batch buffer.
541 brw_new_batch(struct brw_context
*brw
)
543 /* Unreference any BOs held by the previous batch, and reset counts. */
544 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
545 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
546 brw
->batch
.exec_bos
[i
] = NULL
;
548 brw
->batch
.batch_relocs
.reloc_count
= 0;
549 brw
->batch
.state_relocs
.reloc_count
= 0;
550 brw
->batch
.exec_count
= 0;
551 brw
->batch
.aperture_space
= 0;
553 brw_bo_unreference(brw
->batch
.state
.bo
);
555 /* Create a new batchbuffer and reset the associated state: */
556 intel_batchbuffer_reset_and_clear_render_cache(brw
);
558 /* If the kernel supports hardware contexts, then most hardware state is
559 * preserved between batches; we only need to re-emit state that is required
560 * to be in every batch. Otherwise we need to re-emit all the state that
561 * would otherwise be stored in the context (which for all intents and
562 * purposes means everything).
564 if (brw
->hw_ctx
== 0) {
565 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
566 brw_upload_invariant_state(brw
);
569 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
571 brw
->ib
.index_size
= -1;
573 /* We need to periodically reap the shader time results, because rollover
574 * happens every few seconds. We also want to see results every once in a
575 * while, because many programs won't cleanly destroy our context, so the
576 * end-of-run printout may not happen.
578 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
579 brw_collect_and_report_shader_time(brw
);
581 intel_batchbuffer_maybe_noop(brw
);
585 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
588 * This function can emit state (say, to preserve registers that aren't saved
592 brw_finish_batch(struct brw_context
*brw
)
594 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
596 brw
->batch
.no_wrap
= true;
598 /* Capture the closing pipeline statistics register values necessary to
599 * support query objects (in the non-hardware context world).
601 brw_emit_query_end(brw
);
603 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
604 * assume that the L3 cache is configured according to the hardware
605 * defaults. On Kernel 4.16+, we no longer need to do this.
607 if (devinfo
->gen
>= 7 &&
608 !(brw
->screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
))
609 gen7_restore_default_l3_config(brw
);
611 if (devinfo
->is_haswell
) {
612 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
613 * 3DSTATE_CC_STATE_POINTERS > "Note":
615 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
616 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
618 * From the example in the docs, it seems to expect a regular pipe control
619 * flush here as well. We may have done it already, but meh.
621 * See also WaAvoidRCZCounterRollover.
623 brw_emit_mi_flush(brw
);
625 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
626 OUT_BATCH(brw
->cc
.state_offset
| 1);
628 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
629 PIPE_CONTROL_CS_STALL
);
632 /* Do not restore push constant packets during context restore. */
633 if (devinfo
->gen
>= 7)
634 gen10_emit_isp_disable(brw
);
636 /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
637 * requires our batch size to be QWord aligned, so we pad it out if
638 * necessary by emitting an extra MI_NOOP after the end.
640 intel_batchbuffer_require_space(brw
, 8);
641 *brw
->batch
.map_next
++ = MI_BATCH_BUFFER_END
;
642 if (USED_BATCH(brw
->batch
) & 1) {
643 *brw
->batch
.map_next
++ = MI_NOOP
;
646 brw
->batch
.no_wrap
= false;
650 throttle(struct brw_context
*brw
)
652 /* Wait for the swapbuffers before the one we just emitted, so we
653 * don't get too many swaps outstanding for apps that are GPU-heavy
656 * We're using intelDRI2Flush (called from the loader before
657 * swapbuffer) and glFlush (for front buffer rendering) as the
658 * indicator that a frame is done and then throttle when we get
659 * here as we prepare to render the next frame. At this point for
660 * round trips for swap/copy and getting new buffers are done and
661 * we'll spend less time waiting on the GPU.
663 * Unfortunately, we don't have a handle to the batch containing
664 * the swap, and getting our hands on that doesn't seem worth it,
665 * so we just use the first batch we emitted after the last swap.
667 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
668 if (brw
->throttle_batch
[1]) {
669 if (!brw
->disable_throttling
) {
670 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
672 brw_bo_unreference(brw
->throttle_batch
[1]);
674 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
675 brw
->throttle_batch
[0] = NULL
;
676 brw
->need_swap_throttle
= false;
677 /* Throttling here is more precise than the throttle ioctl, so skip it */
678 brw
->need_flush_throttle
= false;
681 if (brw
->need_flush_throttle
) {
682 drmCommandNone(brw
->screen
->fd
, DRM_I915_GEM_THROTTLE
);
683 brw
->need_flush_throttle
= false;
689 struct intel_batchbuffer
*batch
,
696 struct drm_i915_gem_execbuffer2 execbuf
= {
697 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
698 .buffer_count
= batch
->exec_count
,
699 .batch_start_offset
= 0,
702 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
705 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
707 if (in_fence
!= -1) {
708 execbuf
.rsvd2
= in_fence
;
709 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
712 if (out_fence
!= NULL
) {
713 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
715 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
718 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
722 for (int i
= 0; i
< batch
->exec_count
; i
++) {
723 struct brw_bo
*bo
= batch
->exec_bos
[i
];
728 /* Update brw_bo::gtt_offset */
729 if (batch
->validation_list
[i
].offset
!= bo
->gtt_offset
) {
730 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
731 bo
->gem_handle
, bo
->gtt_offset
,
732 batch
->validation_list
[i
].offset
);
733 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
734 bo
->gtt_offset
= batch
->validation_list
[i
].offset
;
738 if (ret
== 0 && out_fence
!= NULL
)
739 *out_fence
= execbuf
.rsvd2
>> 32;
745 submit_batch(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
747 struct intel_batchbuffer
*batch
= &brw
->batch
;
750 if (batch
->use_shadow_copy
) {
751 void *bo_map
= brw_bo_map(brw
, batch
->batch
.bo
, MAP_WRITE
);
752 memcpy(bo_map
, batch
->batch
.map
, 4 * USED_BATCH(*batch
));
754 bo_map
= brw_bo_map(brw
, batch
->state
.bo
, MAP_WRITE
);
755 memcpy(bo_map
, batch
->state
.map
, batch
->state_used
);
758 brw_bo_unmap(batch
->batch
.bo
);
759 brw_bo_unmap(batch
->state
.bo
);
761 if (!brw
->screen
->no_hw
) {
762 /* The requirement for using I915_EXEC_NO_RELOC are:
764 * The addresses written in the objects must match the corresponding
765 * reloc.gtt_offset which in turn must match the corresponding
768 * Any render targets written to in the batch must be flagged with
771 * To avoid stalling, execobject.offset should match the current
772 * address of that object within the active context.
774 int flags
= I915_EXEC_NO_RELOC
| I915_EXEC_RENDER
;
776 if (batch
->needs_sol_reset
)
777 flags
|= I915_EXEC_GEN7_SOL_RESET
;
779 /* Set statebuffer relocations */
780 const unsigned state_index
= batch
->state
.bo
->index
;
781 if (state_index
< batch
->exec_count
&&
782 batch
->exec_bos
[state_index
] == batch
->state
.bo
) {
783 struct drm_i915_gem_exec_object2
*entry
=
784 &batch
->validation_list
[state_index
];
785 assert(entry
->handle
== batch
->state
.bo
->gem_handle
);
786 entry
->relocation_count
= batch
->state_relocs
.reloc_count
;
787 entry
->relocs_ptr
= (uintptr_t) batch
->state_relocs
.relocs
;
790 /* Set batchbuffer relocations */
791 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
792 assert(entry
->handle
== batch
->batch
.bo
->gem_handle
);
793 entry
->relocation_count
= batch
->batch_relocs
.reloc_count
;
794 entry
->relocs_ptr
= (uintptr_t) batch
->batch_relocs
.relocs
;
796 if (batch
->use_batch_first
) {
797 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
799 /* Move the batch to the end of the validation list */
800 struct drm_i915_gem_exec_object2 tmp
;
801 struct brw_bo
*tmp_bo
;
802 const unsigned index
= batch
->exec_count
- 1;
805 *entry
= batch
->validation_list
[index
];
806 batch
->validation_list
[index
] = tmp
;
808 tmp_bo
= batch
->exec_bos
[0];
809 batch
->exec_bos
[0] = batch
->exec_bos
[index
];
810 batch
->exec_bos
[index
] = tmp_bo
;
813 ret
= execbuffer(brw
->screen
->fd
, batch
, brw
->hw_ctx
,
814 4 * USED_BATCH(*batch
),
815 in_fence_fd
, out_fence_fd
, flags
);
820 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
821 gen_print_batch(&batch
->decoder
, batch
->batch
.map
,
822 4 * USED_BATCH(*batch
),
823 batch
->batch
.bo
->gtt_offset
, false);
826 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
827 brw_check_for_reset(brw
);
830 fprintf(stderr
, "i965: Failed to submit batchbuffer: %s\n",
839 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
842 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
843 * of the returned fd.
846 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
847 int in_fence_fd
, int *out_fence_fd
,
848 const char *file
, int line
)
852 if (USED_BATCH(brw
->batch
) == 0)
855 /* Check that we didn't just wrap our batchbuffer at a bad time. */
856 assert(!brw
->batch
.no_wrap
);
858 brw_finish_batch(brw
);
859 brw_upload_finish(&brw
->upload
);
861 finish_growing_bos(&brw
->batch
.batch
);
862 finish_growing_bos(&brw
->batch
.state
);
864 if (brw
->throttle_batch
[0] == NULL
) {
865 brw
->throttle_batch
[0] = brw
->batch
.batch
.bo
;
866 brw_bo_reference(brw
->throttle_batch
[0]);
869 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
870 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
871 int bytes_for_state
= brw
->batch
.state_used
;
872 fprintf(stderr
, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
873 " %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
874 " %4d batch relocs, %4d state relocs\n", file
, line
,
875 bytes_for_commands
, 100.0f
* bytes_for_commands
/ BATCH_SZ
,
876 bytes_for_state
, 100.0f
* bytes_for_state
/ STATE_SZ
,
877 brw
->batch
.exec_count
,
878 (float) (brw
->batch
.aperture_space
/ (1024 * 1024)),
879 brw
->batch
.batch_relocs
.reloc_count
,
880 brw
->batch
.state_relocs
.reloc_count
);
882 dump_validation_list(&brw
->batch
);
885 ret
= submit_batch(brw
, in_fence_fd
, out_fence_fd
);
887 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
888 fprintf(stderr
, "waiting for idle\n");
889 brw_bo_wait_rendering(brw
->batch
.batch
.bo
);
892 /* Start a new batch buffer. */
899 intel_batchbuffer_maybe_noop(struct brw_context
*brw
)
901 if (!brw
->frontend_noop
|| USED_BATCH(brw
->batch
) != 0)
905 OUT_BATCH(MI_BATCH_BUFFER_END
);
910 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
912 unsigned index
= READ_ONCE(bo
->index
);
913 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
916 for (int i
= 0; i
< batch
->exec_count
; i
++) {
917 if (batch
->exec_bos
[i
] == bo
)
923 /* This is the only way buffers get added to the validate list.
926 emit_reloc(struct intel_batchbuffer
*batch
,
927 struct brw_reloc_list
*rlist
, uint32_t offset
,
928 struct brw_bo
*target
, int32_t target_offset
,
929 unsigned int reloc_flags
)
931 assert(target
!= NULL
);
933 if (target
->kflags
& EXEC_OBJECT_PINNED
) {
934 brw_use_pinned_bo(batch
, target
, reloc_flags
& RELOC_WRITE
);
935 return gen_canonical_address(target
->gtt_offset
+ target_offset
);
938 unsigned int index
= add_exec_bo(batch
, target
);
939 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
941 if (rlist
->reloc_count
== rlist
->reloc_array_size
) {
942 rlist
->reloc_array_size
*= 2;
943 rlist
->relocs
= realloc(rlist
->relocs
,
944 rlist
->reloc_array_size
*
945 sizeof(struct drm_i915_gem_relocation_entry
));
948 if (reloc_flags
& RELOC_32BIT
) {
949 /* Restrict this buffer to the low 32 bits of the address space.
951 * Altering the validation list flags restricts it for this batch,
952 * but we also alter the BO's kflags to restrict it permanently
953 * (until the BO is destroyed and put back in the cache). Buffers
954 * may stay bound across batches, and we want keep it constrained.
956 target
->kflags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
957 entry
->flags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
959 /* RELOC_32BIT is not an EXEC_OBJECT_* flag, so get rid of it. */
960 reloc_flags
&= ~RELOC_32BIT
;
964 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
966 rlist
->relocs
[rlist
->reloc_count
++] =
967 (struct drm_i915_gem_relocation_entry
) {
969 .delta
= target_offset
,
970 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
971 .presumed_offset
= entry
->offset
,
974 /* Using the old buffer offset, write in what the right data would be, in
975 * case the buffer doesn't move and we can short-circuit the relocation
976 * processing in the kernel
978 return entry
->offset
+ target_offset
;
982 brw_use_pinned_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
,
983 unsigned writable_flag
)
985 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
986 assert((writable_flag
& ~EXEC_OBJECT_WRITE
) == 0);
988 unsigned int index
= add_exec_bo(batch
, bo
);
989 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
990 assert(entry
->offset
== bo
->gtt_offset
);
993 entry
->flags
|= EXEC_OBJECT_WRITE
;
997 brw_batch_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
998 struct brw_bo
*target
, uint32_t target_offset
,
999 unsigned int reloc_flags
)
1001 assert(batch_offset
<= batch
->batch
.bo
->size
- sizeof(uint32_t));
1003 return emit_reloc(batch
, &batch
->batch_relocs
, batch_offset
,
1004 target
, target_offset
, reloc_flags
);
1008 brw_state_reloc(struct intel_batchbuffer
*batch
, uint32_t state_offset
,
1009 struct brw_bo
*target
, uint32_t target_offset
,
1010 unsigned int reloc_flags
)
1012 assert(state_offset
<= batch
->state
.bo
->size
- sizeof(uint32_t));
1014 return emit_reloc(batch
, &batch
->state_relocs
, state_offset
,
1015 target
, target_offset
, reloc_flags
);
1019 * Reserve some space in the statebuffer, or flush.
1021 * This is used to estimate when we're near the end of the batch,
1022 * so we can flush early.
1025 brw_require_statebuffer_space(struct brw_context
*brw
, int size
)
1027 if (brw
->batch
.state_used
+ size
>= STATE_SZ
)
1028 intel_batchbuffer_flush(brw
);
1032 * Allocates a block of space in the batchbuffer for indirect state.
1035 brw_state_batch(struct brw_context
*brw
,
1038 uint32_t *out_offset
)
1040 struct intel_batchbuffer
*batch
= &brw
->batch
;
1042 assert(size
< batch
->state
.bo
->size
);
1044 uint32_t offset
= ALIGN(batch
->state_used
, alignment
);
1046 if (offset
+ size
>= STATE_SZ
&& !batch
->no_wrap
) {
1047 intel_batchbuffer_flush(brw
);
1048 offset
= ALIGN(batch
->state_used
, alignment
);
1049 } else if (offset
+ size
>= batch
->state
.bo
->size
) {
1050 const unsigned new_size
=
1051 MIN2(batch
->state
.bo
->size
+ batch
->state
.bo
->size
/ 2,
1053 grow_buffer(brw
, &batch
->state
, batch
->state_used
, new_size
);
1054 assert(offset
+ size
< batch
->state
.bo
->size
);
1057 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
1058 _mesa_hash_table_u64_insert(batch
->state_batch_sizes
,
1059 offset
, (void *) (uintptr_t) size
);
1062 batch
->state_used
= offset
+ size
;
1064 *out_offset
= offset
;
1065 return batch
->state
.map
+ (offset
>> 2);
1069 intel_batchbuffer_data(struct brw_context
*brw
,
1070 const void *data
, GLuint bytes
)
1072 assert((bytes
& 3) == 0);
1073 intel_batchbuffer_require_space(brw
, bytes
);
1074 memcpy(brw
->batch
.map_next
, data
, bytes
);
1075 brw
->batch
.map_next
+= bytes
>> 2;
1079 load_sized_register_mem(struct brw_context
*brw
,
1085 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1088 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
1089 assert(devinfo
->gen
>= 7);
1091 if (devinfo
->gen
>= 8) {
1092 BEGIN_BATCH(4 * size
);
1093 for (i
= 0; i
< size
; i
++) {
1094 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
1095 OUT_BATCH(reg
+ i
* 4);
1096 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
1100 BEGIN_BATCH(3 * size
);
1101 for (i
= 0; i
< size
; i
++) {
1102 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
1103 OUT_BATCH(reg
+ i
* 4);
1104 OUT_RELOC(bo
, 0, offset
+ i
* 4);
1111 brw_load_register_mem(struct brw_context
*brw
,
1116 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
1120 brw_load_register_mem64(struct brw_context
*brw
,
1125 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
1129 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
1132 brw_store_register_mem32(struct brw_context
*brw
,
1133 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1135 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1137 assert(devinfo
->gen
>= 6);
1139 if (devinfo
->gen
>= 8) {
1141 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1143 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1147 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1149 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1155 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
1158 brw_store_register_mem64(struct brw_context
*brw
,
1159 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1161 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1163 assert(devinfo
->gen
>= 6);
1165 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
1166 * read a full 64-bit register, we need to do two of them.
1168 if (devinfo
->gen
>= 8) {
1170 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1172 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1173 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1174 OUT_BATCH(reg
+ sizeof(uint32_t));
1175 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
1179 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1181 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1182 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1183 OUT_BATCH(reg
+ sizeof(uint32_t));
1184 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
1190 * Write a 32-bit register using immediate data.
1193 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
1195 assert(brw
->screen
->devinfo
.gen
>= 6);
1198 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
1205 * Write a 64-bit register using immediate data.
1208 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
1210 assert(brw
->screen
->devinfo
.gen
>= 6);
1213 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
1215 OUT_BATCH(imm
& 0xffffffff);
1217 OUT_BATCH(imm
>> 32);
1222 * Copies a 32-bit register.
1225 brw_load_register_reg(struct brw_context
*brw
, uint32_t dest
, uint32_t src
)
1227 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1230 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1237 * Copies a 64-bit register.
1240 brw_load_register_reg64(struct brw_context
*brw
, uint32_t dest
, uint32_t src
)
1242 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1245 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1248 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1249 OUT_BATCH(src
+ sizeof(uint32_t));
1250 OUT_BATCH(dest
+ sizeof(uint32_t));
1255 * Write 32-bits of immediate data to a GPU memory buffer.
1258 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1259 uint32_t offset
, uint32_t imm
)
1261 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1263 assert(devinfo
->gen
>= 6);
1266 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1267 if (devinfo
->gen
>= 8)
1268 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1270 OUT_BATCH(0); /* MBZ */
1271 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1278 * Write 64-bits of immediate data to a GPU memory buffer.
1281 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1282 uint32_t offset
, uint64_t imm
)
1284 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1286 assert(devinfo
->gen
>= 6);
1289 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1290 if (devinfo
->gen
>= 8)
1291 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1293 OUT_BATCH(0); /* MBZ */
1294 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1296 OUT_BATCH(imm
& 0xffffffffu
);
1297 OUT_BATCH(imm
>> 32);