1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "intel_fbo.h"
34 #include "brw_context.h"
35 #include "brw_defines.h"
41 intel_batchbuffer_reset(struct brw_context
*brw
);
44 intel_batchbuffer_init(struct brw_context
*brw
)
46 intel_batchbuffer_reset(brw
);
49 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
50 brw
->batch
.map
= brw
->batch
.cpu_map
;
55 intel_batchbuffer_reset(struct brw_context
*brw
)
57 if (brw
->batch
.last_bo
!= NULL
) {
58 drm_intel_bo_unreference(brw
->batch
.last_bo
);
59 brw
->batch
.last_bo
= NULL
;
61 brw
->batch
.last_bo
= brw
->batch
.bo
;
63 brw_render_cache_set_clear(brw
);
65 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
68 drm_intel_bo_map(brw
->batch
.bo
, true);
69 brw
->batch
.map
= brw
->batch
.bo
->virtual;
72 brw
->batch
.reserved_space
= BATCH_RESERVED
;
73 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
75 brw
->batch
.needs_sol_reset
= false;
77 /* We don't know what ring the new batch will be sent to until we see the
78 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
80 brw
->batch
.ring
= UNKNOWN_RING
;
84 intel_batchbuffer_save_state(struct brw_context
*brw
)
86 brw
->batch
.saved
.used
= brw
->batch
.used
;
87 brw
->batch
.saved
.reloc_count
=
88 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
92 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
94 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
96 brw
->batch
.used
= brw
->batch
.saved
.used
;
97 if (brw
->batch
.used
== 0)
98 brw
->batch
.ring
= UNKNOWN_RING
;
102 intel_batchbuffer_free(struct brw_context
*brw
)
104 free(brw
->batch
.cpu_map
);
105 drm_intel_bo_unreference(brw
->batch
.last_bo
);
106 drm_intel_bo_unreference(brw
->batch
.bo
);
110 do_batch_dump(struct brw_context
*brw
)
112 struct drm_intel_decode
*decode
;
113 struct intel_batchbuffer
*batch
= &brw
->batch
;
116 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
120 ret
= drm_intel_bo_map(batch
->bo
, false);
122 drm_intel_decode_set_batch_pointer(decode
,
128 "WARNING: failed to map batchbuffer (%s), "
129 "dumping uploaded data instead.\n", strerror(ret
));
131 drm_intel_decode_set_batch_pointer(decode
,
137 drm_intel_decode_set_output_file(decode
, stderr
);
138 drm_intel_decode(decode
);
140 drm_intel_decode_context_free(decode
);
143 drm_intel_bo_unmap(batch
->bo
);
145 brw_debug_batch(brw
);
150 intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
)
152 /* We may need to enable and snapshot OA counters. */
153 brw_perf_monitor_new_batch(brw
);
157 * Called when starting a new batch buffer.
160 brw_new_batch(struct brw_context
*brw
)
162 /* Create a new batchbuffer and reset the associated state: */
163 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, 0);
164 intel_batchbuffer_reset(brw
);
166 /* If the kernel supports hardware contexts, then most hardware state is
167 * preserved between batches; we only need to re-emit state that is required
168 * to be in every batch. Otherwise we need to re-emit all the state that
169 * would otherwise be stored in the context (which for all intents and
170 * purposes means everything).
172 if (brw
->hw_ctx
== NULL
)
173 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
175 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
177 brw
->state_batch_count
= 0;
181 /* We need to periodically reap the shader time results, because rollover
182 * happens every few seconds. We also want to see results every once in a
183 * while, because many programs won't cleanly destroy our context, so the
184 * end-of-run printout may not happen.
186 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
187 brw_collect_and_report_shader_time(brw
);
189 if (INTEL_DEBUG
& DEBUG_PERFMON
)
190 brw_dump_perf_monitors(brw
);
194 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
197 * This function can emit state (say, to preserve registers that aren't saved
198 * between batches). All of this state MUST fit in the reserved space at the
199 * end of the batchbuffer. If you add more GPU state, increase the reserved
200 * space by updating the BATCH_RESERVED macro.
203 brw_finish_batch(struct brw_context
*brw
)
205 /* Capture the closing pipeline statistics register values necessary to
206 * support query objects (in the non-hardware context world).
208 brw_emit_query_end(brw
);
210 if (brw
->batch
.ring
== RENDER_RING
) {
211 /* We may also need to snapshot and disable OA counters. */
212 brw_perf_monitor_finish_batch(brw
);
214 if (brw
->is_haswell
) {
215 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
216 * 3DSTATE_CC_STATE_POINTERS > "Note":
218 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
219 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
221 * From the example in the docs, it seems to expect a regular pipe control
222 * flush here as well. We may have done it already, but meh.
224 * See also WaAvoidRCZCounterRollover.
226 brw_emit_mi_flush(brw
);
228 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
229 OUT_BATCH(brw
->cc
.state_offset
| 1);
231 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
232 PIPE_CONTROL_CS_STALL
);
236 /* Mark that the current program cache BO has been used by the GPU.
237 * It will be reallocated if we need to put new programs in for the
240 brw
->cache
.bo_used_by_gpu
= true;
244 throttle(struct brw_context
*brw
)
246 /* Wait for the swapbuffers before the one we just emitted, so we
247 * don't get too many swaps outstanding for apps that are GPU-heavy
250 * We're using intelDRI2Flush (called from the loader before
251 * swapbuffer) and glFlush (for front buffer rendering) as the
252 * indicator that a frame is done and then throttle when we get
253 * here as we prepare to render the next frame. At this point for
254 * round trips for swap/copy and getting new buffers are done and
255 * we'll spend less time waiting on the GPU.
257 * Unfortunately, we don't have a handle to the batch containing
258 * the swap, and getting our hands on that doesn't seem worth it,
259 * so we just use the first batch we emitted after the last swap.
261 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
262 if (brw
->throttle_batch
[1]) {
263 if (!brw
->disable_throttling
)
264 drm_intel_bo_wait_rendering(brw
->throttle_batch
[1]);
265 drm_intel_bo_unreference(brw
->throttle_batch
[1]);
267 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
268 brw
->throttle_batch
[0] = NULL
;
269 brw
->need_swap_throttle
= false;
270 /* Throttling here is more precise than the throttle ioctl, so skip it */
271 brw
->need_flush_throttle
= false;
274 if (brw
->need_flush_throttle
) {
275 __DRIscreen
*psp
= brw
->intelScreen
->driScrnPriv
;
276 drmCommandNone(psp
->fd
, DRM_I915_GEM_THROTTLE
);
277 brw
->need_flush_throttle
= false;
281 /* TODO: Push this whole function into bufmgr.
284 do_flush_locked(struct brw_context
*brw
)
286 struct intel_batchbuffer
*batch
= &brw
->batch
;
290 drm_intel_bo_unmap(batch
->bo
);
292 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
293 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
294 ret
= drm_intel_bo_subdata(batch
->bo
,
295 batch
->state_batch_offset
,
296 batch
->bo
->size
- batch
->state_batch_offset
,
297 (char *)batch
->map
+ batch
->state_batch_offset
);
301 if (!brw
->intelScreen
->no_hw
) {
304 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
305 flags
= I915_EXEC_BLT
;
307 flags
= I915_EXEC_RENDER
;
309 if (batch
->needs_sol_reset
)
310 flags
|= I915_EXEC_GEN7_SOL_RESET
;
313 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
314 brw_annotate_aub(brw
);
316 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
317 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
320 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
321 4 * batch
->used
, flags
);
328 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
332 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
340 _intel_batchbuffer_flush(struct brw_context
*brw
,
341 const char *file
, int line
)
345 if (brw
->batch
.used
== 0)
348 if (brw
->throttle_batch
[0] == NULL
) {
349 brw
->throttle_batch
[0] = brw
->batch
.bo
;
350 drm_intel_bo_reference(brw
->throttle_batch
[0]);
353 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
354 int bytes_for_commands
= 4 * brw
->batch
.used
;
355 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
356 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
357 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
358 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
359 bytes_for_commands
, bytes_for_state
,
361 100.0f
* total_bytes
/ BATCH_SZ
);
364 brw
->batch
.reserved_space
= 0;
366 brw_finish_batch(brw
);
368 /* Mark the end of the buffer. */
369 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
370 if (brw
->batch
.used
& 1) {
371 /* Round batchbuffer usage to 2 DWORDs. */
372 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
375 intel_upload_finish(brw
);
377 /* Check that we didn't just wrap our batchbuffer at a bad time. */
378 assert(!brw
->no_batch_wrap
);
380 ret
= do_flush_locked(brw
);
382 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
383 fprintf(stderr
, "waiting for idle\n");
384 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
387 /* Start a new batch buffer. */
394 /* This is the only way buffers get added to the validate list.
397 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
398 drm_intel_bo
*buffer
,
399 uint32_t read_domains
, uint32_t write_domain
,
404 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
406 read_domains
, write_domain
);
410 /* Using the old buffer offset, write in what the right data would be, in
411 * case the buffer doesn't move and we can short-circuit the relocation
412 * processing in the kernel
414 intel_batchbuffer_emit_dword(brw
, buffer
->offset64
+ delta
);
420 intel_batchbuffer_emit_reloc64(struct brw_context
*brw
,
421 drm_intel_bo
*buffer
,
422 uint32_t read_domains
, uint32_t write_domain
,
425 int ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
427 read_domains
, write_domain
);
431 /* Using the old buffer offset, write in what the right data would be, in
432 * case the buffer doesn't move and we can short-circuit the relocation
433 * processing in the kernel
435 uint64_t offset
= buffer
->offset64
+ delta
;
436 intel_batchbuffer_emit_dword(brw
, offset
);
437 intel_batchbuffer_emit_dword(brw
, offset
>> 32);
444 intel_batchbuffer_data(struct brw_context
*brw
,
445 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
447 assert((bytes
& 3) == 0);
448 intel_batchbuffer_require_space(brw
, bytes
, ring
);
449 memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
450 brw
->batch
.used
+= bytes
>> 2;
454 load_sized_register_mem(struct brw_context
*brw
,
457 uint32_t read_domains
, uint32_t write_domain
,
463 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
464 assert(brw
->gen
>= 7);
467 BEGIN_BATCH(4 * size
);
468 for (i
= 0; i
< size
; i
++) {
469 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
470 OUT_BATCH(reg
+ i
* 4);
471 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
+ i
* 4);
475 BEGIN_BATCH(3 * size
);
476 for (i
= 0; i
< size
; i
++) {
477 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
478 OUT_BATCH(reg
+ i
* 4);
479 OUT_RELOC(bo
, read_domains
, write_domain
, offset
+ i
* 4);
486 brw_load_register_mem(struct brw_context
*brw
,
489 uint32_t read_domains
, uint32_t write_domain
,
492 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 1);
496 brw_load_register_mem64(struct brw_context
*brw
,
499 uint32_t read_domains
, uint32_t write_domain
,
502 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 2);