2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
35 #include "common/gen_gem.h"
37 #include "util/hash_table.h"
40 #include "drm-uapi/i915_drm.h"
42 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
45 * Target sizes of the batch and state buffers. We create the initial
46 * buffers at these sizes, and flush when they're nearly full. If we
47 * underestimate how close we are to the end, and suddenly need more space
48 * in the middle of a draw, we can grow the buffers, and finish the draw.
49 * At that point, we'll be over our target size, so the next operation
50 * should flush. Each time we flush the batch, we recreate both buffers
51 * at the original target size, so it doesn't grow without bound.
53 #define BATCH_SZ (20 * 1024)
54 #define STATE_SZ (16 * 1024)
57 intel_batchbuffer_reset(struct brw_context
*brw
);
59 brw_new_batch(struct brw_context
*brw
);
62 dump_validation_list(struct intel_batchbuffer
*batch
)
64 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
66 for (int i
= 0; i
< batch
->exec_count
; i
++) {
67 uint64_t flags
= batch
->validation_list
[i
].flags
;
68 assert(batch
->validation_list
[i
].handle
==
69 batch
->exec_bos
[i
]->gem_handle
);
70 fprintf(stderr
, "[%2d]: %2d %-14s %p %s%-7s @ 0x%"PRIx64
"%s (%"PRIu64
"B)\n",
72 batch
->validation_list
[i
].handle
,
73 batch
->exec_bos
[i
]->name
,
75 (flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) ? "(48b" : "(32b",
76 (flags
& EXEC_OBJECT_WRITE
) ? " write)" : ")",
77 (uint64_t)batch
->validation_list
[i
].offset
,
78 (flags
& EXEC_OBJECT_PINNED
) ? " (pinned)" : "",
79 batch
->exec_bos
[i
]->size
);
83 static struct gen_batch_decode_bo
84 decode_get_bo(void *v_brw
, bool ppgtt
, uint64_t address
)
86 struct brw_context
*brw
= v_brw
;
87 struct intel_batchbuffer
*batch
= &brw
->batch
;
89 for (int i
= 0; i
< batch
->exec_count
; i
++) {
90 struct brw_bo
*bo
= batch
->exec_bos
[i
];
91 /* The decoder zeroes out the top 16 bits, so we need to as well */
92 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
94 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
95 return (struct gen_batch_decode_bo
) {
98 .map
= brw_bo_map(brw
, bo
, MAP_READ
) + (address
- bo_address
),
103 return (struct gen_batch_decode_bo
) { };
107 decode_get_state_size(void *v_brw
, uint64_t address
, uint64_t base_address
)
109 struct brw_context
*brw
= v_brw
;
110 struct intel_batchbuffer
*batch
= &brw
->batch
;
111 unsigned size
= (uintptr_t)
112 _mesa_hash_table_u64_search(batch
->state_batch_sizes
,
113 address
- base_address
);
118 init_reloc_list(struct brw_reloc_list
*rlist
, int count
)
120 rlist
->reloc_count
= 0;
121 rlist
->reloc_array_size
= count
;
122 rlist
->relocs
= malloc(rlist
->reloc_array_size
*
123 sizeof(struct drm_i915_gem_relocation_entry
));
127 intel_batchbuffer_init(struct brw_context
*brw
)
129 struct intel_screen
*screen
= brw
->screen
;
130 struct intel_batchbuffer
*batch
= &brw
->batch
;
131 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
133 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
134 /* The shadow doesn't get relocs written so state decode fails. */
135 batch
->use_shadow_copy
= false;
137 batch
->use_shadow_copy
= !devinfo
->has_llc
;
139 init_reloc_list(&batch
->batch_relocs
, 250);
140 init_reloc_list(&batch
->state_relocs
, 250);
142 batch
->batch
.map
= NULL
;
143 batch
->state
.map
= NULL
;
144 batch
->exec_count
= 0;
145 batch
->exec_array_size
= 100;
147 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
148 batch
->validation_list
=
149 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
151 if (INTEL_DEBUG
& DEBUG_BATCH
) {
152 batch
->state_batch_sizes
=
153 _mesa_hash_table_u64_create(NULL
);
155 const unsigned decode_flags
=
156 GEN_BATCH_DECODE_FULL
|
157 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
158 GEN_BATCH_DECODE_OFFSETS
|
159 GEN_BATCH_DECODE_FLOATS
;
161 gen_batch_decode_ctx_init(&batch
->decoder
, devinfo
, stderr
,
162 decode_flags
, NULL
, decode_get_bo
,
163 decode_get_state_size
, brw
);
164 batch
->decoder
.max_vbo_decoded_lines
= 100;
167 batch
->use_batch_first
=
168 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
170 /* PIPE_CONTROL needs a w/a but only on gen6 */
171 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
172 if (devinfo
->gen
== 6)
173 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
175 intel_batchbuffer_reset(brw
);
178 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
181 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
183 assert(bo
->bufmgr
== batch
->batch
.bo
->bufmgr
);
185 unsigned index
= READ_ONCE(bo
->index
);
187 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
190 /* May have been shared between multiple active batches */
191 for (index
= 0; index
< batch
->exec_count
; index
++) {
192 if (batch
->exec_bos
[index
] == bo
)
196 brw_bo_reference(bo
);
198 if (batch
->exec_count
== batch
->exec_array_size
) {
199 batch
->exec_array_size
*= 2;
201 realloc(batch
->exec_bos
,
202 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
203 batch
->validation_list
=
204 realloc(batch
->validation_list
,
205 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
208 batch
->validation_list
[batch
->exec_count
] =
209 (struct drm_i915_gem_exec_object2
) {
210 .handle
= bo
->gem_handle
,
211 .offset
= bo
->gtt_offset
,
215 bo
->index
= batch
->exec_count
;
216 batch
->exec_bos
[batch
->exec_count
] = bo
;
217 batch
->aperture_space
+= bo
->size
;
219 return batch
->exec_count
++;
223 recreate_growing_buffer(struct brw_context
*brw
,
224 struct brw_growing_bo
*grow
,
225 const char *name
, unsigned size
,
226 enum brw_memory_zone memzone
)
228 struct intel_screen
*screen
= brw
->screen
;
229 struct intel_batchbuffer
*batch
= &brw
->batch
;
230 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
232 /* We can't grow buffers when using softpin, so just overallocate them. */
233 if (brw_using_softpin(bufmgr
))
236 grow
->bo
= brw_bo_alloc(bufmgr
, name
, size
, memzone
);
237 grow
->bo
->kflags
|= can_do_exec_capture(screen
) ? EXEC_OBJECT_CAPTURE
: 0;
238 grow
->partial_bo
= NULL
;
239 grow
->partial_bo_map
= NULL
;
240 grow
->partial_bytes
= 0;
241 grow
->memzone
= memzone
;
243 if (batch
->use_shadow_copy
)
244 grow
->map
= realloc(grow
->map
, grow
->bo
->size
);
246 grow
->map
= brw_bo_map(brw
, grow
->bo
, MAP_READ
| MAP_WRITE
);
250 intel_batchbuffer_reset(struct brw_context
*brw
)
252 struct intel_batchbuffer
*batch
= &brw
->batch
;
254 if (batch
->last_bo
!= NULL
) {
255 brw_bo_unreference(batch
->last_bo
);
256 batch
->last_bo
= NULL
;
258 batch
->last_bo
= batch
->batch
.bo
;
260 recreate_growing_buffer(brw
, &batch
->batch
, "batchbuffer", BATCH_SZ
,
262 batch
->map_next
= batch
->batch
.map
;
264 recreate_growing_buffer(brw
, &batch
->state
, "statebuffer", STATE_SZ
,
265 BRW_MEMZONE_DYNAMIC
);
267 /* Avoid making 0 a valid state offset - otherwise the decoder will try
268 * and decode data when we use offset 0 as a null pointer.
270 batch
->state_used
= 1;
272 add_exec_bo(batch
, batch
->batch
.bo
);
273 assert(batch
->batch
.bo
->index
== 0);
275 batch
->needs_sol_reset
= false;
276 batch
->state_base_address_emitted
= false;
278 if (batch
->state_batch_sizes
)
279 _mesa_hash_table_u64_clear(batch
->state_batch_sizes
, NULL
);
281 /* Always add workaround_bo which contains a driver identifier to be
282 * recorded in error states.
284 struct brw_bo
*identifier_bo
= brw
->workaround_bo
;
286 add_exec_bo(batch
, identifier_bo
);
290 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
292 intel_batchbuffer_reset(brw
);
293 brw_cache_sets_clear(brw
);
297 intel_batchbuffer_save_state(struct brw_context
*brw
)
299 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
300 brw
->batch
.saved
.batch_reloc_count
= brw
->batch
.batch_relocs
.reloc_count
;
301 brw
->batch
.saved
.state_reloc_count
= brw
->batch
.state_relocs
.reloc_count
;
302 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
306 intel_batchbuffer_saved_state_is_empty(struct brw_context
*brw
)
308 struct intel_batchbuffer
*batch
= &brw
->batch
;
309 return (batch
->saved
.map_next
== batch
->batch
.map
);
313 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
315 for (int i
= brw
->batch
.saved
.exec_count
;
316 i
< brw
->batch
.exec_count
; i
++) {
317 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
319 brw
->batch
.batch_relocs
.reloc_count
= brw
->batch
.saved
.batch_reloc_count
;
320 brw
->batch
.state_relocs
.reloc_count
= brw
->batch
.saved
.state_reloc_count
;
321 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
323 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
324 if (USED_BATCH(brw
->batch
) == 0)
329 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
331 if (batch
->use_shadow_copy
) {
332 free(batch
->batch
.map
);
333 free(batch
->state
.map
);
336 for (int i
= 0; i
< batch
->exec_count
; i
++) {
337 brw_bo_unreference(batch
->exec_bos
[i
]);
339 free(batch
->batch_relocs
.relocs
);
340 free(batch
->state_relocs
.relocs
);
341 free(batch
->exec_bos
);
342 free(batch
->validation_list
);
344 brw_bo_unreference(batch
->last_bo
);
345 brw_bo_unreference(batch
->batch
.bo
);
346 brw_bo_unreference(batch
->state
.bo
);
347 if (batch
->state_batch_sizes
) {
348 _mesa_hash_table_u64_destroy(batch
->state_batch_sizes
, NULL
);
349 gen_batch_decode_ctx_finish(&batch
->decoder
);
354 * Finish copying the old batch/state buffer's contents to the new one
355 * after we tried to "grow" the buffer in an earlier operation.
358 finish_growing_bos(struct brw_growing_bo
*grow
)
360 struct brw_bo
*old_bo
= grow
->partial_bo
;
364 memcpy(grow
->map
, grow
->partial_bo_map
, grow
->partial_bytes
);
366 grow
->partial_bo
= NULL
;
367 grow
->partial_bo_map
= NULL
;
368 grow
->partial_bytes
= 0;
370 brw_bo_unreference(old_bo
);
374 replace_bo_in_reloc_list(struct brw_reloc_list
*rlist
,
375 uint32_t old_handle
, uint32_t new_handle
)
377 for (int i
= 0; i
< rlist
->reloc_count
; i
++) {
378 if (rlist
->relocs
[i
].target_handle
== old_handle
)
379 rlist
->relocs
[i
].target_handle
= new_handle
;
384 * Grow either the batch or state buffer to a new larger size.
386 * We can't actually grow buffers, so we allocate a new one, copy over
387 * the existing contents, and update our lists to refer to the new one.
389 * Note that this is only temporary - each new batch recreates the buffers
390 * at their original target size (BATCH_SZ or STATE_SZ).
393 grow_buffer(struct brw_context
*brw
,
394 struct brw_growing_bo
*grow
,
395 unsigned existing_bytes
,
398 struct intel_batchbuffer
*batch
= &brw
->batch
;
399 struct brw_bufmgr
*bufmgr
= brw
->bufmgr
;
400 struct brw_bo
*bo
= grow
->bo
;
402 /* We can't grow buffers that are softpinned, as the growing mechanism
403 * involves putting a larger buffer at the same gtt_offset...and we've
404 * only allocated the smaller amount of VMA. Without relocations, this
405 * simply won't work. This should never happen, however.
407 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
409 perf_debug("Growing %s - ran out of space\n", bo
->name
);
411 if (grow
->partial_bo
) {
412 /* We've already grown once, and now we need to do it again.
413 * Finish our last grow operation so we can start a new one.
414 * This should basically never happen.
416 perf_debug("Had to grow multiple times");
417 finish_growing_bos(grow
);
420 struct brw_bo
*new_bo
=
421 brw_bo_alloc(bufmgr
, bo
->name
, new_size
, grow
->memzone
);
423 /* Copy existing data to the new larger buffer */
424 grow
->partial_bo_map
= grow
->map
;
426 if (batch
->use_shadow_copy
) {
427 /* We can't safely use realloc, as it may move the existing buffer,
428 * breaking existing pointers the caller may still be using. Just
429 * malloc a new copy and memcpy it like the normal BO path.
431 * Use bo->size rather than new_size because the bufmgr may have
432 * rounded up the size, and we want the shadow size to match.
434 grow
->map
= malloc(new_bo
->size
);
436 grow
->map
= brw_bo_map(brw
, new_bo
, MAP_READ
| MAP_WRITE
);
439 /* Try to put the new BO at the same GTT offset as the old BO (which
440 * we're throwing away, so it doesn't need to be there).
442 * This guarantees that our relocations continue to work: values we've
443 * already written into the buffer, values we're going to write into the
444 * buffer, and the validation/relocation lists all will match.
446 * Also preserve kflags for EXEC_OBJECT_CAPTURE.
448 new_bo
->gtt_offset
= bo
->gtt_offset
;
449 new_bo
->index
= bo
->index
;
450 new_bo
->kflags
= bo
->kflags
;
452 /* Batch/state buffers are per-context, and if we've run out of space,
453 * we must have actually used them before, so...they will be in the list.
455 assert(bo
->index
< batch
->exec_count
);
456 assert(batch
->exec_bos
[bo
->index
] == bo
);
458 /* Update the validation list to use the new BO. */
459 batch
->validation_list
[bo
->index
].handle
= new_bo
->gem_handle
;
461 if (!batch
->use_batch_first
) {
462 /* We're not using I915_EXEC_HANDLE_LUT, which means we need to go
463 * update the relocation list entries to point at the new BO as well.
464 * (With newer kernels, the "handle" is an offset into the validation
465 * list, which remains unchanged, so we can skip this.)
467 replace_bo_in_reloc_list(&batch
->batch_relocs
,
468 bo
->gem_handle
, new_bo
->gem_handle
);
469 replace_bo_in_reloc_list(&batch
->state_relocs
,
470 bo
->gem_handle
, new_bo
->gem_handle
);
473 /* Exchange the two BOs...without breaking pointers to the old BO.
475 * Consider this scenario:
477 * 1. Somebody calls brw_state_batch() to get a region of memory, and
478 * and then creates a brw_address pointing to brw->batch.state.bo.
479 * 2. They then call brw_state_batch() a second time, which happens to
480 * grow and replace the state buffer. They then try to emit a
481 * relocation to their first section of memory.
483 * If we replace the brw->batch.state.bo pointer at step 2, we would
484 * break the address created in step 1. They'd have a pointer to the
485 * old destroyed BO. Emitting a relocation would add this dead BO to
486 * the validation list...causing /both/ statebuffers to be in the list,
487 * and all kinds of disasters.
489 * This is not a contrived case - BLORP vertex data upload hits this.
491 * There are worse scenarios too. Fences for GL sync objects reference
492 * brw->batch.batch.bo. If we replaced the batch pointer when growing,
493 * we'd need to chase down every fence and update it to point to the
494 * new BO. Otherwise, it would refer to a "batch" that never actually
495 * gets submitted, and would fail to trigger.
497 * To work around both of these issues, we transmutate the buffers in
498 * place, making the existing struct brw_bo represent the new buffer,
499 * and "new_bo" represent the old BO. This is highly unusual, but it
500 * seems like a necessary evil.
502 * We also defer the memcpy of the existing batch's contents. Callers
503 * may make multiple brw_state_batch calls, and retain pointers to the
504 * old BO's map. We'll perform the memcpy in finish_growing_bo() when
505 * we finally submit the batch, at which point we've finished uploading
506 * state, and nobody should have any old references anymore.
508 * To do that, we keep a reference to the old BO in grow->partial_bo,
509 * and store the number of bytes to copy in grow->partial_bytes. We
510 * can monkey with the refcounts directly without atomics because these
511 * are per-context BOs and they can only be touched by this thread.
513 assert(new_bo
->refcount
== 1);
514 new_bo
->refcount
= bo
->refcount
;
517 assert(list_is_empty(&bo
->exports
));
518 assert(list_is_empty(&new_bo
->exports
));
521 memcpy(&tmp
, bo
, sizeof(struct brw_bo
));
522 memcpy(bo
, new_bo
, sizeof(struct brw_bo
));
523 memcpy(new_bo
, &tmp
, sizeof(struct brw_bo
));
525 list_inithead(&bo
->exports
);
526 list_inithead(&new_bo
->exports
);
528 grow
->partial_bo
= new_bo
; /* the one reference of the OLD bo */
529 grow
->partial_bytes
= existing_bytes
;
533 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
)
535 struct intel_batchbuffer
*batch
= &brw
->batch
;
537 const unsigned batch_used
= USED_BATCH(*batch
) * 4;
538 if (batch_used
+ sz
>= BATCH_SZ
&& !batch
->no_wrap
) {
539 intel_batchbuffer_flush(brw
);
540 } else if (batch_used
+ sz
>= batch
->batch
.bo
->size
) {
541 const unsigned new_size
=
542 MIN2(batch
->batch
.bo
->size
+ batch
->batch
.bo
->size
/ 2,
544 grow_buffer(brw
, &batch
->batch
, batch_used
, new_size
);
545 batch
->map_next
= (void *) batch
->batch
.map
+ batch_used
;
546 assert(batch_used
+ sz
< batch
->batch
.bo
->size
);
551 * Called when starting a new batch buffer.
554 brw_new_batch(struct brw_context
*brw
)
556 /* Unreference any BOs held by the previous batch, and reset counts. */
557 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
558 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
559 brw
->batch
.exec_bos
[i
] = NULL
;
561 brw
->batch
.batch_relocs
.reloc_count
= 0;
562 brw
->batch
.state_relocs
.reloc_count
= 0;
563 brw
->batch
.exec_count
= 0;
564 brw
->batch
.aperture_space
= 0;
566 brw_bo_unreference(brw
->batch
.state
.bo
);
568 /* Create a new batchbuffer and reset the associated state: */
569 intel_batchbuffer_reset_and_clear_render_cache(brw
);
571 /* If the kernel supports hardware contexts, then most hardware state is
572 * preserved between batches; we only need to re-emit state that is required
573 * to be in every batch. Otherwise we need to re-emit all the state that
574 * would otherwise be stored in the context (which for all intents and
575 * purposes means everything).
577 if (brw
->hw_ctx
== 0) {
578 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
579 brw_upload_invariant_state(brw
);
582 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
584 brw
->ib
.index_size
= -1;
586 /* We need to periodically reap the shader time results, because rollover
587 * happens every few seconds. We also want to see results every once in a
588 * while, because many programs won't cleanly destroy our context, so the
589 * end-of-run printout may not happen.
591 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
592 brw_collect_and_report_shader_time(brw
);
594 intel_batchbuffer_maybe_noop(brw
);
598 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
601 * This function can emit state (say, to preserve registers that aren't saved
605 brw_finish_batch(struct brw_context
*brw
)
607 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
609 brw
->batch
.no_wrap
= true;
611 /* Capture the closing pipeline statistics register values necessary to
612 * support query objects (in the non-hardware context world).
614 brw_emit_query_end(brw
);
616 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
617 * assume that the L3 cache is configured according to the hardware
618 * defaults. On Kernel 4.16+, we no longer need to do this.
620 if (devinfo
->gen
>= 7 &&
621 !(brw
->screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
))
622 gen7_restore_default_l3_config(brw
);
624 if (devinfo
->is_haswell
) {
625 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
626 * 3DSTATE_CC_STATE_POINTERS > "Note":
628 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
629 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
631 * From the example in the docs, it seems to expect a regular pipe control
632 * flush here as well. We may have done it already, but meh.
634 * See also WaAvoidRCZCounterRollover.
636 brw_emit_mi_flush(brw
);
638 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
639 OUT_BATCH(brw
->cc
.state_offset
| 1);
641 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
642 PIPE_CONTROL_CS_STALL
);
645 /* Do not restore push constant packets during context restore. */
646 if (devinfo
->gen
>= 7)
647 gen10_emit_isp_disable(brw
);
649 /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
650 * requires our batch size to be QWord aligned, so we pad it out if
651 * necessary by emitting an extra MI_NOOP after the end.
653 intel_batchbuffer_require_space(brw
, 8);
654 *brw
->batch
.map_next
++ = MI_BATCH_BUFFER_END
;
655 if (USED_BATCH(brw
->batch
) & 1) {
656 *brw
->batch
.map_next
++ = MI_NOOP
;
659 brw
->batch
.no_wrap
= false;
663 throttle(struct brw_context
*brw
)
665 /* Wait for the swapbuffers before the one we just emitted, so we
666 * don't get too many swaps outstanding for apps that are GPU-heavy
669 * We're using intelDRI2Flush (called from the loader before
670 * swapbuffer) and glFlush (for front buffer rendering) as the
671 * indicator that a frame is done and then throttle when we get
672 * here as we prepare to render the next frame. At this point for
673 * round trips for swap/copy and getting new buffers are done and
674 * we'll spend less time waiting on the GPU.
676 * Unfortunately, we don't have a handle to the batch containing
677 * the swap, and getting our hands on that doesn't seem worth it,
678 * so we just use the first batch we emitted after the last swap.
680 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
681 if (brw
->throttle_batch
[1]) {
682 if (!brw
->disable_throttling
) {
683 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
685 brw_bo_unreference(brw
->throttle_batch
[1]);
687 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
688 brw
->throttle_batch
[0] = NULL
;
689 brw
->need_swap_throttle
= false;
690 /* Throttling here is more precise than the throttle ioctl, so skip it */
691 brw
->need_flush_throttle
= false;
694 if (brw
->need_flush_throttle
) {
695 drmCommandNone(brw
->screen
->fd
, DRM_I915_GEM_THROTTLE
);
696 brw
->need_flush_throttle
= false;
702 struct intel_batchbuffer
*batch
,
709 struct drm_i915_gem_execbuffer2 execbuf
= {
710 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
711 .buffer_count
= batch
->exec_count
,
712 .batch_start_offset
= 0,
715 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
718 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
720 if (in_fence
!= -1) {
721 execbuf
.rsvd2
= in_fence
;
722 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
725 if (out_fence
!= NULL
) {
726 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
728 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
731 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
735 for (int i
= 0; i
< batch
->exec_count
; i
++) {
736 struct brw_bo
*bo
= batch
->exec_bos
[i
];
741 /* Update brw_bo::gtt_offset */
742 if (batch
->validation_list
[i
].offset
!= bo
->gtt_offset
) {
743 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
744 bo
->gem_handle
, bo
->gtt_offset
,
745 (uint64_t)batch
->validation_list
[i
].offset
);
746 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
747 bo
->gtt_offset
= batch
->validation_list
[i
].offset
;
751 if (ret
== 0 && out_fence
!= NULL
)
752 *out_fence
= execbuf
.rsvd2
>> 32;
758 submit_batch(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
760 struct intel_batchbuffer
*batch
= &brw
->batch
;
763 if (batch
->use_shadow_copy
) {
764 void *bo_map
= brw_bo_map(brw
, batch
->batch
.bo
, MAP_WRITE
);
765 memcpy(bo_map
, batch
->batch
.map
, 4 * USED_BATCH(*batch
));
767 bo_map
= brw_bo_map(brw
, batch
->state
.bo
, MAP_WRITE
);
768 memcpy(bo_map
, batch
->state
.map
, batch
->state_used
);
771 brw_bo_unmap(batch
->batch
.bo
);
772 brw_bo_unmap(batch
->state
.bo
);
774 if (!brw
->screen
->no_hw
) {
775 /* The requirement for using I915_EXEC_NO_RELOC are:
777 * The addresses written in the objects must match the corresponding
778 * reloc.gtt_offset which in turn must match the corresponding
781 * Any render targets written to in the batch must be flagged with
784 * To avoid stalling, execobject.offset should match the current
785 * address of that object within the active context.
787 int flags
= I915_EXEC_NO_RELOC
| I915_EXEC_RENDER
;
789 if (batch
->needs_sol_reset
)
790 flags
|= I915_EXEC_GEN7_SOL_RESET
;
792 /* Set statebuffer relocations */
793 const unsigned state_index
= batch
->state
.bo
->index
;
794 if (state_index
< batch
->exec_count
&&
795 batch
->exec_bos
[state_index
] == batch
->state
.bo
) {
796 struct drm_i915_gem_exec_object2
*entry
=
797 &batch
->validation_list
[state_index
];
798 assert(entry
->handle
== batch
->state
.bo
->gem_handle
);
799 entry
->relocation_count
= batch
->state_relocs
.reloc_count
;
800 entry
->relocs_ptr
= (uintptr_t) batch
->state_relocs
.relocs
;
803 /* Set batchbuffer relocations */
804 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
805 assert(entry
->handle
== batch
->batch
.bo
->gem_handle
);
806 entry
->relocation_count
= batch
->batch_relocs
.reloc_count
;
807 entry
->relocs_ptr
= (uintptr_t) batch
->batch_relocs
.relocs
;
809 if (batch
->use_batch_first
) {
810 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
812 /* Move the batch to the end of the validation list */
813 struct drm_i915_gem_exec_object2 tmp
;
814 struct brw_bo
*tmp_bo
;
815 const unsigned index
= batch
->exec_count
- 1;
818 *entry
= batch
->validation_list
[index
];
819 batch
->validation_list
[index
] = tmp
;
821 tmp_bo
= batch
->exec_bos
[0];
822 batch
->exec_bos
[0] = batch
->exec_bos
[index
];
823 batch
->exec_bos
[index
] = tmp_bo
;
826 ret
= execbuffer(brw
->screen
->fd
, batch
, brw
->hw_ctx
,
827 4 * USED_BATCH(*batch
),
828 in_fence_fd
, out_fence_fd
, flags
);
833 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
834 gen_print_batch(&batch
->decoder
, batch
->batch
.map
,
835 4 * USED_BATCH(*batch
),
836 batch
->batch
.bo
->gtt_offset
, false);
839 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
840 brw_check_for_reset(brw
);
843 fprintf(stderr
, "i965: Failed to submit batchbuffer: %s\n",
852 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
855 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
856 * of the returned fd.
859 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
860 int in_fence_fd
, int *out_fence_fd
,
861 const char *file
, int line
)
865 if (USED_BATCH(brw
->batch
) == 0)
868 /* Check that we didn't just wrap our batchbuffer at a bad time. */
869 assert(!brw
->batch
.no_wrap
);
871 brw_finish_batch(brw
);
872 brw_upload_finish(&brw
->upload
);
874 finish_growing_bos(&brw
->batch
.batch
);
875 finish_growing_bos(&brw
->batch
.state
);
877 if (brw
->throttle_batch
[0] == NULL
) {
878 brw
->throttle_batch
[0] = brw
->batch
.batch
.bo
;
879 brw_bo_reference(brw
->throttle_batch
[0]);
882 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
883 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
884 int bytes_for_state
= brw
->batch
.state_used
;
885 fprintf(stderr
, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
886 " %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
887 " %4d batch relocs, %4d state relocs\n", file
, line
,
888 bytes_for_commands
, 100.0f
* bytes_for_commands
/ BATCH_SZ
,
889 bytes_for_state
, 100.0f
* bytes_for_state
/ STATE_SZ
,
890 brw
->batch
.exec_count
,
891 (float) (brw
->batch
.aperture_space
/ (1024 * 1024)),
892 brw
->batch
.batch_relocs
.reloc_count
,
893 brw
->batch
.state_relocs
.reloc_count
);
895 dump_validation_list(&brw
->batch
);
898 ret
= submit_batch(brw
, in_fence_fd
, out_fence_fd
);
900 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
901 fprintf(stderr
, "waiting for idle\n");
902 brw_bo_wait_rendering(brw
->batch
.batch
.bo
);
905 /* Start a new batch buffer. */
912 intel_batchbuffer_maybe_noop(struct brw_context
*brw
)
914 if (!brw
->frontend_noop
|| USED_BATCH(brw
->batch
) != 0)
918 OUT_BATCH(MI_BATCH_BUFFER_END
);
923 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
925 unsigned index
= READ_ONCE(bo
->index
);
926 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
929 for (int i
= 0; i
< batch
->exec_count
; i
++) {
930 if (batch
->exec_bos
[i
] == bo
)
936 /* This is the only way buffers get added to the validate list.
939 emit_reloc(struct intel_batchbuffer
*batch
,
940 struct brw_reloc_list
*rlist
, uint32_t offset
,
941 struct brw_bo
*target
, int32_t target_offset
,
942 unsigned int reloc_flags
)
944 assert(target
!= NULL
);
946 if (target
->kflags
& EXEC_OBJECT_PINNED
) {
947 brw_use_pinned_bo(batch
, target
, reloc_flags
& RELOC_WRITE
);
948 return gen_canonical_address(target
->gtt_offset
+ target_offset
);
951 unsigned int index
= add_exec_bo(batch
, target
);
952 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
954 if (rlist
->reloc_count
== rlist
->reloc_array_size
) {
955 rlist
->reloc_array_size
*= 2;
956 rlist
->relocs
= realloc(rlist
->relocs
,
957 rlist
->reloc_array_size
*
958 sizeof(struct drm_i915_gem_relocation_entry
));
961 if (reloc_flags
& RELOC_32BIT
) {
962 /* Restrict this buffer to the low 32 bits of the address space.
964 * Altering the validation list flags restricts it for this batch,
965 * but we also alter the BO's kflags to restrict it permanently
966 * (until the BO is destroyed and put back in the cache). Buffers
967 * may stay bound across batches, and we want keep it constrained.
969 target
->kflags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
970 entry
->flags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
972 /* RELOC_32BIT is not an EXEC_OBJECT_* flag, so get rid of it. */
973 reloc_flags
&= ~RELOC_32BIT
;
977 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
979 rlist
->relocs
[rlist
->reloc_count
++] =
980 (struct drm_i915_gem_relocation_entry
) {
982 .delta
= target_offset
,
983 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
984 .presumed_offset
= entry
->offset
,
987 /* Using the old buffer offset, write in what the right data would be, in
988 * case the buffer doesn't move and we can short-circuit the relocation
989 * processing in the kernel
991 return entry
->offset
+ target_offset
;
995 brw_use_pinned_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
,
996 unsigned writable_flag
)
998 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
999 assert((writable_flag
& ~EXEC_OBJECT_WRITE
) == 0);
1001 unsigned int index
= add_exec_bo(batch
, bo
);
1002 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
1003 assert(entry
->offset
== bo
->gtt_offset
);
1006 entry
->flags
|= EXEC_OBJECT_WRITE
;
1010 brw_batch_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
1011 struct brw_bo
*target
, uint32_t target_offset
,
1012 unsigned int reloc_flags
)
1014 assert(batch_offset
<= batch
->batch
.bo
->size
- sizeof(uint32_t));
1016 return emit_reloc(batch
, &batch
->batch_relocs
, batch_offset
,
1017 target
, target_offset
, reloc_flags
);
1021 brw_state_reloc(struct intel_batchbuffer
*batch
, uint32_t state_offset
,
1022 struct brw_bo
*target
, uint32_t target_offset
,
1023 unsigned int reloc_flags
)
1025 assert(state_offset
<= batch
->state
.bo
->size
- sizeof(uint32_t));
1027 return emit_reloc(batch
, &batch
->state_relocs
, state_offset
,
1028 target
, target_offset
, reloc_flags
);
1032 * Reserve some space in the statebuffer, or flush.
1034 * This is used to estimate when we're near the end of the batch,
1035 * so we can flush early.
1038 brw_require_statebuffer_space(struct brw_context
*brw
, int size
)
1040 if (brw
->batch
.state_used
+ size
>= STATE_SZ
)
1041 intel_batchbuffer_flush(brw
);
1045 * Allocates a block of space in the batchbuffer for indirect state.
1048 brw_state_batch(struct brw_context
*brw
,
1051 uint32_t *out_offset
)
1053 struct intel_batchbuffer
*batch
= &brw
->batch
;
1055 assert(size
< batch
->state
.bo
->size
);
1057 uint32_t offset
= ALIGN(batch
->state_used
, alignment
);
1059 if (offset
+ size
>= STATE_SZ
&& !batch
->no_wrap
) {
1060 intel_batchbuffer_flush(brw
);
1061 offset
= ALIGN(batch
->state_used
, alignment
);
1062 } else if (offset
+ size
>= batch
->state
.bo
->size
) {
1063 const unsigned new_size
=
1064 MIN2(batch
->state
.bo
->size
+ batch
->state
.bo
->size
/ 2,
1066 grow_buffer(brw
, &batch
->state
, batch
->state_used
, new_size
);
1067 assert(offset
+ size
< batch
->state
.bo
->size
);
1070 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
1071 _mesa_hash_table_u64_insert(batch
->state_batch_sizes
,
1072 offset
, (void *) (uintptr_t) size
);
1075 batch
->state_used
= offset
+ size
;
1077 *out_offset
= offset
;
1078 return batch
->state
.map
+ (offset
>> 2);
1082 intel_batchbuffer_data(struct brw_context
*brw
,
1083 const void *data
, GLuint bytes
)
1085 assert((bytes
& 3) == 0);
1086 intel_batchbuffer_require_space(brw
, bytes
);
1087 memcpy(brw
->batch
.map_next
, data
, bytes
);
1088 brw
->batch
.map_next
+= bytes
>> 2;
1092 load_sized_register_mem(struct brw_context
*brw
,
1098 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1101 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
1102 assert(devinfo
->gen
>= 7);
1104 if (devinfo
->gen
>= 8) {
1105 BEGIN_BATCH(4 * size
);
1106 for (i
= 0; i
< size
; i
++) {
1107 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
1108 OUT_BATCH(reg
+ i
* 4);
1109 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
1113 BEGIN_BATCH(3 * size
);
1114 for (i
= 0; i
< size
; i
++) {
1115 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
1116 OUT_BATCH(reg
+ i
* 4);
1117 OUT_RELOC(bo
, 0, offset
+ i
* 4);
1124 brw_load_register_mem(struct brw_context
*brw
,
1129 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
1133 brw_load_register_mem64(struct brw_context
*brw
,
1138 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
1142 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
1145 brw_store_register_mem32(struct brw_context
*brw
,
1146 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1148 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1150 assert(devinfo
->gen
>= 6);
1152 if (devinfo
->gen
>= 8) {
1154 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1156 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1160 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1162 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1168 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
1171 brw_store_register_mem64(struct brw_context
*brw
,
1172 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1174 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1176 assert(devinfo
->gen
>= 6);
1178 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
1179 * read a full 64-bit register, we need to do two of them.
1181 if (devinfo
->gen
>= 8) {
1183 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1185 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1186 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1187 OUT_BATCH(reg
+ sizeof(uint32_t));
1188 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
1192 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1194 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1195 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1196 OUT_BATCH(reg
+ sizeof(uint32_t));
1197 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
1203 * Write a 32-bit register using immediate data.
1206 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
1208 assert(brw
->screen
->devinfo
.gen
>= 6);
1211 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
1218 * Write a 64-bit register using immediate data.
1221 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
1223 assert(brw
->screen
->devinfo
.gen
>= 6);
1226 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
1228 OUT_BATCH(imm
& 0xffffffff);
1230 OUT_BATCH(imm
>> 32);
1235 * Copies a 32-bit register.
1238 brw_load_register_reg(struct brw_context
*brw
, uint32_t dest
, uint32_t src
)
1240 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1243 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1250 * Copies a 64-bit register.
1253 brw_load_register_reg64(struct brw_context
*brw
, uint32_t dest
, uint32_t src
)
1255 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1258 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1261 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1262 OUT_BATCH(src
+ sizeof(uint32_t));
1263 OUT_BATCH(dest
+ sizeof(uint32_t));
1268 * Write 32-bits of immediate data to a GPU memory buffer.
1271 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1272 uint32_t offset
, uint32_t imm
)
1274 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1276 assert(devinfo
->gen
>= 6);
1279 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1280 if (devinfo
->gen
>= 8)
1281 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1283 OUT_BATCH(0); /* MBZ */
1284 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1291 * Write 64-bits of immediate data to a GPU memory buffer.
1294 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1295 uint32_t offset
, uint64_t imm
)
1297 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1299 assert(devinfo
->gen
>= 6);
1302 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1303 if (devinfo
->gen
>= 8)
1304 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1306 OUT_BATCH(0); /* MBZ */
1307 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1309 OUT_BATCH(imm
& 0xffffffffu
);
1310 OUT_BATCH(imm
>> 32);