src/mesa/drivers/dri/i965/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
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  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
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  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_batchbuffer.h"
  29 #include "intel_buffer_objects.h"
  30 #include "intel_reg.h"
  31 #include "intel_bufmgr.h"
  32 #include "intel_buffers.h"
  33 #include "intel_fbo.h"
  34 #include "brw_context.h"
  35 #include "brw_defines.h"
  36
  37 #include <xf86drm.h>
  38 #include <i915_drm.h>
  39
  40 static void
  41 intel_batchbuffer_reset(struct brw_context *brw);
  42
  43 void
  44 intel_batchbuffer_init(struct brw_context *brw)
  45 {
  46    intel_batchbuffer_reset(brw);
  47
  48    if (!brw->has_llc) {
  49       brw->batch.cpu_map = malloc(BATCH_SZ);
  50       brw->batch.map = brw->batch.cpu_map;
  51    }
  52 }
  53
  54 static void
  55 intel_batchbuffer_reset(struct brw_context *brw)
  56 {
  57    if (brw->batch.last_bo != NULL) {
  58       drm_intel_bo_unreference(brw->batch.last_bo);
  59       brw->batch.last_bo = NULL;
  60    }
  61    brw->batch.last_bo = brw->batch.bo;
  62
  63    brw_render_cache_set_clear(brw);
  64
  65    brw->batch.bo = drm_intel_bo_alloc(brw->bufmgr, "batchbuffer",
  66                                         BATCH_SZ, 4096);
  67    if (brw->has_llc) {
  68       drm_intel_bo_map(brw->batch.bo, true);
  69       brw->batch.map = brw->batch.bo->virtual;
  70    }
  71
  72    brw->batch.reserved_space = BATCH_RESERVED;
  73    brw->batch.state_batch_offset = brw->batch.bo->size;
  74    brw->batch.used = 0;
  75    brw->batch.needs_sol_reset = false;
  76
  77    /* We don't know what ring the new batch will be sent to until we see the
  78     * first BEGIN_BATCH or BEGIN_BATCH_BLT.  Mark it as unknown.
  79     */
  80    brw->batch.ring = UNKNOWN_RING;
  81 }
  82
  83 void
  84 intel_batchbuffer_save_state(struct brw_context *brw)
  85 {
  86    brw->batch.saved.used = brw->batch.used;
  87    brw->batch.saved.reloc_count =
  88       drm_intel_gem_bo_get_reloc_count(brw->batch.bo);
  89 }
  90
  91 void
  92 intel_batchbuffer_reset_to_saved(struct brw_context *brw)
  93 {
  94    drm_intel_gem_bo_clear_relocs(brw->batch.bo, brw->batch.saved.reloc_count);
  95
  96    brw->batch.used = brw->batch.saved.used;
  97    if (brw->batch.used == 0)
  98       brw->batch.ring = UNKNOWN_RING;
  99 }
 100
 101 void
 102 intel_batchbuffer_free(struct brw_context *brw)
 103 {
 104    free(brw->batch.cpu_map);
 105    drm_intel_bo_unreference(brw->batch.last_bo);
 106    drm_intel_bo_unreference(brw->batch.bo);
 107 }
 108
 109 static void
 110 do_batch_dump(struct brw_context *brw)
 111 {
 112    struct drm_intel_decode *decode;
 113    struct intel_batchbuffer *batch = &brw->batch;
 114    int ret;
 115
 116    decode = drm_intel_decode_context_alloc(brw->intelScreen->deviceID);
 117    if (!decode)
 118       return;
 119
 120    ret = drm_intel_bo_map(batch->bo, false);
 121    if (ret == 0) {
 122       drm_intel_decode_set_batch_pointer(decode,
 123                                          batch->bo->virtual,
 124                                          batch->bo->offset64,
 125                                          batch->used);
 126    } else {
 127       fprintf(stderr,
 128               "WARNING: failed to map batchbuffer (%s), "
 129               "dumping uploaded data instead.\n", strerror(ret));
 130
 131       drm_intel_decode_set_batch_pointer(decode,
 132                                          batch->map,
 133                                          batch->bo->offset64,
 134                                          batch->used);
 135    }
 136
 137    drm_intel_decode_set_output_file(decode, stderr);
 138    drm_intel_decode(decode);
 139
 140    drm_intel_decode_context_free(decode);
 141
 142    if (ret == 0) {
 143       drm_intel_bo_unmap(batch->bo);
 144
 145       brw_debug_batch(brw);
 146    }
 147 }
 148
 149 void
 150 intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw)
 151 {
 152    /* We may need to enable and snapshot OA counters. */
 153    brw_perf_monitor_new_batch(brw);
 154 }
 155
 156 /**
 157  * Called when starting a new batch buffer.
 158  */
 159 static void
 160 brw_new_batch(struct brw_context *brw)
 161 {
 162    /* Create a new batchbuffer and reset the associated state: */
 163    drm_intel_gem_bo_clear_relocs(brw->batch.bo, 0);
 164    intel_batchbuffer_reset(brw);
 165
 166    /* If the kernel supports hardware contexts, then most hardware state is
 167     * preserved between batches; we only need to re-emit state that is required
 168     * to be in every batch.  Otherwise we need to re-emit all the state that
 169     * would otherwise be stored in the context (which for all intents and
 170     * purposes means everything).
 171     */
 172    if (brw->hw_ctx == NULL)
 173       brw->ctx.NewDriverState |= BRW_NEW_CONTEXT;
 174
 175    brw->ctx.NewDriverState |= BRW_NEW_BATCH;
 176
 177    brw->state_batch_count = 0;
 178
 179    brw->ib.type = -1;
 180
 181    /* We need to periodically reap the shader time results, because rollover
 182     * happens every few seconds.  We also want to see results every once in a
 183     * while, because many programs won't cleanly destroy our context, so the
 184     * end-of-run printout may not happen.
 185     */
 186    if (INTEL_DEBUG & DEBUG_SHADER_TIME)
 187       brw_collect_and_report_shader_time(brw);
 188
 189    if (INTEL_DEBUG & DEBUG_PERFMON)
 190       brw_dump_perf_monitors(brw);
 191 }
 192
 193 /**
 194  * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
 195  * sending it off.
 196  *
 197  * This function can emit state (say, to preserve registers that aren't saved
 198  * between batches).  All of this state MUST fit in the reserved space at the
 199  * end of the batchbuffer.  If you add more GPU state, increase the reserved
 200  * space by updating the BATCH_RESERVED macro.
 201  */
 202 static void
 203 brw_finish_batch(struct brw_context *brw)
 204 {
 205    /* Capture the closing pipeline statistics register values necessary to
 206     * support query objects (in the non-hardware context world).
 207     */
 208    brw_emit_query_end(brw);
 209
 210    if (brw->batch.ring == RENDER_RING) {
 211       /* We may also need to snapshot and disable OA counters. */
 212       brw_perf_monitor_finish_batch(brw);
 213
 214       if (brw->is_haswell) {
 215          /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
 216           * 3DSTATE_CC_STATE_POINTERS > "Note":
 217           *
 218           * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
 219           *  3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
 220           *
 221           * From the example in the docs, it seems to expect a regular pipe control
 222           * flush here as well. We may have done it already, but meh.
 223           *
 224           * See also WaAvoidRCZCounterRollover.
 225           */
 226          brw_emit_mi_flush(brw);
 227          BEGIN_BATCH(2);
 228          OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
 229          OUT_BATCH(brw->cc.state_offset | 1);
 230          ADVANCE_BATCH();
 231          brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH |
 232                                           PIPE_CONTROL_CS_STALL);
 233       }
 234    }
 235
 236    /* Mark that the current program cache BO has been used by the GPU.
 237     * It will be reallocated if we need to put new programs in for the
 238     * next batch.
 239     */
 240    brw->cache.bo_used_by_gpu = true;
 241 }
 242
 243 static void
 244 throttle(struct brw_context *brw)
 245 {
 246    /* Wait for the swapbuffers before the one we just emitted, so we
 247     * don't get too many swaps outstanding for apps that are GPU-heavy
 248     * but not CPU-heavy.
 249     *
 250     * We're using intelDRI2Flush (called from the loader before
 251     * swapbuffer) and glFlush (for front buffer rendering) as the
 252     * indicator that a frame is done and then throttle when we get
 253     * here as we prepare to render the next frame.  At this point for
 254     * round trips for swap/copy and getting new buffers are done and
 255     * we'll spend less time waiting on the GPU.
 256     *
 257     * Unfortunately, we don't have a handle to the batch containing
 258     * the swap, and getting our hands on that doesn't seem worth it,
 259     * so we just use the first batch we emitted after the last swap.
 260     */
 261    if (brw->need_swap_throttle && brw->throttle_batch[0]) {
 262       if (brw->throttle_batch[1]) {
 263          if (!brw->disable_throttling)
 264             drm_intel_bo_wait_rendering(brw->throttle_batch[1]);
 265          drm_intel_bo_unreference(brw->throttle_batch[1]);
 266       }
 267       brw->throttle_batch[1] = brw->throttle_batch[0];
 268       brw->throttle_batch[0] = NULL;
 269       brw->need_swap_throttle = false;
 270       /* Throttling here is more precise than the throttle ioctl, so skip it */
 271       brw->need_flush_throttle = false;
 272    }
 273
 274    if (brw->need_flush_throttle) {
 275       __DRIscreen *psp = brw->intelScreen->driScrnPriv;
 276       drmCommandNone(psp->fd, DRM_I915_GEM_THROTTLE);
 277       brw->need_flush_throttle = false;
 278    }
 279 }
 280
 281 /* TODO: Push this whole function into bufmgr.
 282  */
 283 static int
 284 do_flush_locked(struct brw_context *brw)
 285 {
 286    struct intel_batchbuffer *batch = &brw->batch;
 287    int ret = 0;
 288
 289    if (brw->has_llc) {
 290       drm_intel_bo_unmap(batch->bo);
 291    } else {
 292       ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
 293       if (ret == 0 && batch->state_batch_offset != batch->bo->size) {
 294          ret = drm_intel_bo_subdata(batch->bo,
 295                                     batch->state_batch_offset,
 296                                     batch->bo->size - batch->state_batch_offset,
 297                                     (char *)batch->map + batch->state_batch_offset);
 298       }
 299    }
 300
 301    if (!brw->intelScreen->no_hw) {
 302       int flags;
 303
 304       if (brw->gen >= 6 && batch->ring == BLT_RING) {
 305          flags = I915_EXEC_BLT;
 306       } else {
 307          flags = I915_EXEC_RENDER;
 308       }
 309       if (batch->needs_sol_reset)
 310          flags |= I915_EXEC_GEN7_SOL_RESET;
 311
 312       if (ret == 0) {
 313          if (unlikely(INTEL_DEBUG & DEBUG_AUB))
 314             brw_annotate_aub(brw);
 315
 316          if (brw->hw_ctx == NULL || batch->ring != RENDER_RING) {
 317             ret = drm_intel_bo_mrb_exec(batch->bo, 4 * batch->used, NULL, 0, 0,
 318                                         flags);
 319          } else {
 320             ret = drm_intel_gem_bo_context_exec(batch->bo, brw->hw_ctx,
 321                                                 4 * batch->used, flags);
 322          }
 323       }
 324
 325       throttle(brw);
 326    }
 327
 328    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 329       do_batch_dump(brw);
 330
 331    if (ret != 0) {
 332       fprintf(stderr, "intel_do_flush_locked failed: %s\n", strerror(-ret));
 333       exit(1);
 334    }
 335
 336    return ret;
 337 }
 338
 339 int
 340 _intel_batchbuffer_flush(struct brw_context *brw,
 341                          const char *file, int line)
 342 {
 343    int ret;
 344
 345    if (brw->batch.used == 0)
 346       return 0;
 347
 348    if (brw->throttle_batch[0] == NULL) {
 349       brw->throttle_batch[0] = brw->batch.bo;
 350       drm_intel_bo_reference(brw->throttle_batch[0]);
 351    }
 352
 353    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
 354       int bytes_for_commands = 4 * brw->batch.used;
 355       int bytes_for_state = brw->batch.bo->size - brw->batch.state_batch_offset;
 356       int total_bytes = bytes_for_commands + bytes_for_state;
 357       fprintf(stderr, "%s:%d: Batchbuffer flush with %4db (pkt) + "
 358               "%4db (state) = %4db (%0.1f%%)\n", file, line,
 359               bytes_for_commands, bytes_for_state,
 360               total_bytes,
 361               100.0f * total_bytes / BATCH_SZ);
 362    }
 363
 364    brw->batch.reserved_space = 0;
 365
 366    brw_finish_batch(brw);
 367
 368    /* Mark the end of the buffer. */
 369    intel_batchbuffer_emit_dword(brw, MI_BATCH_BUFFER_END);
 370    if (brw->batch.used & 1) {
 371       /* Round batchbuffer usage to 2 DWORDs. */
 372       intel_batchbuffer_emit_dword(brw, MI_NOOP);
 373    }
 374
 375    intel_upload_finish(brw);
 376
 377    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 378    assert(!brw->no_batch_wrap);
 379
 380    ret = do_flush_locked(brw);
 381
 382    if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
 383       fprintf(stderr, "waiting for idle\n");
 384       drm_intel_bo_wait_rendering(brw->batch.bo);
 385    }
 386
 387    /* Start a new batch buffer. */
 388    brw_new_batch(brw);
 389
 390    return ret;
 391 }
 392
 393
 394 /*  This is the only way buffers get added to the validate list.
 395  */
 396 uint32_t
 397 intel_batchbuffer_reloc(struct brw_context *brw,
 398                         drm_intel_bo *buffer,
 399                         uint32_t read_domains, uint32_t write_domain,
 400                         uint32_t delta)
 401 {
 402    int ret;
 403
 404    ret = drm_intel_bo_emit_reloc(brw->batch.bo, 4*brw->batch.used,
 405                                  buffer, delta,
 406                                  read_domains, write_domain);
 407    assert(ret == 0);
 408    (void)ret;
 409
 410    /* Using the old buffer offset, write in what the right data would be, in
 411     * case the buffer doesn't move and we can short-circuit the relocation
 412     * processing in the kernel
 413     */
 414    return buffer->offset64 + delta;
 415 }
 416
 417 uint64_t
 418 intel_batchbuffer_reloc64(struct brw_context *brw,
 419                           drm_intel_bo *buffer,
 420                           uint32_t read_domains, uint32_t write_domain,
 421                           uint32_t delta)
 422 {
 423    int ret = drm_intel_bo_emit_reloc(brw->batch.bo, 4*brw->batch.used,
 424                                      buffer, delta,
 425                                      read_domains, write_domain);
 426    assert(ret == 0);
 427    (void) ret;
 428
 429    /* Using the old buffer offset, write in what the right data would be, in
 430     * case the buffer doesn't move and we can short-circuit the relocation
 431     * processing in the kernel
 432     */
 433    return buffer->offset64 + delta;
 434 }
 435
 436
 437 void
 438 intel_batchbuffer_data(struct brw_context *brw,
 439                        const void *data, GLuint bytes, enum brw_gpu_ring ring)
 440 {
 441    assert((bytes & 3) == 0);
 442    intel_batchbuffer_require_space(brw, bytes, ring);
 443    memcpy(brw->batch.map + brw->batch.used, data, bytes);
 444    brw->batch.used += bytes >> 2;
 445 }
 446
 447 static void
 448 load_sized_register_mem(struct brw_context *brw,
 449                         uint32_t reg,
 450                         drm_intel_bo *bo,
 451                         uint32_t read_domains, uint32_t write_domain,
 452                         uint32_t offset,
 453                         int size)
 454 {
 455    int i;
 456
 457    /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
 458    assert(brw->gen >= 7);
 459
 460    if (brw->gen >= 8) {
 461       BEGIN_BATCH(4 * size);
 462       for (i = 0; i < size; i++) {
 463          OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
 464          OUT_BATCH(reg + i * 4);
 465          OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
 466       }
 467       ADVANCE_BATCH();
 468    } else {
 469       BEGIN_BATCH(3 * size);
 470       for (i = 0; i < size; i++) {
 471          OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
 472          OUT_BATCH(reg + i * 4);
 473          OUT_RELOC(bo, read_domains, write_domain, offset + i * 4);
 474       }
 475       ADVANCE_BATCH();
 476    }
 477 }
 478
 479 void
 480 brw_load_register_mem(struct brw_context *brw,
 481                       uint32_t reg,
 482                       drm_intel_bo *bo,
 483                       uint32_t read_domains, uint32_t write_domain,
 484                       uint32_t offset)
 485 {
 486    load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 1);
 487 }
 488
 489 void
 490 brw_load_register_mem64(struct brw_context *brw,
 491                         uint32_t reg,
 492                         drm_intel_bo *bo,
 493                         uint32_t read_domains, uint32_t write_domain,
 494                         uint32_t offset)
 495 {
 496    load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 2);
 497 }