2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
36 #include "util/hash_table.h"
41 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
44 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
45 struct brw_bufmgr
*bufmgr
,
49 uint_key_compare(const void *a
, const void *b
)
55 uint_key_hash(const void *key
)
57 return (uintptr_t) key
;
61 intel_batchbuffer_init(struct intel_batchbuffer
*batch
,
62 struct brw_bufmgr
*bufmgr
,
65 intel_batchbuffer_reset(batch
, bufmgr
, has_llc
);
68 batch
->cpu_map
= malloc(BATCH_SZ
);
69 batch
->map
= batch
->cpu_map
;
70 batch
->map_next
= batch
->cpu_map
;
73 batch
->reloc_count
= 0;
74 batch
->reloc_array_size
= 250;
75 batch
->relocs
= malloc(batch
->reloc_array_size
*
76 sizeof(struct drm_i915_gem_relocation_entry
));
77 batch
->exec_count
= 0;
78 batch
->exec_array_size
= 100;
80 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
81 batch
->validation_list
=
82 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
84 if (INTEL_DEBUG
& DEBUG_BATCH
) {
85 batch
->state_batch_sizes
=
86 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
91 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
92 struct brw_bufmgr
*bufmgr
,
95 if (batch
->last_bo
!= NULL
) {
96 brw_bo_unreference(batch
->last_bo
);
97 batch
->last_bo
= NULL
;
99 batch
->last_bo
= batch
->bo
;
101 batch
->bo
= brw_bo_alloc(bufmgr
, "batchbuffer", BATCH_SZ
, 4096);
103 batch
->map
= brw_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
105 batch
->map_next
= batch
->map
;
107 batch
->reserved_space
= BATCH_RESERVED
;
108 batch
->state_batch_offset
= batch
->bo
->size
;
109 batch
->needs_sol_reset
= false;
110 batch
->state_base_address_emitted
= false;
112 /* We don't know what ring the new batch will be sent to until we see the
113 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
115 batch
->ring
= UNKNOWN_RING
;
117 if (batch
->state_batch_sizes
)
118 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
122 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
124 intel_batchbuffer_reset(&brw
->batch
, brw
->bufmgr
, brw
->has_llc
);
125 brw_render_cache_set_clear(brw
);
129 intel_batchbuffer_save_state(struct brw_context
*brw
)
131 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
132 brw
->batch
.saved
.reloc_count
= brw
->batch
.reloc_count
;
133 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
137 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
139 for (int i
= brw
->batch
.saved
.exec_count
;
140 i
< brw
->batch
.exec_count
; i
++) {
141 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
142 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
145 brw
->batch
.reloc_count
= brw
->batch
.saved
.reloc_count
;
146 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
148 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
149 if (USED_BATCH(brw
->batch
) == 0)
150 brw
->batch
.ring
= UNKNOWN_RING
;
154 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
156 free(batch
->cpu_map
);
158 for (int i
= 0; i
< batch
->exec_count
; i
++) {
159 if (batch
->exec_bos
[i
] != batch
->bo
) {
160 brw_bo_unreference(batch
->exec_bos
[i
]);
164 free(batch
->exec_bos
);
165 free(batch
->validation_list
);
167 brw_bo_unreference(batch
->last_bo
);
168 brw_bo_unreference(batch
->bo
);
169 if (batch
->state_batch_sizes
)
170 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
174 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
175 enum brw_gpu_ring ring
)
177 /* If we're switching rings, implicitly flush the batch. */
178 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
180 intel_batchbuffer_flush(brw
);
184 assert(sz
< BATCH_SZ
- BATCH_RESERVED
);
186 if (intel_batchbuffer_space(&brw
->batch
) < sz
)
187 intel_batchbuffer_flush(brw
);
189 /* The intel_batchbuffer_flush() calls above might have changed
190 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
192 brw
->batch
.ring
= ring
;
197 #define BLUE_HEADER CSI "0;44m"
198 #define NORMAL CSI "0m"
202 decode_struct(struct brw_context
*brw
, struct gen_spec
*spec
,
203 const char *struct_name
, uint32_t *data
,
204 uint32_t gtt_offset
, uint32_t offset
, bool color
)
206 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
210 fprintf(stderr
, "%s\n", struct_name
);
211 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
212 &data
[offset
/ 4], color
);
216 decode_structs(struct brw_context
*brw
, struct gen_spec
*spec
,
217 const char *struct_name
,
218 uint32_t *data
, uint32_t gtt_offset
, uint32_t offset
,
219 int struct_size
, bool color
)
221 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
225 int entries
= brw_state_batch_size(brw
, offset
) / struct_size
;
226 for (int i
= 0; i
< entries
; i
++) {
227 fprintf(stderr
, "%s %d\n", struct_name
, i
);
228 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
229 &data
[(offset
+ i
* struct_size
) / 4], color
);
234 do_batch_dump(struct brw_context
*brw
)
236 struct intel_batchbuffer
*batch
= &brw
->batch
;
237 struct gen_spec
*spec
= gen_spec_load(&brw
->screen
->devinfo
);
239 if (batch
->ring
!= RENDER_RING
)
242 void *map
= brw_bo_map(brw
, batch
->bo
, MAP_READ
);
245 "WARNING: failed to map batchbuffer, "
246 "dumping uploaded data instead.\n");
249 uint32_t *data
= map
? map
: batch
->map
;
250 uint32_t *end
= data
+ USED_BATCH(*batch
);
251 uint32_t gtt_offset
= map
? batch
->bo
->offset64
: 0;
254 bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
255 const char *header_color
= color
? BLUE_HEADER
: "";
256 const char *reset_color
= color
? NORMAL
: "";
258 for (uint32_t *p
= data
; p
< end
; p
+= length
) {
259 struct gen_group
*inst
= gen_spec_find_instruction(spec
, p
);
260 length
= gen_group_get_length(inst
, p
);
261 assert(inst
== NULL
|| length
> 0);
262 length
= MAX2(1, length
);
264 fprintf(stderr
, "unknown instruction %08x\n", p
[0]);
268 uint64_t offset
= gtt_offset
+ 4 * (p
- data
);
270 fprintf(stderr
, "%s0x%08"PRIx64
": 0x%08x: %-80s%s\n", header_color
,
271 offset
, p
[0], gen_group_get_name(inst
), reset_color
);
273 gen_print_group(stderr
, inst
, offset
, p
, color
);
275 switch (gen_group_get_opcode(inst
) >> 16) {
276 case _3DSTATE_PIPELINED_POINTERS
:
277 /* Note: these Gen4-5 pointers are full relocations rather than
278 * offsets from the start of the batch. So we need to subtract
279 * gtt_offset (the start of the batch) to obtain an offset we
280 * can add to the map and get at the data.
282 decode_struct(brw
, spec
, "VS_STATE", data
, gtt_offset
,
283 (p
[1] & ~0x1fu
) - gtt_offset
, color
);
285 decode_struct(brw
, spec
, "GS_STATE", data
, gtt_offset
,
286 (p
[2] & ~0x1fu
) - gtt_offset
, color
);
289 decode_struct(brw
, spec
, "CLIP_STATE", data
, gtt_offset
,
290 (p
[3] & ~0x1fu
) - gtt_offset
, color
);
292 decode_struct(brw
, spec
, "SF_STATE", data
, gtt_offset
,
293 (p
[4] & ~0x1fu
) - gtt_offset
, color
);
294 decode_struct(brw
, spec
, "WM_STATE", data
, gtt_offset
,
295 (p
[5] & ~0x1fu
) - gtt_offset
, color
);
296 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
, gtt_offset
,
297 (p
[6] & ~0x3fu
) - gtt_offset
, color
);
299 case _3DSTATE_BINDING_TABLE_POINTERS_VS
:
300 case _3DSTATE_BINDING_TABLE_POINTERS_HS
:
301 case _3DSTATE_BINDING_TABLE_POINTERS_DS
:
302 case _3DSTATE_BINDING_TABLE_POINTERS_GS
:
303 case _3DSTATE_BINDING_TABLE_POINTERS_PS
: {
304 struct gen_group
*group
=
305 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
309 uint32_t bt_offset
= p
[1] & ~0x1fu
;
310 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
311 uint32_t *bt_pointers
= &data
[bt_offset
/ 4];
312 for (int i
= 0; i
< bt_entries
; i
++) {
313 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
314 gen_print_group(stderr
, group
, gtt_offset
+ bt_pointers
[i
],
315 &data
[bt_pointers
[i
] / 4], color
);
319 case _3DSTATE_SAMPLER_STATE_POINTERS_VS
:
320 case _3DSTATE_SAMPLER_STATE_POINTERS_HS
:
321 case _3DSTATE_SAMPLER_STATE_POINTERS_DS
:
322 case _3DSTATE_SAMPLER_STATE_POINTERS_GS
:
323 case _3DSTATE_SAMPLER_STATE_POINTERS_PS
:
324 decode_structs(brw
, spec
, "SAMPLER_STATE", data
,
325 gtt_offset
, p
[1] & ~0x1fu
, 4 * 4, color
);
327 case _3DSTATE_VIEWPORT_STATE_POINTERS
:
328 decode_structs(brw
, spec
, "CLIP_VIEWPORT", data
,
329 gtt_offset
, p
[1] & ~0x3fu
, 4 * 4, color
);
330 decode_structs(brw
, spec
, "SF_VIEWPORT", data
,
331 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
332 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
333 gtt_offset
, p
[3] & ~0x3fu
, 2 * 4, color
);
335 case _3DSTATE_VIEWPORT_STATE_POINTERS_CC
:
336 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
337 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
339 case _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
:
340 decode_structs(brw
, spec
, "SF_CLIP_VIEWPORT", data
,
341 gtt_offset
, p
[1] & ~0x3fu
, 16 * 4, color
);
343 case _3DSTATE_SCISSOR_STATE_POINTERS
:
344 decode_structs(brw
, spec
, "SCISSOR_RECT", data
,
345 gtt_offset
, p
[1] & ~0x1fu
, 2 * 4, color
);
347 case _3DSTATE_BLEND_STATE_POINTERS
:
348 /* TODO: handle Gen8+ extra dword at the beginning */
349 decode_structs(brw
, spec
, "BLEND_STATE", data
,
350 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
352 case _3DSTATE_CC_STATE_POINTERS
:
354 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
355 gtt_offset
, p
[1] & ~0x3fu
, color
);
356 } else if (brw
->gen
== 6) {
357 decode_structs(brw
, spec
, "BLEND_STATE", data
,
358 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
359 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
360 gtt_offset
, p
[2] & ~0x3fu
, color
);
361 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
362 gtt_offset
, p
[3] & ~0x3fu
, color
);
365 case _3DSTATE_DEPTH_STENCIL_STATE_POINTERS
:
366 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
367 gtt_offset
, p
[1] & ~0x3fu
, color
);
373 brw_bo_unmap(batch
->bo
);
377 static void do_batch_dump(struct brw_context
*brw
) { }
381 * Called when starting a new batch buffer.
384 brw_new_batch(struct brw_context
*brw
)
386 /* Unreference any BOs held by the previous batch, and reset counts. */
387 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
388 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
389 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
391 brw
->batch
.exec_bos
[i
] = NULL
;
393 brw
->batch
.reloc_count
= 0;
394 brw
->batch
.exec_count
= 0;
395 brw
->batch
.aperture_space
= BATCH_SZ
;
397 /* Create a new batchbuffer and reset the associated state: */
398 intel_batchbuffer_reset_and_clear_render_cache(brw
);
400 /* If the kernel supports hardware contexts, then most hardware state is
401 * preserved between batches; we only need to re-emit state that is required
402 * to be in every batch. Otherwise we need to re-emit all the state that
403 * would otherwise be stored in the context (which for all intents and
404 * purposes means everything).
406 if (brw
->hw_ctx
== 0)
407 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
409 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
411 brw
->ib
.index_size
= -1;
413 /* We need to periodically reap the shader time results, because rollover
414 * happens every few seconds. We also want to see results every once in a
415 * while, because many programs won't cleanly destroy our context, so the
416 * end-of-run printout may not happen.
418 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
419 brw_collect_and_report_shader_time(brw
);
423 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
426 * This function can emit state (say, to preserve registers that aren't saved
427 * between batches). All of this state MUST fit in the reserved space at the
428 * end of the batchbuffer. If you add more GPU state, increase the reserved
429 * space by updating the BATCH_RESERVED macro.
432 brw_finish_batch(struct brw_context
*brw
)
434 /* Capture the closing pipeline statistics register values necessary to
435 * support query objects (in the non-hardware context world).
437 brw_emit_query_end(brw
);
439 if (brw
->batch
.ring
== RENDER_RING
) {
440 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
441 * assume that the L3 cache is configured according to the hardware
445 gen7_restore_default_l3_config(brw
);
447 if (brw
->is_haswell
) {
448 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
449 * 3DSTATE_CC_STATE_POINTERS > "Note":
451 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
452 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
454 * From the example in the docs, it seems to expect a regular pipe control
455 * flush here as well. We may have done it already, but meh.
457 * See also WaAvoidRCZCounterRollover.
459 brw_emit_mi_flush(brw
);
461 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
462 OUT_BATCH(brw
->cc
.state_offset
| 1);
464 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
465 PIPE_CONTROL_CS_STALL
);
469 /* Mark that the current program cache BO has been used by the GPU.
470 * It will be reallocated if we need to put new programs in for the
473 brw
->cache
.bo_used_by_gpu
= true;
477 throttle(struct brw_context
*brw
)
479 /* Wait for the swapbuffers before the one we just emitted, so we
480 * don't get too many swaps outstanding for apps that are GPU-heavy
483 * We're using intelDRI2Flush (called from the loader before
484 * swapbuffer) and glFlush (for front buffer rendering) as the
485 * indicator that a frame is done and then throttle when we get
486 * here as we prepare to render the next frame. At this point for
487 * round trips for swap/copy and getting new buffers are done and
488 * we'll spend less time waiting on the GPU.
490 * Unfortunately, we don't have a handle to the batch containing
491 * the swap, and getting our hands on that doesn't seem worth it,
492 * so we just use the first batch we emitted after the last swap.
494 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
495 if (brw
->throttle_batch
[1]) {
496 if (!brw
->disable_throttling
) {
497 /* Pass NULL rather than brw so we avoid perf_debug warnings;
498 * stalling is common and expected here...
500 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
502 brw_bo_unreference(brw
->throttle_batch
[1]);
504 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
505 brw
->throttle_batch
[0] = NULL
;
506 brw
->need_swap_throttle
= false;
507 /* Throttling here is more precise than the throttle ioctl, so skip it */
508 brw
->need_flush_throttle
= false;
511 if (brw
->need_flush_throttle
) {
512 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
513 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
514 brw
->need_flush_throttle
= false;
519 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
521 if (bo
!= batch
->bo
) {
522 for (int i
= 0; i
< batch
->exec_count
; i
++) {
523 if (batch
->exec_bos
[i
] == bo
)
527 brw_bo_reference(bo
);
530 if (batch
->exec_count
== batch
->exec_array_size
) {
531 batch
->exec_array_size
*= 2;
533 realloc(batch
->exec_bos
,
534 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
535 batch
->validation_list
=
536 realloc(batch
->validation_list
,
537 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
540 struct drm_i915_gem_exec_object2
*validation_entry
=
541 &batch
->validation_list
[batch
->exec_count
];
542 validation_entry
->handle
= bo
->gem_handle
;
543 if (bo
== batch
->bo
) {
544 validation_entry
->relocation_count
= batch
->reloc_count
;
545 validation_entry
->relocs_ptr
= (uintptr_t) batch
->relocs
;
547 validation_entry
->relocation_count
= 0;
548 validation_entry
->relocs_ptr
= 0;
550 validation_entry
->alignment
= bo
->align
;
551 validation_entry
->offset
= bo
->offset64
;
552 validation_entry
->flags
= bo
->kflags
;
553 validation_entry
->rsvd1
= 0;
554 validation_entry
->rsvd2
= 0;
556 batch
->exec_bos
[batch
->exec_count
] = bo
;
558 batch
->aperture_space
+= bo
->size
;
563 struct intel_batchbuffer
*batch
,
570 struct drm_i915_gem_execbuffer2 execbuf
= {
571 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
572 .buffer_count
= batch
->exec_count
,
573 .batch_start_offset
= 0,
576 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
579 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
581 if (in_fence
!= -1) {
582 execbuf
.rsvd2
= in_fence
;
583 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
586 if (out_fence
!= NULL
) {
587 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
589 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
592 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
596 for (int i
= 0; i
< batch
->exec_count
; i
++) {
597 struct brw_bo
*bo
= batch
->exec_bos
[i
];
601 /* Update brw_bo::offset64 */
602 if (batch
->validation_list
[i
].offset
!= bo
->offset64
) {
603 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
604 bo
->gem_handle
, bo
->offset64
, batch
->validation_list
[i
].offset
);
605 bo
->offset64
= batch
->validation_list
[i
].offset
;
609 if (ret
== 0 && out_fence
!= NULL
)
610 *out_fence
= execbuf
.rsvd2
>> 32;
616 do_flush_locked(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
618 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
619 struct intel_batchbuffer
*batch
= &brw
->batch
;
623 brw_bo_unmap(batch
->bo
);
625 ret
= brw_bo_subdata(batch
->bo
, 0, 4 * USED_BATCH(*batch
), batch
->map
);
626 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
627 ret
= brw_bo_subdata(batch
->bo
,
628 batch
->state_batch_offset
,
629 batch
->bo
->size
- batch
->state_batch_offset
,
630 (char *)batch
->map
+ batch
->state_batch_offset
);
634 if (!brw
->screen
->no_hw
) {
637 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
638 flags
= I915_EXEC_BLT
;
640 flags
= I915_EXEC_RENDER
;
642 if (batch
->needs_sol_reset
)
643 flags
|= I915_EXEC_GEN7_SOL_RESET
;
646 uint32_t hw_ctx
= batch
->ring
== RENDER_RING
? brw
->hw_ctx
: 0;
648 /* Add the batch itself to the end of the validation list */
649 add_exec_bo(batch
, batch
->bo
);
651 ret
= execbuffer(dri_screen
->fd
, batch
, hw_ctx
,
652 4 * USED_BATCH(*batch
),
653 in_fence_fd
, out_fence_fd
, flags
);
659 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
662 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
663 brw_check_for_reset(brw
);
666 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
674 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
677 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
678 * of the returned fd.
681 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
682 int in_fence_fd
, int *out_fence_fd
,
683 const char *file
, int line
)
687 if (USED_BATCH(brw
->batch
) == 0)
690 if (brw
->throttle_batch
[0] == NULL
) {
691 brw
->throttle_batch
[0] = brw
->batch
.bo
;
692 brw_bo_reference(brw
->throttle_batch
[0]);
695 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
696 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
697 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
698 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
699 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
700 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
701 bytes_for_commands
, bytes_for_state
,
703 100.0f
* total_bytes
/ BATCH_SZ
);
706 brw
->batch
.reserved_space
= 0;
708 brw_finish_batch(brw
);
710 /* Mark the end of the buffer. */
711 intel_batchbuffer_emit_dword(&brw
->batch
, MI_BATCH_BUFFER_END
);
712 if (USED_BATCH(brw
->batch
) & 1) {
713 /* Round batchbuffer usage to 2 DWORDs. */
714 intel_batchbuffer_emit_dword(&brw
->batch
, MI_NOOP
);
717 intel_upload_finish(brw
);
719 /* Check that we didn't just wrap our batchbuffer at a bad time. */
720 assert(!brw
->no_batch_wrap
);
722 ret
= do_flush_locked(brw
, in_fence_fd
, out_fence_fd
);
724 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
725 fprintf(stderr
, "waiting for idle\n");
726 brw_bo_wait_rendering(brw
->batch
.bo
);
729 /* Start a new batch buffer. */
736 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
738 return brw
->batch
.aperture_space
+ extra_space
<=
739 brw
->screen
->aperture_threshold
;
743 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
745 for (int i
= 0; i
< batch
->exec_count
; i
++) {
746 if (batch
->exec_bos
[i
] == bo
)
752 /* This is the only way buffers get added to the validate list.
755 brw_emit_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
756 struct brw_bo
*target
, uint32_t target_offset
,
757 uint32_t read_domains
, uint32_t write_domain
)
761 if (batch
->reloc_count
== batch
->reloc_array_size
) {
762 batch
->reloc_array_size
*= 2;
763 batch
->relocs
= realloc(batch
->relocs
,
764 batch
->reloc_array_size
*
765 sizeof(struct drm_i915_gem_relocation_entry
));
769 assert(batch_offset
<= BATCH_SZ
- sizeof(uint32_t));
770 assert(_mesa_bitcount(write_domain
) <= 1);
772 if (target
!= batch
->bo
)
773 add_exec_bo(batch
, target
);
775 struct drm_i915_gem_relocation_entry
*reloc
=
776 &batch
->relocs
[batch
->reloc_count
];
778 batch
->reloc_count
++;
780 /* ensure gcc doesn't reload */
781 offset64
= *((volatile uint64_t *)&target
->offset64
);
782 reloc
->offset
= batch_offset
;
783 reloc
->delta
= target_offset
;
784 reloc
->target_handle
= target
->gem_handle
;
785 reloc
->read_domains
= read_domains
;
786 reloc
->write_domain
= write_domain
;
787 reloc
->presumed_offset
= offset64
;
789 /* Using the old buffer offset, write in what the right data would be, in
790 * case the buffer doesn't move and we can short-circuit the relocation
791 * processing in the kernel
793 return offset64
+ target_offset
;
797 intel_batchbuffer_data(struct brw_context
*brw
,
798 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
800 assert((bytes
& 3) == 0);
801 intel_batchbuffer_require_space(brw
, bytes
, ring
);
802 memcpy(brw
->batch
.map_next
, data
, bytes
);
803 brw
->batch
.map_next
+= bytes
>> 2;
807 load_sized_register_mem(struct brw_context
*brw
,
810 uint32_t read_domains
, uint32_t write_domain
,
816 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
817 assert(brw
->gen
>= 7);
820 BEGIN_BATCH(4 * size
);
821 for (i
= 0; i
< size
; i
++) {
822 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
823 OUT_BATCH(reg
+ i
* 4);
824 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
+ i
* 4);
828 BEGIN_BATCH(3 * size
);
829 for (i
= 0; i
< size
; i
++) {
830 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
831 OUT_BATCH(reg
+ i
* 4);
832 OUT_RELOC(bo
, read_domains
, write_domain
, offset
+ i
* 4);
839 brw_load_register_mem(struct brw_context
*brw
,
842 uint32_t read_domains
, uint32_t write_domain
,
845 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 1);
849 brw_load_register_mem64(struct brw_context
*brw
,
852 uint32_t read_domains
, uint32_t write_domain
,
855 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 2);
859 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
862 brw_store_register_mem32(struct brw_context
*brw
,
863 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
865 assert(brw
->gen
>= 6);
869 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
871 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
876 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
878 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
885 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
888 brw_store_register_mem64(struct brw_context
*brw
,
889 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
891 assert(brw
->gen
>= 6);
893 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
894 * read a full 64-bit register, we need to do two of them.
898 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
900 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
902 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
903 OUT_BATCH(reg
+ sizeof(uint32_t));
904 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
905 offset
+ sizeof(uint32_t));
909 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
911 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
913 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
914 OUT_BATCH(reg
+ sizeof(uint32_t));
915 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
916 offset
+ sizeof(uint32_t));
922 * Write a 32-bit register using immediate data.
925 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
927 assert(brw
->gen
>= 6);
930 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
937 * Write a 64-bit register using immediate data.
940 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
942 assert(brw
->gen
>= 6);
945 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
947 OUT_BATCH(imm
& 0xffffffff);
949 OUT_BATCH(imm
>> 32);
954 * Copies a 32-bit register.
957 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
959 assert(brw
->gen
>= 8 || brw
->is_haswell
);
962 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
969 * Copies a 64-bit register.
972 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
974 assert(brw
->gen
>= 8 || brw
->is_haswell
);
977 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
980 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
981 OUT_BATCH(src
+ sizeof(uint32_t));
982 OUT_BATCH(dest
+ sizeof(uint32_t));
987 * Write 32-bits of immediate data to a GPU memory buffer.
990 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
991 uint32_t offset
, uint32_t imm
)
993 assert(brw
->gen
>= 6);
996 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
998 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1001 OUT_BATCH(0); /* MBZ */
1002 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1010 * Write 64-bits of immediate data to a GPU memory buffer.
1013 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1014 uint32_t offset
, uint64_t imm
)
1016 assert(brw
->gen
>= 6);
1019 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1021 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1024 OUT_BATCH(0); /* MBZ */
1025 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1028 OUT_BATCH(imm
& 0xffffffffu
);
1029 OUT_BATCH(imm
>> 32);