2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "intel_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
39 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
, dri_bufmgr
*bufmgr
,
43 intel_batchbuffer_init(struct intel_batchbuffer
*batch
, dri_bufmgr
*bufmgr
,
46 intel_batchbuffer_reset(batch
, bufmgr
, has_llc
);
49 batch
->cpu_map
= malloc(BATCH_SZ
);
50 batch
->map
= batch
->cpu_map
;
51 batch
->map_next
= batch
->cpu_map
;
56 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
, dri_bufmgr
*bufmgr
,
59 if (batch
->last_bo
!= NULL
) {
60 drm_intel_bo_unreference(batch
->last_bo
);
61 batch
->last_bo
= NULL
;
63 batch
->last_bo
= batch
->bo
;
65 batch
->bo
= drm_intel_bo_alloc(bufmgr
, "batchbuffer", BATCH_SZ
, 4096);
67 drm_intel_bo_map(batch
->bo
, true);
68 batch
->map
= batch
->bo
->virtual;
70 batch
->map_next
= batch
->map
;
72 batch
->reserved_space
= BATCH_RESERVED
;
73 batch
->state_batch_offset
= batch
->bo
->size
;
74 batch
->needs_sol_reset
= false;
75 batch
->state_base_address_emitted
= false;
77 /* We don't know what ring the new batch will be sent to until we see the
78 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
80 batch
->ring
= UNKNOWN_RING
;
84 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
86 intel_batchbuffer_reset(&brw
->batch
, brw
->bufmgr
, brw
->has_llc
);
87 brw_render_cache_set_clear(brw
);
91 intel_batchbuffer_save_state(struct brw_context
*brw
)
93 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
94 brw
->batch
.saved
.reloc_count
=
95 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
99 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
101 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
103 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
104 if (USED_BATCH(brw
->batch
) == 0)
105 brw
->batch
.ring
= UNKNOWN_RING
;
109 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
111 free(batch
->cpu_map
);
112 drm_intel_bo_unreference(batch
->last_bo
);
113 drm_intel_bo_unreference(batch
->bo
);
117 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
118 enum brw_gpu_ring ring
)
120 /* If we're switching rings, implicitly flush the batch. */
121 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
123 intel_batchbuffer_flush(brw
);
127 assert(sz
< BATCH_SZ
- BATCH_RESERVED
);
129 if (intel_batchbuffer_space(&brw
->batch
) < sz
)
130 intel_batchbuffer_flush(brw
);
132 enum brw_gpu_ring prev_ring
= brw
->batch
.ring
;
133 /* The intel_batchbuffer_flush() calls above might have changed
134 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
136 brw
->batch
.ring
= ring
;
138 if (unlikely(prev_ring
== UNKNOWN_RING
&& ring
== RENDER_RING
))
139 intel_batchbuffer_emit_render_ring_prelude(brw
);
143 do_batch_dump(struct brw_context
*brw
)
145 struct drm_intel_decode
*decode
;
146 struct intel_batchbuffer
*batch
= &brw
->batch
;
149 decode
= drm_intel_decode_context_alloc(brw
->screen
->deviceID
);
153 ret
= drm_intel_bo_map(batch
->bo
, false);
155 drm_intel_decode_set_batch_pointer(decode
,
161 "WARNING: failed to map batchbuffer (%s), "
162 "dumping uploaded data instead.\n", strerror(ret
));
164 drm_intel_decode_set_batch_pointer(decode
,
170 drm_intel_decode_set_output_file(decode
, stderr
);
171 drm_intel_decode(decode
);
173 drm_intel_decode_context_free(decode
);
176 drm_intel_bo_unmap(batch
->bo
);
178 brw_debug_batch(brw
);
183 intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
)
185 /* Un-used currently */
189 * Called when starting a new batch buffer.
192 brw_new_batch(struct brw_context
*brw
)
194 /* Create a new batchbuffer and reset the associated state: */
195 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, 0);
196 intel_batchbuffer_reset_and_clear_render_cache(brw
);
198 /* If the kernel supports hardware contexts, then most hardware state is
199 * preserved between batches; we only need to re-emit state that is required
200 * to be in every batch. Otherwise we need to re-emit all the state that
201 * would otherwise be stored in the context (which for all intents and
202 * purposes means everything).
204 if (brw
->hw_ctx
== NULL
)
205 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
207 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
209 brw
->state_batch_count
= 0;
213 /* We need to periodically reap the shader time results, because rollover
214 * happens every few seconds. We also want to see results every once in a
215 * while, because many programs won't cleanly destroy our context, so the
216 * end-of-run printout may not happen.
218 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
219 brw_collect_and_report_shader_time(brw
);
223 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
226 * This function can emit state (say, to preserve registers that aren't saved
227 * between batches). All of this state MUST fit in the reserved space at the
228 * end of the batchbuffer. If you add more GPU state, increase the reserved
229 * space by updating the BATCH_RESERVED macro.
232 brw_finish_batch(struct brw_context
*brw
)
234 /* Capture the closing pipeline statistics register values necessary to
235 * support query objects (in the non-hardware context world).
237 brw_emit_query_end(brw
);
239 if (brw
->batch
.ring
== RENDER_RING
) {
240 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
241 * assume that the L3 cache is configured according to the hardware
245 gen7_restore_default_l3_config(brw
);
247 if (brw
->is_haswell
) {
248 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
249 * 3DSTATE_CC_STATE_POINTERS > "Note":
251 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
252 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
254 * From the example in the docs, it seems to expect a regular pipe control
255 * flush here as well. We may have done it already, but meh.
257 * See also WaAvoidRCZCounterRollover.
259 brw_emit_mi_flush(brw
);
261 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
262 OUT_BATCH(brw
->cc
.state_offset
| 1);
264 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
265 PIPE_CONTROL_CS_STALL
);
269 /* Mark that the current program cache BO has been used by the GPU.
270 * It will be reallocated if we need to put new programs in for the
273 brw
->cache
.bo_used_by_gpu
= true;
277 throttle(struct brw_context
*brw
)
279 /* Wait for the swapbuffers before the one we just emitted, so we
280 * don't get too many swaps outstanding for apps that are GPU-heavy
283 * We're using intelDRI2Flush (called from the loader before
284 * swapbuffer) and glFlush (for front buffer rendering) as the
285 * indicator that a frame is done and then throttle when we get
286 * here as we prepare to render the next frame. At this point for
287 * round trips for swap/copy and getting new buffers are done and
288 * we'll spend less time waiting on the GPU.
290 * Unfortunately, we don't have a handle to the batch containing
291 * the swap, and getting our hands on that doesn't seem worth it,
292 * so we just use the first batch we emitted after the last swap.
294 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
295 if (brw
->throttle_batch
[1]) {
296 if (!brw
->disable_throttling
)
297 drm_intel_bo_wait_rendering(brw
->throttle_batch
[1]);
298 drm_intel_bo_unreference(brw
->throttle_batch
[1]);
300 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
301 brw
->throttle_batch
[0] = NULL
;
302 brw
->need_swap_throttle
= false;
303 /* Throttling here is more precise than the throttle ioctl, so skip it */
304 brw
->need_flush_throttle
= false;
307 if (brw
->need_flush_throttle
) {
308 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
309 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
310 brw
->need_flush_throttle
= false;
314 /* Drop when RS headers get pulled to libdrm */
315 #ifndef I915_EXEC_RESOURCE_STREAMER
316 #define I915_EXEC_RESOURCE_STREAMER (1<<15)
319 /* TODO: Push this whole function into bufmgr.
322 do_flush_locked(struct brw_context
*brw
)
324 struct intel_batchbuffer
*batch
= &brw
->batch
;
328 drm_intel_bo_unmap(batch
->bo
);
330 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4 * USED_BATCH(*batch
), batch
->map
);
331 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
332 ret
= drm_intel_bo_subdata(batch
->bo
,
333 batch
->state_batch_offset
,
334 batch
->bo
->size
- batch
->state_batch_offset
,
335 (char *)batch
->map
+ batch
->state_batch_offset
);
339 if (!brw
->screen
->no_hw
) {
342 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
343 flags
= I915_EXEC_BLT
;
345 flags
= I915_EXEC_RENDER
|
346 (brw
->use_resource_streamer
? I915_EXEC_RESOURCE_STREAMER
: 0);
348 if (batch
->needs_sol_reset
)
349 flags
|= I915_EXEC_GEN7_SOL_RESET
;
352 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
353 brw_annotate_aub(brw
);
355 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
356 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * USED_BATCH(*batch
),
359 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
360 4 * USED_BATCH(*batch
), flags
);
367 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
370 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
371 brw_check_for_reset(brw
);
374 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
382 _intel_batchbuffer_flush(struct brw_context
*brw
,
383 const char *file
, int line
)
387 if (USED_BATCH(brw
->batch
) == 0)
390 if (brw
->throttle_batch
[0] == NULL
) {
391 brw
->throttle_batch
[0] = brw
->batch
.bo
;
392 drm_intel_bo_reference(brw
->throttle_batch
[0]);
395 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
396 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
397 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
398 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
399 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
400 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
401 bytes_for_commands
, bytes_for_state
,
403 100.0f
* total_bytes
/ BATCH_SZ
);
406 brw
->batch
.reserved_space
= 0;
408 brw_finish_batch(brw
);
410 /* Mark the end of the buffer. */
411 intel_batchbuffer_emit_dword(&brw
->batch
, MI_BATCH_BUFFER_END
);
412 if (USED_BATCH(brw
->batch
) & 1) {
413 /* Round batchbuffer usage to 2 DWORDs. */
414 intel_batchbuffer_emit_dword(&brw
->batch
, MI_NOOP
);
417 intel_upload_finish(brw
);
419 /* Check that we didn't just wrap our batchbuffer at a bad time. */
420 assert(!brw
->no_batch_wrap
);
422 ret
= do_flush_locked(brw
);
424 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
425 fprintf(stderr
, "waiting for idle\n");
426 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
429 if (brw
->use_resource_streamer
)
430 gen7_reset_hw_bt_pool_offsets(brw
);
432 /* Start a new batch buffer. */
439 /* This is the only way buffers get added to the validate list.
442 intel_batchbuffer_reloc(struct intel_batchbuffer
*batch
,
443 drm_intel_bo
*buffer
, uint32_t offset
,
444 uint32_t read_domains
, uint32_t write_domain
,
449 ret
= drm_intel_bo_emit_reloc(batch
->bo
, offset
,
451 read_domains
, write_domain
);
455 /* Using the old buffer offset, write in what the right data would be, in
456 * case the buffer doesn't move and we can short-circuit the relocation
457 * processing in the kernel
459 return buffer
->offset64
+ delta
;
463 intel_batchbuffer_reloc64(struct intel_batchbuffer
*batch
,
464 drm_intel_bo
*buffer
, uint32_t offset
,
465 uint32_t read_domains
, uint32_t write_domain
,
468 int ret
= drm_intel_bo_emit_reloc(batch
->bo
, offset
,
470 read_domains
, write_domain
);
474 /* Using the old buffer offset, write in what the right data would be, in
475 * case the buffer doesn't move and we can short-circuit the relocation
476 * processing in the kernel
478 return buffer
->offset64
+ delta
;
483 intel_batchbuffer_data(struct brw_context
*brw
,
484 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
486 assert((bytes
& 3) == 0);
487 intel_batchbuffer_require_space(brw
, bytes
, ring
);
488 memcpy(brw
->batch
.map_next
, data
, bytes
);
489 brw
->batch
.map_next
+= bytes
>> 2;
493 load_sized_register_mem(struct brw_context
*brw
,
496 uint32_t read_domains
, uint32_t write_domain
,
502 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
503 assert(brw
->gen
>= 7);
506 BEGIN_BATCH(4 * size
);
507 for (i
= 0; i
< size
; i
++) {
508 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
509 OUT_BATCH(reg
+ i
* 4);
510 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
+ i
* 4);
514 BEGIN_BATCH(3 * size
);
515 for (i
= 0; i
< size
; i
++) {
516 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
517 OUT_BATCH(reg
+ i
* 4);
518 OUT_RELOC(bo
, read_domains
, write_domain
, offset
+ i
* 4);
525 brw_load_register_mem(struct brw_context
*brw
,
528 uint32_t read_domains
, uint32_t write_domain
,
531 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 1);
535 brw_load_register_mem64(struct brw_context
*brw
,
538 uint32_t read_domains
, uint32_t write_domain
,
541 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 2);
545 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
548 brw_store_register_mem32(struct brw_context
*brw
,
549 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
)
551 assert(brw
->gen
>= 6);
555 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
557 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
562 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
564 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
571 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
574 brw_store_register_mem64(struct brw_context
*brw
,
575 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
)
577 assert(brw
->gen
>= 6);
579 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
580 * read a full 64-bit register, we need to do two of them.
584 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
586 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
588 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
589 OUT_BATCH(reg
+ sizeof(uint32_t));
590 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
591 offset
+ sizeof(uint32_t));
595 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
597 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
599 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
600 OUT_BATCH(reg
+ sizeof(uint32_t));
601 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
602 offset
+ sizeof(uint32_t));
608 * Write a 32-bit register using immediate data.
611 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
613 assert(brw
->gen
>= 6);
616 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
623 * Write a 64-bit register using immediate data.
626 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
628 assert(brw
->gen
>= 6);
631 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
633 OUT_BATCH(imm
& 0xffffffff);
635 OUT_BATCH(imm
>> 32);
640 * Copies a 32-bit register.
643 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
645 assert(brw
->gen
>= 8 || brw
->is_haswell
);
648 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
655 * Copies a 64-bit register.
658 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
660 assert(brw
->gen
>= 8 || brw
->is_haswell
);
663 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
666 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
667 OUT_BATCH(src
+ sizeof(uint32_t));
668 OUT_BATCH(dest
+ sizeof(uint32_t));
673 * Write 32-bits of immediate data to a GPU memory buffer.
676 brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
677 uint32_t offset
, uint32_t imm
)
679 assert(brw
->gen
>= 6);
682 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
684 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
687 OUT_BATCH(0); /* MBZ */
688 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
696 * Write 64-bits of immediate data to a GPU memory buffer.
699 brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
700 uint32_t offset
, uint64_t imm
)
702 assert(brw
->gen
>= 6);
705 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
707 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
710 OUT_BATCH(0); /* MBZ */
711 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
714 OUT_BATCH(imm
& 0xffffffffu
);
715 OUT_BATCH(imm
>> 32);