1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "brw_context.h"
36 intel_batchbuffer_reset(struct brw_context
*brw
);
38 struct cached_batch_item
{
39 struct cached_batch_item
*next
;
45 intel_batchbuffer_clear_cache(struct brw_context
*brw
)
47 struct cached_batch_item
*item
= brw
->batch
.cached_items
;
50 struct cached_batch_item
*next
= item
->next
;
55 brw
->batch
.cached_items
= NULL
;
59 intel_batchbuffer_init(struct brw_context
*brw
)
61 intel_batchbuffer_reset(brw
);
64 /* We can't just use brw_state_batch to get a chunk of space for
65 * the gen6 workaround because it involves actually writing to
66 * the buffer, and the kernel doesn't let us write to the batch.
68 brw
->batch
.workaround_bo
= drm_intel_bo_alloc(brw
->bufmgr
,
69 "pipe_control workaround",
73 brw
->batch
.need_workaround_flush
= true;
76 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
77 brw
->batch
.map
= brw
->batch
.cpu_map
;
82 intel_batchbuffer_reset(struct brw_context
*brw
)
84 if (brw
->batch
.last_bo
!= NULL
) {
85 drm_intel_bo_unreference(brw
->batch
.last_bo
);
86 brw
->batch
.last_bo
= NULL
;
88 brw
->batch
.last_bo
= brw
->batch
.bo
;
90 intel_batchbuffer_clear_cache(brw
);
92 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
95 drm_intel_bo_map(brw
->batch
.bo
, true);
96 brw
->batch
.map
= brw
->batch
.bo
->virtual;
99 brw
->batch
.reserved_space
= BATCH_RESERVED
;
100 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
102 brw
->batch
.needs_sol_reset
= false;
104 /* We don't know what ring the new batch will be sent to until we see the
105 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
107 brw
->batch
.ring
= UNKNOWN_RING
;
111 intel_batchbuffer_save_state(struct brw_context
*brw
)
113 brw
->batch
.saved
.used
= brw
->batch
.used
;
114 brw
->batch
.saved
.reloc_count
=
115 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
119 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
121 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
123 brw
->batch
.used
= brw
->batch
.saved
.used
;
124 if (brw
->batch
.used
== 0)
125 brw
->batch
.ring
= UNKNOWN_RING
;
127 /* Cached batch state is dead, since we just cleared some unknown part of the
128 * batchbuffer. Assume that the caller resets any other state necessary.
130 intel_batchbuffer_clear_cache(brw
);
134 intel_batchbuffer_free(struct brw_context
*brw
)
136 free(brw
->batch
.cpu_map
);
137 drm_intel_bo_unreference(brw
->batch
.last_bo
);
138 drm_intel_bo_unreference(brw
->batch
.bo
);
139 drm_intel_bo_unreference(brw
->batch
.workaround_bo
);
140 intel_batchbuffer_clear_cache(brw
);
144 do_batch_dump(struct brw_context
*brw
)
146 struct drm_intel_decode
*decode
;
147 struct intel_batchbuffer
*batch
= &brw
->batch
;
150 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
154 ret
= drm_intel_bo_map(batch
->bo
, false);
156 drm_intel_decode_set_batch_pointer(decode
,
162 "WARNING: failed to map batchbuffer (%s), "
163 "dumping uploaded data instead.\n", strerror(ret
));
165 drm_intel_decode_set_batch_pointer(decode
,
171 drm_intel_decode(decode
);
173 drm_intel_decode_context_free(decode
);
176 drm_intel_bo_unmap(batch
->bo
);
178 brw_debug_batch(brw
);
183 intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
)
185 /* Without hardware contexts, we need to capture the pipeline statistics
186 * registers at the start and end of each render ring batch, so we can see
187 * what that batch contributed. Emit state packets to write them to a BO.
189 brw_emit_query_begin(brw
);
191 /* We may also need to enable and snapshot OA counters. */
192 brw_perf_monitor_new_batch(brw
);
196 * Called when starting a new batch buffer.
199 brw_new_batch(struct brw_context
*brw
)
201 /* Create a new batchbuffer and reset the associated state: */
202 intel_batchbuffer_reset(brw
);
204 /* If the kernel supports hardware contexts, then most hardware state is
205 * preserved between batches; we only need to re-emit state that is required
206 * to be in every batch. Otherwise we need to re-emit all the state that
207 * would otherwise be stored in the context (which for all intents and
208 * purposes means everything).
210 if (brw
->hw_ctx
== NULL
)
211 brw
->state
.dirty
.brw
|= BRW_NEW_CONTEXT
;
213 brw
->state
.dirty
.brw
|= BRW_NEW_BATCH
;
215 /* Assume that the last command before the start of our batch was a
216 * primitive, for safety.
218 brw
->batch
.need_workaround_flush
= true;
220 brw
->state_batch_count
= 0;
224 /* We need to periodically reap the shader time results, because rollover
225 * happens every few seconds. We also want to see results every once in a
226 * while, because many programs won't cleanly destroy our context, so the
227 * end-of-run printout may not happen.
229 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
230 brw_collect_and_report_shader_time(brw
);
232 if (INTEL_DEBUG
& DEBUG_PERFMON
)
233 brw_dump_perf_monitors(brw
);
237 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
240 * This function can emit state (say, to preserve registers that aren't saved
241 * between batches). All of this state MUST fit in the reserved space at the
242 * end of the batchbuffer. If you add more GPU state, increase the reserved
243 * space by updating the BATCH_RESERVED macro.
246 brw_finish_batch(struct brw_context
*brw
)
248 /* Capture the closing pipeline statistics register values necessary to
249 * support query objects (in the non-hardware context world).
251 brw_emit_query_end(brw
);
253 /* We may also need to snapshot and disable OA counters. */
254 if (brw
->batch
.ring
== RENDER_RING
)
255 brw_perf_monitor_finish_batch(brw
);
257 if (brw
->curbe
.curbe_bo
) {
258 drm_intel_gem_bo_unmap_gtt(brw
->curbe
.curbe_bo
);
259 drm_intel_bo_unreference(brw
->curbe
.curbe_bo
);
260 brw
->curbe
.curbe_bo
= NULL
;
263 /* Mark that the current program cache BO has been used by the GPU.
264 * It will be reallocated if we need to put new programs in for the
267 brw
->cache
.bo_used_by_gpu
= true;
270 /* TODO: Push this whole function into bufmgr.
273 do_flush_locked(struct brw_context
*brw
)
275 struct intel_batchbuffer
*batch
= &brw
->batch
;
279 drm_intel_bo_unmap(batch
->bo
);
281 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
282 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
283 ret
= drm_intel_bo_subdata(batch
->bo
,
284 batch
->state_batch_offset
,
285 batch
->bo
->size
- batch
->state_batch_offset
,
286 (char *)batch
->map
+ batch
->state_batch_offset
);
290 if (!brw
->intelScreen
->no_hw
) {
293 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
294 flags
= I915_EXEC_BLT
;
296 flags
= I915_EXEC_RENDER
;
298 if (batch
->needs_sol_reset
)
299 flags
|= I915_EXEC_GEN7_SOL_RESET
;
302 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
303 brw_annotate_aub(brw
);
304 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
305 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
308 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
309 4 * batch
->used
, flags
);
314 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
318 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
326 _intel_batchbuffer_flush(struct brw_context
*brw
,
327 const char *file
, int line
)
331 if (brw
->batch
.used
== 0)
334 if (brw
->first_post_swapbuffers_batch
== NULL
) {
335 brw
->first_post_swapbuffers_batch
= brw
->batch
.bo
;
336 drm_intel_bo_reference(brw
->first_post_swapbuffers_batch
);
339 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
340 int bytes_for_commands
= 4 * brw
->batch
.used
;
341 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
342 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
343 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
344 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
345 bytes_for_commands
, bytes_for_state
,
347 100.0f
* total_bytes
/ BATCH_SZ
);
350 brw
->batch
.reserved_space
= 0;
352 brw_finish_batch(brw
);
354 /* Mark the end of the buffer. */
355 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
356 if (brw
->batch
.used
& 1) {
357 /* Round batchbuffer usage to 2 DWORDs. */
358 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
361 intel_upload_finish(brw
);
363 /* Check that we didn't just wrap our batchbuffer at a bad time. */
364 assert(!brw
->no_batch_wrap
);
366 ret
= do_flush_locked(brw
);
368 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
369 fprintf(stderr
, "waiting for idle\n");
370 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
373 /* Start a new batch buffer. */
380 /* This is the only way buffers get added to the validate list.
383 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
384 drm_intel_bo
*buffer
,
385 uint32_t read_domains
, uint32_t write_domain
,
390 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
392 read_domains
, write_domain
);
397 * Using the old buffer offset, write in what the right data would be, in case
398 * the buffer doesn't move and we can short-circuit the relocation processing
401 intel_batchbuffer_emit_dword(brw
, buffer
->offset
+ delta
);
407 intel_batchbuffer_emit_reloc_fenced(struct brw_context
*brw
,
408 drm_intel_bo
*buffer
,
409 uint32_t read_domains
,
410 uint32_t write_domain
,
415 ret
= drm_intel_bo_emit_reloc_fence(brw
->batch
.bo
, 4*brw
->batch
.used
,
417 read_domains
, write_domain
);
422 * Using the old buffer offset, write in what the right data would
423 * be, in case the buffer doesn't move and we can short-circuit the
424 * relocation processing in the kernel
426 intel_batchbuffer_emit_dword(brw
, buffer
->offset
+ delta
);
432 intel_batchbuffer_data(struct brw_context
*brw
,
433 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
435 assert((bytes
& 3) == 0);
436 intel_batchbuffer_require_space(brw
, bytes
, ring
);
437 __memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
438 brw
->batch
.used
+= bytes
>> 2;
442 intel_batchbuffer_cached_advance(struct brw_context
*brw
)
444 struct cached_batch_item
**prev
= &brw
->batch
.cached_items
, *item
;
445 uint32_t sz
= (brw
->batch
.used
- brw
->batch
.emit
) * sizeof(uint32_t);
446 uint32_t *start
= brw
->batch
.map
+ brw
->batch
.emit
;
447 uint16_t op
= *start
>> 16;
453 old
= brw
->batch
.map
+ item
->header
;
454 if (op
== *old
>> 16) {
455 if (item
->size
== sz
&& memcmp(old
, start
, sz
) == 0) {
456 if (prev
!= &brw
->batch
.cached_items
) {
458 item
->next
= brw
->batch
.cached_items
;
459 brw
->batch
.cached_items
= item
;
461 brw
->batch
.used
= brw
->batch
.emit
;
462 assert(brw
->batch
.used
> 0);
471 item
= malloc(sizeof(struct cached_batch_item
));
475 item
->next
= brw
->batch
.cached_items
;
476 brw
->batch
.cached_items
= item
;
480 item
->header
= brw
->batch
.emit
;
484 * Restriction [DevSNB, DevIVB]:
486 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
487 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
488 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
489 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
490 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
491 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
492 * unless SW can otherwise guarantee that the pipeline from WM onwards is
493 * already flushed (e.g., via a preceding MI_FLUSH).
496 intel_emit_depth_stall_flushes(struct brw_context
*brw
)
498 assert(brw
->gen
>= 6 && brw
->gen
<= 7);
501 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
502 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
503 OUT_BATCH(0); /* address */
504 OUT_BATCH(0); /* write data */
508 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
509 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
510 OUT_BATCH(0); /* address */
511 OUT_BATCH(0); /* write data */
515 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
516 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
517 OUT_BATCH(0); /* address */
518 OUT_BATCH(0); /* write data */
523 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
524 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
525 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
526 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
527 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
528 * to be sent before any combination of VS associated 3DSTATE."
531 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
533 assert(brw
->gen
== 7);
536 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
537 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE
);
538 OUT_RELOC(brw
->batch
.workaround_bo
,
539 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
540 OUT_BATCH(0); /* write data */
546 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
549 gen7_emit_cs_stall_flush(struct brw_context
*brw
)
552 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
553 /* From p61 of the Ivy Bridge PRM (1.10.4 PIPE_CONTROL Command: DW1[20]
556 * One of the following must also be set:
557 * - Render Target Cache Flush Enable ([12] of DW1)
558 * - Depth Cache Flush Enable ([0] of DW1)
559 * - Stall at Pixel Scoreboard ([1] of DW1)
560 * - Depth Stall ([13] of DW1)
561 * - Post-Sync Operation ([13] of DW1)
563 * We choose to do a Post-Sync Operation (Write Immediate Data), since
564 * it seems like it will incur the least additional performance penalty.
566 OUT_BATCH(PIPE_CONTROL_CS_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE
);
567 OUT_RELOC(brw
->batch
.workaround_bo
,
568 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
575 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
576 * implementing two workarounds on gen6. From section 1.4.7.1
577 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
579 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
580 * produced by non-pipelined state commands), software needs to first
581 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
584 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
585 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
587 * And the workaround for these two requires this workaround first:
589 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
590 * BEFORE the pipe-control with a post-sync op and no write-cache
593 * And this last workaround is tricky because of the requirements on
594 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
597 * "1 of the following must also be set:
598 * - Render Target Cache Flush Enable ([12] of DW1)
599 * - Depth Cache Flush Enable ([0] of DW1)
600 * - Stall at Pixel Scoreboard ([1] of DW1)
601 * - Depth Stall ([13] of DW1)
602 * - Post-Sync Operation ([13] of DW1)
603 * - Notify Enable ([8] of DW1)"
605 * The cache flushes require the workaround flush that triggered this
606 * one, so we can't use it. Depth stall would trigger the same.
607 * Post-sync nonzero is what triggered this second workaround, so we
608 * can't use that one either. Notify enable is IRQs, which aren't
609 * really our business. That leaves only stall at scoreboard.
612 intel_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
614 if (!brw
->batch
.need_workaround_flush
)
618 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
619 OUT_BATCH(PIPE_CONTROL_CS_STALL
|
620 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
621 OUT_BATCH(0); /* address */
622 OUT_BATCH(0); /* write data */
626 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
627 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE
);
628 OUT_RELOC(brw
->batch
.workaround_bo
,
629 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
630 OUT_BATCH(0); /* write data */
633 brw
->batch
.need_workaround_flush
= false;
636 /* Emit a pipelined flush to either flush render and texture cache for
637 * reading from a FBO-drawn texture, or flush so that frontbuffer
638 * render appears on the screen in DRI1.
640 * This is also used for the always_flush_cache driconf debug option.
643 intel_batchbuffer_emit_mi_flush(struct brw_context
*brw
)
646 if (brw
->batch
.ring
== BLT_RING
) {
648 OUT_BATCH(MI_FLUSH_DW
);
655 /* Hardware workaround: SNB B-Spec says:
657 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
658 * Flush Enable =1, a PIPE_CONTROL with any non-zero
659 * post-sync-op is required.
661 intel_emit_post_sync_nonzero_flush(brw
);
665 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
666 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH
|
667 PIPE_CONTROL_WRITE_FLUSH
|
668 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
669 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
670 PIPE_CONTROL_TC_FLUSH
|
671 PIPE_CONTROL_NO_WRITE
|
672 PIPE_CONTROL_CS_STALL
);
673 OUT_BATCH(0); /* write address */
674 OUT_BATCH(0); /* write data */
679 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2) |
680 PIPE_CONTROL_WRITE_FLUSH
|
681 PIPE_CONTROL_NO_WRITE
);
682 OUT_BATCH(0); /* write address */
683 OUT_BATCH(0); /* write data */
684 OUT_BATCH(0); /* write data */