1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "intel_fbo.h"
34 #include "brw_context.h"
37 intel_batchbuffer_reset(struct brw_context
*brw
);
40 intel_batchbuffer_init(struct brw_context
*brw
)
42 intel_batchbuffer_reset(brw
);
45 /* We can't just use brw_state_batch to get a chunk of space for
46 * the gen6 workaround because it involves actually writing to
47 * the buffer, and the kernel doesn't let us write to the batch.
49 brw
->batch
.workaround_bo
= drm_intel_bo_alloc(brw
->bufmgr
,
50 "pipe_control workaround",
55 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
56 brw
->batch
.map
= brw
->batch
.cpu_map
;
61 intel_batchbuffer_reset(struct brw_context
*brw
)
63 if (brw
->batch
.last_bo
!= NULL
) {
64 drm_intel_bo_unreference(brw
->batch
.last_bo
);
65 brw
->batch
.last_bo
= NULL
;
67 brw
->batch
.last_bo
= brw
->batch
.bo
;
69 brw_render_cache_set_clear(brw
);
71 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
74 drm_intel_bo_map(brw
->batch
.bo
, true);
75 brw
->batch
.map
= brw
->batch
.bo
->virtual;
78 brw
->batch
.reserved_space
= BATCH_RESERVED
;
79 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
81 brw
->batch
.needs_sol_reset
= false;
82 brw
->batch
.pipe_controls_since_last_cs_stall
= 0;
84 /* We don't know what ring the new batch will be sent to until we see the
85 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
87 brw
->batch
.ring
= UNKNOWN_RING
;
91 intel_batchbuffer_save_state(struct brw_context
*brw
)
93 brw
->batch
.saved
.used
= brw
->batch
.used
;
94 brw
->batch
.saved
.reloc_count
=
95 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
99 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
101 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
103 brw
->batch
.used
= brw
->batch
.saved
.used
;
104 if (brw
->batch
.used
== 0)
105 brw
->batch
.ring
= UNKNOWN_RING
;
109 intel_batchbuffer_free(struct brw_context
*brw
)
111 free(brw
->batch
.cpu_map
);
112 drm_intel_bo_unreference(brw
->batch
.last_bo
);
113 drm_intel_bo_unreference(brw
->batch
.bo
);
114 drm_intel_bo_unreference(brw
->batch
.workaround_bo
);
118 do_batch_dump(struct brw_context
*brw
)
120 struct drm_intel_decode
*decode
;
121 struct intel_batchbuffer
*batch
= &brw
->batch
;
124 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
128 ret
= drm_intel_bo_map(batch
->bo
, false);
130 drm_intel_decode_set_batch_pointer(decode
,
136 "WARNING: failed to map batchbuffer (%s), "
137 "dumping uploaded data instead.\n", strerror(ret
));
139 drm_intel_decode_set_batch_pointer(decode
,
145 drm_intel_decode_set_output_file(decode
, stderr
);
146 drm_intel_decode(decode
);
148 drm_intel_decode_context_free(decode
);
151 drm_intel_bo_unmap(batch
->bo
);
153 brw_debug_batch(brw
);
158 intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
)
160 /* We may need to enable and snapshot OA counters. */
161 brw_perf_monitor_new_batch(brw
);
165 * Called when starting a new batch buffer.
168 brw_new_batch(struct brw_context
*brw
)
170 /* Create a new batchbuffer and reset the associated state: */
171 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, 0);
172 intel_batchbuffer_reset(brw
);
174 /* If the kernel supports hardware contexts, then most hardware state is
175 * preserved between batches; we only need to re-emit state that is required
176 * to be in every batch. Otherwise we need to re-emit all the state that
177 * would otherwise be stored in the context (which for all intents and
178 * purposes means everything).
180 if (brw
->hw_ctx
== NULL
)
181 brw
->state
.dirty
.brw
|= BRW_NEW_CONTEXT
;
183 brw
->state
.dirty
.brw
|= BRW_NEW_BATCH
;
185 brw
->state_batch_count
= 0;
189 /* We need to periodically reap the shader time results, because rollover
190 * happens every few seconds. We also want to see results every once in a
191 * while, because many programs won't cleanly destroy our context, so the
192 * end-of-run printout may not happen.
194 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
195 brw_collect_and_report_shader_time(brw
);
197 if (INTEL_DEBUG
& DEBUG_PERFMON
)
198 brw_dump_perf_monitors(brw
);
202 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
205 * This function can emit state (say, to preserve registers that aren't saved
206 * between batches). All of this state MUST fit in the reserved space at the
207 * end of the batchbuffer. If you add more GPU state, increase the reserved
208 * space by updating the BATCH_RESERVED macro.
211 brw_finish_batch(struct brw_context
*brw
)
213 /* Capture the closing pipeline statistics register values necessary to
214 * support query objects (in the non-hardware context world).
216 brw_emit_query_end(brw
);
218 /* We may also need to snapshot and disable OA counters. */
219 if (brw
->batch
.ring
== RENDER_RING
)
220 brw_perf_monitor_finish_batch(brw
);
222 /* Mark that the current program cache BO has been used by the GPU.
223 * It will be reallocated if we need to put new programs in for the
226 brw
->cache
.bo_used_by_gpu
= true;
229 /* TODO: Push this whole function into bufmgr.
232 do_flush_locked(struct brw_context
*brw
)
234 struct intel_batchbuffer
*batch
= &brw
->batch
;
238 drm_intel_bo_unmap(batch
->bo
);
240 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
241 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
242 ret
= drm_intel_bo_subdata(batch
->bo
,
243 batch
->state_batch_offset
,
244 batch
->bo
->size
- batch
->state_batch_offset
,
245 (char *)batch
->map
+ batch
->state_batch_offset
);
249 if (!brw
->intelScreen
->no_hw
) {
252 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
253 flags
= I915_EXEC_BLT
;
255 flags
= I915_EXEC_RENDER
;
257 if (batch
->needs_sol_reset
)
258 flags
|= I915_EXEC_GEN7_SOL_RESET
;
261 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
262 brw_annotate_aub(brw
);
263 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
264 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
267 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
268 4 * batch
->used
, flags
);
273 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
277 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
285 _intel_batchbuffer_flush(struct brw_context
*brw
,
286 const char *file
, int line
)
290 if (brw
->batch
.used
== 0)
293 if (brw
->throttle_batch
[0] == NULL
) {
294 brw
->throttle_batch
[0] = brw
->batch
.bo
;
295 drm_intel_bo_reference(brw
->throttle_batch
[0]);
298 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
299 int bytes_for_commands
= 4 * brw
->batch
.used
;
300 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
301 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
302 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
303 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
304 bytes_for_commands
, bytes_for_state
,
306 100.0f
* total_bytes
/ BATCH_SZ
);
309 brw
->batch
.reserved_space
= 0;
311 brw_finish_batch(brw
);
313 /* Mark the end of the buffer. */
314 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
315 if (brw
->batch
.used
& 1) {
316 /* Round batchbuffer usage to 2 DWORDs. */
317 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
320 intel_upload_finish(brw
);
322 /* Check that we didn't just wrap our batchbuffer at a bad time. */
323 assert(!brw
->no_batch_wrap
);
325 ret
= do_flush_locked(brw
);
327 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
328 fprintf(stderr
, "waiting for idle\n");
329 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
332 /* Start a new batch buffer. */
339 /* This is the only way buffers get added to the validate list.
342 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
343 drm_intel_bo
*buffer
,
344 uint32_t read_domains
, uint32_t write_domain
,
349 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
351 read_domains
, write_domain
);
355 /* Using the old buffer offset, write in what the right data would be, in
356 * case the buffer doesn't move and we can short-circuit the relocation
357 * processing in the kernel
359 intel_batchbuffer_emit_dword(brw
, buffer
->offset64
+ delta
);
365 intel_batchbuffer_emit_reloc64(struct brw_context
*brw
,
366 drm_intel_bo
*buffer
,
367 uint32_t read_domains
, uint32_t write_domain
,
370 int ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
372 read_domains
, write_domain
);
376 /* Using the old buffer offset, write in what the right data would be, in
377 * case the buffer doesn't move and we can short-circuit the relocation
378 * processing in the kernel
380 uint64_t offset
= buffer
->offset64
+ delta
;
381 intel_batchbuffer_emit_dword(brw
, offset
);
382 intel_batchbuffer_emit_dword(brw
, offset
>> 32);
389 intel_batchbuffer_data(struct brw_context
*brw
,
390 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
392 assert((bytes
& 3) == 0);
393 intel_batchbuffer_require_space(brw
, bytes
, ring
);
394 memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
395 brw
->batch
.used
+= bytes
>> 2;
399 * According to the latest documentation, any PIPE_CONTROL with the
400 * "Command Streamer Stall" bit set must also have another bit set,
401 * with five different options:
403 * - Render Target Cache Flush
404 * - Depth Cache Flush
405 * - Stall at Pixel Scoreboard
406 * - Post-Sync Operation
409 * I chose "Stall at Pixel Scoreboard" since we've used it effectively
410 * in the past, but the choice is fairly arbitrary.
413 gen8_add_cs_stall_workaround_bits(uint32_t *flags
)
415 uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
416 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
417 PIPE_CONTROL_WRITE_IMMEDIATE
|
418 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
419 PIPE_CONTROL_WRITE_TIMESTAMP
|
420 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
421 PIPE_CONTROL_DEPTH_STALL
;
423 /* If we're doing a CS stall, and don't already have one of the
424 * workaround bits set, add "Stall at Pixel Scoreboard."
426 if ((*flags
& PIPE_CONTROL_CS_STALL
) != 0 && (*flags
& wa_bits
) == 0)
427 *flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
430 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
432 * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
433 * only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
435 * Note that the kernel does CS stalls between batches, so we only need
436 * to count them within a batch.
439 gen7_cs_stall_every_four_pipe_controls(struct brw_context
*brw
, uint32_t flags
)
441 if (brw
->gen
== 7 && !brw
->is_haswell
) {
442 if (flags
& PIPE_CONTROL_CS_STALL
) {
443 /* If we're doing a CS stall, reset the counter and carry on. */
444 brw
->batch
.pipe_controls_since_last_cs_stall
= 0;
448 /* If this is the fourth pipe control without a CS stall, do one now. */
449 if (++brw
->batch
.pipe_controls_since_last_cs_stall
== 4) {
450 brw
->batch
.pipe_controls_since_last_cs_stall
= 0;
451 return PIPE_CONTROL_CS_STALL
;
458 * Emit a PIPE_CONTROL with various flushing flags.
460 * The caller is responsible for deciding what flags are appropriate for the
464 brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
)
467 gen8_add_cs_stall_workaround_bits(&flags
);
470 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
477 } else if (brw
->gen
>= 6) {
478 flags
|= gen7_cs_stall_every_four_pipe_controls(brw
, flags
);
481 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
489 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
498 * Emit a PIPE_CONTROL that writes to a buffer object.
500 * \p flags should contain one of the following items:
501 * - PIPE_CONTROL_WRITE_IMMEDIATE
502 * - PIPE_CONTROL_WRITE_TIMESTAMP
503 * - PIPE_CONTROL_WRITE_DEPTH_COUNT
506 brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
507 drm_intel_bo
*bo
, uint32_t offset
,
508 uint32_t imm_lower
, uint32_t imm_upper
)
511 gen8_add_cs_stall_workaround_bits(&flags
);
514 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
516 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
518 OUT_BATCH(imm_lower
);
519 OUT_BATCH(imm_upper
);
521 } else if (brw
->gen
>= 6) {
522 flags
|= gen7_cs_stall_every_four_pipe_controls(brw
, flags
);
524 /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
525 * on later platforms. We always use PPGTT on Gen7+.
527 unsigned gen6_gtt
= brw
->gen
== 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE
: 0;
530 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
532 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
534 OUT_BATCH(imm_lower
);
535 OUT_BATCH(imm_upper
);
539 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
540 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
541 PIPE_CONTROL_GLOBAL_GTT_WRITE
| offset
);
542 OUT_BATCH(imm_lower
);
543 OUT_BATCH(imm_upper
);
549 * Restriction [DevSNB, DevIVB]:
551 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
552 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
553 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
554 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
555 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
556 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
557 * unless SW can otherwise guarantee that the pipeline from WM onwards is
558 * already flushed (e.g., via a preceding MI_FLUSH).
561 intel_emit_depth_stall_flushes(struct brw_context
*brw
)
563 assert(brw
->gen
>= 6 && brw
->gen
<= 9);
565 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
566 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
567 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
571 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
572 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
573 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
574 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
575 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
576 * to be sent before any combination of VS associated 3DSTATE."
579 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
581 assert(brw
->gen
== 7);
582 brw_emit_pipe_control_write(brw
,
583 PIPE_CONTROL_WRITE_IMMEDIATE
584 | PIPE_CONTROL_DEPTH_STALL
,
585 brw
->batch
.workaround_bo
, 0,
591 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
594 gen7_emit_cs_stall_flush(struct brw_context
*brw
)
596 brw_emit_pipe_control_write(brw
,
597 PIPE_CONTROL_CS_STALL
598 | PIPE_CONTROL_WRITE_IMMEDIATE
,
599 brw
->batch
.workaround_bo
, 0,
605 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
606 * implementing two workarounds on gen6. From section 1.4.7.1
607 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
609 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
610 * produced by non-pipelined state commands), software needs to first
611 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
614 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
615 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
617 * And the workaround for these two requires this workaround first:
619 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
620 * BEFORE the pipe-control with a post-sync op and no write-cache
623 * And this last workaround is tricky because of the requirements on
624 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
627 * "1 of the following must also be set:
628 * - Render Target Cache Flush Enable ([12] of DW1)
629 * - Depth Cache Flush Enable ([0] of DW1)
630 * - Stall at Pixel Scoreboard ([1] of DW1)
631 * - Depth Stall ([13] of DW1)
632 * - Post-Sync Operation ([13] of DW1)
633 * - Notify Enable ([8] of DW1)"
635 * The cache flushes require the workaround flush that triggered this
636 * one, so we can't use it. Depth stall would trigger the same.
637 * Post-sync nonzero is what triggered this second workaround, so we
638 * can't use that one either. Notify enable is IRQs, which aren't
639 * really our business. That leaves only stall at scoreboard.
642 intel_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
644 brw_emit_pipe_control_flush(brw
,
645 PIPE_CONTROL_CS_STALL
|
646 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
648 brw_emit_pipe_control_write(brw
, PIPE_CONTROL_WRITE_IMMEDIATE
,
649 brw
->batch
.workaround_bo
, 0, 0, 0);
652 /* Emit a pipelined flush to either flush render and texture cache for
653 * reading from a FBO-drawn texture, or flush so that frontbuffer
654 * render appears on the screen in DRI1.
656 * This is also used for the always_flush_cache driconf debug option.
659 intel_batchbuffer_emit_mi_flush(struct brw_context
*brw
)
661 if (brw
->batch
.ring
== BLT_RING
&& brw
->gen
>= 6) {
663 OUT_BATCH(MI_FLUSH_DW
);
669 int flags
= PIPE_CONTROL_NO_WRITE
| PIPE_CONTROL_RENDER_TARGET_FLUSH
;
672 /* Hardware workaround: SKL
674 * Emit Pipe Control with all bits set to zero before emitting
675 * a Pipe Control with VF Cache Invalidate set.
677 brw_emit_pipe_control_flush(brw
, 0);
680 flags
|= PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
681 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
682 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
683 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
684 PIPE_CONTROL_CS_STALL
;
687 /* Hardware workaround: SNB B-Spec says:
689 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
690 * Flush Enable =1, a PIPE_CONTROL with any non-zero
691 * post-sync-op is required.
693 intel_emit_post_sync_nonzero_flush(brw
);
696 brw_emit_pipe_control_flush(brw
, flags
);
699 brw_render_cache_set_clear(brw
);
703 brw_load_register_mem(struct brw_context
*brw
,
706 uint32_t read_domains
, uint32_t write_domain
,
709 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
710 assert(brw
->gen
>= 7);
714 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
716 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
);
720 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
722 OUT_RELOC(bo
, read_domains
, write_domain
, offset
);