2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
35 #include "common/gen_gem.h"
37 #include "util/hash_table.h"
40 #include "drm-uapi/i915_drm.h"
42 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
45 * Target sizes of the batch and state buffers. We create the initial
46 * buffers at these sizes, and flush when they're nearly full. If we
47 * underestimate how close we are to the end, and suddenly need more space
48 * in the middle of a draw, we can grow the buffers, and finish the draw.
49 * At that point, we'll be over our target size, so the next operation
50 * should flush. Each time we flush the batch, we recreate both buffers
51 * at the original target size, so it doesn't grow without bound.
53 #define BATCH_SZ (20 * 1024)
54 #define STATE_SZ (16 * 1024)
57 intel_batchbuffer_reset(struct brw_context
*brw
);
59 brw_new_batch(struct brw_context
*brw
);
62 dump_validation_list(struct intel_batchbuffer
*batch
)
64 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
66 for (int i
= 0; i
< batch
->exec_count
; i
++) {
67 uint64_t flags
= batch
->validation_list
[i
].flags
;
68 assert(batch
->validation_list
[i
].handle
==
69 batch
->exec_bos
[i
]->gem_handle
);
70 fprintf(stderr
, "[%2d]: %2d %-14s %p %s%-7s @ 0x%016llx%s (%"PRIu64
"B)\n",
72 batch
->validation_list
[i
].handle
,
73 batch
->exec_bos
[i
]->name
,
75 (flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) ? "(48b" : "(32b",
76 (flags
& EXEC_OBJECT_WRITE
) ? " write)" : ")",
77 batch
->validation_list
[i
].offset
,
78 (flags
& EXEC_OBJECT_PINNED
) ? " (pinned)" : "",
79 batch
->exec_bos
[i
]->size
);
83 static struct gen_batch_decode_bo
84 decode_get_bo(void *v_brw
, bool ppgtt
, uint64_t address
)
86 struct brw_context
*brw
= v_brw
;
87 struct intel_batchbuffer
*batch
= &brw
->batch
;
89 for (int i
= 0; i
< batch
->exec_count
; i
++) {
90 struct brw_bo
*bo
= batch
->exec_bos
[i
];
91 /* The decoder zeroes out the top 16 bits, so we need to as well */
92 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
94 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
95 return (struct gen_batch_decode_bo
) {
98 .map
= brw_bo_map(brw
, bo
, MAP_READ
) + (address
- bo_address
),
103 return (struct gen_batch_decode_bo
) { };
107 decode_get_state_size(void *v_brw
, uint64_t address
, uint64_t base_address
)
109 struct brw_context
*brw
= v_brw
;
110 struct intel_batchbuffer
*batch
= &brw
->batch
;
111 unsigned size
= (uintptr_t)
112 _mesa_hash_table_u64_search(batch
->state_batch_sizes
,
113 address
- base_address
);
118 init_reloc_list(struct brw_reloc_list
*rlist
, int count
)
120 rlist
->reloc_count
= 0;
121 rlist
->reloc_array_size
= count
;
122 rlist
->relocs
= malloc(rlist
->reloc_array_size
*
123 sizeof(struct drm_i915_gem_relocation_entry
));
127 intel_batchbuffer_init(struct brw_context
*brw
)
129 struct intel_screen
*screen
= brw
->screen
;
130 struct intel_batchbuffer
*batch
= &brw
->batch
;
131 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
133 batch
->use_shadow_copy
= !devinfo
->has_llc
;
135 init_reloc_list(&batch
->batch_relocs
, 250);
136 init_reloc_list(&batch
->state_relocs
, 250);
138 batch
->batch
.map
= NULL
;
139 batch
->state
.map
= NULL
;
140 batch
->exec_count
= 0;
141 batch
->exec_array_size
= 100;
143 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
144 batch
->validation_list
=
145 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
147 if (INTEL_DEBUG
& DEBUG_BATCH
) {
148 batch
->state_batch_sizes
=
149 _mesa_hash_table_u64_create(NULL
);
151 const unsigned decode_flags
=
152 GEN_BATCH_DECODE_FULL
|
153 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
154 GEN_BATCH_DECODE_OFFSETS
|
155 GEN_BATCH_DECODE_FLOATS
;
157 gen_batch_decode_ctx_init(&batch
->decoder
, devinfo
, stderr
,
158 decode_flags
, NULL
, decode_get_bo
,
159 decode_get_state_size
, brw
);
160 batch
->decoder
.max_vbo_decoded_lines
= 100;
163 batch
->use_batch_first
=
164 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
166 /* PIPE_CONTROL needs a w/a but only on gen6 */
167 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
168 if (devinfo
->gen
== 6)
169 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
171 intel_batchbuffer_reset(brw
);
174 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
177 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
179 assert(bo
->bufmgr
== batch
->batch
.bo
->bufmgr
);
181 unsigned index
= READ_ONCE(bo
->index
);
183 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
186 /* May have been shared between multiple active batches */
187 for (index
= 0; index
< batch
->exec_count
; index
++) {
188 if (batch
->exec_bos
[index
] == bo
)
192 brw_bo_reference(bo
);
194 if (batch
->exec_count
== batch
->exec_array_size
) {
195 batch
->exec_array_size
*= 2;
197 realloc(batch
->exec_bos
,
198 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
199 batch
->validation_list
=
200 realloc(batch
->validation_list
,
201 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
204 batch
->validation_list
[batch
->exec_count
] =
205 (struct drm_i915_gem_exec_object2
) {
206 .handle
= bo
->gem_handle
,
207 .offset
= bo
->gtt_offset
,
211 bo
->index
= batch
->exec_count
;
212 batch
->exec_bos
[batch
->exec_count
] = bo
;
213 batch
->aperture_space
+= bo
->size
;
215 return batch
->exec_count
++;
219 recreate_growing_buffer(struct brw_context
*brw
,
220 struct brw_growing_bo
*grow
,
221 const char *name
, unsigned size
,
222 enum brw_memory_zone memzone
)
224 struct intel_screen
*screen
= brw
->screen
;
225 struct intel_batchbuffer
*batch
= &brw
->batch
;
226 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
228 /* We can't grow buffers when using softpin, so just overallocate them. */
229 if (brw_using_softpin(bufmgr
))
232 grow
->bo
= brw_bo_alloc(bufmgr
, name
, size
, memzone
);
233 grow
->bo
->kflags
|= can_do_exec_capture(screen
) ? EXEC_OBJECT_CAPTURE
: 0;
234 grow
->partial_bo
= NULL
;
235 grow
->partial_bo_map
= NULL
;
236 grow
->partial_bytes
= 0;
237 grow
->memzone
= memzone
;
239 if (batch
->use_shadow_copy
)
240 grow
->map
= realloc(grow
->map
, grow
->bo
->size
);
242 grow
->map
= brw_bo_map(brw
, grow
->bo
, MAP_READ
| MAP_WRITE
);
246 intel_batchbuffer_reset(struct brw_context
*brw
)
248 struct intel_batchbuffer
*batch
= &brw
->batch
;
250 if (batch
->last_bo
!= NULL
) {
251 brw_bo_unreference(batch
->last_bo
);
252 batch
->last_bo
= NULL
;
254 batch
->last_bo
= batch
->batch
.bo
;
256 recreate_growing_buffer(brw
, &batch
->batch
, "batchbuffer", BATCH_SZ
,
258 batch
->map_next
= batch
->batch
.map
;
260 recreate_growing_buffer(brw
, &batch
->state
, "statebuffer", STATE_SZ
,
261 BRW_MEMZONE_DYNAMIC
);
263 /* Avoid making 0 a valid state offset - otherwise the decoder will try
264 * and decode data when we use offset 0 as a null pointer.
266 batch
->state_used
= 1;
268 add_exec_bo(batch
, batch
->batch
.bo
);
269 assert(batch
->batch
.bo
->index
== 0);
271 batch
->needs_sol_reset
= false;
272 batch
->state_base_address_emitted
= false;
274 if (batch
->state_batch_sizes
)
275 _mesa_hash_table_u64_clear(batch
->state_batch_sizes
, NULL
);
279 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
281 intel_batchbuffer_reset(brw
);
282 brw_cache_sets_clear(brw
);
286 intel_batchbuffer_save_state(struct brw_context
*brw
)
288 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
289 brw
->batch
.saved
.batch_reloc_count
= brw
->batch
.batch_relocs
.reloc_count
;
290 brw
->batch
.saved
.state_reloc_count
= brw
->batch
.state_relocs
.reloc_count
;
291 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
295 intel_batchbuffer_saved_state_is_empty(struct brw_context
*brw
)
297 struct intel_batchbuffer
*batch
= &brw
->batch
;
298 return (batch
->saved
.map_next
== batch
->batch
.map
);
302 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
304 for (int i
= brw
->batch
.saved
.exec_count
;
305 i
< brw
->batch
.exec_count
; i
++) {
306 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
308 brw
->batch
.batch_relocs
.reloc_count
= brw
->batch
.saved
.batch_reloc_count
;
309 brw
->batch
.state_relocs
.reloc_count
= brw
->batch
.saved
.state_reloc_count
;
310 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
312 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
313 if (USED_BATCH(brw
->batch
) == 0)
318 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
320 if (batch
->use_shadow_copy
) {
321 free(batch
->batch
.map
);
322 free(batch
->state
.map
);
325 for (int i
= 0; i
< batch
->exec_count
; i
++) {
326 brw_bo_unreference(batch
->exec_bos
[i
]);
328 free(batch
->batch_relocs
.relocs
);
329 free(batch
->state_relocs
.relocs
);
330 free(batch
->exec_bos
);
331 free(batch
->validation_list
);
333 brw_bo_unreference(batch
->last_bo
);
334 brw_bo_unreference(batch
->batch
.bo
);
335 brw_bo_unreference(batch
->state
.bo
);
336 if (batch
->state_batch_sizes
) {
337 _mesa_hash_table_u64_destroy(batch
->state_batch_sizes
, NULL
);
338 gen_batch_decode_ctx_finish(&batch
->decoder
);
343 * Finish copying the old batch/state buffer's contents to the new one
344 * after we tried to "grow" the buffer in an earlier operation.
347 finish_growing_bos(struct brw_growing_bo
*grow
)
349 struct brw_bo
*old_bo
= grow
->partial_bo
;
353 memcpy(grow
->map
, grow
->partial_bo_map
, grow
->partial_bytes
);
355 grow
->partial_bo
= NULL
;
356 grow
->partial_bo_map
= NULL
;
357 grow
->partial_bytes
= 0;
359 brw_bo_unreference(old_bo
);
363 replace_bo_in_reloc_list(struct brw_reloc_list
*rlist
,
364 uint32_t old_handle
, uint32_t new_handle
)
366 for (int i
= 0; i
< rlist
->reloc_count
; i
++) {
367 if (rlist
->relocs
[i
].target_handle
== old_handle
)
368 rlist
->relocs
[i
].target_handle
= new_handle
;
373 * Grow either the batch or state buffer to a new larger size.
375 * We can't actually grow buffers, so we allocate a new one, copy over
376 * the existing contents, and update our lists to refer to the new one.
378 * Note that this is only temporary - each new batch recreates the buffers
379 * at their original target size (BATCH_SZ or STATE_SZ).
382 grow_buffer(struct brw_context
*brw
,
383 struct brw_growing_bo
*grow
,
384 unsigned existing_bytes
,
387 struct intel_batchbuffer
*batch
= &brw
->batch
;
388 struct brw_bufmgr
*bufmgr
= brw
->bufmgr
;
389 struct brw_bo
*bo
= grow
->bo
;
391 /* We can't grow buffers that are softpinned, as the growing mechanism
392 * involves putting a larger buffer at the same gtt_offset...and we've
393 * only allocated the smaller amount of VMA. Without relocations, this
394 * simply won't work. This should never happen, however.
396 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
398 perf_debug("Growing %s - ran out of space\n", bo
->name
);
400 if (grow
->partial_bo
) {
401 /* We've already grown once, and now we need to do it again.
402 * Finish our last grow operation so we can start a new one.
403 * This should basically never happen.
405 perf_debug("Had to grow multiple times");
406 finish_growing_bos(grow
);
409 struct brw_bo
*new_bo
=
410 brw_bo_alloc(bufmgr
, bo
->name
, new_size
, grow
->memzone
);
412 /* Copy existing data to the new larger buffer */
413 grow
->partial_bo_map
= grow
->map
;
415 if (batch
->use_shadow_copy
) {
416 /* We can't safely use realloc, as it may move the existing buffer,
417 * breaking existing pointers the caller may still be using. Just
418 * malloc a new copy and memcpy it like the normal BO path.
420 * Use bo->size rather than new_size because the bufmgr may have
421 * rounded up the size, and we want the shadow size to match.
423 grow
->map
= malloc(new_bo
->size
);
425 grow
->map
= brw_bo_map(brw
, new_bo
, MAP_READ
| MAP_WRITE
);
428 /* Try to put the new BO at the same GTT offset as the old BO (which
429 * we're throwing away, so it doesn't need to be there).
431 * This guarantees that our relocations continue to work: values we've
432 * already written into the buffer, values we're going to write into the
433 * buffer, and the validation/relocation lists all will match.
435 * Also preserve kflags for EXEC_OBJECT_CAPTURE.
437 new_bo
->gtt_offset
= bo
->gtt_offset
;
438 new_bo
->index
= bo
->index
;
439 new_bo
->kflags
= bo
->kflags
;
441 /* Batch/state buffers are per-context, and if we've run out of space,
442 * we must have actually used them before, so...they will be in the list.
444 assert(bo
->index
< batch
->exec_count
);
445 assert(batch
->exec_bos
[bo
->index
] == bo
);
447 /* Update the validation list to use the new BO. */
448 batch
->validation_list
[bo
->index
].handle
= new_bo
->gem_handle
;
450 if (!batch
->use_batch_first
) {
451 /* We're not using I915_EXEC_HANDLE_LUT, which means we need to go
452 * update the relocation list entries to point at the new BO as well.
453 * (With newer kernels, the "handle" is an offset into the validation
454 * list, which remains unchanged, so we can skip this.)
456 replace_bo_in_reloc_list(&batch
->batch_relocs
,
457 bo
->gem_handle
, new_bo
->gem_handle
);
458 replace_bo_in_reloc_list(&batch
->state_relocs
,
459 bo
->gem_handle
, new_bo
->gem_handle
);
462 /* Exchange the two BOs...without breaking pointers to the old BO.
464 * Consider this scenario:
466 * 1. Somebody calls brw_state_batch() to get a region of memory, and
467 * and then creates a brw_address pointing to brw->batch.state.bo.
468 * 2. They then call brw_state_batch() a second time, which happens to
469 * grow and replace the state buffer. They then try to emit a
470 * relocation to their first section of memory.
472 * If we replace the brw->batch.state.bo pointer at step 2, we would
473 * break the address created in step 1. They'd have a pointer to the
474 * old destroyed BO. Emitting a relocation would add this dead BO to
475 * the validation list...causing /both/ statebuffers to be in the list,
476 * and all kinds of disasters.
478 * This is not a contrived case - BLORP vertex data upload hits this.
480 * There are worse scenarios too. Fences for GL sync objects reference
481 * brw->batch.batch.bo. If we replaced the batch pointer when growing,
482 * we'd need to chase down every fence and update it to point to the
483 * new BO. Otherwise, it would refer to a "batch" that never actually
484 * gets submitted, and would fail to trigger.
486 * To work around both of these issues, we transmutate the buffers in
487 * place, making the existing struct brw_bo represent the new buffer,
488 * and "new_bo" represent the old BO. This is highly unusual, but it
489 * seems like a necessary evil.
491 * We also defer the memcpy of the existing batch's contents. Callers
492 * may make multiple brw_state_batch calls, and retain pointers to the
493 * old BO's map. We'll perform the memcpy in finish_growing_bo() when
494 * we finally submit the batch, at which point we've finished uploading
495 * state, and nobody should have any old references anymore.
497 * To do that, we keep a reference to the old BO in grow->partial_bo,
498 * and store the number of bytes to copy in grow->partial_bytes. We
499 * can monkey with the refcounts directly without atomics because these
500 * are per-context BOs and they can only be touched by this thread.
502 assert(new_bo
->refcount
== 1);
503 new_bo
->refcount
= bo
->refcount
;
507 memcpy(&tmp
, bo
, sizeof(struct brw_bo
));
508 memcpy(bo
, new_bo
, sizeof(struct brw_bo
));
509 memcpy(new_bo
, &tmp
, sizeof(struct brw_bo
));
511 grow
->partial_bo
= new_bo
; /* the one reference of the OLD bo */
512 grow
->partial_bytes
= existing_bytes
;
516 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
)
518 struct intel_batchbuffer
*batch
= &brw
->batch
;
520 const unsigned batch_used
= USED_BATCH(*batch
) * 4;
521 if (batch_used
+ sz
>= BATCH_SZ
&& !batch
->no_wrap
) {
522 intel_batchbuffer_flush(brw
);
523 } else if (batch_used
+ sz
>= batch
->batch
.bo
->size
) {
524 const unsigned new_size
=
525 MIN2(batch
->batch
.bo
->size
+ batch
->batch
.bo
->size
/ 2,
527 grow_buffer(brw
, &batch
->batch
, batch_used
, new_size
);
528 batch
->map_next
= (void *) batch
->batch
.map
+ batch_used
;
529 assert(batch_used
+ sz
< batch
->batch
.bo
->size
);
534 * Called when starting a new batch buffer.
537 brw_new_batch(struct brw_context
*brw
)
539 /* Unreference any BOs held by the previous batch, and reset counts. */
540 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
541 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
542 brw
->batch
.exec_bos
[i
] = NULL
;
544 brw
->batch
.batch_relocs
.reloc_count
= 0;
545 brw
->batch
.state_relocs
.reloc_count
= 0;
546 brw
->batch
.exec_count
= 0;
547 brw
->batch
.aperture_space
= 0;
549 brw_bo_unreference(brw
->batch
.state
.bo
);
551 /* Create a new batchbuffer and reset the associated state: */
552 intel_batchbuffer_reset_and_clear_render_cache(brw
);
554 /* If the kernel supports hardware contexts, then most hardware state is
555 * preserved between batches; we only need to re-emit state that is required
556 * to be in every batch. Otherwise we need to re-emit all the state that
557 * would otherwise be stored in the context (which for all intents and
558 * purposes means everything).
560 if (brw
->hw_ctx
== 0) {
561 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
562 brw_upload_invariant_state(brw
);
565 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
567 brw
->ib
.index_size
= -1;
569 /* We need to periodically reap the shader time results, because rollover
570 * happens every few seconds. We also want to see results every once in a
571 * while, because many programs won't cleanly destroy our context, so the
572 * end-of-run printout may not happen.
574 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
575 brw_collect_and_report_shader_time(brw
);
579 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
582 * This function can emit state (say, to preserve registers that aren't saved
586 brw_finish_batch(struct brw_context
*brw
)
588 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
590 brw
->batch
.no_wrap
= true;
592 /* Capture the closing pipeline statistics register values necessary to
593 * support query objects (in the non-hardware context world).
595 brw_emit_query_end(brw
);
597 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
598 * assume that the L3 cache is configured according to the hardware
599 * defaults. On Kernel 4.16+, we no longer need to do this.
601 if (devinfo
->gen
>= 7 &&
602 !(brw
->screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
))
603 gen7_restore_default_l3_config(brw
);
605 if (devinfo
->is_haswell
) {
606 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
607 * 3DSTATE_CC_STATE_POINTERS > "Note":
609 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
610 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
612 * From the example in the docs, it seems to expect a regular pipe control
613 * flush here as well. We may have done it already, but meh.
615 * See also WaAvoidRCZCounterRollover.
617 brw_emit_mi_flush(brw
);
619 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
620 OUT_BATCH(brw
->cc
.state_offset
| 1);
622 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
623 PIPE_CONTROL_CS_STALL
);
626 /* Do not restore push constant packets during context restore. */
627 if (devinfo
->gen
>= 7)
628 gen10_emit_isp_disable(brw
);
630 /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
631 * requires our batch size to be QWord aligned, so we pad it out if
632 * necessary by emitting an extra MI_NOOP after the end.
634 intel_batchbuffer_require_space(brw
, 8);
635 *brw
->batch
.map_next
++ = MI_BATCH_BUFFER_END
;
636 if (USED_BATCH(brw
->batch
) & 1) {
637 *brw
->batch
.map_next
++ = MI_NOOP
;
640 brw
->batch
.no_wrap
= false;
644 throttle(struct brw_context
*brw
)
646 /* Wait for the swapbuffers before the one we just emitted, so we
647 * don't get too many swaps outstanding for apps that are GPU-heavy
650 * We're using intelDRI2Flush (called from the loader before
651 * swapbuffer) and glFlush (for front buffer rendering) as the
652 * indicator that a frame is done and then throttle when we get
653 * here as we prepare to render the next frame. At this point for
654 * round trips for swap/copy and getting new buffers are done and
655 * we'll spend less time waiting on the GPU.
657 * Unfortunately, we don't have a handle to the batch containing
658 * the swap, and getting our hands on that doesn't seem worth it,
659 * so we just use the first batch we emitted after the last swap.
661 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
662 if (brw
->throttle_batch
[1]) {
663 if (!brw
->disable_throttling
) {
664 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
666 brw_bo_unreference(brw
->throttle_batch
[1]);
668 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
669 brw
->throttle_batch
[0] = NULL
;
670 brw
->need_swap_throttle
= false;
671 /* Throttling here is more precise than the throttle ioctl, so skip it */
672 brw
->need_flush_throttle
= false;
675 if (brw
->need_flush_throttle
) {
676 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
677 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
678 brw
->need_flush_throttle
= false;
684 struct intel_batchbuffer
*batch
,
691 struct drm_i915_gem_execbuffer2 execbuf
= {
692 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
693 .buffer_count
= batch
->exec_count
,
694 .batch_start_offset
= 0,
697 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
700 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
702 if (in_fence
!= -1) {
703 execbuf
.rsvd2
= in_fence
;
704 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
707 if (out_fence
!= NULL
) {
708 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
710 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
713 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
717 for (int i
= 0; i
< batch
->exec_count
; i
++) {
718 struct brw_bo
*bo
= batch
->exec_bos
[i
];
723 /* Update brw_bo::gtt_offset */
724 if (batch
->validation_list
[i
].offset
!= bo
->gtt_offset
) {
725 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
726 bo
->gem_handle
, bo
->gtt_offset
,
727 batch
->validation_list
[i
].offset
);
728 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
729 bo
->gtt_offset
= batch
->validation_list
[i
].offset
;
733 if (ret
== 0 && out_fence
!= NULL
)
734 *out_fence
= execbuf
.rsvd2
>> 32;
740 submit_batch(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
742 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
743 struct intel_batchbuffer
*batch
= &brw
->batch
;
746 if (batch
->use_shadow_copy
) {
747 void *bo_map
= brw_bo_map(brw
, batch
->batch
.bo
, MAP_WRITE
);
748 memcpy(bo_map
, batch
->batch
.map
, 4 * USED_BATCH(*batch
));
750 bo_map
= brw_bo_map(brw
, batch
->state
.bo
, MAP_WRITE
);
751 memcpy(bo_map
, batch
->state
.map
, batch
->state_used
);
754 brw_bo_unmap(batch
->batch
.bo
);
755 brw_bo_unmap(batch
->state
.bo
);
757 if (!brw
->screen
->no_hw
) {
758 /* The requirement for using I915_EXEC_NO_RELOC are:
760 * The addresses written in the objects must match the corresponding
761 * reloc.gtt_offset which in turn must match the corresponding
764 * Any render targets written to in the batch must be flagged with
767 * To avoid stalling, execobject.offset should match the current
768 * address of that object within the active context.
770 int flags
= I915_EXEC_NO_RELOC
| I915_EXEC_RENDER
;
772 if (batch
->needs_sol_reset
)
773 flags
|= I915_EXEC_GEN7_SOL_RESET
;
775 /* Set statebuffer relocations */
776 const unsigned state_index
= batch
->state
.bo
->index
;
777 if (state_index
< batch
->exec_count
&&
778 batch
->exec_bos
[state_index
] == batch
->state
.bo
) {
779 struct drm_i915_gem_exec_object2
*entry
=
780 &batch
->validation_list
[state_index
];
781 assert(entry
->handle
== batch
->state
.bo
->gem_handle
);
782 entry
->relocation_count
= batch
->state_relocs
.reloc_count
;
783 entry
->relocs_ptr
= (uintptr_t) batch
->state_relocs
.relocs
;
786 /* Set batchbuffer relocations */
787 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
788 assert(entry
->handle
== batch
->batch
.bo
->gem_handle
);
789 entry
->relocation_count
= batch
->batch_relocs
.reloc_count
;
790 entry
->relocs_ptr
= (uintptr_t) batch
->batch_relocs
.relocs
;
792 if (batch
->use_batch_first
) {
793 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
795 /* Move the batch to the end of the validation list */
796 struct drm_i915_gem_exec_object2 tmp
;
797 struct brw_bo
*tmp_bo
;
798 const unsigned index
= batch
->exec_count
- 1;
801 *entry
= batch
->validation_list
[index
];
802 batch
->validation_list
[index
] = tmp
;
804 tmp_bo
= batch
->exec_bos
[0];
805 batch
->exec_bos
[0] = batch
->exec_bos
[index
];
806 batch
->exec_bos
[index
] = tmp_bo
;
809 ret
= execbuffer(dri_screen
->fd
, batch
, brw
->hw_ctx
,
810 4 * USED_BATCH(*batch
),
811 in_fence_fd
, out_fence_fd
, flags
);
816 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
817 gen_print_batch(&batch
->decoder
, batch
->batch
.map
,
818 4 * USED_BATCH(*batch
),
819 batch
->batch
.bo
->gtt_offset
, false);
822 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
823 brw_check_for_reset(brw
);
826 fprintf(stderr
, "i965: Failed to submit batchbuffer: %s\n",
835 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
838 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
839 * of the returned fd.
842 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
843 int in_fence_fd
, int *out_fence_fd
,
844 const char *file
, int line
)
848 if (USED_BATCH(brw
->batch
) == 0)
851 /* Check that we didn't just wrap our batchbuffer at a bad time. */
852 assert(!brw
->batch
.no_wrap
);
854 brw_finish_batch(brw
);
855 brw_upload_finish(&brw
->upload
);
857 finish_growing_bos(&brw
->batch
.batch
);
858 finish_growing_bos(&brw
->batch
.state
);
860 if (brw
->throttle_batch
[0] == NULL
) {
861 brw
->throttle_batch
[0] = brw
->batch
.batch
.bo
;
862 brw_bo_reference(brw
->throttle_batch
[0]);
865 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
866 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
867 int bytes_for_state
= brw
->batch
.state_used
;
868 fprintf(stderr
, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
869 " %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
870 " %4d batch relocs, %4d state relocs\n", file
, line
,
871 bytes_for_commands
, 100.0f
* bytes_for_commands
/ BATCH_SZ
,
872 bytes_for_state
, 100.0f
* bytes_for_state
/ STATE_SZ
,
873 brw
->batch
.exec_count
,
874 (float) (brw
->batch
.aperture_space
/ (1024 * 1024)),
875 brw
->batch
.batch_relocs
.reloc_count
,
876 brw
->batch
.state_relocs
.reloc_count
);
878 dump_validation_list(&brw
->batch
);
881 ret
= submit_batch(brw
, in_fence_fd
, out_fence_fd
);
883 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
884 fprintf(stderr
, "waiting for idle\n");
885 brw_bo_wait_rendering(brw
->batch
.batch
.bo
);
888 /* Start a new batch buffer. */
895 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
897 unsigned index
= READ_ONCE(bo
->index
);
898 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
901 for (int i
= 0; i
< batch
->exec_count
; i
++) {
902 if (batch
->exec_bos
[i
] == bo
)
908 /* This is the only way buffers get added to the validate list.
911 emit_reloc(struct intel_batchbuffer
*batch
,
912 struct brw_reloc_list
*rlist
, uint32_t offset
,
913 struct brw_bo
*target
, int32_t target_offset
,
914 unsigned int reloc_flags
)
916 assert(target
!= NULL
);
918 if (target
->kflags
& EXEC_OBJECT_PINNED
) {
919 brw_use_pinned_bo(batch
, target
, reloc_flags
& RELOC_WRITE
);
920 return gen_canonical_address(target
->gtt_offset
+ target_offset
);
923 unsigned int index
= add_exec_bo(batch
, target
);
924 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
926 if (rlist
->reloc_count
== rlist
->reloc_array_size
) {
927 rlist
->reloc_array_size
*= 2;
928 rlist
->relocs
= realloc(rlist
->relocs
,
929 rlist
->reloc_array_size
*
930 sizeof(struct drm_i915_gem_relocation_entry
));
933 if (reloc_flags
& RELOC_32BIT
) {
934 /* Restrict this buffer to the low 32 bits of the address space.
936 * Altering the validation list flags restricts it for this batch,
937 * but we also alter the BO's kflags to restrict it permanently
938 * (until the BO is destroyed and put back in the cache). Buffers
939 * may stay bound across batches, and we want keep it constrained.
941 target
->kflags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
942 entry
->flags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
944 /* RELOC_32BIT is not an EXEC_OBJECT_* flag, so get rid of it. */
945 reloc_flags
&= ~RELOC_32BIT
;
949 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
951 rlist
->relocs
[rlist
->reloc_count
++] =
952 (struct drm_i915_gem_relocation_entry
) {
954 .delta
= target_offset
,
955 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
956 .presumed_offset
= entry
->offset
,
959 /* Using the old buffer offset, write in what the right data would be, in
960 * case the buffer doesn't move and we can short-circuit the relocation
961 * processing in the kernel
963 return entry
->offset
+ target_offset
;
967 brw_use_pinned_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
,
968 unsigned writable_flag
)
970 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
971 assert((writable_flag
& ~EXEC_OBJECT_WRITE
) == 0);
973 unsigned int index
= add_exec_bo(batch
, bo
);
974 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
975 assert(entry
->offset
== bo
->gtt_offset
);
978 entry
->flags
|= EXEC_OBJECT_WRITE
;
982 brw_batch_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
983 struct brw_bo
*target
, uint32_t target_offset
,
984 unsigned int reloc_flags
)
986 assert(batch_offset
<= batch
->batch
.bo
->size
- sizeof(uint32_t));
988 return emit_reloc(batch
, &batch
->batch_relocs
, batch_offset
,
989 target
, target_offset
, reloc_flags
);
993 brw_state_reloc(struct intel_batchbuffer
*batch
, uint32_t state_offset
,
994 struct brw_bo
*target
, uint32_t target_offset
,
995 unsigned int reloc_flags
)
997 assert(state_offset
<= batch
->state
.bo
->size
- sizeof(uint32_t));
999 return emit_reloc(batch
, &batch
->state_relocs
, state_offset
,
1000 target
, target_offset
, reloc_flags
);
1004 * Reserve some space in the statebuffer, or flush.
1006 * This is used to estimate when we're near the end of the batch,
1007 * so we can flush early.
1010 brw_require_statebuffer_space(struct brw_context
*brw
, int size
)
1012 if (brw
->batch
.state_used
+ size
>= STATE_SZ
)
1013 intel_batchbuffer_flush(brw
);
1017 * Allocates a block of space in the batchbuffer for indirect state.
1020 brw_state_batch(struct brw_context
*brw
,
1023 uint32_t *out_offset
)
1025 struct intel_batchbuffer
*batch
= &brw
->batch
;
1027 assert(size
< batch
->state
.bo
->size
);
1029 uint32_t offset
= ALIGN(batch
->state_used
, alignment
);
1031 if (offset
+ size
>= STATE_SZ
&& !batch
->no_wrap
) {
1032 intel_batchbuffer_flush(brw
);
1033 offset
= ALIGN(batch
->state_used
, alignment
);
1034 } else if (offset
+ size
>= batch
->state
.bo
->size
) {
1035 const unsigned new_size
=
1036 MIN2(batch
->state
.bo
->size
+ batch
->state
.bo
->size
/ 2,
1038 grow_buffer(brw
, &batch
->state
, batch
->state_used
, new_size
);
1039 assert(offset
+ size
< batch
->state
.bo
->size
);
1042 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
1043 _mesa_hash_table_u64_insert(batch
->state_batch_sizes
,
1044 offset
, (void *) (uintptr_t) size
);
1047 batch
->state_used
= offset
+ size
;
1049 *out_offset
= offset
;
1050 return batch
->state
.map
+ (offset
>> 2);
1054 intel_batchbuffer_data(struct brw_context
*brw
,
1055 const void *data
, GLuint bytes
)
1057 assert((bytes
& 3) == 0);
1058 intel_batchbuffer_require_space(brw
, bytes
);
1059 memcpy(brw
->batch
.map_next
, data
, bytes
);
1060 brw
->batch
.map_next
+= bytes
>> 2;
1064 load_sized_register_mem(struct brw_context
*brw
,
1070 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1073 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
1074 assert(devinfo
->gen
>= 7);
1076 if (devinfo
->gen
>= 8) {
1077 BEGIN_BATCH(4 * size
);
1078 for (i
= 0; i
< size
; i
++) {
1079 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
1080 OUT_BATCH(reg
+ i
* 4);
1081 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
1085 BEGIN_BATCH(3 * size
);
1086 for (i
= 0; i
< size
; i
++) {
1087 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
1088 OUT_BATCH(reg
+ i
* 4);
1089 OUT_RELOC(bo
, 0, offset
+ i
* 4);
1096 brw_load_register_mem(struct brw_context
*brw
,
1101 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
1105 brw_load_register_mem64(struct brw_context
*brw
,
1110 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
1114 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
1117 brw_store_register_mem32(struct brw_context
*brw
,
1118 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1120 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1122 assert(devinfo
->gen
>= 6);
1124 if (devinfo
->gen
>= 8) {
1126 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1128 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1132 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1134 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1140 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
1143 brw_store_register_mem64(struct brw_context
*brw
,
1144 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1146 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1148 assert(devinfo
->gen
>= 6);
1150 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
1151 * read a full 64-bit register, we need to do two of them.
1153 if (devinfo
->gen
>= 8) {
1155 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1157 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1158 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1159 OUT_BATCH(reg
+ sizeof(uint32_t));
1160 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
1164 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1166 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1167 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1168 OUT_BATCH(reg
+ sizeof(uint32_t));
1169 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
1175 * Write a 32-bit register using immediate data.
1178 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
1180 assert(brw
->screen
->devinfo
.gen
>= 6);
1183 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
1190 * Write a 64-bit register using immediate data.
1193 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
1195 assert(brw
->screen
->devinfo
.gen
>= 6);
1198 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
1200 OUT_BATCH(imm
& 0xffffffff);
1202 OUT_BATCH(imm
>> 32);
1207 * Copies a 32-bit register.
1210 brw_load_register_reg(struct brw_context
*brw
, uint32_t dest
, uint32_t src
)
1212 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1215 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1222 * Copies a 64-bit register.
1225 brw_load_register_reg64(struct brw_context
*brw
, uint32_t dest
, uint32_t src
)
1227 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1230 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1233 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1234 OUT_BATCH(src
+ sizeof(uint32_t));
1235 OUT_BATCH(dest
+ sizeof(uint32_t));
1240 * Write 32-bits of immediate data to a GPU memory buffer.
1243 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1244 uint32_t offset
, uint32_t imm
)
1246 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1248 assert(devinfo
->gen
>= 6);
1251 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1252 if (devinfo
->gen
>= 8)
1253 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1255 OUT_BATCH(0); /* MBZ */
1256 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1263 * Write 64-bits of immediate data to a GPU memory buffer.
1266 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1267 uint32_t offset
, uint64_t imm
)
1269 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1271 assert(devinfo
->gen
>= 6);
1274 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1275 if (devinfo
->gen
>= 8)
1276 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1278 OUT_BATCH(0); /* MBZ */
1279 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1281 OUT_BATCH(imm
& 0xffffffffu
);
1282 OUT_BATCH(imm
>> 32);