1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "brw_context.h"
36 intel_batchbuffer_reset(struct brw_context
*brw
);
38 struct cached_batch_item
{
39 struct cached_batch_item
*next
;
45 intel_batchbuffer_clear_cache(struct brw_context
*brw
)
47 struct cached_batch_item
*item
= brw
->batch
.cached_items
;
50 struct cached_batch_item
*next
= item
->next
;
55 brw
->batch
.cached_items
= NULL
;
59 intel_batchbuffer_init(struct brw_context
*brw
)
61 intel_batchbuffer_reset(brw
);
64 /* We can't just use brw_state_batch to get a chunk of space for
65 * the gen6 workaround because it involves actually writing to
66 * the buffer, and the kernel doesn't let us write to the batch.
68 brw
->batch
.workaround_bo
= drm_intel_bo_alloc(brw
->bufmgr
,
69 "pipe_control workaround",
73 brw
->batch
.need_workaround_flush
= true;
76 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
77 brw
->batch
.map
= brw
->batch
.cpu_map
;
82 intel_batchbuffer_reset(struct brw_context
*brw
)
84 if (brw
->batch
.last_bo
!= NULL
) {
85 drm_intel_bo_unreference(brw
->batch
.last_bo
);
86 brw
->batch
.last_bo
= NULL
;
88 brw
->batch
.last_bo
= brw
->batch
.bo
;
90 intel_batchbuffer_clear_cache(brw
);
92 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
95 drm_intel_bo_map(brw
->batch
.bo
, true);
96 brw
->batch
.map
= brw
->batch
.bo
->virtual;
99 brw
->batch
.reserved_space
= BATCH_RESERVED
;
100 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
102 brw
->batch
.needs_sol_reset
= false;
106 intel_batchbuffer_save_state(struct brw_context
*brw
)
108 brw
->batch
.saved
.used
= brw
->batch
.used
;
109 brw
->batch
.saved
.reloc_count
=
110 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
114 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
116 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
118 brw
->batch
.used
= brw
->batch
.saved
.used
;
120 /* Cached batch state is dead, since we just cleared some unknown part of the
121 * batchbuffer. Assume that the caller resets any other state necessary.
123 intel_batchbuffer_clear_cache(brw
);
127 intel_batchbuffer_free(struct brw_context
*brw
)
129 free(brw
->batch
.cpu_map
);
130 drm_intel_bo_unreference(brw
->batch
.last_bo
);
131 drm_intel_bo_unreference(brw
->batch
.bo
);
132 drm_intel_bo_unreference(brw
->batch
.workaround_bo
);
133 intel_batchbuffer_clear_cache(brw
);
137 do_batch_dump(struct brw_context
*brw
)
139 struct drm_intel_decode
*decode
;
140 struct intel_batchbuffer
*batch
= &brw
->batch
;
143 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
147 ret
= drm_intel_bo_map(batch
->bo
, false);
149 drm_intel_decode_set_batch_pointer(decode
,
155 "WARNING: failed to map batchbuffer (%s), "
156 "dumping uploaded data instead.\n", strerror(ret
));
158 drm_intel_decode_set_batch_pointer(decode
,
164 drm_intel_decode(decode
);
166 drm_intel_decode_context_free(decode
);
169 drm_intel_bo_unmap(batch
->bo
);
171 brw_debug_batch(brw
);
176 * Called when starting a new batch buffer.
179 brw_new_batch(struct brw_context
*brw
)
181 /* If the kernel supports hardware contexts, then most hardware state is
182 * preserved between batches; we only need to re-emit state that is required
183 * to be in every batch. Otherwise we need to re-emit all the state that
184 * would otherwise be stored in the context (which for all intents and
185 * purposes means everything).
187 if (brw
->hw_ctx
== NULL
)
188 brw
->state
.dirty
.brw
|= BRW_NEW_CONTEXT
;
190 brw
->state
.dirty
.brw
|= BRW_NEW_BATCH
;
192 /* Assume that the last command before the start of our batch was a
193 * primitive, for safety.
195 brw
->batch
.need_workaround_flush
= true;
197 brw
->state_batch_count
= 0;
201 /* Mark that the current program cache BO has been used by the GPU.
202 * It will be reallocated if we need to put new programs in for the
205 brw
->cache
.bo_used_by_gpu
= true;
207 /* We need to periodically reap the shader time results, because rollover
208 * happens every few seconds. We also want to see results every once in a
209 * while, because many programs won't cleanly destroy our context, so the
210 * end-of-run printout may not happen.
212 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
213 brw_collect_and_report_shader_time(brw
);
217 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
220 * This function can emit state (say, to preserve registers that aren't saved
221 * between batches). All of this state MUST fit in the reserved space at the
222 * end of the batchbuffer. If you add more GPU state, increase the reserved
223 * space by updating the BATCH_RESERVED macro.
226 brw_finish_batch(struct brw_context
*brw
)
228 brw_emit_query_end(brw
);
230 if (brw
->curbe
.curbe_bo
) {
231 drm_intel_gem_bo_unmap_gtt(brw
->curbe
.curbe_bo
);
232 drm_intel_bo_unreference(brw
->curbe
.curbe_bo
);
233 brw
->curbe
.curbe_bo
= NULL
;
237 /* TODO: Push this whole function into bufmgr.
240 do_flush_locked(struct brw_context
*brw
)
242 struct intel_batchbuffer
*batch
= &brw
->batch
;
246 drm_intel_bo_unmap(batch
->bo
);
248 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
249 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
250 ret
= drm_intel_bo_subdata(batch
->bo
,
251 batch
->state_batch_offset
,
252 batch
->bo
->size
- batch
->state_batch_offset
,
253 (char *)batch
->map
+ batch
->state_batch_offset
);
257 if (!brw
->intelScreen
->no_hw
) {
260 if (brw
->gen
< 6 || !batch
->is_blit
) {
261 flags
= I915_EXEC_RENDER
;
263 flags
= I915_EXEC_BLT
;
266 if (batch
->needs_sol_reset
)
267 flags
|= I915_EXEC_GEN7_SOL_RESET
;
270 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
271 brw_annotate_aub(brw
);
272 if (brw
->hw_ctx
== NULL
|| batch
->is_blit
) {
273 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
276 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
277 4 * batch
->used
, flags
);
282 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
286 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
295 _intel_batchbuffer_flush(struct brw_context
*brw
,
296 const char *file
, int line
)
300 if (brw
->batch
.used
== 0)
303 if (brw
->first_post_swapbuffers_batch
== NULL
) {
304 brw
->first_post_swapbuffers_batch
= brw
->batch
.bo
;
305 drm_intel_bo_reference(brw
->first_post_swapbuffers_batch
);
308 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
309 int bytes_for_commands
= 4 * brw
->batch
.used
;
310 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
311 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
312 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
313 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
314 bytes_for_commands
, bytes_for_state
,
316 100.0f
* total_bytes
/ BATCH_SZ
);
319 brw
->batch
.reserved_space
= 0;
321 brw_finish_batch(brw
);
323 /* Mark the end of the buffer. */
324 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
325 if (brw
->batch
.used
& 1) {
326 /* Round batchbuffer usage to 2 DWORDs. */
327 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
330 intel_upload_finish(brw
);
332 /* Check that we didn't just wrap our batchbuffer at a bad time. */
333 assert(!brw
->no_batch_wrap
);
335 ret
= do_flush_locked(brw
);
337 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
338 fprintf(stderr
, "waiting for idle\n");
339 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
344 intel_batchbuffer_reset(brw
);
350 /* This is the only way buffers get added to the validate list.
353 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
354 drm_intel_bo
*buffer
,
355 uint32_t read_domains
, uint32_t write_domain
,
360 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
362 read_domains
, write_domain
);
367 * Using the old buffer offset, write in what the right data would be, in case
368 * the buffer doesn't move and we can short-circuit the relocation processing
371 intel_batchbuffer_emit_dword(brw
, buffer
->offset
+ delta
);
377 intel_batchbuffer_emit_reloc_fenced(struct brw_context
*brw
,
378 drm_intel_bo
*buffer
,
379 uint32_t read_domains
,
380 uint32_t write_domain
,
385 ret
= drm_intel_bo_emit_reloc_fence(brw
->batch
.bo
, 4*brw
->batch
.used
,
387 read_domains
, write_domain
);
392 * Using the old buffer offset, write in what the right data would
393 * be, in case the buffer doesn't move and we can short-circuit the
394 * relocation processing in the kernel
396 intel_batchbuffer_emit_dword(brw
, buffer
->offset
+ delta
);
402 intel_batchbuffer_data(struct brw_context
*brw
,
403 const void *data
, GLuint bytes
, bool is_blit
)
405 assert((bytes
& 3) == 0);
406 intel_batchbuffer_require_space(brw
, bytes
, is_blit
);
407 __memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
408 brw
->batch
.used
+= bytes
>> 2;
412 intel_batchbuffer_cached_advance(struct brw_context
*brw
)
414 struct cached_batch_item
**prev
= &brw
->batch
.cached_items
, *item
;
415 uint32_t sz
= (brw
->batch
.used
- brw
->batch
.emit
) * sizeof(uint32_t);
416 uint32_t *start
= brw
->batch
.map
+ brw
->batch
.emit
;
417 uint16_t op
= *start
>> 16;
423 old
= brw
->batch
.map
+ item
->header
;
424 if (op
== *old
>> 16) {
425 if (item
->size
== sz
&& memcmp(old
, start
, sz
) == 0) {
426 if (prev
!= &brw
->batch
.cached_items
) {
428 item
->next
= brw
->batch
.cached_items
;
429 brw
->batch
.cached_items
= item
;
431 brw
->batch
.used
= brw
->batch
.emit
;
440 item
= malloc(sizeof(struct cached_batch_item
));
444 item
->next
= brw
->batch
.cached_items
;
445 brw
->batch
.cached_items
= item
;
449 item
->header
= brw
->batch
.emit
;
453 * Restriction [DevSNB, DevIVB]:
455 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
456 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
457 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
458 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
459 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
460 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
461 * unless SW can otherwise guarantee that the pipeline from WM onwards is
462 * already flushed (e.g., via a preceding MI_FLUSH).
465 intel_emit_depth_stall_flushes(struct brw_context
*brw
)
467 assert(brw
->gen
>= 6 && brw
->gen
<= 7);
470 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
471 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
472 OUT_BATCH(0); /* address */
473 OUT_BATCH(0); /* write data */
477 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
478 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
479 OUT_BATCH(0); /* address */
480 OUT_BATCH(0); /* write data */
484 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
485 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
486 OUT_BATCH(0); /* address */
487 OUT_BATCH(0); /* write data */
492 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
493 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
494 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
495 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
496 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
497 * to be sent before any combination of VS associated 3DSTATE."
500 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
502 assert(brw
->gen
== 7);
505 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
506 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE
);
507 OUT_RELOC(brw
->batch
.workaround_bo
,
508 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
509 OUT_BATCH(0); /* write data */
514 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
515 * implementing two workarounds on gen6. From section 1.4.7.1
516 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
518 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
519 * produced by non-pipelined state commands), software needs to first
520 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
523 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
524 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
526 * And the workaround for these two requires this workaround first:
528 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
529 * BEFORE the pipe-control with a post-sync op and no write-cache
532 * And this last workaround is tricky because of the requirements on
533 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
536 * "1 of the following must also be set:
537 * - Render Target Cache Flush Enable ([12] of DW1)
538 * - Depth Cache Flush Enable ([0] of DW1)
539 * - Stall at Pixel Scoreboard ([1] of DW1)
540 * - Depth Stall ([13] of DW1)
541 * - Post-Sync Operation ([13] of DW1)
542 * - Notify Enable ([8] of DW1)"
544 * The cache flushes require the workaround flush that triggered this
545 * one, so we can't use it. Depth stall would trigger the same.
546 * Post-sync nonzero is what triggered this second workaround, so we
547 * can't use that one either. Notify enable is IRQs, which aren't
548 * really our business. That leaves only stall at scoreboard.
551 intel_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
553 if (!brw
->batch
.need_workaround_flush
)
557 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
558 OUT_BATCH(PIPE_CONTROL_CS_STALL
|
559 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
560 OUT_BATCH(0); /* address */
561 OUT_BATCH(0); /* write data */
565 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
566 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE
);
567 OUT_RELOC(brw
->batch
.workaround_bo
,
568 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
569 OUT_BATCH(0); /* write data */
572 brw
->batch
.need_workaround_flush
= false;
575 /* Emit a pipelined flush to either flush render and texture cache for
576 * reading from a FBO-drawn texture, or flush so that frontbuffer
577 * render appears on the screen in DRI1.
579 * This is also used for the always_flush_cache driconf debug option.
582 intel_batchbuffer_emit_mi_flush(struct brw_context
*brw
)
585 if (brw
->batch
.is_blit
) {
587 OUT_BATCH(MI_FLUSH_DW
);
594 /* Hardware workaround: SNB B-Spec says:
596 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
597 * Flush Enable =1, a PIPE_CONTROL with any non-zero
598 * post-sync-op is required.
600 intel_emit_post_sync_nonzero_flush(brw
);
604 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
605 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH
|
606 PIPE_CONTROL_WRITE_FLUSH
|
607 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
608 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
609 PIPE_CONTROL_TC_FLUSH
|
610 PIPE_CONTROL_NO_WRITE
|
611 PIPE_CONTROL_CS_STALL
);
612 OUT_BATCH(0); /* write address */
613 OUT_BATCH(0); /* write data */
618 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2) |
619 PIPE_CONTROL_WRITE_FLUSH
|
620 PIPE_CONTROL_NO_WRITE
);
621 OUT_BATCH(0); /* write address */
622 OUT_BATCH(0); /* write data */
623 OUT_BATCH(0); /* write data */